Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
On 13.11.18 08:04, Yogesh Narayan Gaur wrote: > Hi Frieder, > > Thanks for review. > >> -Original Message- >> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] >> Sent: Wednesday, November 7, 2018 9:52 PM >> To: Yogesh Narayan Gaur ; linux- >> m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; >> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org >> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- >> arm-ker...@lists.infradead.org; computersforpe...@gmail.com; >> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org >> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI >> controller >> >> Hi Yogesh, >> >> I didn't have time to look at all of the code, but nevertheless here are some >> comments. >> >> On 23.10.18 10:56, Yogesh Narayan Gaur wrote: >>> - Add driver for NXP FlexSPI host controller >>> >>> (0) What is the FlexSPI controller? >>>FlexSPI is a flexsible SPI host controller which supports two SPI >>>channels and up to 4 external devices. Each channel supports >>>Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional >>>data lines) i.e. FlexSPI acts as an interface to external devices, >>>maximum 4, each with up to 8 bidirectional data lines. >>> >>>It uses new SPI memory interface of the SPI framework to issue >>>flash memory operations to up to four connected flash >>>devices (2 buses with 2 CS each). >>> >>> (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility >>>on NXP LX2160ARDB and LX2160AQDS targets. >>>LX2160ARDB is having two NOR slave device connected on single bus A >>>i.e. A0 and A1 (CS0 and CS1). >>>LX2160AQDS is having two NOR slave device connected on separate buses >>>one flash on A0 and second on B1 i.e. (CS0 and CS3). >>>Verified this driver on following SPI NOR flashes: >>> Micron, mt35xu512ab, [Read - 1 bit mode] >>> Cypress, s25fl512s, [Read - 1/2/4 bit mode] >>> >>> Signed-off-by: Yogesh Gaur >>> --- >>> Changes for v4: >>> - Incorporate Boris review comments >>> * Use readl_poll_timeout() instead of busy looping. >>> * Re-define register masking as per comment. >>> * Drop fspi_devtype enum. >>> Changes for v3: >>> - Added endianness flag in platform specific structure instead of DTS. >>> - Modified nxp_fspi_read_ahb(), removed remapping code. >>> - Added Boris and Frieder as Author and provided reference of >>> spi-fsl-qspi.c Changes for v2: >>> - Incorporated Boris review comments. >>> - Remove dependency of driver over connected flash device size. >>> - Modified the logic to select requested CS. >>> - Remove SPI-Octal Macros. >>> >>>drivers/spi/Kconfig| 10 + >>>drivers/spi/Makefile |1 + >>>drivers/spi/spi-nxp-fspi.c | 1158 >> >>>3 files changed, 1169 insertions(+) >>>create mode 100644 drivers/spi/spi-nxp-fspi.c >>> >>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index >>> ad5d68e..68da874 100644 >>> --- a/drivers/spi/Kconfig >>> +++ b/drivers/spi/Kconfig >>> @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI >>> help >>> This enables Freescale i.MX LPSPI controllers in master mode. >>> >>> +config SPI_NXP_FLEXSPI >>> + tristate "NXP Flex SPI controller" >>> + depends on ARCH_LAYERSCAPE || HAS_IOMEM >>> + help >>> + This enables support for the Flex SPI controller in master mode. >>> + Up to four slave devices can be connected on two buses with two >>> + chipselects each. >>> + This controller does not support generic SPI messages and only >>> + supports the high-level SPI memory interface. >>> + >>>config SPI_GPIO >>> tristate "GPIO-based bitbanging SPI Master" >>> depends on GPIOLIB || COMPILE_TEST >>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index >>> cb1f437..52c9f18 100644 >>> --- a/drivers/spi/Makefile >>> +++ b/drivers/spi/Makefile >>> @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi- >> mpc52xx.o >>>obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o >>>obj-$(CONFIG_
Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
On 13.11.18 08:04, Yogesh Narayan Gaur wrote: > Hi Frieder, > > Thanks for review. > >> -Original Message- >> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] >> Sent: Wednesday, November 7, 2018 9:52 PM >> To: Yogesh Narayan Gaur ; linux- >> m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; >> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org >> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- >> arm-ker...@lists.infradead.org; computersforpe...@gmail.com; >> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org >> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI >> controller >> >> Hi Yogesh, >> >> I didn't have time to look at all of the code, but nevertheless here are some >> comments. >> >> On 23.10.18 10:56, Yogesh Narayan Gaur wrote: >>> - Add driver for NXP FlexSPI host controller >>> >>> (0) What is the FlexSPI controller? >>>FlexSPI is a flexsible SPI host controller which supports two SPI >>>channels and up to 4 external devices. Each channel supports >>>Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional >>>data lines) i.e. FlexSPI acts as an interface to external devices, >>>maximum 4, each with up to 8 bidirectional data lines. >>> >>>It uses new SPI memory interface of the SPI framework to issue >>>flash memory operations to up to four connected flash >>>devices (2 buses with 2 CS each). >>> >>> (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility >>>on NXP LX2160ARDB and LX2160AQDS targets. >>>LX2160ARDB is having two NOR slave device connected on single bus A >>>i.e. A0 and A1 (CS0 and CS1). >>>LX2160AQDS is having two NOR slave device connected on separate buses >>>one flash on A0 and second on B1 i.e. (CS0 and CS3). >>>Verified this driver on following SPI NOR flashes: >>> Micron, mt35xu512ab, [Read - 1 bit mode] >>> Cypress, s25fl512s, [Read - 1/2/4 bit mode] >>> >>> Signed-off-by: Yogesh Gaur >>> --- >>> Changes for v4: >>> - Incorporate Boris review comments >>> * Use readl_poll_timeout() instead of busy looping. >>> * Re-define register masking as per comment. >>> * Drop fspi_devtype enum. >>> Changes for v3: >>> - Added endianness flag in platform specific structure instead of DTS. >>> - Modified nxp_fspi_read_ahb(), removed remapping code. >>> - Added Boris and Frieder as Author and provided reference of >>> spi-fsl-qspi.c Changes for v2: >>> - Incorporated Boris review comments. >>> - Remove dependency of driver over connected flash device size. >>> - Modified the logic to select requested CS. >>> - Remove SPI-Octal Macros. >>> >>>drivers/spi/Kconfig| 10 + >>>drivers/spi/Makefile |1 + >>>drivers/spi/spi-nxp-fspi.c | 1158 >> >>>3 files changed, 1169 insertions(+) >>>create mode 100644 drivers/spi/spi-nxp-fspi.c >>> >>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index >>> ad5d68e..68da874 100644 >>> --- a/drivers/spi/Kconfig >>> +++ b/drivers/spi/Kconfig >>> @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI >>> help >>> This enables Freescale i.MX LPSPI controllers in master mode. >>> >>> +config SPI_NXP_FLEXSPI >>> + tristate "NXP Flex SPI controller" >>> + depends on ARCH_LAYERSCAPE || HAS_IOMEM >>> + help >>> + This enables support for the Flex SPI controller in master mode. >>> + Up to four slave devices can be connected on two buses with two >>> + chipselects each. >>> + This controller does not support generic SPI messages and only >>> + supports the high-level SPI memory interface. >>> + >>>config SPI_GPIO >>> tristate "GPIO-based bitbanging SPI Master" >>> depends on GPIOLIB || COMPILE_TEST >>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index >>> cb1f437..52c9f18 100644 >>> --- a/drivers/spi/Makefile >>> +++ b/drivers/spi/Makefile >>> @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi- >> mpc52xx.o >>>obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o >>>obj-$(CONFIG_
RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Frieder, Thanks for review. > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Wednesday, November 7, 2018 9:52 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; > broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > Hi Yogesh, > > I didn't have time to look at all of the code, but nevertheless here are some > comments. > > On 23.10.18 10:56, Yogesh Narayan Gaur wrote: > > - Add driver for NXP FlexSPI host controller > > > > (0) What is the FlexSPI controller? > > FlexSPI is a flexsible SPI host controller which supports two SPI > > channels and up to 4 external devices. Each channel supports > > Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > > data lines) i.e. FlexSPI acts as an interface to external devices, > > maximum 4, each with up to 8 bidirectional data lines. > > > > It uses new SPI memory interface of the SPI framework to issue > > flash memory operations to up to four connected flash > > devices (2 buses with 2 CS each). > > > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility > > on NXP LX2160ARDB and LX2160AQDS targets. > > LX2160ARDB is having two NOR slave device connected on single bus A > > i.e. A0 and A1 (CS0 and CS1). > > LX2160AQDS is having two NOR slave device connected on separate buses > > one flash on A0 and second on B1 i.e. (CS0 and CS3). > > Verified this driver on following SPI NOR flashes: > > Micron, mt35xu512ab, [Read - 1 bit mode] > > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > > > Signed-off-by: Yogesh Gaur > > --- > > Changes for v4: > > - Incorporate Boris review comments > >* Use readl_poll_timeout() instead of busy looping. > >* Re-define register masking as per comment. > >* Drop fspi_devtype enum. > > Changes for v3: > > - Added endianness flag in platform specific structure instead of DTS. > > - Modified nxp_fspi_read_ahb(), removed remapping code. > > - Added Boris and Frieder as Author and provided reference of > > spi-fsl-qspi.c Changes for v2: > > - Incorporated Boris review comments. > > - Remove dependency of driver over connected flash device size. > > - Modified the logic to select requested CS. > > - Remove SPI-Octal Macros. > > > > drivers/spi/Kconfig| 10 + > > drivers/spi/Makefile |1 + > > drivers/spi/spi-nxp-fspi.c | 1158 > > > 3 files changed, 1169 insertions(+) > > create mode 100644 drivers/spi/spi-nxp-fspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > ad5d68e..68da874 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI > > help > > This enables Freescale i.MX LPSPI controllers in master mode. > > > > +config SPI_NXP_FLEXSPI > > + tristate "NXP Flex SPI controller" > > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > > + help > > + This enables support for the Flex SPI controller in master mode. > > + Up to four slave devices can be connected on two buses with two > > + chipselects each. > > + This controller does not support generic SPI messages and only > > + supports the high-level SPI memory interface. > > + > > config SPI_GPIO > > tristate "GPIO-based bitbanging SPI Master" > > depends on GPIOLIB || COMPILE_TEST > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > cb1f437..52c9f18 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi- > mpc52xx.o > > obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o > > obj-$(CONFIG_SPI_MXS) += spi-mxs.o > > obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o > > +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o > > obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o > > spi-octeon-objs := spi-cavium.o spi-cavium- > octeon.o > > obj-$(CONFIG_SPI_OCTEON) += s
RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Frieder, Thanks for review. > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Wednesday, November 7, 2018 9:52 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; > broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > Hi Yogesh, > > I didn't have time to look at all of the code, but nevertheless here are some > comments. > > On 23.10.18 10:56, Yogesh Narayan Gaur wrote: > > - Add driver for NXP FlexSPI host controller > > > > (0) What is the FlexSPI controller? > > FlexSPI is a flexsible SPI host controller which supports two SPI > > channels and up to 4 external devices. Each channel supports > > Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > > data lines) i.e. FlexSPI acts as an interface to external devices, > > maximum 4, each with up to 8 bidirectional data lines. > > > > It uses new SPI memory interface of the SPI framework to issue > > flash memory operations to up to four connected flash > > devices (2 buses with 2 CS each). > > > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility > > on NXP LX2160ARDB and LX2160AQDS targets. > > LX2160ARDB is having two NOR slave device connected on single bus A > > i.e. A0 and A1 (CS0 and CS1). > > LX2160AQDS is having two NOR slave device connected on separate buses > > one flash on A0 and second on B1 i.e. (CS0 and CS3). > > Verified this driver on following SPI NOR flashes: > > Micron, mt35xu512ab, [Read - 1 bit mode] > > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > > > Signed-off-by: Yogesh Gaur > > --- > > Changes for v4: > > - Incorporate Boris review comments > >* Use readl_poll_timeout() instead of busy looping. > >* Re-define register masking as per comment. > >* Drop fspi_devtype enum. > > Changes for v3: > > - Added endianness flag in platform specific structure instead of DTS. > > - Modified nxp_fspi_read_ahb(), removed remapping code. > > - Added Boris and Frieder as Author and provided reference of > > spi-fsl-qspi.c Changes for v2: > > - Incorporated Boris review comments. > > - Remove dependency of driver over connected flash device size. > > - Modified the logic to select requested CS. > > - Remove SPI-Octal Macros. > > > > drivers/spi/Kconfig| 10 + > > drivers/spi/Makefile |1 + > > drivers/spi/spi-nxp-fspi.c | 1158 > > > 3 files changed, 1169 insertions(+) > > create mode 100644 drivers/spi/spi-nxp-fspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > ad5d68e..68da874 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI > > help > > This enables Freescale i.MX LPSPI controllers in master mode. > > > > +config SPI_NXP_FLEXSPI > > + tristate "NXP Flex SPI controller" > > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > > + help > > + This enables support for the Flex SPI controller in master mode. > > + Up to four slave devices can be connected on two buses with two > > + chipselects each. > > + This controller does not support generic SPI messages and only > > + supports the high-level SPI memory interface. > > + > > config SPI_GPIO > > tristate "GPIO-based bitbanging SPI Master" > > depends on GPIOLIB || COMPILE_TEST > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > cb1f437..52c9f18 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi- > mpc52xx.o > > obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o > > obj-$(CONFIG_SPI_MXS) += spi-mxs.o > > obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o > > +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o > > obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o > > spi-octeon-objs := spi-cavium.o spi-cavium- > octeon.o > > obj-$(CONFIG_SPI_OCTEON) += s
Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Yogesh, I didn't have time to look at all of the code, but nevertheless here are some comments. On 23.10.18 10:56, Yogesh Narayan Gaur wrote: > - Add driver for NXP FlexSPI host controller > > (0) What is the FlexSPI controller? > FlexSPI is a flexsible SPI host controller which supports two SPI > channels and up to 4 external devices. Each channel supports > Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > data lines) i.e. FlexSPI acts as an interface to external devices, > maximum 4, each with up to 8 bidirectional data lines. > > It uses new SPI memory interface of the SPI framework to issue > flash memory operations to up to four connected flash > devices (2 buses with 2 CS each). > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility > on NXP LX2160ARDB and LX2160AQDS targets. > LX2160ARDB is having two NOR slave device connected on single bus A > i.e. A0 and A1 (CS0 and CS1). > LX2160AQDS is having two NOR slave device connected on separate buses > one flash on A0 and second on B1 i.e. (CS0 and CS3). > Verified this driver on following SPI NOR flashes: > Micron, mt35xu512ab, [Read - 1 bit mode] > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > Signed-off-by: Yogesh Gaur > --- > Changes for v4: > - Incorporate Boris review comments >* Use readl_poll_timeout() instead of busy looping. >* Re-define register masking as per comment. >* Drop fspi_devtype enum. > Changes for v3: > - Added endianness flag in platform specific structure instead of DTS. > - Modified nxp_fspi_read_ahb(), removed remapping code. > - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c > Changes for v2: > - Incorporated Boris review comments. > - Remove dependency of driver over connected flash device size. > - Modified the logic to select requested CS. > - Remove SPI-Octal Macros. > > drivers/spi/Kconfig| 10 + > drivers/spi/Makefile |1 + > drivers/spi/spi-nxp-fspi.c | 1158 > > 3 files changed, 1169 insertions(+) > create mode 100644 drivers/spi/spi-nxp-fspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index ad5d68e..68da874 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_NXP_FLEXSPI > + tristate "NXP Flex SPI controller" > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > + help > + This enables support for the Flex SPI controller in master mode. > + Up to four slave devices can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages and only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index cb1f437..52c9f18 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o > obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o > obj-$(CONFIG_SPI_MXS) += spi-mxs.o > obj-$(CONFIG_SPI_NUC900)+= spi-nuc900.o > +obj-$(CONFIG_SPI_NXP_FLEXSPI)+= spi-nxp-fspi.o > obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o > spi-octeon-objs := spi-cavium.o > spi-cavium-octeon.o > obj-$(CONFIG_SPI_OCTEON)+= spi-octeon.o > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c > new file mode 100644 > index 000..e5188b2 > --- /dev/null > +++ b/drivers/spi/spi-nxp-fspi.c > @@ -0,0 +1,1158 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * NXP FlexSPI(FSPI) controller driver. > + * > + * Copyright 2018 NXP. > + * > + * FlexSPI is a flexsible SPI host controller which supports two SPI > + * channels and up to 4 external devices. Each channel supports > + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > + * data lines). > + * > + * FlexSPI controller is driven by the LUT(Look-up Table) registers > + * LUT registers are a look-up-table for sequences of instructions. > + * A valid sequence consists of four LUT registers. > + * Maximum 32 LUT sequences can be programmed simultaneously. > + * > + * LUTs are being created at run-time based on the commands passed > + * from the spi-mem framework, thus using single LUT index. > + * > + * Software triggered Flash read/write access by IP Bus. > + * > + * Memory mapped read access by AHB Bus. > + * > + * Based on SPI MEM interface and spi-fsl-qspi.c driver. > + * > + * Author: > + * Yogesh Gaur > + * Boris Brezillion > + * Frieder Schrempf > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include
Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Yogesh, I didn't have time to look at all of the code, but nevertheless here are some comments. On 23.10.18 10:56, Yogesh Narayan Gaur wrote: > - Add driver for NXP FlexSPI host controller > > (0) What is the FlexSPI controller? > FlexSPI is a flexsible SPI host controller which supports two SPI > channels and up to 4 external devices. Each channel supports > Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > data lines) i.e. FlexSPI acts as an interface to external devices, > maximum 4, each with up to 8 bidirectional data lines. > > It uses new SPI memory interface of the SPI framework to issue > flash memory operations to up to four connected flash > devices (2 buses with 2 CS each). > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility > on NXP LX2160ARDB and LX2160AQDS targets. > LX2160ARDB is having two NOR slave device connected on single bus A > i.e. A0 and A1 (CS0 and CS1). > LX2160AQDS is having two NOR slave device connected on separate buses > one flash on A0 and second on B1 i.e. (CS0 and CS3). > Verified this driver on following SPI NOR flashes: > Micron, mt35xu512ab, [Read - 1 bit mode] > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > Signed-off-by: Yogesh Gaur > --- > Changes for v4: > - Incorporate Boris review comments >* Use readl_poll_timeout() instead of busy looping. >* Re-define register masking as per comment. >* Drop fspi_devtype enum. > Changes for v3: > - Added endianness flag in platform specific structure instead of DTS. > - Modified nxp_fspi_read_ahb(), removed remapping code. > - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c > Changes for v2: > - Incorporated Boris review comments. > - Remove dependency of driver over connected flash device size. > - Modified the logic to select requested CS. > - Remove SPI-Octal Macros. > > drivers/spi/Kconfig| 10 + > drivers/spi/Makefile |1 + > drivers/spi/spi-nxp-fspi.c | 1158 > > 3 files changed, 1169 insertions(+) > create mode 100644 drivers/spi/spi-nxp-fspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index ad5d68e..68da874 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_NXP_FLEXSPI > + tristate "NXP Flex SPI controller" > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > + help > + This enables support for the Flex SPI controller in master mode. > + Up to four slave devices can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages and only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index cb1f437..52c9f18 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o > obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o > obj-$(CONFIG_SPI_MXS) += spi-mxs.o > obj-$(CONFIG_SPI_NUC900)+= spi-nuc900.o > +obj-$(CONFIG_SPI_NXP_FLEXSPI)+= spi-nxp-fspi.o > obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o > spi-octeon-objs := spi-cavium.o > spi-cavium-octeon.o > obj-$(CONFIG_SPI_OCTEON)+= spi-octeon.o > diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c > new file mode 100644 > index 000..e5188b2 > --- /dev/null > +++ b/drivers/spi/spi-nxp-fspi.c > @@ -0,0 +1,1158 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * NXP FlexSPI(FSPI) controller driver. > + * > + * Copyright 2018 NXP. > + * > + * FlexSPI is a flexsible SPI host controller which supports two SPI > + * channels and up to 4 external devices. Each channel supports > + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > + * data lines). > + * > + * FlexSPI controller is driven by the LUT(Look-up Table) registers > + * LUT registers are a look-up-table for sequences of instructions. > + * A valid sequence consists of four LUT registers. > + * Maximum 32 LUT sequences can be programmed simultaneously. > + * > + * LUTs are being created at run-time based on the commands passed > + * from the spi-mem framework, thus using single LUT index. > + * > + * Software triggered Flash read/write access by IP Bus. > + * > + * Memory mapped read access by AHB Bus. > + * > + * Based on SPI MEM interface and spi-fsl-qspi.c driver. > + * > + * Author: > + * Yogesh Gaur > + * Boris Brezillion > + * Frieder Schrempf > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include
RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:37 PM
> To: Yogesh Narayan Gaur
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com;
> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
> r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI
> controller
>
> On Tue, 23 Oct 2018 08:56:46 +
> Yogesh Narayan Gaur wrote:
>
> > +struct nxp_fspi {
> > + void __iomem *iobase;
> > + void __iomem *ahb_addr;
> > + u32 memmap_phy;
> > + u32 memmap_phy_size;
> > + struct clk *clk, *clk_en;
> > + struct device *dev;
> > + struct completion c;
> > + const struct nxp_fspi_devtype_data *devtype_data;
> > + struct mutex lock;
> > + struct pm_qos_request pm_qos_req;
> > + int selected;
> > + void (*write)(u32 val, void __iomem *addr);
> > + u32 (*read)(void __iomem *addr);
>
> I think I already commented on this aspect, and I keep thinking having a
> function
> pointer is overkill here.
> Just declare 2 functions and do the f->devtype_data->little_endian check in
> there:
>
> static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) {
> if (f->devtype_data->little_endian)
> return ioread32(addr);
>
> return ioread32be(addr);
> }
>
> static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) {
> if (f->devtype_data->little_endian)
> iowrite32(val, addr);
>
> iowrite32be(val, addr);
> }
This, I have kept same as being done in spi-fsl-qspi.c driver file as Frieder
have got the comment to remove the condition in read/write path and he has
introduced these hooks there.
Would remove in next version. Please review other changes and complete driver
file.
--
Regards
Yogesh Gaur
RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:37 PM
> To: Yogesh Narayan Gaur
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com;
> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
> r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI
> controller
>
> On Tue, 23 Oct 2018 08:56:46 +
> Yogesh Narayan Gaur wrote:
>
> > +struct nxp_fspi {
> > + void __iomem *iobase;
> > + void __iomem *ahb_addr;
> > + u32 memmap_phy;
> > + u32 memmap_phy_size;
> > + struct clk *clk, *clk_en;
> > + struct device *dev;
> > + struct completion c;
> > + const struct nxp_fspi_devtype_data *devtype_data;
> > + struct mutex lock;
> > + struct pm_qos_request pm_qos_req;
> > + int selected;
> > + void (*write)(u32 val, void __iomem *addr);
> > + u32 (*read)(void __iomem *addr);
>
> I think I already commented on this aspect, and I keep thinking having a
> function
> pointer is overkill here.
> Just declare 2 functions and do the f->devtype_data->little_endian check in
> there:
>
> static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) {
> if (f->devtype_data->little_endian)
> return ioread32(addr);
>
> return ioread32be(addr);
> }
>
> static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) {
> if (f->devtype_data->little_endian)
> iowrite32(val, addr);
>
> iowrite32be(val, addr);
> }
This, I have kept same as being done in spi-fsl-qspi.c driver file as Frieder
have got the comment to remove the condition in read/write path and he has
introduced these hooks there.
Would remove in next version. Please review other changes and complete driver
file.
--
Regards
Yogesh Gaur
Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
On Tue, 23 Oct 2018 08:56:46 +
Yogesh Narayan Gaur wrote:
> +struct nxp_fspi {
> + void __iomem *iobase;
> + void __iomem *ahb_addr;
> + u32 memmap_phy;
> + u32 memmap_phy_size;
> + struct clk *clk, *clk_en;
> + struct device *dev;
> + struct completion c;
> + const struct nxp_fspi_devtype_data *devtype_data;
> + struct mutex lock;
> + struct pm_qos_request pm_qos_req;
> + int selected;
> + void (*write)(u32 val, void __iomem *addr);
> + u32 (*read)(void __iomem *addr);
I think I already commented on this aspect, and I keep thinking having a
function pointer is overkill here.
Just declare 2 functions and do the f->devtype_data->little_endian
check in there:
static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
{
if (f->devtype_data->little_endian)
return ioread32(addr);
return ioread32be(addr);
}
static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
{
if (f->devtype_data->little_endian)
iowrite32(val, addr);
iowrite32be(val, addr);
}
Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
On Tue, 23 Oct 2018 08:56:46 +
Yogesh Narayan Gaur wrote:
> +struct nxp_fspi {
> + void __iomem *iobase;
> + void __iomem *ahb_addr;
> + u32 memmap_phy;
> + u32 memmap_phy_size;
> + struct clk *clk, *clk_en;
> + struct device *dev;
> + struct completion c;
> + const struct nxp_fspi_devtype_data *devtype_data;
> + struct mutex lock;
> + struct pm_qos_request pm_qos_req;
> + int selected;
> + void (*write)(u32 val, void __iomem *addr);
> + u32 (*read)(void __iomem *addr);
I think I already commented on this aspect, and I keep thinking having a
function pointer is overkill here.
Just declare 2 functions and do the f->devtype_data->little_endian
check in there:
static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
{
if (f->devtype_data->little_endian)
return ioread32(addr);
return ioread32be(addr);
}
static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
{
if (f->devtype_data->little_endian)
iowrite32(val, addr);
iowrite32be(val, addr);
}
[PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Gaur --- Changes for v4: - Incorporate Boris review comments * Use readl_poll_timeout() instead of busy looping. * Re-define register masking as per comment. * Drop fspi_devtype enum. Changes for v3: - Added endianness flag in platform specific structure instead of DTS. - Modified nxp_fspi_read_ahb(), removed remapping code. - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c Changes for v2: - Incorporated Boris review comments. - Remove dependency of driver over connected flash device size. - Modified the logic to select requested CS. - Remove SPI-Octal Macros. drivers/spi/Kconfig| 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c | 1158 3 files changed, 1169 insertions(+) create mode 100644 drivers/spi/spi-nxp-fspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ad5d68e..68da874 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI help This enables Freescale i.MX LPSPI controllers in master mode. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_LAYERSCAPE || HAS_IOMEM + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + config SPI_GPIO tristate "GPIO-based bitbanging SPI Master" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..52c9f18 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs:= spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index 000..e5188b2 --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1158 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2018 NXP. + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registers + * LUT registers are a look-up-table for sequences of instructions. + * A valid sequence consists of four LUT registers. + * Maximum 32 LUT sequences can be programmed simultaneously. + * + * LUTs are being created at run-time based on the commands passed + * from the spi-mem framework, thus using single LUT index. + * + * Software triggered Flash read/write access by IP Bus. + * + * Memory mapped read access by AHB Bus. + * + * Based on SPI MEM interface and spi-fsl-qspi.c driver. + * + * Author: + * Yogesh Gaur + * Boris Brezillion + * Frieder Schrempf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (31). + */ +#defineSEQID_LUT
[PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Gaur --- Changes for v4: - Incorporate Boris review comments * Use readl_poll_timeout() instead of busy looping. * Re-define register masking as per comment. * Drop fspi_devtype enum. Changes for v3: - Added endianness flag in platform specific structure instead of DTS. - Modified nxp_fspi_read_ahb(), removed remapping code. - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c Changes for v2: - Incorporated Boris review comments. - Remove dependency of driver over connected flash device size. - Modified the logic to select requested CS. - Remove SPI-Octal Macros. drivers/spi/Kconfig| 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c | 1158 3 files changed, 1169 insertions(+) create mode 100644 drivers/spi/spi-nxp-fspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ad5d68e..68da874 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI help This enables Freescale i.MX LPSPI controllers in master mode. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_LAYERSCAPE || HAS_IOMEM + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + config SPI_GPIO tristate "GPIO-based bitbanging SPI Master" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..52c9f18 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs:= spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index 000..e5188b2 --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1158 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2018 NXP. + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registers + * LUT registers are a look-up-table for sequences of instructions. + * A valid sequence consists of four LUT registers. + * Maximum 32 LUT sequences can be programmed simultaneously. + * + * LUTs are being created at run-time based on the commands passed + * from the spi-mem framework, thus using single LUT index. + * + * Software triggered Flash read/write access by IP Bus. + * + * Memory mapped read access by AHB Bus. + * + * Based on SPI MEM interface and spi-fsl-qspi.c driver. + * + * Author: + * Yogesh Gaur + * Boris Brezillion + * Frieder Schrempf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (31). + */ +#defineSEQID_LUT
