Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Maxime Coquelin]

2016-09-21 9:50 GMT+02:00 Thomas Gleixner :
> On Wed, 21 Sep 2016, Alexandre Torgue wrote:
>
>> Hi Thomas,
>>
>> On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
>> > Alexandre,
>> >
>> > On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
>> >
>> > > The STM32 external interrupt controller consists of edge detectors that
>> > > generate interrupts requests or wake-up events.
>> > >
>> > > Each line can be independently configured as interrupt or wake-up source,
>> > > and triggers either on rising, falling or both edges. Each line can also
>> > > be masked independently.
>> > >
>> > > Signed-off-by: Maxime Coquelin 
>> > > Signed-off-by: Alexandre TORGUE 
>> >
>> > That all looks very reasonable now. The only remaining question is your SOB
>> > chain. Who is the author of these patches? You or Maxime? If it's Maxime,
>> > then the changelog misses a From: tag. If it's you then Maximes SOB is
>> > bogus.
>>
>> Actually Maxime wrote the main part of this driver and sent version 1 and 2 
>> of
>> the series. After Linus W. reviews, rework was required to use hierarchical
>> domain. According to Maxime, I coded the rework (adaptation to hierarchical
>> domain) and sent other version of the series.
>
> So I replace Maximes SOB with Originally-by: Does that apply to all four
> patches?
Yes, that's fine.
Alex did a lot of rework on this series, he deserves the SoB.

Thanks,
Maxime

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Maxime Coquelin]

2016-09-21 9:50 GMT+02:00 Thomas Gleixner :
> On Wed, 21 Sep 2016, Alexandre Torgue wrote:
>
>> Hi Thomas,
>>
>> On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
>> > Alexandre,
>> >
>> > On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
>> >
>> > > The STM32 external interrupt controller consists of edge detectors that
>> > > generate interrupts requests or wake-up events.
>> > >
>> > > Each line can be independently configured as interrupt or wake-up source,
>> > > and triggers either on rising, falling or both edges. Each line can also
>> > > be masked independently.
>> > >
>> > > Signed-off-by: Maxime Coquelin 
>> > > Signed-off-by: Alexandre TORGUE 
>> >
>> > That all looks very reasonable now. The only remaining question is your SOB
>> > chain. Who is the author of these patches? You or Maxime? If it's Maxime,
>> > then the changelog misses a From: tag. If it's you then Maximes SOB is
>> > bogus.
>>
>> Actually Maxime wrote the main part of this driver and sent version 1 and 2 
>> of
>> the series. After Linus W. reviews, rework was required to use hierarchical
>> domain. According to Maxime, I coded the rework (adaptation to hierarchical
>> domain) and sent other version of the series.
>
> So I replace Maximes SOB with Originally-by: Does that apply to all four
> patches?
Yes, that's fine.
Alex did a lot of rework on this series, he deserves the SoB.

Thanks,
Maxime

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Wed, 21 Sep 2016, Alexandre Torgue wrote:

> Hi Thomas,
> 
> On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
> > Alexandre,
> > 
> > On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
> > 
> > > The STM32 external interrupt controller consists of edge detectors that
> > > generate interrupts requests or wake-up events.
> > > 
> > > Each line can be independently configured as interrupt or wake-up source,
> > > and triggers either on rising, falling or both edges. Each line can also
> > > be masked independently.
> > > 
> > > Signed-off-by: Maxime Coquelin 
> > > Signed-off-by: Alexandre TORGUE 
> > 
> > That all looks very reasonable now. The only remaining question is your SOB
> > chain. Who is the author of these patches? You or Maxime? If it's Maxime,
> > then the changelog misses a From: tag. If it's you then Maximes SOB is
> > bogus.
> 
> Actually Maxime wrote the main part of this driver and sent version 1 and 2 of
> the series. After Linus W. reviews, rework was required to use hierarchical
> domain. According to Maxime, I coded the rework (adaptation to hierarchical
> domain) and sent other version of the series.

So I replace Maximes SOB with Originally-by: Does that apply to all four
patches?

Thanks,

tglx

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

On Wed, 21 Sep 2016, Alexandre Torgue wrote:

> Hi Thomas,
> 
> On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
> > Alexandre,
> > 
> > On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
> > 
> > > The STM32 external interrupt controller consists of edge detectors that
> > > generate interrupts requests or wake-up events.
> > > 
> > > Each line can be independently configured as interrupt or wake-up source,
> > > and triggers either on rising, falling or both edges. Each line can also
> > > be masked independently.
> > > 
> > > Signed-off-by: Maxime Coquelin 
> > > Signed-off-by: Alexandre TORGUE 
> > 
> > That all looks very reasonable now. The only remaining question is your SOB
> > chain. Who is the author of these patches? You or Maxime? If it's Maxime,
> > then the changelog misses a From: tag. If it's you then Maximes SOB is
> > bogus.
> 
> Actually Maxime wrote the main part of this driver and sent version 1 and 2 of
> the series. After Linus W. reviews, rework was required to use hierarchical
> domain. According to Maxime, I coded the rework (adaptation to hierarchical
> domain) and sent other version of the series.

So I replace Maximes SOB with Originally-by: Does that apply to all four
patches?

Thanks,

tglx

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/20/2016 10:16 PM, Thomas Gleixner wrote:

Alexandre,

On Tue, 20 Sep 2016, Alexandre TORGUE wrote:


The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin 
Signed-off-by: Alexandre TORGUE 


That all looks very reasonable now. The only remaining question is your SOB
chain. Who is the author of these patches? You or Maxime? If it's Maxime,
then the changelog misses a From: tag. If it's you then Maximes SOB is
bogus.


Actually Maxime wrote the main part of this driver and sent version 1 
and 2 of the series. After Linus W. reviews, rework was required to use 
hierarchical domain. According to Maxime, I coded the rework (adaptation 
to hierarchical domain) and sent other version of the series.


Regards

Alex



Thanks,

tglx

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Alexandre Torgue]

Hi Thomas,

On 09/20/2016 10:16 PM, Thomas Gleixner wrote:

Alexandre,

On Tue, 20 Sep 2016, Alexandre TORGUE wrote:


The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin 
Signed-off-by: Alexandre TORGUE 


That all looks very reasonable now. The only remaining question is your SOB
chain. Who is the author of these patches? You or Maxime? If it's Maxime,
then the changelog misses a From: tag. If it's you then Maximes SOB is
bogus.


Actually Maxime wrote the main part of this driver and sent version 1 
and 2 of the series. After Linus W. reviews, rework was required to use 
hierarchical domain. According to Maxime, I coded the rework (adaptation 
to hierarchical domain) and sent other version of the series.


Regards

Alex



Thanks,

tglx

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

Alexandre,

On Tue, 20 Sep 2016, Alexandre TORGUE wrote:

> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
> 
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
> 
> Signed-off-by: Maxime Coquelin 
> Signed-off-by: Alexandre TORGUE 

That all looks very reasonable now. The only remaining question is your SOB
chain. Who is the author of these patches? You or Maxime? If it's Maxime,
then the changelog misses a From: tag. If it's you then Maximes SOB is
bogus.

Thanks,

tglx

Re: [PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Thomas Gleixner]

Alexandre,

On Tue, 20 Sep 2016, Alexandre TORGUE wrote:

> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
> 
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
> 
> Signed-off-by: Maxime Coquelin 
> Signed-off-by: Alexandre TORGUE 

That all looks very reasonable now. The only remaining question is your SOB
chain. Who is the author of these patches? You or Maxime? If it's Maxime,
then the changelog misses a From: tag. If it's you then Maximes SOB is
bogus.

Thanks,

tglx

[PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Alexandre TORGUE]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin 
Signed-off-by: Alexandre TORGUE 

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
  Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+   bool
+   select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)  += irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)  += irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)  += irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..491568c
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin 
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EXTI_IMR   0x0
+#define EXTI_EMR   0x4
+#define EXTI_RTSR  0x8
+#define EXTI_FTSR  0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+   struct irq_domain *domain = irq_desc_get_handler_data(desc);
+   struct irq_chip_generic *gc = domain->gc->gc[0];
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   unsigned long pending;
+   int n;
+
+   chained_irq_enter(chip, desc);
+
+   while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+   for_each_set_bit(n, , BITS_PER_LONG) {
+   generic_handle_irq(irq_find_mapping(domain, n));
+   irq_reg_writel(gc, BIT(n), EXTI_PR);
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   int pin = data->hwirq;
+   u32 rtsr, ftsr;
+
+   irq_gc_lock(gc);
+
+   rtsr = irq_reg_readl(gc, EXTI_RTSR);
+   ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+   switch (type) {
+   case IRQ_TYPE_EDGE_RISING:
+   rtsr |= BIT(pin);
+   ftsr &= ~BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_FALLING:
+   rtsr &= ~BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_BOTH:
+   rtsr |= BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   default:
+   irq_gc_unlock(gc);
+   return -EINVAL;
+   }
+
+   irq_reg_writel(gc, rtsr, EXTI_RTSR);
+   irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   int pin = data->hwirq;
+   u32 emr;
+
+   irq_gc_lock(gc);
+
+   emr = irq_reg_readl(gc, EXTI_EMR);
+   if (on)
+   emr |= BIT(pin);
+   else
+   emr &= ~BIT(pin);
+   irq_reg_writel(gc, emr, EXTI_EMR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+   unsigned int nr_irqs, void *data)
+{
+   struct irq_chip_generic *gc = d->gc->gc[0];
+   struct irq_fwspec *fwspec = data;
+   irq_hw_number_t hwirq;
+
+   hwirq = fwspec->param[0];
+
+   irq_map_generic_chip(d, virq, hwirq);
+   irq_domain_set_info(d, virq, hwirq, >chip_types->chip, gc,
+   handle_simple_irq, NULL, NULL);
+
+   return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+   unsigned int nr_irqs)
+{
+   struct irq_data *data = irq_domain_get_irq_data(d, virq);
+
+   irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+   .map= irq_map_generic_chip,
+   .xlate  = irq_domain_xlate_onetwocell,
+   .alloc  = stm32_exti_alloc,
+   .free   = stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+ 

[PATCH v6 2/4] drivers: irqchip: Add STM32 external interrupts support

[Alexandre TORGUE]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin 
Signed-off-by: Alexandre TORGUE 

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
  Support the EZchip NPS400 global interrupt controller
+
+config STM32_EXTI
+   bool
+   select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 4c203b6..96383b2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)  += irq-mvebu-odmi.o
 obj-$(CONFIG_LS_SCFG_MSI)  += irq-ls-scfg-msi.o
 obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)  += irq-aspeed-vic.o
+obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..491568c
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin 
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EXTI_IMR   0x0
+#define EXTI_EMR   0x4
+#define EXTI_RTSR  0x8
+#define EXTI_FTSR  0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+   struct irq_domain *domain = irq_desc_get_handler_data(desc);
+   struct irq_chip_generic *gc = domain->gc->gc[0];
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   unsigned long pending;
+   int n;
+
+   chained_irq_enter(chip, desc);
+
+   while ((pending = irq_reg_readl(gc, EXTI_PR))) {
+   for_each_set_bit(n, , BITS_PER_LONG) {
+   generic_handle_irq(irq_find_mapping(domain, n));
+   irq_reg_writel(gc, BIT(n), EXTI_PR);
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   int pin = data->hwirq;
+   u32 rtsr, ftsr;
+
+   irq_gc_lock(gc);
+
+   rtsr = irq_reg_readl(gc, EXTI_RTSR);
+   ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+   switch (type) {
+   case IRQ_TYPE_EDGE_RISING:
+   rtsr |= BIT(pin);
+   ftsr &= ~BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_FALLING:
+   rtsr &= ~BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_BOTH:
+   rtsr |= BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   default:
+   irq_gc_unlock(gc);
+   return -EINVAL;
+   }
+
+   irq_reg_writel(gc, rtsr, EXTI_RTSR);
+   irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   int pin = data->hwirq;
+   u32 emr;
+
+   irq_gc_lock(gc);
+
+   emr = irq_reg_readl(gc, EXTI_EMR);
+   if (on)
+   emr |= BIT(pin);
+   else
+   emr &= ~BIT(pin);
+   irq_reg_writel(gc, emr, EXTI_EMR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
+   unsigned int nr_irqs, void *data)
+{
+   struct irq_chip_generic *gc = d->gc->gc[0];
+   struct irq_fwspec *fwspec = data;
+   irq_hw_number_t hwirq;
+
+   hwirq = fwspec->param[0];
+
+   irq_map_generic_chip(d, virq, hwirq);
+   irq_domain_set_info(d, virq, hwirq, >chip_types->chip, gc,
+   handle_simple_irq, NULL, NULL);
+
+   return 0;
+}
+
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+   unsigned int nr_irqs)
+{
+   struct irq_data *data = irq_domain_get_irq_data(d, virq);
+
+   irq_domain_reset_irq_data(data);
+}
+
+struct irq_domain_ops irq_exti_domain_ops = {
+   .map= irq_map_generic_chip,
+   .xlate  = irq_domain_xlate_onetwocell,
+   .alloc  = stm32_exti_alloc,
+   .free   = stm32_exti_free,
+};
+
+static int __init stm32_exti_init(struct device_node *node,
+ struct device_node *parent)
+{
+   unsigned int clr = IRQ_NOREQUEST |