This patch adds support for MPC8308RDB development board from
Freescale.
Supported devices:
DUART
Dual Ethernet
NOR and NAND flashes
I2C
USB in peripheral mode
PCIE support is broken by the commit 3da34aa ("powerpc/fsl: Support
unique MSI addresses per PCIe Root Complex"). Works after revert.
Signed-off-by: Ilya Yanok
---
arch/powerpc/boot/dts/mpc8308rdb.dts | 303 +
arch/powerpc/platforms/83xx/Kconfig |8 +
arch/powerpc/platforms/83xx/Makefile |1 +
arch/powerpc/platforms/83xx/mpc830x_rdb.c | 94 +
4 files changed, 406 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8308rdb.dts
create mode 100644 arch/powerpc/platforms/83xx/mpc830x_rdb.c
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts
b/arch/powerpc/boot/dts/mpc8308rdb.dts
new file mode 100644
index 000..a97eb2d
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -0,0 +1,303 @@
+/*
+ * MPC8308RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, ya...@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "fsl,mpc8308rdb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8...@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>;// from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x 0x0800>; // 128MB at 0
+ };
+
+ local...@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+
+ // CS0 and CS1 are swapped when
+ // booting from nand, but the
+ // addresses are the same.
+ ranges = <0x0 0x0 0xfe00 0x0080
+ 0x1 0x0 0xe060 0x2000
+ 0x2 0x0 0xf000 0x0002
+ 0x3 0x0 0xfa00 0x8000>;
+
+ fl...@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x80>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-b...@0 {
+ reg = <0x0 0x6>;
+ read-only;
+ };
+ e...@6 {
+ reg = <0x6 0x1>;
+ };
+ e...@7 {
+ reg = <0x7 0x1>;
+ };
+ ker...@8 {
+ reg = <0x8 0x20>;
+ };
+ d...@28 {
+ reg = <0x28 0x1>;
+ };
+ ramd...@29 {
+ reg = <0x29 0x57>;
+ };
+ };
+
+ n...@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-fcm-nand",
+"fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x2000>;
+
+ jf...@0 {
+ reg = <0x0 0x200>;
+ };
+ };
+ };
+
+ i...@e000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8315-immr", "simple-bus";
+ ranges = <0 0xe000 0x0010>;
+ reg = <0xe000 0x0200>;
+
