Mesa (master): vc4: When asked to sample from a raster texture, make a shadow tiled copy.
Module: Mesa
Branch: master
Commit: 44b63cf5c051f7eccfc1d7427247fd58dabb7761
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44b63cf5c051f7eccfc1d7427247fd58dabb7761
Author: Eric Anholt
Date: Wed Apr 8 12:49:24 2015 -0700
vc4: When asked to sample from a raster texture, make a shadow tiled copy.
So, it turns out my simulator doesn't *quite* match the hardware. And the
errata about raster textures tells you most of what's wrong, but there's
still stuff wrong after that. Instead, if we're asked to sample from
raster, we'll just blit it to a tiled temporary.
Raster textures should only be screen scanout, and word is that it's
faster to copy to tiled using the tiling engine first than to texture from
an entire raster texture, anyway.
---
src/gallium/drivers/vc4/vc4_state.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_state.c
b/src/gallium/drivers/vc4/vc4_state.c
index 332f310..df75b6e 100644
--- a/src/gallium/drivers/vc4/vc4_state.c
+++ b/src/gallium/drivers/vc4/vc4_state.c
@@ -516,6 +516,7 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct
pipe_resource *prsc,
const struct pipe_sampler_view *cso)
{
struct pipe_sampler_view *so = malloc(sizeof(*so));
+struct vc4_resource *rsc = vc4_resource(prsc);
if (!so)
return NULL;
@@ -527,8 +528,12 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct
pipe_resource *prsc,
/* There is no hardware level clamping, and the start address of a
* texture may be misaligned, so in that case we have to copy to a
* temporary.
+ *
+ * Also, Raspberry Pi doesn't support sampling from raster textures,
+ * so we also have to copy to a temporary then.
*/
-if (so->u.tex.first_level) {
+if (so->u.tex.first_level ||
+rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) {
struct vc4_resource *shadow_parent = vc4_resource(prsc);
struct pipe_resource tmpl = shadow_parent->base.b;
struct vc4_resource *clone;
@@ -574,8 +579,10 @@ vc4_set_sampler_views(struct pipe_context *pctx, unsigned
shader,
for (i = 0; i < nr; i++) {
if (views[i]) {
+struct vc4_resource *rsc =
+vc4_resource(views[i]->texture);
new_nr = i + 1;
-if (views[i]->u.tex.first_level != 0)
+if (rsc->shadow_parent)
vc4_update_shadow_baselevel_texture(pctx,
views[i]);
}
pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
___
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Mesa (master): vc4: Add a blitter path using just the render thread.
Module: Mesa
Branch: master
Commit: 1be329e64cd035e3ee088cff3a50d39e1ad66868
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1be329e64cd035e3ee088cff3a50d39e1ad66868
Author: Eric Anholt
Date: Mon Apr 6 15:12:58 2015 -0700
vc4: Add a blitter path using just the render thread.
This accelerates the path for generating the shadow tiled texture when
asked to sample from a raster texture (typical in glamor).
---
src/gallium/drivers/vc4/vc4_blit.c | 127
1 file changed, 127 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_blit.c
b/src/gallium/drivers/vc4/vc4_blit.c
index 5c98fb6..4f87189 100644
--- a/src/gallium/drivers/vc4/vc4_blit.c
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -26,6 +26,130 @@
#include "util/u_blitter.h"
#include "vc4_context.h"
+static void
+vc4_tile_blit_color_rcl(struct vc4_context *vc4,
+struct vc4_surface *dst_surf,
+struct vc4_surface *src_surf)
+{
+struct vc4_resource *src = vc4_resource(src_surf->base.texture);
+struct vc4_resource *dst = vc4_resource(dst_surf->base.texture);
+
+uint32_t min_x_tile = 0;
+uint32_t min_y_tile = 0;
+uint32_t max_x_tile = (dst_surf->base.width - 1) / 64;
+uint32_t max_y_tile = (dst_surf->base.height - 1) / 64;
+uint32_t xtiles = max_x_tile - min_x_tile + 1;
+uint32_t ytiles = max_y_tile - min_y_tile + 1;
+uint32_t reloc_size = 9;
+uint32_t config_size = 11 + reloc_size;
+uint32_t loadstore_size = 7 + reloc_size;
+uint32_t tilecoords_size = 3;
+cl_ensure_space(&vc4->rcl,
+config_size +
+xtiles * ytiles * (loadstore_size * 2 +
+ tilecoords_size * 1));
+cl_ensure_space(&vc4->bo_handles, 2 * sizeof(uint32_t));
+cl_ensure_space(&vc4->bo_pointers, 2 * sizeof(struct vc4_bo *));
+
+cl_start_reloc(&vc4->rcl, 1);
+cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
+cl_reloc(vc4, &vc4->rcl, dst->bo, dst_surf->offset);
+cl_u16(&vc4->rcl, dst_surf->base.width);
+cl_u16(&vc4->rcl, dst_surf->base.height);
+cl_u16(&vc4->rcl, ((dst_surf->tiling <<
+VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
+ (vc4_rt_format_is_565(dst_surf->base.format) ?
+VC4_RENDER_CONFIG_FORMAT_BGR565 :
+VC4_RENDER_CONFIG_FORMAT_RGBA)));
+
+uint32_t src_hindex = vc4_gem_hindex(vc4, src->bo);
+
+for (int y = min_y_tile; y <= max_y_tile; y++) {
+for (int x = min_x_tile; x <= max_x_tile; x++) {
+bool end_of_frame = (x == max_x_tile &&
+ y == max_y_tile);
+
+cl_start_reloc(&vc4->rcl, 1);
+cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
+cl_u8(&vc4->rcl,
+ VC4_LOADSTORE_TILE_BUFFER_COLOR |
+ (src_surf->tiling <<
+ VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
+cl_u8(&vc4->rcl,
+ vc4_rt_format_is_565(src_surf->base.format) ?
+ VC4_LOADSTORE_TILE_BUFFER_BGR565 :
+ VC4_LOADSTORE_TILE_BUFFER_RGBA);
+cl_reloc_hindex(&vc4->rcl, src_hindex,
+src_surf->offset);
+
+cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
+cl_u8(&vc4->rcl, x);
+cl_u8(&vc4->rcl, y);
+
+if (end_of_frame) {
+cl_u8(&vc4->rcl,
+ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
+} else {
+cl_u8(&vc4->rcl,
+ VC4_PACKET_STORE_MS_TILE_BUFFER);
+}
+}
+}
+
+vc4->draw_min_x = 0;
+vc4->draw_min_y = 0;
+vc4->draw_max_x = dst_surf->base.width;
+vc4->draw_max_y = dst_surf->base.height;
+
+dst->writes++;
+vc4->needs_flush = true;
+}
+
+static struct vc4_surface *
+vc4_get_blit_surface(struct pipe_context *pctx,
+ struct pipe_resource *prsc, unsigned level)
+{
+struct pipe_surface tmpl;
+
+memset(&tmpl, 0, sizeof(tmpl));
+tmpl.format = prsc->format;
+tmpl.u.tex.level = level;
+tmpl.u.tex.first_layer = 0;
+tmpl.u.tex.last_layer = 0;
+
+return vc4_surface(pctx->create_surface(pctx, prsc, &tmpl));
+}
+
+static bool
+vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
+{
+struct vc4_context *vc4 = vc4_co
Mesa (master): vc4: Allow submitting jobs with no bin CL in validation.
Module: Mesa
Branch: master
Commit: 76d56752ccff5bca3a0808705d5da76f186afb33
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76d56752ccff5bca3a0808705d5da76f186afb33
Author: Eric Anholt
Date: Thu Apr 9 13:35:57 2015 -0700
vc4: Allow submitting jobs with no bin CL in validation.
For blitting, we want to fire off an RCL-only job. This takes a bit of
tweaking in our validation and the simulator support (and corresponding
new code in the kernel).
---
src/gallium/drivers/vc4/kernel/vc4_drv.h |1 +
src/gallium/drivers/vc4/kernel/vc4_gem.c |2 ++
src/gallium/drivers/vc4/kernel/vc4_validate.c |9 ++---
src/gallium/drivers/vc4/vc4_simulator.c | 18 ++
4 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/vc4/kernel/vc4_drv.h
b/src/gallium/drivers/vc4/kernel/vc4_drv.h
index 12a3cef..325f944 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_drv.h
+++ b/src/gallium/drivers/vc4/kernel/vc4_drv.h
@@ -162,6 +162,7 @@ vc4_validate_cl(struct drm_device *dev,
void *unvalidated,
uint32_t len,
bool is_bin,
+bool has_bin,
struct vc4_exec_info *exec);
int
diff --git a/src/gallium/drivers/vc4/kernel/vc4_gem.c
b/src/gallium/drivers/vc4/kernel/vc4_gem.c
index c9a7573..ac29ab3 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_gem.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_gem.c
@@ -130,6 +130,7 @@ vc4_cl_validate(struct drm_device *dev, struct
vc4_exec_info *exec)
bin,
args->bin_cl_size,
true,
+ args->bin_cl_size != 0,
exec);
if (ret)
goto fail;
@@ -139,6 +140,7 @@ vc4_cl_validate(struct drm_device *dev, struct
vc4_exec_info *exec)
render,
args->render_cl_size,
false,
+ args->bin_cl_size != 0,
exec);
if (ret)
goto fail;
diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c
b/src/gallium/drivers/vc4/kernel/vc4_validate.c
index aeac29e..2d04a4a 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_validate.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c
@@ -702,6 +702,7 @@ vc4_validate_cl(struct drm_device *dev,
void *unvalidated,
uint32_t len,
bool is_bin,
+ bool has_bin,
struct vc4_exec_info *exec)
{
uint32_t dst_offset = 0;
@@ -772,7 +773,7 @@ vc4_validate_cl(struct drm_device *dev,
if (is_bin) {
exec->ct0ea = exec->ct0ca + dst_offset;
- if (!exec->found_start_tile_binning_packet) {
+ if (has_bin && !exec->found_start_tile_binning_packet) {
DRM_ERROR("Bin CL missing
VC4_PACKET_START_TILE_BINNING\n");
return -EINVAL;
}
@@ -786,8 +787,10 @@ vc4_validate_cl(struct drm_device *dev,
* increment from the bin CL. Otherwise a later submit would
* have render execute immediately.
*/
- if (!exec->found_wait_on_semaphore_packet) {
- DRM_ERROR("Render CL missing
VC4_PACKET_WAIT_ON_SEMAPHORE\n");
+ if (exec->found_wait_on_semaphore_packet != has_bin) {
+ DRM_ERROR("Render CL %s VC4_PACKET_WAIT_ON_SEMAPHORE\n",
+ exec->found_wait_on_semaphore_packet ?
+ "has" : "missing");
return -EINVAL;
}
exec->ct1ea = exec->ct1ca + dst_offset;
diff --git a/src/gallium/drivers/vc4/vc4_simulator.c
b/src/gallium/drivers/vc4/vc4_simulator.c
index cd8cc5b..2f72e72 100644
--- a/src/gallium/drivers/vc4/vc4_simulator.c
+++ b/src/gallium/drivers/vc4/vc4_simulator.c
@@ -151,14 +151,16 @@ vc4_simulator_flush(struct vc4_context *vc4, struct
drm_vc4_submit_cl *args)
if (ret)
return ret;
-int bfc = simpenrose_do_binning(exec.ct0ca, exec.ct0ea);
-if (bfc != 1) {
-fprintf(stderr, "Binning returned %d flushes, should be 1.\n",
-bfc);
-fprintf(stderr, "Relocated binning command list:\n");
-vc4_dump_cl(screen->simulator_mem_base + exec.ct0ca,
-exec.ct0ea - exec.ct0ca, false);
-abort();
+if (exec.ct0ca != exec.ct0ea) {
+int bfc = simpenrose_do_binning(exec.ct0ca, exec.ct0ea);
+if (bfc != 1) {
+fprintf(stderr, "Binning returned %d flushes, should
be 1.\n",
+bfc);
+fprintf(stderr, "Relocated binning command list:\n");
+
Mesa (master): vc4: Add a bunch of type conversions.
Module: Mesa Branch: master Commit: 84ebaff1b7f78cb47cd8eed5476f03c5c3d0e14b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84ebaff1b7f78cb47cd8eed5476f03c5c3d0e14b Author: Eric Anholt Date: Wed Apr 1 15:35:13 2015 -0700 vc4: Add a bunch of type conversions. These are required to get piglit's idiv tests working. The unsigned<->float conversions are wrong, but are good enough to get piglit's small ranges of values working. --- src/gallium/drivers/vc4/vc4_program.c | 12 1 file changed, 12 insertions(+) diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index bcceb3c..ca2e81c 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -925,15 +925,27 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) case nir_op_fmax: *dest = qir_FMAX(c, src[0], src[1]); break; + case nir_op_f2i: +case nir_op_f2u: *dest = qir_FTOI(c, src[0]); break; case nir_op_i2f: +case nir_op_u2f: *dest = qir_ITOF(c, src[0]); break; case nir_op_b2f: *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0)); break; +case nir_op_b2i: +*dest = qir_AND(c, src[0], qir_uniform_ui(c, 1)); +break; +case nir_op_i2b: +case nir_op_f2b: +qir_SF(c, src[0]); +*dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0)); +break; + case nir_op_iadd: *dest = qir_ADD(c, src[0], src[1]); break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vc4: Separate out a bit of code for submitting jobs to the kernel.
Module: Mesa
Branch: master
Commit: e214a596352e67c89ce379a1e5a060dbc1ce31e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e214a596352e67c89ce379a1e5a060dbc1ce31e1
Author: Eric Anholt
Date: Mon Apr 6 12:58:51 2015 -0700
vc4: Separate out a bit of code for submitting jobs to the kernel.
I want to be able to have multiple jobs being set up at the same time (for
example, a render job to do a little fixup blit in the course of doing a
render to the main FBO).
---
src/gallium/drivers/vc4/Makefile.sources |1 +
src/gallium/drivers/vc4/vc4_context.c| 93 +
src/gallium/drivers/vc4/vc4_context.h|3 +
src/gallium/drivers/vc4/vc4_job.c| 132 ++
4 files changed, 139 insertions(+), 90 deletions(-)
diff --git a/src/gallium/drivers/vc4/Makefile.sources
b/src/gallium/drivers/vc4/Makefile.sources
index ec0f25c..62cd0e0 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -11,6 +11,7 @@ C_SOURCES := \
vc4_emit.c \
vc4_fence.c \
vc4_formats.c \
+ vc4_job.c \
vc4_opt_algebraic.c \
vc4_opt_constant_folding.c \
vc4_opt_copy_propagation.c \
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index daa5ba5..b394c18 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -296,40 +296,6 @@ vc4_setup_rcl(struct vc4_context *vc4)
ztex->writes++;
}
-static void
-vc4_draw_reset(struct vc4_context *vc4)
-{
-struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
-for (int i = 0; i < (vc4->bo_handles.next -
- vc4->bo_handles.base) / 4; i++) {
-vc4_bo_unreference(&referenced_bos[i]);
-}
-vc4_reset_cl(&vc4->bcl);
-vc4_reset_cl(&vc4->rcl);
-vc4_reset_cl(&vc4->shader_rec);
-vc4_reset_cl(&vc4->uniforms);
-vc4_reset_cl(&vc4->bo_handles);
-vc4_reset_cl(&vc4->bo_pointers);
-vc4->shader_rec_count = 0;
-
-vc4->needs_flush = false;
-vc4->draw_call_queued = false;
-
-/* We have no hardware context saved between our draw calls, so we
- * need to flag the next draw as needing all state emitted. Emitting
- * all state at the start of our draws is also what ensures that we
- * return to the state we need after a previous tile has finished.
- */
-vc4->dirty = ~0;
-vc4->resolve = 0;
-vc4->cleared = 0;
-
-vc4->draw_min_x = ~0;
-vc4->draw_min_y = ~0;
-vc4->draw_max_x = 0;
-vc4->draw_max_y = 0;
-}
-
void
vc4_flush(struct pipe_context *pctx)
{
@@ -343,7 +309,7 @@ vc4_flush(struct pipe_context *pctx)
*/
if (vc4->draw_max_x <= vc4->draw_min_x ||
vc4->draw_max_y <= vc4->draw_min_y) {
-vc4_draw_reset(vc4);
+vc4_job_reset(vc4);
return;
}
@@ -358,54 +324,7 @@ vc4_flush(struct pipe_context *pctx)
vc4_setup_rcl(vc4);
-if (vc4_debug & VC4_DEBUG_CL) {
-fprintf(stderr, "BCL:\n");
-vc4_dump_cl(vc4->bcl.base, vc4->bcl.next - vc4->bcl.base,
false);
-fprintf(stderr, "RCL:\n");
-vc4_dump_cl(vc4->rcl.base, vc4->rcl.next - vc4->rcl.base,
true);
-}
-
-struct drm_vc4_submit_cl submit;
-memset(&submit, 0, sizeof(submit));
-
-submit.bo_handles = (uintptr_t)vc4->bo_handles.base;
-submit.bo_handle_count = (vc4->bo_handles.next -
- vc4->bo_handles.base) / 4;
-submit.bin_cl = (uintptr_t)vc4->bcl.base;
-submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
-submit.render_cl = (uintptr_t)vc4->rcl.base;
-submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
-submit.shader_rec = (uintptr_t)vc4->shader_rec.base;
-submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
-submit.shader_rec_count = vc4->shader_rec_count;
-submit.uniforms = (uintptr_t)vc4->uniforms.base;
-submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
-
-if (!(vc4_debug & VC4_DEBUG_NORAST)) {
-int ret;
-
-#ifndef USE_VC4_SIMULATOR
-ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
-#else
-ret = vc4_simulator_flush(vc4, &submit);
-#endif
-if (ret) {
-fprintf(stderr, "VC4 submit failed\n");
-abort();
-}
-}
-
-vc4->last_emit_seqno = submit.seqno;
-
-if (vc4_debug & VC4_DEBUG_ALWAYS_SYNC) {
-if (!vc4_wait_seqno(vc4->screen, vc4->last_emit_seqno,
-PIPE_TIMEOUT_INFINITE)) {
-fprintf(stderr, "Wait failed.\n");
-
Mesa (master): vc4: Use NIR-level lowering for idiv.
Module: Mesa
Branch: master
Commit: 7fa2f2e36660afe9f50f652baa6d65903d3a9dea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fa2f2e36660afe9f50f652baa6d65903d3a9dea
Author: Eric Anholt
Date: Mon Apr 13 14:12:59 2015 -0700
vc4: Use NIR-level lowering for idiv.
This fixes the idiv tests in piglit.
---
src/gallium/drivers/vc4/vc4_program.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_program.c
b/src/gallium/drivers/vc4/vc4_program.c
index ca2e81c..ec649c9 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -311,14 +311,6 @@ ntq_umul(struct vc4_compile *c, struct qreg src0, struct
qreg src1)
qir_uniform_ui(c, 24)));
}
-static struct qreg
-ntq_idiv(struct vc4_compile *c, struct qreg src0, struct qreg src1)
-{
-return qir_FTOI(c, qir_FMUL(c,
-qir_ITOF(c, src0),
-qir_RCP(c, qir_ITOF(c, src1;
-}
-
static void
ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
{
@@ -983,9 +975,6 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
case nir_op_imul:
*dest = ntq_umul(c, src[0], src[1]);
break;
-case nir_op_idiv:
-*dest = ntq_idiv(c, src[0], src[1]);
-break;
case nir_op_seq:
qir_SF(c, qir_FSUB(c, src[0], src[1]));
@@ -2096,6 +2085,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
c->s = tgsi_to_nir(tokens, &nir_options);
nir_opt_global_to_local(c->s);
nir_convert_to_ssa(c->s);
+nir_lower_idiv(c->s);
vc4_optimize_nir(c->s);
___
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Mesa (master): vc4: Fix off-by-one in branch target validation.
Module: Mesa
Branch: master
Commit: d04b07f8e2eb61bb389f2d6b8ed0a501952466ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04b07f8e2eb61bb389f2d6b8ed0a501952466ee
Author: Eric Anholt
Date: Thu Apr 9 13:43:55 2015 -0700
vc4: Fix off-by-one in branch target validation.
---
src/gallium/drivers/vc4/kernel/vc4_validate.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c
b/src/gallium/drivers/vc4/kernel/vc4_validate.c
index 6b73587..aeac29e 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_validate.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c
@@ -287,7 +287,7 @@ validate_branch_to_sublist(VALIDATE_ARGS)
offset = *(uint32_t *)(untrusted + 0);
if (offset % exec->tile_alloc_init_block_size ||
- offset / exec->tile_alloc_init_block_size >
+ offset / exec->tile_alloc_init_block_size >=
exec->bin_tiles_x * exec->bin_tiles_y) {
DRM_ERROR("VC4_PACKET_BRANCH_TO_SUB_LIST must jump to initial "
"tile allocation space.\n");
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Mesa (master): vc4: Move the blit code to a separate file.
Module: Mesa
Branch: master
Commit: 43b20795b742b9f1608dd6f2dc586337408760ad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43b20795b742b9f1608dd6f2dc586337408760ad
Author: Eric Anholt
Date: Thu Apr 9 12:12:20 2015 -0700
vc4: Move the blit code to a separate file.
There will be other blit code showing up, and it seems like the place
you'd look.
---
src/gallium/drivers/vc4/Makefile.sources |1 +
src/gallium/drivers/vc4/vc4_blit.c | 90 ++
src/gallium/drivers/vc4/vc4_context.h|1 +
src/gallium/drivers/vc4/vc4_resource.c | 64 -
4 files changed, 92 insertions(+), 64 deletions(-)
diff --git a/src/gallium/drivers/vc4/Makefile.sources
b/src/gallium/drivers/vc4/Makefile.sources
index 62cd0e0..49474df 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -1,4 +1,5 @@
C_SOURCES := \
+ vc4_blit.c \
vc4_bufmgr.c \
vc4_bufmgr.h \
vc4_cl.c \
diff --git a/src/gallium/drivers/vc4/vc4_blit.c
b/src/gallium/drivers/vc4/vc4_blit.c
new file mode 100644
index 000..5c98fb6
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright © 2015 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "util/u_format.h"
+#include "util/u_surface.h"
+#include "util/u_blitter.h"
+#include "vc4_context.h"
+
+static bool
+vc4_render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
+{
+struct vc4_context *vc4 = vc4_context(ctx);
+
+if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
+fprintf(stderr, "blit unsupported %s -> %s",
+util_format_short_name(info->src.resource->format),
+util_format_short_name(info->dst.resource->format));
+return false;
+}
+
+util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
+util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
+util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
+util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
+util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
+util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
+util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
+util_blitter_save_blend(vc4->blitter, vc4->blend);
+util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
+util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
+util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
+util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
+util_blitter_save_fragment_sampler_states(vc4->blitter,
+vc4->fragtex.num_samplers,
+(void **)vc4->fragtex.samplers);
+util_blitter_save_fragment_sampler_views(vc4->blitter,
+vc4->fragtex.num_textures, vc4->fragtex.textures);
+
+util_blitter_blit(vc4->blitter, info);
+
+return true;
+}
+
+/* Optimal hardware path for blitting pixels.
+ * Scaling, format conversion, up- and downsampling (resolve) are allowed.
+ */
+void
+vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
+{
+struct pipe_blit_info info = *blit_info;
+
+if (info.src.resource->nr_samples > 1 &&
+info.dst.resource->nr_samples <= 1 &&
+!util_format_is_depth_or_stencil(info.src.resource->format) &&
+!util_format_is_pure_integer(info.src.resource->format)) {
+fprintf(stderr, "color resolve unimplemented");
+return;
+}
+
+if (util_try_blit_via_copy_region(pctx, &info)) {
+return; /* done */
+}
+
+if (info.mask & PIPE_MASK_S) {
+fpr
Mesa (master): st/mesa: convert sub image for cube map arrays to 2d arrays for upload
Module: Mesa
Branch: master
Commit: 5ed79312ed99f3b141c35569b9767f82f5ba0a93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ed79312ed99f3b141c35569b9767f82f5ba0a93
Author: Dave Airlie
Date: Wed Apr 8 10:59:20 2015 +1000
st/mesa: convert sub image for cube map arrays to 2d arrays for upload
Since we can subimage upload a number of cube map array layers,
that aren't a complete cube map array, we should specify things
as a 2D array and blit from that.
Suggested by Ilia Mirkin as an alternate fix for texsubimage
cube map array issues.
seems to work just as well.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_cb_texture.c |5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 5c520b4..353f80d 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -738,6 +738,11 @@ st_TexSubImage(struct gl_context *ctx, GLuint dims,
if (gl_target == GL_TEXTURE_CUBE_MAP) {
gl_target = GL_TEXTURE_2D;
}
+ /* TexSubImage can specify subsets of cube map array faces
+* so we need to upload via 2D array instead */
+ if (gl_target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ gl_target = GL_TEXTURE_2D_ARRAY;
+ }
/* Initialize the source texture description. */
memset(&src_templ, 0, sizeof(src_templ));
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Mesa (master): st/mesa: align cube map arrays layers
Module: Mesa Branch: master Commit: cc5860e40787b3afe36856674f028e830685271b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc5860e40787b3afe36856674f028e830685271b Author: Dave Airlie Date: Wed Apr 8 10:00:27 2015 +1000 st/mesa: align cube map arrays layers We create textures internally for texsubimage, and we use the values from sub image to create a new texture, however we don't align these to valid sizes, and cube map arrays must have an array size aligned to 6. This fixes texsubimage cube_map_array on CAYMAN at least, (it was causing GPU hang and bad values), it probably also fixes it on radeonsi and evergreen. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89957 Tested-by: Tom Stellard Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Marek Olšák Signed-off-by: Dave Airlie --- src/mesa/state_tracker/st_texture.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_texture.c b/src/mesa/state_tracker/st_texture.c index ca7c83c..de4a6eb 100644 --- a/src/mesa/state_tracker/st_texture.c +++ b/src/mesa/state_tracker/st_texture.c @@ -177,7 +177,7 @@ st_gl_texture_dims_to_pipe_dims(GLenum texture, *widthOut = widthIn; *heightOut = heightIn; *depthOut = 1; - *layersOut = depthIn; + *layersOut = util_align_npot(depthIn, 6); break; default: assert(0 && "Unexpected texture in st_gl_texture_dims_to_pipe_dims()"); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Flush batchbuffer containing the query on glQueryCounter.
Module: Mesa Branch: master Commit: 1e1d5456ba3dff82301ad4bbdde2fb6e2f562fe3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e1d5456ba3dff82301ad4bbdde2fb6e2f562fe3 Author: Mathias Froehlich Date: Sun Apr 12 18:23:58 2015 +0200 i965: Flush batchbuffer containing the query on glQueryCounter. This change fixes a regression with timer queries introduced with commit 3eb6258. There the pending batchbuffer is flushed only if glEndQuery is executed. This present change adds such a flush to glQueryCounter which also schedules a value query just like glEndQuery does. The patch fixes GPU timer queries going mad from within osgviewer. Reviewed-by: Kenneth Graunke Signed-off-by: Mathias Froehlich Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_queryobj.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 917a24f..667c900 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -472,6 +472,8 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q) drm_intel_bo_unreference(query->bo); query->bo = drm_intel_bo_alloc(brw->bufmgr, "timestamp query", 4096, 4096); brw_write_timestamp(brw, query->bo, 0); + + query->flushed = false; } /** ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vc4: Skip sending down the clear colors if not clearing.
Module: Mesa
Branch: master
Commit: 5100221ff705019334fcdc17da99d257224d2aff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5100221ff705019334fcdc17da99d257224d2aff
Author: Eric Anholt
Date: Mon Apr 6 15:19:30 2015 -0700
vc4: Skip sending down the clear colors if not clearing.
---
src/gallium/drivers/vc4/vc4_context.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 9b2ee5c..daa5ba5 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -129,11 +129,13 @@ vc4_setup_rcl(struct vc4_context *vc4)
branch_size +
color_store_size));
-cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
-cl_u32(&vc4->rcl, vc4->clear_color[0]);
-cl_u32(&vc4->rcl, vc4->clear_color[1]);
-cl_u32(&vc4->rcl, vc4->clear_depth);
-cl_u8(&vc4->rcl, vc4->clear_stencil);
+if (vc4->cleared) {
+cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
+cl_u32(&vc4->rcl, vc4->clear_color[0]);
+cl_u32(&vc4->rcl, vc4->clear_color[1]);
+cl_u32(&vc4->rcl, vc4->clear_depth);
+cl_u8(&vc4->rcl, vc4->clear_stencil);
+}
/* The rendering mode config determines the pointer that's used for
* VC4_PACKET_STORE_MS_TILE_BUFFER address computations. The kernel
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Mesa (master): vc4: Fix another space allocation mistake.
Module: Mesa Branch: master Commit: cb88d2cfcb1fd1ec351277e8b662cda81a5e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb88d2cfcb1fd1ec351277e8b662cda81a5e Author: Eric Anholt Date: Thu Apr 9 13:05:00 2015 -0700 vc4: Fix another space allocation mistake. We're over-allocating our BCL in vc4_draw.c, so this never mattered. However, new RCL-only blit support might end up here without having set up any BCL contents. --- src/gallium/drivers/vc4/vc4_context.c |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c index 1859dd6..9b2ee5c 100644 --- a/src/gallium/drivers/vc4/vc4_context.c +++ b/src/gallium/drivers/vc4/vc4_context.c @@ -349,6 +349,7 @@ vc4_flush(struct pipe_context *pctx) * unblocking the render thread. Note that this doesn't act until the * FLUSH completes. */ +cl_ensure_space(&vc4->bcl, 8); cl_u8(&vc4->bcl, VC4_PACKET_INCREMENT_SEMAPHORE); /* The FLUSH caps all of our bin lists with a VC4_PACKET_RETURN. */ cl_u8(&vc4->bcl, VC4_PACKET_FLUSH); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vc4: Remove dead fields from vc4_surface.
Module: Mesa
Branch: master
Commit: 39b6f7e76c909505df8590b6414e8f710121108a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39b6f7e76c909505df8590b6414e8f710121108a
Author: Eric Anholt
Date: Thu Apr 9 13:13:23 2015 -0700
vc4: Remove dead fields from vc4_surface.
---
src/gallium/drivers/vc4/vc4_resource.h |3 ---
1 file changed, 3 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_resource.h
b/src/gallium/drivers/vc4/vc4_resource.h
index b2359f0..2ed848b 100644
--- a/src/gallium/drivers/vc4/vc4_resource.h
+++ b/src/gallium/drivers/vc4/vc4_resource.h
@@ -46,9 +46,6 @@ struct vc4_surface {
struct pipe_surface base;
uint32_t offset;
uint32_t stride;
-uint32_t width;
-uint16_t height;
-uint16_t depth;
uint8_t tiling;
};
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Mesa (master): vc4: Add missed accounting for the size of the semaphore.
Module: Mesa Branch: master Commit: 8eb9304ee74b7f4a3ef9f8ac9cb04f3031a61ded URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eb9304ee74b7f4a3ef9f8ac9cb04f3031a61ded Author: Eric Anholt Date: Mon Apr 6 15:15:37 2015 -0700 vc4: Add missed accounting for the size of the semaphore. This wouldn't have mattered except in the worst case scenario RCL setup. --- src/gallium/drivers/vc4/vc4_context.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c index ed10f7a..1859dd6 100644 --- a/src/gallium/drivers/vc4/vc4_context.c +++ b/src/gallium/drivers/vc4/vc4_context.c @@ -118,10 +118,12 @@ vc4_setup_rcl(struct vc4_context *vc4) uint32_t tilecoords_size = 3; uint32_t branch_size = 5 + reloc_size; uint32_t color_store_size = 1; +uint32_t semaphore_size = 1; cl_ensure_space(&vc4->rcl, clear_size + config_size + loadstore_size + +semaphore_size + xtiles * ytiles * (loadstore_size * 4 + tilecoords_size * 3 + branch_size + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vc4: Use the blit interface for updating shadow textures.
Module: Mesa
Branch: master
Commit: adae027260bedc7af73e5cc7a74af3cafa4ab460
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=adae027260bedc7af73e5cc7a74af3cafa4ab460
Author: Eric Anholt
Date: Wed Apr 8 13:11:01 2015 -0700
vc4: Use the blit interface for updating shadow textures.
This lets us plug in a better blit implementation and have it impact the
shadow update, too.
---
src/gallium/drivers/vc4/vc4_resource.c | 44 ++--
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_resource.c
b/src/gallium/drivers/vc4/vc4_resource.c
index cbb334f..10e1d6c 100644
--- a/src/gallium/drivers/vc4/vc4_resource.c
+++ b/src/gallium/drivers/vc4/vc4_resource.c
@@ -651,20 +651,38 @@ vc4_update_shadow_baselevel_texture(struct pipe_context
*pctx,
return;
for (int i = 0; i <= shadow->base.b.last_level; i++) {
-struct pipe_box box = {
-.x = 0,
-.y = 0,
-.z = 0,
-.width = u_minify(shadow->base.b.width0, i),
-.height = u_minify(shadow->base.b.height0, i),
-.depth = 1,
+unsigned width = u_minify(shadow->base.b.width0, i);
+unsigned height = u_minify(shadow->base.b.height0, i);
+struct pipe_blit_info info = {
+.dst = {
+.resource = &shadow->base.b,
+.level = i,
+.box = {
+.x = 0,
+.y = 0,
+.z = 0,
+.width = width,
+.height = height,
+.depth = 1,
+},
+.format = shadow->base.b.format,
+},
+.src = {
+.resource = &orig->base.b,
+.level = view->u.tex.first_level + i,
+.box = {
+.x = 0,
+.y = 0,
+.z = 0,
+.width = width,
+.height = height,
+.depth = 1,
+},
+.format = orig->base.b.format,
+},
+.mask = ~0,
};
-
-util_resource_copy_region(pctx,
- &shadow->base.b, i, 0, 0, 0,
- &orig->base.b,
- view->u.tex.first_level + i,
- &box);
+pctx->blit(pctx, &info);
}
shadow->writes = orig->writes;
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Mesa (master): vc4: Sync with kernel changes to relax BCL versus RCL validation.
Module: Mesa
Branch: master
Commit: 725620f21d19365d7a8a34d0c72694384c680afc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=725620f21d19365d7a8a34d0c72694384c680afc
Author: Eric Anholt
Date: Thu Apr 9 13:41:29 2015 -0700
vc4: Sync with kernel changes to relax BCL versus RCL validation.
There was no reason to tie the two packets' values together.
---
src/gallium/drivers/vc4/kernel/vc4_validate.c | 25 +++--
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c
b/src/gallium/drivers/vc4/kernel/vc4_validate.c
index 568b625..6b73587 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_validate.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c
@@ -589,21 +589,6 @@ validate_tile_rendering_mode_config(VALIDATE_ARGS)
exec->fb_width = *(uint16_t *)(untrusted + 4);
exec->fb_height = *(uint16_t *)(untrusted + 6);
- /* Make sure that the fb width/height matches the binning config -- we
-* rely on being able to interchange these for various assertions.
-* (Within a tile, loads and stores will be clipped to the
-* width/height, but we allow load/storing to any binned tile).
-*/
- if (exec->fb_width <= (exec->bin_tiles_x - 1) * 64 ||
- exec->fb_width > exec->bin_tiles_x * 64 ||
- exec->fb_height <= (exec->bin_tiles_y - 1) * 64 ||
- exec->fb_height > exec->bin_tiles_y * 64) {
- DRM_ERROR("bin config %dx%d doesn't match FB %dx%d\n",
- exec->bin_tiles_x, exec->bin_tiles_y,
- exec->fb_width, exec->fb_height);
- return -EINVAL;
- }
-
flags = *(uint16_t *)(untrusted + 8);
if ((flags & VC4_RENDER_CONFIG_FORMAT_MASK) ==
VC4_RENDER_CONFIG_FORMAT_RGBA) {
@@ -632,13 +617,9 @@ validate_tile_coordinates(VALIDATE_ARGS)
uint8_t tile_x = *(uint8_t *)(untrusted + 0);
uint8_t tile_y = *(uint8_t *)(untrusted + 1);
- if (tile_x >= exec->bin_tiles_x ||
- tile_y >= exec->bin_tiles_y) {
- DRM_ERROR("Tile coordinates %d,%d > bin config %d,%d\n",
- tile_x,
- tile_y,
- exec->bin_tiles_x,
- exec->bin_tiles_y);
+ if (tile_x * 64 >= exec->fb_width || tile_y * 64 >= exec->fb_height) {
+ DRM_ERROR("Tile coordinates %d,%d > render config %dx%d\n",
+ tile_x, tile_y, exec->fb_width, exec->fb_height);
return -EINVAL;
}
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Mesa (master): i965: Don't bother freeing NULL.
Module: Mesa
Branch: master
Commit: 1c9db39d54508608ea9518bc82eacbd8e27c410c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c9db39d54508608ea9518bc82eacbd8e27c410c
Author: Matt Turner
Date: Sat Apr 11 10:05:31 2015 -0700
i965: Don't bother freeing NULL.
Commit e16c5c90 was replacing 'region' with 'mt', leaving this
nonsensical code.
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c0a3452..0424a87 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -749,10 +749,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
width, height, depth,
true, 0, false,
disable_aux_buffers);
- if (!mt) {
- free(mt);
- return mt;
- }
+ if (!mt)
+ return NULL;
drm_intel_bo_reference(bo);
mt->bo = bo;
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Mesa (master): swrast: Mark MAX_GLUINT literal with u suffix.
Module: Mesa Branch: master Commit: 89b140dfaeacb8fb0a784c8dd7da26b0d14189e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=89b140dfaeacb8fb0a784c8dd7da26b0d14189e8 Author: Matt Turner Date: Sat Apr 11 10:14:00 2015 -0700 swrast: Mark MAX_GLUINT literal with u suffix. Coverity is confused by the "float < int / 2" expression and suggests casting MAX_GLUINT to unsigned, which I believe it was supposed to have been already. Reviewed-by: Brian Paul --- src/mesa/swrast/s_tritemp.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/swrast/s_tritemp.h b/src/mesa/swrast/s_tritemp.h index fb73b2d..3cd1b44 100644 --- a/src/mesa/swrast/s_tritemp.h +++ b/src/mesa/swrast/s_tritemp.h @@ -92,7 +92,7 @@ #ifndef MAX_GLUINT -#define MAX_GLUINT 0x +#define MAX_GLUINT 0xu #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Lift some restrictions on dma_buf EGLImages
Module: Mesa
Branch: master
Commit: a76dc15b2b37db18151b42be63b49438588a92fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a76dc15b2b37db18151b42be63b49438588a92fe
Author: Chad Versace
Date: Thu Apr 9 20:29:59 2015 -0700
i965: Lift some restrictions on dma_buf EGLImages
Allow glEGLImageTargetRenderbufferStorageOES and
glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is
a single RGBA8 unorm plane. This is safe, despite fast color clears,
because i965 disables allocation of auxiliary buffers for EGLImages.
Chrome OS needs this, because its compositor uses dma_buf EGLImages for
its scanout buffers.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`, with my Piglit patches that update the
EGL_EXT_image_dma_buf_import tests.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_fbo.c |7 ---
src/mesa/drivers/dri/i965/intel_image.h | 10 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 12 ++--
3 files changed, 7 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index fb26038..8a398f7 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -363,13 +363,6 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
return;
}
- /* Buffers originating from outside are for read-only. */
- if (image->dma_buf_imported) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
-"glEGLImageTargetRenderbufferStorage(dma buffers are read-only)");
- return;
- }
-
/* __DRIimage is opaque to the core so it has to be checked here */
switch (image->format) {
case MESA_FORMAT_R8G8B8A8_UNORM:
diff --git a/src/mesa/drivers/dri/i965/intel_image.h
b/src/mesa/drivers/dri/i965/intel_image.h
index 0cae711..a82cf3b 100644
--- a/src/mesa/drivers/dri/i965/intel_image.h
+++ b/src/mesa/drivers/dri/i965/intel_image.h
@@ -89,18 +89,18 @@ struct __DRIimageRec {
GLuint tile_y;
bool has_depthstencil;
+ /** The image was created with EGL_EXT_image_dma_buf_import. */
+ bool dma_buf_imported;
+
/**
* Provided by EGL_EXT_image_dma_buf_import.
-*
-* The flag is set in order to restrict the use of the image later on.
-*
-* See intel_image_target_texture_2d()
+* \{
*/
- bool dma_buf_imported;
enum __DRIYUVColorSpace yuv_color_space;
enum __DRISampleRange sample_range;
enum __DRIChromaSiting horizontal_siting;
enum __DRIChromaSiting vertical_siting;
+ /* \} */
void *data;
};
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 290d313..b70f8de 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -320,17 +320,9 @@ intel_image_target_texture_2d(struct gl_context *ctx,
GLenum target,
if (image == NULL)
return;
- /**
-* Images originating via EGL_EXT_image_dma_buf_import can be used only
-* with GL_OES_EGL_image_external only.
+ /* We support external textures only for EGLImages created with
+* EGL_EXT_image_dma_buf_import. We may lift that restriction in the future.
*/
- if (image->dma_buf_imported && target != GL_TEXTURE_EXTERNAL_OES) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
-"glEGLImageTargetTexture2DOES(dma buffers can be used with "
- "GL_OES_EGL_image_external only");
- return;
- }
-
if (target == GL_TEXTURE_EXTERNAL_OES && !image->dma_buf_imported) {
_mesa_error(ctx, GL_INVALID_OPERATION,
"glEGLImageTargetTexture2DOES(external target is enabled only "
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Mesa (master): i965: Disable aux buffers for EGLImage-backed miptrees
Module: Mesa
Branch: master
Commit: 2943b15ce7ce1bc29424949124a69538253008f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2943b15ce7ce1bc29424949124a69538253008f7
Author: Chad Versace
Date: Mon Apr 6 08:07:27 2015 -0700
i965: Disable aux buffers for EGLImage-backed miptrees
EGL does not yet have extensions to manage the flushing and invalidating
of driver-internal aux buffers. So we must disable aux buffers of
dma_buf-backed EGLImages in order to safely render into them.
This patch is obviously needed for renderbufers. It's also needed for
textures because the user can attach the texture to a framebuffer and
because the driver sometimes renders to textures for internal reasons.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_fbo.c |8 +++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 16
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 4c38583..fb26038 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -383,6 +383,12 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
irb = intel_renderbuffer(rb);
intel_miptree_release(&irb->mt);
+
+ /* Disable creation of the miptree's aux buffers because the driver exposes
+* no EGL API to manage them. That is, there is no API for resolving the aux
+* buffer's content to the main buffer nor for invalidating the aux buffer's
+* content.
+*/
irb->mt = intel_miptree_create_for_bo(brw,
image->bo,
image->format,
@@ -391,7 +397,7 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
image->height,
1,
image->pitch,
- false /*disable_aux_buffers*/);
+ true /*disable_aux_buffers*/);
if (!irb->mt)
return;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index c581010..290d313 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -154,7 +154,8 @@ intel_set_texture_image_bo(struct gl_context *ctx,
uint32_t offset,
GLuint width, GLuint height,
GLuint pitch,
- GLuint tile_x, GLuint tile_y)
+ GLuint tile_x, GLuint tile_y,
+ bool disable_aux_buffers)
{
struct brw_context *brw = brw_context(ctx);
struct intel_texture_image *intel_image = intel_texture_image(image);
@@ -170,7 +171,7 @@ intel_set_texture_image_bo(struct gl_context *ctx,
intel_image->mt = intel_miptree_create_for_bo(brw, bo, image->TexFormat,
0, width, height, 1, pitch,
- false
/*disable_aux_buffers*/);
+ disable_aux_buffers);
if (intel_image->mt == NULL)
return;
intel_image->mt->target = target;
@@ -254,7 +255,8 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
rb->Base.Base.Width,
rb->Base.Base.Height,
rb->mt->pitch,
- 0, 0);
+ 0, 0,
+ false /*disable_aux_buffers*/);
_mesa_unlock_texture(&brw->ctx, texObj);
}
@@ -344,12 +346,18 @@ intel_image_target_texture_2d(struct gl_context *ctx,
GLenum target,
return;
}
+ /* Disable creation of the texture's aux buffers because the driver exposes
+* no EGL API to manage them. That is, there is no API for resolving the aux
+* buffer's content to the main buffer nor for invalidating the aux buffer's
+* content.
+*/
intel_set_texture_image_bo(ctx, texImage, image->bo,
target, image->internal_format,
image->format, image->offset,
image->width, image->height,
image->pitch,
- image->tile_x, image->tile_y);
+ image->tile_x, image->tile_y,
+ true /*disable_aux_buffers*/);
}
/**
___
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Mesa (master): i965: Change intel_miptree_create_for_bo() signature
Module: Mesa
Branch: master
Commit: bf504b61274123f09720c80569a8b4f2d3495630
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf504b61274123f09720c80569a8b4f2d3495630
Author: Chad Versace
Date: Mon Apr 6 08:11:43 2015 -0700
i965: Change intel_miptree_create_for_bo() signature
Add parameter 'bool disable_aux_buffers'.
This is a refactor patch. The patch changes no behavior because the new
parameter is false in every call.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_fbo.c |3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |3 ++-
src/mesa/drivers/dri/i965/intel_pixel_draw.c |3 ++-
src/mesa/drivers/dri/i965/intel_tex.c |3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c |3 ++-
6 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 7babd29..4c38583 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -390,7 +390,8 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
image->width,
image->height,
1,
- image->pitch);
+ image->pitch,
+ false /*disable_aux_buffers*/);
if (!irb->mt)
return;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ec0bb19..c0a3452 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -246,7 +246,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint depth0,
bool for_bo,
GLuint num_samples,
-bool force_all_slices_at_each_lod)
+bool force_all_slices_at_each_lod,
+bool disable_aux_buffers)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
@@ -285,7 +286,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
- mt->disable_aux_buffers = false; /* hardcoded for now */
+ mt->disable_aux_buffers = disable_aux_buffers;
exec_list_make_empty(&mt->hiz_map);
/* The cpp is bytes per (1, blockheight)-sized block for compressed
@@ -629,7 +630,8 @@ intel_miptree_create(struct brw_context *brw,
first_level, last_level, width0,
height0, depth0,
false, num_samples,
-force_all_slices_at_each_lod);
+force_all_slices_at_each_lod,
+false /*disable_aux_buffers*/);
/*
* pitch == 0 || height == 0 indicates the null texture
*/
@@ -720,7 +722,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t width,
uint32_t height,
uint32_t depth,
-int pitch)
+int pitch,
+bool disable_aux_buffers)
{
struct intel_mipmap_tree *mt;
uint32_t tiling, swizzle;
@@ -744,7 +747,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt = intel_miptree_create_layout(brw, target, format,
0, 0,
width, height, depth,
-true, 0, false);
+true, 0, false,
+disable_aux_buffers);
if (!mt) {
free(mt);
return mt;
@@ -795,7 +799,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel,
width,
height,
1,
- pitch);
+ pitch,
+ false);
if (!singlesample_mt)
goto fail;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 3dd37883..0796059 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -544,7 +544,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
uint32_t width,
Mesa (master): i965: Refactor brw_is_hiz_depth_format()
Module: Mesa
Branch: master
Commit: e1338f267fa5670fc02a450774fa89b42e990883
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1338f267fa5670fc02a450774fa89b42e990883
Author: Chad Versace
Date: Mon Apr 6 06:54:30 2015 -0700
i965: Refactor brw_is_hiz_depth_format()
Every caller of this function uses it to determine if the current
miptree needs a hiz buffer to be allocated. Strangely, the function
doesn't take a miptree argument. So, this function effectively decides
if and when a miptree's hiz buffer gets allocated without inspecting the
miptree itself. Luckily, the driver behaves correctly despite the
brw_is_hiz_depth_format's quirk.
I will soon make some changes to the miptree that will require
inspecting the miptree to determine if it needs a hiz buffer. So this
patch renames
brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer
and gives it a miptree parameter.
This patch shouldn't change any behavior.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h |1 -
src/mesa/drivers/dri/i965/brw_surface_formats.c | 19 -
src/mesa/drivers/dri/i965/intel_fbo.c |4 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |5 -
5 files changed, 30 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 6c168a3..0bd0ed1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1681,7 +1681,6 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
struct brw_stage_prog_data *prog_data);
/* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 7524ad9..c7fb707 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -798,22 +798,3 @@ brw_depth_format(struct brw_context *brw, mesa_format
format)
unreachable("Unexpected depth format.");
}
}
-
-/** Can HiZ be enabled on a depthbuffer of the given format? */
-bool
-brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format)
-{
- if (!brw->has_hiz)
- return false;
-
- switch (format) {
- case MESA_FORMAT_Z_FLOAT32:
- case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
- case MESA_FORMAT_Z24_UNORM_X8_UINT:
- case MESA_FORMAT_Z24_UNORM_S8_UINT:
- case MESA_FORMAT_Z_UNORM16:
- return true;
- default:
- return false;
- }
-}
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 2cf4771..7babd29 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -561,7 +561,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
intel_renderbuffer_set_draw_offset(irb);
- if (mt->hiz_buf == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
+ if (intel_miptree_wants_hiz_buffer(brw, mt)) {
intel_miptree_alloc_hiz(brw, mt);
if (!mt->hiz_buf)
return false;
@@ -1032,7 +1032,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
INTEL_MIPTREE_TILING_ANY,
false);
- if (brw_is_hiz_depth_format(brw, new_mt->format)) {
+ if (intel_miptree_wants_hiz_buffer(brw, new_mt)) {
intel_miptree_alloc_hiz(brw, new_mt);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a906460..492338b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -403,7 +403,8 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!for_bo &&
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
- (brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format {
+ (brw->has_separate_stencil &&
+ intel_miptree_wants_hiz_buffer(brw, mt {
const bool force_all_slices_at_each_lod = brw->gen == 6;
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
@@ -843,7 +844,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context
*brw,
if (!mt)
goto fail;
- if (brw_is_hiz_depth_format(brw, format)) {
+ if (intel_miptree_wants_hiz_buffer(brw, mt)) {
ok = intel_miptree_alloc_hiz(brw, mt);
if (!ok)
goto fail;
@@ -1681,6 +1682,27 @@ intel_hiz_miptree_buf_create(struct br
Mesa (master): i965: Add field intel_mipmap_tree::disable_aux_buffers
Module: Mesa
Branch: master
Commit: d3b042f359df5836d4a4f56664eb228fc80772c0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3b042f359df5836d4a4f56664eb228fc80772c0
Author: Chad Versace
Date: Mon Apr 6 06:46:09 2015 -0700
i965: Add field intel_mipmap_tree::disable_aux_buffers
The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.
We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.
Nothing yet enables this field. That's left to follow-up patches.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |7 +++
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 492338b..ec0bb19 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,7 +59,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
* created, based on the chip generation and the surface type.
*/
static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
+compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target,
+bool disable_aux_buffers)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -85,6 +86,11 @@ compute_msaa_layout(struct brw_context *brw, mesa_format
format, GLenum target)
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
+ } else if (disable_aux_buffers) {
+ /* We can't use the CMS layout because it uses an aux buffer, the MCS
+ * buffer. So fallback to UMS, which is identical to CMS without the
+ * MCS. */
+ return INTEL_MSAA_LAYOUT_UMS;
} else {
return INTEL_MSAA_LAYOUT_CMS;
}
@@ -176,6 +182,9 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw,
if (brw->gen < 7)
return false;
+ if (mt->disable_aux_buffers)
+ return false;
+
/* MCS is only supported for color buffers */
switch (_mesa_get_format_base_format(mt->format)) {
case GL_DEPTH_COMPONENT:
@@ -276,6 +285,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
+ mt->disable_aux_buffers = false; /* hardcoded for now */
exec_list_make_empty(&mt->hiz_map);
/* The cpp is bytes per (1, blockheight)-sized block for compressed
@@ -293,7 +303,8 @@ intel_miptree_create_layout(struct brw_context *brw,
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format, mt->target);
+ mt->msaa_layout = compute_msaa_layout(brw, format,
+mt->target,
mt->disable_aux_buffers);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
@@ -440,6 +451,9 @@ intel_miptree_create_layout(struct brw_context *brw,
brw_miptree_layout(brw, mt);
+ if (mt->disable_aux_buffers)
+ assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
+
return mt;
}
@@ -1313,6 +1327,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_mt == NULL);
+ assert(!mt->disable_aux_buffers);
/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1379,6 +1394,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->mcs_mt == NULL);
+ assert(!mt->disable_aux_buffers);
/* The format of the MCS buffer is opaque to the driver; all that matters
* is that we get its size and pitch right. We'll pretend that the format
@@ -1692,6 +1708,9 @@ intel_miptree_wants_hiz_buffer(struct brw_context *brw,
if (mt->hiz_buf != NULL)
return false;
+ if (mt->disable_aux_buffers)
+ return false;
+
switch (mt->format) {
case MESA_FORMAT_Z_FLOAT32:
case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
@@ -1709,6 +1728,7 @@ intel_mip
Mesa (master): i965: Declare intel_miptree_create_layout() as static
Module: Mesa
Branch: master
Commit: 5776d65114b553643eea74c58699910cbdb29b55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5776d65114b553643eea74c58699910cbdb29b55
Author: Chad Versace
Date: Mon Apr 6 07:13:53 2015 -0700
i965: Declare intel_miptree_create_layout() as static
It's not used outside intel_mipmap_tree.c.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c |2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 13 -
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f766b96..a906460 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -226,7 +226,7 @@ intel_depth_format_for_depthstencil_format(mesa_format
format) {
*intel_miptree_create_for_bo(). If true, then do not create
*\c stencil_mt.
*/
-struct intel_mipmap_tree *
+static struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
GLenum target,
mesa_format format,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index e3e2127..3c41893 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -530,19 +530,6 @@ struct intel_mipmap_tree *intel_miptree_create(struct
brw_context *brw,
bool
force_all_slices_at_each_lod);
struct intel_mipmap_tree *
-intel_miptree_create_layout(struct brw_context *brw,
-GLenum target,
-mesa_format format,
-GLuint first_level,
-GLuint last_level,
-GLuint width0,
-GLuint height0,
-GLuint depth0,
-bool for_bo,
-GLuint num_samples,
-bool force_all_slices_at_each_lod);
-
-struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
drm_intel_bo *bo,
mesa_format format,
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Mesa (master): i965: Declare intel_miptree_alloc_mcs() as static
Module: Mesa
Branch: master
Commit: 1ef4bf71914c79b703fd9a75f047b24e0f16c59a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ef4bf71914c79b703fd9a75f047b24e0f16c59a
Author: Chad Versace
Date: Mon Apr 6 07:04:06 2015 -0700
i965: Declare intel_miptree_alloc_mcs() as static
It's not used outside of intel_mipmap_tree.c, nor should it ever be.
Reviewed-by: Kenneth Graunke
Reviewed-by: Tapani Pälli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c |7 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |5 -
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index eb226d5..f766b96 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -49,6 +49,11 @@
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
+static bool
+intel_miptree_alloc_mcs(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+GLuint num_samples);
+
/**
* Determine which MSAA layout should be used by the MSAA surface being
* created, based on the chip generation and the surface type.
@@ -1300,7 +1305,7 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
}
-bool
+static bool
intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLuint num_samples)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 41b6036..e3e2127 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -637,11 +637,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
struct intel_texture_image *intelImage,
struct intel_mipmap_tree *dst_mt, bool invalidate);
-bool
-intel_miptree_alloc_mcs(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-GLuint num_samples);
-
/**
* \name Miptree HiZ functions
* \{
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Mesa (master): mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
Module: Mesa
Branch: master
Commit: 85dd46d90cd7d3d6898d28626063563c1aaba369
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85dd46d90cd7d3d6898d28626063563c1aaba369
Author: Jose Fonseca
Date: Thu Apr 2 10:09:38 2015 +0100
mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.
Reviewed-by: Roland Scheidegger
---
configure.ac |2 +-
src/mesa/main/texcompress_s3tc.c |8
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/configure.ac b/configure.ac
index a40cc20..9e8c1d8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -230,7 +230,7 @@ _SAVE_LDFLAGS="$LDFLAGS"
_SAVE_CPPFLAGS="$CPPFLAGS"
dnl Compiler macros
-DEFINES="-DUSE_EXTERNAL_DXTN_LIB=1"
+DEFINES=""
AC_SUBST([DEFINES])
case "$host_os" in
linux*|*-gnu*|gnu*)
diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c
index 38ce5f8..7ce3cb8 100644
--- a/src/mesa/main/texcompress_s3tc.c
+++ b/src/mesa/main/texcompress_s3tc.c
@@ -29,10 +29,6 @@
* GL_EXT_texture_compression_s3tc support.
*/
-#ifndef USE_EXTERNAL_DXTN_LIB
-#define USE_EXTERNAL_DXTN_LIB 1
-#endif
-
#include "glheader.h"
#include "imports.h"
#include "dlopen.h"
@@ -76,7 +72,6 @@ _mesa_init_texture_s3tc( struct gl_context *ctx )
{
/* called during context initialization */
ctx->Mesa_DXTn = GL_FALSE;
-#if USE_EXTERNAL_DXTN_LIB
if (!dxtlibhandle) {
dxtlibhandle = _mesa_dlopen(DXTN_LIBNAME, 0);
if (!dxtlibhandle) {
@@ -117,9 +112,6 @@ _mesa_init_texture_s3tc( struct gl_context *ctx )
if (dxtlibhandle) {
ctx->Mesa_DXTn = GL_TRUE;
}
-#else
- (void) ctx;
-#endif
}
/**
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Mesa (master): glx: Include util/ macros.h instead of redefining PRINTFLIKE.
Module: Mesa Branch: master Commit: fa1b3e1501da3d24ec4205e0056d67ef9d2663ac URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa1b3e1501da3d24ec4205e0056d67ef9d2663ac Author: Jose Fonseca Date: Thu Apr 2 11:25:06 2015 +0100 glx: Include util/macros.h instead of redefining PRINTFLIKE. Reviewed-by: Roland Scheidegger --- src/glx/dri_common.h |7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/glx/dri_common.h b/src/glx/dri_common.h index 5cd150a..947d331 100644 --- a/src/glx/dri_common.h +++ b/src/glx/dri_common.h @@ -39,12 +39,7 @@ #include #include #include "loader.h" - -#if (__GNUC__) -#define PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a))) -#else -#define PRINTFLIKE(f, a) -#endif +#include "util/macros.h" /* for PRINTFLIKE */ typedef struct __GLXDRIconfigPrivateRec __GLXDRIconfigPrivate; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): docs: Improve LLVM_USE_CRT_xxx instructions.
Module: Mesa Branch: master Commit: 36ceda4eced243c1fab487b878e20944d1238d50 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ceda4eced243c1fab487b878e20944d1238d50 Author: Jose Fonseca Date: Mon Apr 13 13:08:13 2015 +0100 docs: Improve LLVM_USE_CRT_xxx instructions. --- docs/llvmpipe.html | 32 +++- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/docs/llvmpipe.html b/docs/llvmpipe.html index 72db93a..f603bd6 100644 --- a/docs/llvmpipe.html +++ b/docs/llvmpipe.html @@ -58,15 +58,37 @@ It's the fastest software rasterizer for Mesa. -For Windows you will need to build LLVM from source with MSVC or MINGW -(either natively or through cross compilers) and CMake, and set the LLVM -environment variable to the directory you installed it to. + For Windows you will need to build LLVM from source with MSVC or MINGW + (either natively or through cross compilers) and CMake, and set the LLVM + environment variable to the directory you installed it to. LLVM will be statically linked, so when building on MSVC it needs to be built with a matching CRT as Mesa, and you'll need to pass - -DLLVM_USE_CRT_RELEASE=MTd for debug and checked builds, - -DLLVM_USE_CRT_RELEASE=MTd for profile and release builds. + -DLLVM_USE_CRT_xxx=yyy as described below. + + + + + LLVM build-type + Mesa build-type + + + debug,checked + release,profile + + + Debug + -DLLVM_USE_CRT_DEBUG=MTd + -DLLVM_USE_CRT_DEBUG=MT + + + Release + -DLLVM_USE_CRT_RELEASE=MTd + -DLLVM_USE_CRT_RELEASE=MT + + + You can build only the x86 target by passing -DLLVM_TARGETS_TO_BUILD=X86 to cmake. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): util/ralloc: Fix `extern "C"` usage.
Module: Mesa
Branch: master
Commit: 978753e84368ef3afa9288cbfbee1c85b3ab09d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=978753e84368ef3afa9288cbfbee1c85b3ab09d1
Author: Jose Fonseca
Date: Thu Apr 2 11:24:26 2015 +0100
util/ralloc: Fix `extern "C"` usage.
Reviewed-by: Roland Scheidegger
Reviewed-by: Kenneth Graunke
---
src/util/ralloc.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/util/ralloc.h b/src/util/ralloc.h
index 01f102b..7587e11 100644
--- a/src/util/ralloc.h
+++ b/src/util/ralloc.h
@@ -46,16 +46,16 @@
#ifndef RALLOC_H
#define RALLOC_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-
#include
#include
#include
#include "macros.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/**
* \def ralloc(ctx, type)
* Allocate a new object chained off of the given context.
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