Mesa (master): nir: Silence GCC maybe-uninitialized warnings.
Module: Mesa
Branch: master
Commit: 3a0fef0005eca63c6f8067d55145b8e884221cfa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a0fef0005eca63c6f8067d55145b8e884221cfa
Author: Vinson Lee
Date: Mon Nov 2 01:23:59 2015 -0800
nir: Silence GCC maybe-uninitialized warnings.
nir/nir_control_flow.c: In function ‘split_block_cursor.isra.11’:
nir/nir_control_flow.c:460:15: warning: ‘after’ may be used uninitialized in
this function [-Wmaybe-uninitialized]
*_after = after;
^
nir/nir_control_flow.c:458:16: warning: ‘before’ may be used uninitialized in
this function [-Wmaybe-uninitialized]
*_before = before;
^
Signed-off-by: Vinson Lee
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_control_flow.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/glsl/nir/nir_control_flow.c b/src/glsl/nir/nir_control_flow.c
index 7f51c4f..96395a4 100644
--- a/src/glsl/nir/nir_control_flow.c
+++ b/src/glsl/nir/nir_control_flow.c
@@ -452,6 +452,9 @@ split_block_cursor(nir_cursor cursor,
before = split_block_before_instr(nir_instr_next(cursor.instr));
}
break;
+
+ default:
+ unreachable("not reached");
}
if (_before)
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Mesa (master): glsl: Allow implicit int -> uint conversions for the % operator.
Module: Mesa
Branch: master
Commit: 511de1a80cedc0add386dad79cce56dd68d2f611
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=511de1a80cedc0add386dad79cce56dd68d2f611
Author: Kenneth Graunke
Date: Thu Nov 12 13:02:05 2015 -0800
glsl: Allow implicit int -> uint conversions for the % operator.
GLSL 4.00 and GL_ARB_gpu_shader5 introduced a new int -> uint implicit
conversion rule and updated the rules for modulus to use them. (In
earlier languages, none of the implicit conversion rules did anything
relevant, so there was no point in applying them.)
This allows expressions such as:
int foo;
uint bar;
uint mod = foo % bar;
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
Reviewed-by: Ian Romanick
---
src/glsl/ast_to_hir.cpp | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 51ea183..f529243 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -538,18 +538,20 @@ bit_logic_result_type(const struct glsl_type *type_a,
}
static const struct glsl_type *
-modulus_result_type(const struct glsl_type *type_a,
-const struct glsl_type *type_b,
+modulus_result_type(ir_rvalue * &value_a, ir_rvalue * &value_b,
struct _mesa_glsl_parse_state *state, YYLTYPE *loc)
{
+ const glsl_type *type_a = value_a->type;
+ const glsl_type *type_b = value_b->type;
+
if (!state->check_version(130, 300, loc, "operator '%%' is reserved")) {
return glsl_type::error_type;
}
- /* From GLSL 1.50 spec, page 56:
+ /* Section 5.9 (Expressions) of the GLSL 4.00 specification says:
+*
*"The operator modulus (%) operates on signed or unsigned integers or
-*integer vectors. The operand types must both be signed or both be
-*unsigned."
+*integer vectors."
*/
if (!type_a->is_integer()) {
_mesa_glsl_error(loc, state, "LHS of operator %% must be an integer");
@@ -559,11 +561,28 @@ modulus_result_type(const struct glsl_type *type_a,
_mesa_glsl_error(loc, state, "RHS of operator %% must be an integer");
return glsl_type::error_type;
}
- if (type_a->base_type != type_b->base_type) {
+
+ /*"If the fundamental types in the operands do not match, then the
+*conversions from section 4.1.10 "Implicit Conversions" are applied
+*to create matching types."
+*
+* Note that GLSL 4.00 (and GL_ARB_gpu_shader5) introduced implicit
+* int -> uint conversion rules. Prior to that, there were no implicit
+* conversions. So it's harmless to apply them universally - no implicit
+* conversions will exist. If the types don't match, we'll receive false,
+* and raise an error, satisfying the GLSL 1.50 spec, page 56:
+*
+*"The operand types must both be signed or unsigned."
+*/
+ if (!apply_implicit_conversion(type_a, value_b, state) &&
+ !apply_implicit_conversion(type_b, value_a, state)) {
_mesa_glsl_error(loc, state,
- "operands of %% must have the same base type");
+ "could not implicitly convert operands to "
+ "modulus (%%) operator");
return glsl_type::error_type;
}
+ type_a = value_a->type;
+ type_b = value_b->type;
/*"The operands cannot be vectors of differing size. If one operand is
*a scalar and the other vector, then the scalar is applied component-
@@ -1311,7 +1330,7 @@ ast_expression::do_hir(exec_list *instructions,
op[0] = this->subexpressions[0]->hir(instructions, state);
op[1] = this->subexpressions[1]->hir(instructions, state);
- type = modulus_result_type(op[0]->type, op[1]->type, state, & loc);
+ type = modulus_result_type(op[0], op[1], state, &loc);
assert(operations[this->oper] == ir_binop_mod);
@@ -1558,7 +1577,7 @@ ast_expression::do_hir(exec_list *instructions,
op[0] = this->subexpressions[0]->hir(instructions, state);
op[1] = this->subexpressions[1]->hir(instructions, state);
- type = modulus_result_type(op[0]->type, op[1]->type, state, & loc);
+ type = modulus_result_type(op[0], op[1], state, &loc);
assert(operations[this->oper] == ir_binop_mod);
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Mesa (master): i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.
Module: Mesa
Branch: master
Commit: 5480bbd90ea288877b6e56d4860feb8f97bcba80
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5480bbd90ea288877b6e56d4860feb8f97bcba80
Author: Kenneth Graunke
Date: Sat Nov 7 01:37:33 2015 -0800
i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.
We need to use per-slot offsets when there's non-uniform indexing,
as each SIMD channel could have a different index. We want to use
them for any non-constant index (even if uniform), as it lives in
the message header instead of the descriptor, allowing us to set
offsets in GRFs rather than immediates.
Signed-off-by: Kenneth Graunke
Reviewed-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_defines.h|7 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp |2 ++
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |4
src/mesa/drivers/dri/i965/brw_shader.cpp |2 ++
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 5044982..6484484 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1055,13 +1055,10 @@ enum opcode {
SHADER_OPCODE_GEN7_SCRATCH_READ,
/**
-* Gen8+ SIMD8 URB Read message.
-*
-* Source 0: The header register, containing URB handles (g1).
-*
-* Currently only supports constant offsets, in inst->offset.
+* Gen8+ SIMD8 URB Read messages.
*/
SHADER_OPCODE_URB_READ_SIMD8,
+ SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
SHADER_OPCODE_URB_WRITE_SIMD8,
SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b8d48da..80b8c8e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -285,6 +285,7 @@ fs_inst::is_send_from_grf() const
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
return true;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return src[1].file == VGRF;
@@ -807,6 +808,7 @@ fs_inst::regs_read(int arg) const
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e986021..139cda3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -387,6 +387,9 @@ fs_generator::generate_urb_read(fs_inst *inst,
brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
+ if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
+ brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
+
brw_inst_set_mlen(p->devinfo, send, inst->mlen);
brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
brw_inst_set_header_present(p->devinfo, send, true);
@@ -2077,6 +2080,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
break;
case SHADER_OPCODE_URB_READ_SIMD8:
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
generate_urb_read(inst, dst, src[0]);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index a0c74a2..a438e18 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -429,6 +429,8 @@ brw_instruction_name(enum opcode op)
return "gen8_urb_write_simd8_masked_per_slot";
case SHADER_OPCODE_URB_READ_SIMD8:
return "urb_read_simd8";
+ case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
+ return "urb_read_simd8_per_slot";
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
return "find_live_channel";
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Mesa (master): nir: Allow outputs reads and add the relevant intrinsics.
Module: Mesa
Branch: master
Commit: 134728fdaef9d2a5d072d25b31437ac0fecd9076
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=134728fdaef9d2a5d072d25b31437ac0fecd9076
Author: Kenneth Graunke
Date: Mon Oct 19 11:44:28 2015 -0700
nir: Allow outputs reads and add the relevant intrinsics.
Normally, we rely on nir_lower_outputs_to_temporaries to create shadow
variables for outputs, buffering the results and writing them all out
at the end of the program. However, this is infeasible for tessellation
control shader outputs.
Tessellation control shaders can generate multiple output vertices, and
write per-vertex outputs. These are arrays indexed by the vertex
number; each thread only writes one element, but can read any other
element - including those being concurrently written by other threads.
The barrier() intrinsic synchronizes between threads.
Even if we tried to shadow every output element (which is of dubious
value), we'd have to read updated values in at barrier() time, which
means we need to allow output reads.
Most stages should continue using nir_lower_outputs_to_temporaries(),
but in theory drivers could choose not to if they really wanted.
v2: Rebase to accomodate Jason's review feedback.
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/glsl/nir/nir_intrinsics.h |2 ++
src/glsl/nir/nir_lower_io.c | 23 +--
src/glsl/nir/nir_print.c |2 ++
src/glsl/nir/nir_validate.c |2 --
4 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h
index 26ac7ce..b8d7d6c 100644
--- a/src/glsl/nir/nir_intrinsics.h
+++ b/src/glsl/nir/nir_intrinsics.h
@@ -255,6 +255,8 @@ LOAD(ubo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
LOAD(input, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
LOAD(per_vertex_input, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
LOAD(ssbo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(output, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(per_vertex_output, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE)
/*
* Stores work the same way as loads, except now the first register input is
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index b7b599d..8a4177f 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -161,6 +161,15 @@ load_op(struct lower_io_state *state,
nir_intrinsic_load_input;
}
break;
+ case nir_var_shader_out:
+ if (per_vertex) {
+ op = has_indirect ? nir_intrinsic_load_per_vertex_output_indirect :
+ nir_intrinsic_load_per_vertex_output;
+ } else {
+ op = has_indirect ? nir_intrinsic_load_output_indirect :
+ nir_intrinsic_load_output;
+ }
+ break;
case nir_var_uniform:
op = has_indirect ? nir_intrinsic_load_uniform_indirect :
nir_intrinsic_load_uniform;
@@ -191,13 +200,16 @@ nir_lower_io_block(nir_block *block, void *void_state)
if (state->mode != -1 && state->mode != mode)
continue;
+ if (mode != nir_var_shader_in &&
+ mode != nir_var_shader_out &&
+ mode != nir_var_uniform)
+ continue;
+
switch (intrin->intrinsic) {
case nir_intrinsic_load_var: {
- if (mode != nir_var_shader_in && mode != nir_var_uniform)
-continue;
-
bool per_vertex =
-is_per_vertex_input(state, intrin->variables[0]->var);
+is_per_vertex_input(state, intrin->variables[0]->var) ||
+is_per_vertex_output(state, intrin->variables[0]->var);
nir_ssa_def *indirect;
nir_ssa_def *vertex_index;
@@ -241,8 +253,7 @@ nir_lower_io_block(nir_block *block, void *void_state)
}
case nir_intrinsic_store_var: {
- if (intrin->variables[0]->var->data.mode != nir_var_shader_out)
-continue;
+ assert(mode == nir_var_shader_out);
nir_ssa_def *indirect;
nir_ssa_def *vertex_index;
diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index 23fcafe..f7f5fdf 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print.c
@@ -448,6 +448,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr,
print_state *state)
case nir_intrinsic_load_per_vertex_input_indirect:
var_list = &state->shader->inputs;
break;
+ case nir_intrinsic_load_output:
+ case nir_intrinsic_load_output_indirect:
case nir_intrinsic_store_output:
case nir_intrinsic_store_output_indirect:
case nir_intrinsic_store_per_vertex_output:
diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c
index 51c2529..ed374b9 100644
--- a/src/glsl/nir/nir_validate.c
+++ b/src/glsl/nir/nir_validate.c
@@ -405,7 +405,6 @@ validate_intrinsic_instr(nir_intrinsic_instr *instr,
validate_state *state)
(instr->varia
Mesa (master): nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.
Module: Mesa
Branch: master
Commit: 0df452cd0d9da031d2ef29853d39112fdf8e1d46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0df452cd0d9da031d2ef29853d39112fdf8e1d46
Author: Kenneth Graunke
Date: Wed Sep 30 17:17:35 2015 -0700
nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.
Tessellation control shader inputs are an array indexed by the vertex
number, like geometry shader inputs. There aren't per-patch TCS inputs.
Tessellation evaluation shaders have both per-vertex and per-patch
inputs. Per-vertex inputs get the new intrinsics; per-patch inputs
continue to use the ordinary load_input intrinsics, as they already
work like we want them to.
v2: Change stage_uses_per_vertex_inputs into is_per_vertex_input(),
which takes a variable (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/glsl/nir/nir_lower_io.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 688b48f..16ba1a1 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -68,10 +68,14 @@ nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
* by a vertex number (such as geometry shader inputs).
*/
static bool
-stage_uses_per_vertex_inputs(struct lower_io_state *state)
+is_per_vertex_input(struct lower_io_state *state, nir_variable *var)
{
gl_shader_stage stage = state->builder.shader->stage;
- return stage == MESA_SHADER_GEOMETRY;
+
+ return var->data.mode == nir_var_shader_in && !var->data.patch &&
+ (stage == MESA_SHADER_TESS_CTRL ||
+ stage == MESA_SHADER_TESS_EVAL ||
+ stage == MESA_SHADER_GEOMETRY);
}
static unsigned
@@ -184,8 +188,8 @@ nir_lower_io_block(nir_block *block, void *void_state)
if (mode != nir_var_shader_in && mode != nir_var_uniform)
continue;
- bool per_vertex = stage_uses_per_vertex_inputs(state) &&
- mode == nir_var_shader_in;
+ bool per_vertex =
+is_per_vertex_input(state, intrin->variables[0]->var);
nir_ssa_def *indirect;
nir_ssa_def *vertex_index;
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Mesa (master): nir: Don't lower TCS outputs to temporaries.
Module: Mesa
Branch: master
Commit: d12bde0944d1d69401ef1d854aa0ab92b5a6af54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d12bde0944d1d69401ef1d854aa0ab92b5a6af54
Author: Kenneth Graunke
Date: Mon Oct 19 11:28:15 2015 -0700
nir: Don't lower TCS outputs to temporaries.
We'd like to shadow these when possible, but the current code doesn't
work properly for TCS outputs. For now, disable it.
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/glsl/nir/nir_lower_outputs_to_temporaries.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/glsl/nir/nir_lower_outputs_to_temporaries.c
b/src/glsl/nir/nir_lower_outputs_to_temporaries.c
index 80f4395..9441f47 100644
--- a/src/glsl/nir/nir_lower_outputs_to_temporaries.c
+++ b/src/glsl/nir/nir_lower_outputs_to_temporaries.c
@@ -78,6 +78,9 @@ nir_lower_outputs_to_temporaries(nir_shader *shader)
{
struct lower_outputs_state state;
+ if (shader->stage == MESA_SHADER_TESS_CTRL)
+ return;
+
state.shader = shader;
exec_list_move_nodes_to(&shader->outputs, &state.old_outputs);
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Mesa (master): nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.
Module: Mesa
Branch: master
Commit: c51d7d5fe3425b0b1cb551f47979a1e41f1f73d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c51d7d5fe3425b0b1cb551f47979a1e41f1f73d8
Author: Kenneth Graunke
Date: Fri Oct 2 00:11:01 2015 -0700
nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.
Similar to nir_load_per_vertex_input, but for outputs. This is not
useful in geometry shaders, but will be useful in tessellation shaders.
v2: Change stage_uses_per_vertex_outputs() to is_per_vertex_output(),
taking a nir_variable (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/glsl/nir/nir_intrinsics.h |1 +
src/glsl/nir/nir_lower_io.c | 28 +++-
src/glsl/nir/nir_print.c |2 ++
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h
index 36fb286..26ac7ce 100644
--- a/src/glsl/nir/nir_intrinsics.h
+++ b/src/glsl/nir/nir_intrinsics.h
@@ -272,6 +272,7 @@ LOAD(ssbo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE)
false, 0, 0, 1 + extra_indices, flags)
STORE(output, 0, 0, 0, 0)
+STORE(per_vertex_output, 1, 1, 0, 0)
STORE(ssbo, 1, 1, 1, 0)
LAST_INTRINSIC(store_ssbo_indirect)
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 16ba1a1..b7b599d 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -78,6 +78,14 @@ is_per_vertex_input(struct lower_io_state *state,
nir_variable *var)
stage == MESA_SHADER_GEOMETRY);
}
+static bool
+is_per_vertex_output(struct lower_io_state *state, nir_variable *var)
+{
+ gl_shader_stage stage = state->builder.shader->stage;
+ return var->data.mode == nir_var_shader_out && !var->data.patch &&
+ stage == MESA_SHADER_TESS_CTRL;
+}
+
static unsigned
get_io_offset(nir_deref_var *deref, nir_instr *instr,
nir_ssa_def **vertex_index,
@@ -237,16 +245,23 @@ nir_lower_io_block(nir_block *block, void *void_state)
continue;
nir_ssa_def *indirect;
+ nir_ssa_def *vertex_index;
+
+ bool per_vertex =
+is_per_vertex_output(state, intrin->variables[0]->var);
unsigned offset = get_io_offset(intrin->variables[0], &intrin->instr,
- NULL, &indirect, state);
+ per_vertex ? &vertex_index : NULL,
+ &indirect, state);
offset += intrin->variables[0]->var->data.driver_location;
nir_intrinsic_op store_op;
- if (indirect) {
-store_op = nir_intrinsic_store_output_indirect;
+ if (per_vertex) {
+store_op = indirect ?
nir_intrinsic_store_per_vertex_output_indirect
+: nir_intrinsic_store_per_vertex_output;
} else {
-store_op = nir_intrinsic_store_output;
+store_op = indirect ? nir_intrinsic_store_output_indirect
+: nir_intrinsic_store_output;
}
nir_intrinsic_instr *store =
nir_intrinsic_instr_create(state->mem_ctx,
@@ -256,8 +271,11 @@ nir_lower_io_block(nir_block *block, void *void_state)
nir_src_copy(&store->src[0], &intrin->src[0], store);
+ if (per_vertex)
+store->src[1] = nir_src_for_ssa(vertex_index);
+
if (indirect)
-store->src[1] = nir_src_for_ssa(indirect);
+store->src[per_vertex ? 2 : 1] = nir_src_for_ssa(indirect);
nir_instr_insert_before(&intrin->instr, &store->instr);
nir_instr_remove(&intrin->instr);
diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index 30220c5..23fcafe 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print.c
@@ -450,6 +450,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr,
print_state *state)
break;
case nir_intrinsic_store_output:
case nir_intrinsic_store_output_indirect:
+ case nir_intrinsic_store_per_vertex_output:
+ case nir_intrinsic_store_per_vertex_output_indirect:
var_list = &state->shader->outputs;
break;
default:
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Mesa (master): i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.
Module: Mesa
Branch: master
Commit: a4ba476c30ebcb99694c6167ac9b8af9414cb656
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4ba476c30ebcb99694c6167ac9b8af9414cb656
Author: Kenneth Graunke
Date: Tue Nov 10 00:48:33 2015 -0800
i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.
I've been carrying around a patch to do this for the last few months,
and it's been exceedingly useful for debugging GS and tessellation
problems. I've caught lots of bugs by inspecting the interface
expectations of two adjacent stages.
It's not that much spam, so I figure we may as well just print it.
Signed-off-by: Kenneth Graunke
Acked-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_compiler.h |2 ++
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |6 +
src/mesa/drivers/dri/i965/brw_vs.c|6 -
src/mesa/drivers/dri/i965/brw_vue_map.c | 27 +
4 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index f022f38..e3a26d6 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -458,6 +458,8 @@ struct brw_vue_map {
int num_slots;
};
+void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
+
/**
* Convert a VUE slot number into a byte offset within the VUE.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 49c1083..1a09f76 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -812,6 +812,12 @@ brw_compile_gs(const struct brw_compiler *compiler, void
*log_data,
/* Now that prog_data setup is done, we are ready to actually compile the
* program.
*/
+ if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
+ fprintf(stderr, "GS Input ");
+ brw_print_vue_map(stderr, &c.input_vue_map);
+ fprintf(stderr, "GS Output ");
+ brw_print_vue_map(stderr, &prog_data->base.vue_map);
+ }
if (compiler->scalar_gs) {
/* TODO: Support instanced GS. We have basically no tests... */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 0b805b1..967448e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -159,9 +159,13 @@ brw_codegen_vs_prog(struct brw_context *brw,
start_time = get_time();
}
- if (unlikely(INTEL_DEBUG & DEBUG_VS))
+ if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
brw_dump_ir("vertex", prog, vs ? &vs->base : NULL, &vp->program.Base);
+ fprintf(stderr, "VS Output ");
+ brw_print_vue_map(stderr, &prog_data.base.vue_map);
+ }
+
int st_index = -1;
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
st_index = brw_get_shader_time_index(brw, prog, &vp->program.Base,
ST_VS);
diff --git a/src/mesa/drivers/dri/i965/brw_vue_map.c
b/src/mesa/drivers/dri/i965/brw_vue_map.c
index 45662bd..edb1608 100644
--- a/src/mesa/drivers/dri/i965/brw_vue_map.c
+++ b/src/mesa/drivers/dri/i965/brw_vue_map.c
@@ -178,3 +178,30 @@ brw_compute_vue_map(const struct brw_device_info *devinfo,
vue_map->num_slots = separate ? slot + 1 : slot;
}
+
+static const char *
+varying_name(brw_varying_slot slot)
+{
+ if (slot < VARYING_SLOT_MAX)
+ return gl_varying_slot_name(slot);
+
+ static const char *brw_names[] = {
+ [BRW_VARYING_SLOT_NDC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_NDC",
+ [BRW_VARYING_SLOT_PAD - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PAD",
+ [BRW_VARYING_SLOT_PNTC - VARYING_SLOT_MAX] = "BRW_VARYING_SLOT_PNTC",
+ };
+
+ return brw_names[slot - VARYING_SLOT_MAX];
+}
+
+void
+brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map)
+{
+ fprintf(fp, "VUE map (%d slots, %s)\n",
+ vue_map->num_slots, vue_map->separate ? "SSO" : "non-SSO");
+ for (int i = 0; i < vue_map->num_slots; i++) {
+ fprintf(fp, " [%d] %s\n", i,
+ varying_name(vue_map->slot_to_varying[i]));
+ }
+ fprintf(fp, "\n");
+}
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Mesa (master): nir: Add helpers for getting input/ output intrinsic sources.
Module: Mesa
Branch: master
Commit: 26f9469a46585f64b24fb1037aaae7c757a5e6e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26f9469a46585f64b24fb1037aaae7c757a5e6e1
Author: Kenneth Graunke
Date: Sat Nov 7 22:35:33 2015 -0800
nir: Add helpers for getting input/output intrinsic sources.
With the many variants of IO intrinsics, particular sources are often in
different locations. It's convenient to say "give me the indirect
offset" or "give me the vertex index" and have it just work, without
having to think about exactly which kind of intrinsic you have.
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
src/glsl/nir/nir.h |3 +++
src/glsl/nir/nir_lower_io.c | 42 ++
2 files changed, 45 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 4ed2cbd..beabcaf 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1933,6 +1933,9 @@ void nir_assign_var_locations(struct exec_list *var_list,
void nir_lower_io(nir_shader *shader,
nir_variable_mode mode,
int (*type_size)(const struct glsl_type *));
+nir_src *nir_get_io_indirect_src(nir_intrinsic_instr *instr);
+nir_src *nir_get_io_vertex_index_src(nir_intrinsic_instr *instr);
+
void nir_lower_vars_to_ssa(nir_shader *shader);
bool nir_remove_dead_variables(nir_shader *shader);
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 8a4177f..00a3145 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -328,3 +328,45 @@ nir_lower_io(nir_shader *shader, nir_variable_mode mode,
nir_lower_io_impl(overload->impl, mode, type_size);
}
}
+
+/**
+ * Return the indirect source for a load/store indirect intrinsic.
+ */
+nir_src *
+nir_get_io_indirect_src(nir_intrinsic_instr *instr)
+{
+ switch (instr->intrinsic) {
+ case nir_intrinsic_load_input_indirect:
+ case nir_intrinsic_load_output_indirect:
+ case nir_intrinsic_load_uniform_indirect:
+ return &instr->src[0];
+ case nir_intrinsic_load_per_vertex_input_indirect:
+ case nir_intrinsic_load_per_vertex_output_indirect:
+ case nir_intrinsic_store_output_indirect:
+ return &instr->src[1];
+ case nir_intrinsic_store_per_vertex_output_indirect:
+ return &instr->src[2];
+ default:
+ return NULL;
+ }
+}
+
+/**
+ * Return the vertex index source for a load/store per_vertex intrinsic.
+ */
+nir_src *
+nir_get_io_vertex_index_src(nir_intrinsic_instr *instr)
+{
+ switch (instr->intrinsic) {
+ case nir_intrinsic_load_per_vertex_input:
+ case nir_intrinsic_load_per_vertex_output:
+ case nir_intrinsic_load_per_vertex_input_indirect:
+ case nir_intrinsic_load_per_vertex_output_indirect:
+ return &instr->src[0];
+ case nir_intrinsic_store_per_vertex_output:
+ case nir_intrinsic_store_per_vertex_output_indirect:
+ return &instr->src[1];
+ default:
+ return NULL;
+ }
+}
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Mesa (master): i965: Make convert_attr_sources_to_hw_regs handle stride == 0.
Module: Mesa Branch: master Commit: f88c175a29bb287d41ef90343eb6670525475a06 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f88c175a29bb287d41ef90343eb6670525475a06 Author: Kenneth Graunke Date: Wed Nov 11 22:37:53 2015 -0800 i965: Make convert_attr_sources_to_hw_regs handle stride == 0. This makes expressions like component(fs_reg(ATTR, n), 7) get a proper <0,1,0> region instead of the invalid <0,8,0>. Nobody uses this today, but I plan to. v2: Rebase on Matt's changes; simplify. Signed-off-by: Kenneth Graunke Reviewed-by: Matt Turner [v1] --- src/mesa/drivers/dri/i965/brw_fs.cpp |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index b8c88f7..b8d48da 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1614,11 +1614,12 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) inst->src[i].nr + inst->src[i].reg_offset; + unsigned width = inst->src[i].stride == 0 ? 1 : inst->exec_size; struct brw_reg reg = stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type), inst->src[i].subreg_offset), inst->exec_size * inst->src[i].stride, - inst->exec_size, inst->src[i].stride); + width, inst->src[i].stride); reg.abs = inst->src[i].abs; reg.negate = inst->src[i].negate; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta/generate_mipmap: Don't leak the sampler object
Module: Mesa Branch: master Commit: 758f12fd98dea9a9682becf2d496bd38ef3959e5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=758f12fd98dea9a9682becf2d496bd38ef3959e5 Author: Ian Romanick Date: Tue Nov 10 12:36:58 2015 -0800 meta/generate_mipmap: Don't leak the sampler object Signed-off-by: Ian Romanick Cc: "10.6 11.0" Reviewed-by: Anuj Phogat --- src/mesa/drivers/common/meta_generate_mipmap.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c b/src/mesa/drivers/common/meta_generate_mipmap.c index 4800278..a9da0a2 100644 --- a/src/mesa/drivers/common/meta_generate_mipmap.c +++ b/src/mesa/drivers/common/meta_generate_mipmap.c @@ -128,6 +128,8 @@ _mesa_meta_glsl_generate_mipmap_cleanup(struct gen_mipmap_state *mipmap) mipmap->VAO = 0; _mesa_DeleteBuffers(1, &mipmap->VBO); mipmap->VBO = 0; + _mesa_DeleteSamplers(1, &mipmap->Sampler); + mipmap->Sampler = 0; _mesa_meta_blit_shader_table_cleanup(&mipmap->shaders); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Silence unused parameter warnings in get_buffer_rect
Module: Mesa
Branch: master
Commit: 1cb49eedb52c387caf6a0035e5baad29bb55e3ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cb49eedb52c387caf6a0035e5baad29bb55e3ff
Author: Ian Romanick
Date: Mon Nov 2 14:29:42 2015 -0800
i965: Silence unused parameter warnings in get_buffer_rect
brw_meta_fast_clear.c: In function 'get_buffer_rect':
brw_meta_fast_clear.c:318:37: warning: unused parameter 'brw'
[-Wunused-parameter]
get_buffer_rect(struct brw_context *brw, struct gl_framebuffer *fb,
^
brw_meta_fast_clear.c:319:44: warning: unused parameter 'irb'
[-Wunused-parameter]
struct intel_renderbuffer *irb, struct rect *rect)
^
Signed-off-by: Ian Romanick
Reviewed-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 69fe7b4..12e7c32 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -314,8 +314,7 @@ get_fast_clear_rect(struct gl_framebuffer *fb,
}
static void
-get_buffer_rect(struct brw_context *brw, struct gl_framebuffer *fb,
-struct intel_renderbuffer *irb, struct rect *rect)
+get_buffer_rect(const struct gl_framebuffer *fb, struct rect *rect)
{
rect->x0 = fb->_Xmin;
rect->x1 = fb->_Xmax;
@@ -526,12 +525,12 @@ brw_meta_fast_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
case REP_CLEAR:
rep_clear_buffers |= 1 << index;
- get_buffer_rect(brw, fb, irb, &clear_rect);
+ get_buffer_rect(fb, &clear_rect);
break;
case PLAIN_CLEAR:
plain_clear_buffers |= 1 << index;
- get_buffer_rect(brw, fb, irb, &clear_rect);
+ get_buffer_rect(fb, &clear_rect);
continue;
}
}
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Mesa (master): i965: Silence warning.
Module: Mesa
Branch: master
Commit: 386759b02dac1382072cecef4d6520a0770f995e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=386759b02dac1382072cecef4d6520a0770f995e
Author: Matt Turner
Date: Fri Nov 13 12:13:14 2015 -0800
i965: Silence warning.
intel_asm_annotation.c: In function ‘annotation_insert_error’:
intel_asm_annotation.c:214:18:
warning: ‘ann’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
ann->error = ralloc_strdup(annotation->mem_ctx, error);
^
I initially tried changing the type of ann_count to unsigned (is
currently int), since that in addition to the check that it's non-zero
at the beginning of the function seems sufficient to prove that it must
be greater than zero. Unfortunately that wasn't sufficient.
---
src/mesa/drivers/dri/i965/intel_asm_annotation.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
index 52878fd..bb7786b 100644
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
@@ -185,6 +185,8 @@ annotation_insert_error(struct annotation_info *annotation,
unsigned offset,
if (!annotation_array_ensure_space(annotation))
return;
+ assume(annotation->ann_count > 0);
+
for (int i = 0; i < annotation->ann_count; i++) {
struct annotation *cur = &annotation->ann[i];
struct annotation *next = &annotation->ann[i + 1];
@@ -206,8 +208,6 @@ annotation_insert_error(struct annotation_info *annotation,
unsigned offset,
break;
}
- assume(ann != NULL);
-
if (ann->error)
ralloc_strcat(&ann->error, error);
else
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Mesa (master): i965: Remove unneeded #includes.
Module: Mesa Branch: master Commit: 7a879e422bcdaf89bde286de6c7b9db5c34f7fc3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a879e422bcdaf89bde286de6c7b9db5c34f7fc3 Author: Matt Turner Date: Fri Nov 13 12:16:48 2015 -0800 i965: Remove unneeded #includes. Some of these are no longer needed since all the backends switched to NIR. --- src/mesa/drivers/dri/i965/intel_asm_annotation.c |4 1 file changed, 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c b/src/mesa/drivers/dri/i965/intel_asm_annotation.c index bb7786b..fdd605a 100644 --- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c +++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c @@ -23,12 +23,8 @@ #include "brw_cfg.h" #include "brw_eu.h" -#include "brw_context.h" #include "intel_debug.h" #include "intel_asm_annotation.h" -#include "program/prog_print.h" -#include "program/prog_instruction.h" -#include "main/macros.h" #include "glsl/nir/nir.h" void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don't write beyond allocated memory.
Module: Mesa
Branch: master
Commit: 8b145d6a3de381a568d8001131e48257611a542a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b145d6a3de381a568d8001131e48257611a542a
Author: Juha-Pekka Heikkila
Date: Fri Nov 13 13:36:43 2015 +0200
i965: Don't write beyond allocated memory.
Reviewed-by: Eduardo Lima Mitev
Reviewed-by: Matt Turner
Signed-off-by: Juha-Pekka Heikkila
---
src/mesa/drivers/dri/i965/brw_eu_validate.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c
b/src/mesa/drivers/dri/i965/brw_eu_validate.c
index eb57962..2de2ea1 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_validate.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_validate.c
@@ -39,7 +39,7 @@ cat(struct string *dest, const struct string src)
{
dest->str = realloc(dest->str, dest->len + src.len + 1);
memcpy(dest->str + dest->len, src.str, src.len);
- dest->str[dest->len + src.len + 1] = '\0';
+ dest->str[dest->len + src.len] = '\0';
dest->len = dest->len + src.len;
}
#define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
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Mesa (master): i965: Make backend_reg inherit from brw_reg.
Module: Mesa
Branch: master
Commit: c7ed5d1d1ca5d0e537cd5eb2cc8d4cae7ae73564
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7ed5d1d1ca5d0e537cd5eb2cc8d4cae7ae73564
Author: Matt Turner
Date: Sat Oct 24 14:32:03 2015 -0700
i965: Make backend_reg inherit from brw_reg.
Some fields (file, type, abs, negate) in brw_reg are shadowed by
backend_reg.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.h |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 29baebf..e1e89dd 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -48,16 +48,15 @@ enum PACKED register_file {
UNIFORM, /* prog_data->params[reg] */
};
-struct backend_reg
-{
#ifdef __cplusplus
+struct backend_reg : public brw_reg
+{
bool is_zero() const;
bool is_one() const;
bool is_negative_one() const;
bool is_null() const;
bool is_accumulator() const;
bool in_range(const backend_reg &r, unsigned n) const;
-#endif
enum register_file file; /**< Register file: GRF, MRF, IMM. */
enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */
@@ -87,6 +86,7 @@ struct backend_reg
bool negate;
bool abs;
};
+#endif
struct cfg_t;
struct bblock_t;
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Mesa (master): i965/fs: Replace nested ternary with if ladder.
Module: Mesa
Branch: master
Commit: 88f349c4e100acd5dd3e7137496444907a175c39
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88f349c4e100acd5dd3e7137496444907a175c39
Author: Matt Turner
Date: Thu Nov 12 16:02:22 2015 -0800
i965/fs: Replace nested ternary with if ladder.
Since the types of the expression were
bool ? src_reg : (bool ? brw_reg : brw_reg)
the result of the second (nested) ternary would be implicitly
converted to a src_reg by the src_reg(struct brw_reg) constructor. I.e.,
bool ? src_reg : src_reg(bool ? brw_reg : brw_reg)
In the next patch, I make backend_reg (the parent of src_reg) inherit
from brw_reg, which changes this expression to return brw_reg, which
throws away any fields that exist in the classes derived from brw_reg.
I.e.,
src_reg(bool ? brw_reg(src_reg) : bool ? brw_reg : brw_reg)
Generally this code was gross, and wasn't actually shorter or easier to
read than an if ladder.
Reviewed-by: Kenneth Graunke
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index f121f34..d5763f6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -224,12 +224,13 @@ namespace brw {
src_reg
sample_mask_reg() const
{
- const bool uses_kill =
-(shader->stage == MESA_SHADER_FRAGMENT &&
- ((brw_wm_prog_data *)shader->stage_prog_data)->uses_kill);
- return (shader->stage != MESA_SHADER_FRAGMENT ? src_reg(0x) :
- uses_kill ? brw_flag_reg(0, 1) :
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD));
+ if (shader->stage != MESA_SHADER_FRAGMENT) {
+return src_reg(0x);
+ } else if (((brw_wm_prog_data *)shader->stage_prog_data)->uses_kill) {
+return brw_flag_reg(0, 1);
+ } else {
+return retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD);
+ }
}
/**
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Mesa (master): i965: Unwrap some lines.
Module: Mesa
Branch: master
Commit: 3048053908310eaf082058e5be34ae902e1fc02c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3048053908310eaf082058e5be34ae902e1fc02c
Author: Matt Turner
Date: Mon Oct 26 04:04:16 2015 -0700
i965: Unwrap some lines.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp|5 +
src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp |3 +--
src/mesa/drivers/dri/i965/brw_vec4.cpp |5 +
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp |3 +--
4 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c2d04d9..f589e6e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -417,10 +417,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
- this->ud = (vf0 << 0) |
- (vf1 << 8) |
- (vf2 << 16) |
- (vf3 << 24);
+ this->ud = (vf0 << 0) | (vf1 << 8) | (vf2 << 16) | (vf3 << 24);
}
fs_reg::fs_reg(struct brw_reg reg) :
diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
index c956459..234bbec 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
@@ -299,8 +299,7 @@ fs_visitor::opt_combine_constants()
reg->reg = table.imm[i].reg;
reg->subreg_offset = table.imm[i].subreg_offset;
reg->stride = 0;
- reg->negate = signbit(reg->f) !=
- signbit(table.imm[i].val);
+ reg->negate = signbit(reg->f) != signbit(table.imm[i].val);
assert(fabsf(reg->f) == table.imm[i].val);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 37170e7..8c2056b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -113,10 +113,7 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
- this->ud = (vf0 << 0) |
- (vf1 << 8) |
- (vf2 << 16) |
- (vf3 << 24);
+ this->ud = (vf0 << 0) | (vf1 << 8) | (vf2 << 16) | (vf3 << 24);
}
src_reg::src_reg(struct brw_reg reg) :
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index 523866e..2be7b14 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -147,8 +147,7 @@ try_constant_propagate(const struct brw_device_info
*devinfo,
}
if (value.type == BRW_REGISTER_TYPE_VF)
- value.ud = swizzle_vf_imm(value.ud,
- inst->src[arg].swizzle);
+ value.ud = swizzle_vf_imm(value.ud, inst->src[arg].swizzle);
switch (inst->opcode) {
case BRW_OPCODE_MOV:
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Mesa (master): i965/vec4: Remove swizzle/writemask fields from src/ dst_reg.
Module: Mesa
Branch: master
Commit: 58fa9d47b536403c4e3ca5d6a2495691338388fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58fa9d47b536403c4e3ca5d6a2495691338388fd
Author: Matt Turner
Date: Sun Oct 25 21:14:56 2015 -0700
i965/vec4: Remove swizzle/writemask fields from src/dst_reg.
Also allows us to handle HW_REGs in the swizzle() and writemask()
functions.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_ir_vec4.h |7 +--
src/mesa/drivers/dri/i965/brw_vec4.cpp |2 --
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 0b2a925..a19a262 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -55,8 +55,6 @@ public:
explicit src_reg(const dst_reg ®);
- unsigned swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
-
src_reg *reladdr;
};
@@ -82,7 +80,6 @@ offset(src_reg reg, unsigned delta)
static inline src_reg
swizzle(src_reg reg, unsigned swizzle)
{
- assert(reg.file != HW_REG);
reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
return reg;
}
@@ -122,8 +119,6 @@ public:
bool equals(const dst_reg &r) const;
- unsigned writemask; /**< Bitfield of WRITEMASK_[XYZW] */
-
src_reg *reladdr;
};
@@ -145,7 +140,7 @@ offset(dst_reg reg, unsigned delta)
static inline dst_reg
writemask(dst_reg reg, unsigned mask)
{
- assert(reg.file != HW_REG && reg.file != IMM);
+ assert(reg.file != IMM);
assert((reg.writemask & mask) != 0);
reg.writemask &= mask;
return reg;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 9155c2e..37170e7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -125,7 +125,6 @@ src_reg::src_reg(struct brw_reg reg) :
this->file = HW_REG;
this->reg = 0;
this->reg_offset = 0;
- this->swizzle = BRW_SWIZZLE_;
this->reladdr = NULL;
}
@@ -188,7 +187,6 @@ dst_reg::dst_reg(struct brw_reg reg) :
this->file = HW_REG;
this->reg = 0;
this->reg_offset = 0;
- this->writemask = WRITEMASK_XYZW;
this->reladdr = NULL;
}
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Mesa (master): i965: Delete type field from backend_reg.
Module: Mesa Branch: master Commit: 182f137521f9c81f89a473ca5a411e6a7c531e19 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=182f137521f9c81f89a473ca5a411e6a7c531e19 Author: Matt Turner Date: Sat Oct 24 15:04:23 2015 -0700 i965: Delete type field from backend_reg. Switching from an implicitly-sized type field to field with an explicit bit width is safe because we have fewer than 2^4 types, and gcc will warn if you attempt to set a value that will not fit. Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_shader.h |1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 73b57f4..3f435e2 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -59,7 +59,6 @@ struct backend_reg : public brw_reg bool in_range(const backend_reg &r, unsigned n) const; enum register_file file; /**< Register file: GRF, MRF, IMM. */ - enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */ /** * Register number. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Rename GRF to VGRF.
Module: Mesa Branch: master Commit: b163aa01487ab5f9b22c48b7badc5d65999c4985 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b163aa01487ab5f9b22c48b7badc5d65999c4985 Author: Matt Turner Date: Mon Oct 26 17:09:25 2015 -0700 i965: Rename GRF to VGRF. The 2-bit hardware register file field is ARF, GRF, MRF, IMM. Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to mean an assigned general purpose register. Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 104 ++-- src/mesa/drivers/dri/i965/brw_fs.h |2 +- src/mesa/drivers/dri/i965/brw_fs_builder.h |4 +- .../drivers/dri/i965/brw_fs_cmod_propagation.cpp |2 +- .../drivers/dri/i965/brw_fs_combine_constants.cpp |4 +- .../drivers/dri/i965/brw_fs_copy_propagation.cpp | 26 ++--- src/mesa/drivers/dri/i965/brw_fs_cse.cpp |6 +- .../dri/i965/brw_fs_dead_code_eliminate.cpp|6 +- src/mesa/drivers/dri/i965/brw_fs_generator.cpp |4 +- .../drivers/dri/i965/brw_fs_live_variables.cpp |6 +- src/mesa/drivers/dri/i965/brw_fs_nir.cpp |6 +- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 ++--- .../drivers/dri/i965/brw_fs_register_coalesce.cpp |8 +- .../dri/i965/brw_fs_saturate_propagation.cpp |6 +- src/mesa/drivers/dri/i965/brw_fs_validate.cpp |4 +- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 +-- src/mesa/drivers/dri/i965/brw_ir_fs.h |6 +- .../drivers/dri/i965/brw_schedule_instructions.cpp | 26 ++--- src/mesa/drivers/dri/i965/brw_shader.h |4 +- src/mesa/drivers/dri/i965/brw_vec4.cpp | 32 +++--- src/mesa/drivers/dri/i965/brw_vec4_builder.h |2 +- .../drivers/dri/i965/brw_vec4_cmod_propagation.cpp |2 +- .../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 14 +-- src/mesa/drivers/dri/i965/brw_vec4_cse.cpp |4 +- .../dri/i965/brw_vec4_dead_code_eliminate.cpp |8 +- .../drivers/dri/i965/brw_vec4_live_variables.cpp |8 +- .../drivers/dri/i965/brw_vec4_live_variables.h |4 +- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |8 +- .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 26 ++--- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +-- 30 files changed, 194 insertions(+), 194 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=b163aa01487ab5f9b22c48b7badc5d65999c4985 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Replace HW_REG with ARF/FIXED_GRF.
Module: Mesa
Branch: master
Commit: b3315a6f56fb93f2884168cbf9358b2606641db5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3315a6f56fb93f2884168cbf9358b2606641db5
Author: Matt Turner
Date: Mon Oct 26 17:52:57 2015 -0700
i965: Replace HW_REG with ARF/FIXED_GRF.
HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to
look at different fields for type, abs, negate, writemask, swizzle, and
a second file. They also caused annoying problems like immediate sources
being considered scheduling barriers (commit 6148e94e2) and other such
nonsense.
Instead use ARF/FIXED_GRF/MRF for fixed registers in those files.
After a sufficient amount of time has passed since "GRF" was used, we
can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 120 -
src/mesa/drivers/dri/i965/brw_fs.h |5 +-
.../drivers/dri/i965/brw_fs_copy_propagation.cpp |3 +-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp |3 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |7 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |5 +-
src/mesa/drivers/dri/i965/brw_ir_fs.h |9 +-
src/mesa/drivers/dri/i965/brw_ir_vec4.h|6 +-
.../drivers/dri/i965/brw_schedule_instructions.cpp | 53 +++-
src/mesa/drivers/dri/i965/brw_shader.cpp |8 +-
src/mesa/drivers/dri/i965/brw_shader.h |5 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 141
src/mesa/drivers/dri/i965/brw_vec4_cse.cpp |3 +-
13 files changed, 157 insertions(+), 211 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ba42d71..9a89872 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -77,7 +77,8 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const
fs_reg &dst,
/* This will be the case for almost all instructions. */
switch (dst.file) {
case VGRF:
- case HW_REG:
+ case ARF:
+ case FIXED_GRF:
case MRF:
case ATTR:
this->regs_written = DIV_ROUND_UP(dst.component_size(exec_size),
@@ -423,7 +424,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
fs_reg::fs_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = HW_REG;
+ this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->subreg_offset = 0;
this->reladdr = NULL;
@@ -439,24 +440,17 @@ fs_reg::fs_reg(struct brw_reg reg) :
bool
fs_reg::equals(const fs_reg &r) const
{
- return (file == r.file &&
- nr == r.nr &&
+ return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
subreg_offset == r.subreg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
!reladdr && !r.reladdr &&
- (file != HW_REG ||
-memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
- (file != IMM || d == r.d) &&
stride == r.stride);
}
fs_reg &
fs_reg::set_smear(unsigned subreg)
{
- assert(file != HW_REG && file != IMM);
+ assert(file != ARF && file != FIXED_GRF && file != IMM);
subreg_offset = subreg * type_sz(type);
stride = 0;
return *this;
@@ -471,7 +465,7 @@ fs_reg::is_contiguous() const
unsigned
fs_reg::component_size(unsigned width) const
{
- const unsigned stride = (file != HW_REG ? this->stride :
+ const unsigned stride = ((file != ARF && file != FIXED_GRF) ? this->stride :
hstride == 0 ? 0 :
1 << (hstride - 1));
return MAX2(width * stride, 1) * type_sz(type);
@@ -857,9 +851,10 @@ fs_inst::regs_read(int arg) const
case UNIFORM:
case IMM:
return 1;
+ case ARF:
+ case FIXED_GRF:
case VGRF:
case ATTR:
- case HW_REG:
return DIV_ROUND_UP(components_read(arg) *
src[arg].component_size(exec_size),
REG_SIZE);
@@ -1596,12 +1591,12 @@ fs_visitor::assign_urb_setup()
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->opcode == FS_OPCODE_LINTERP) {
-assert(inst->src[1].file == HW_REG);
+assert(inst->src[1].file == FIXED_GRF);
inst->src[1].nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
-assert(inst->src[0].file == HW_REG);
+assert(inst->src[0].file == FIXED_GRF);
inst->src[0].nr += urb_start;
}
}
@@ -1682,7 +1677,7 @@ fs_visitor::assign_gs_urb_setup()
inst->base_mrf = -1;
}
- /* Rewrite all ATTR file references to HW_REGs. */
+ /* Rewrite all ATTR file references to GRFs. */
convert_attr_sources_to_hw_regs(inst);
}
}
@@
Mesa (master): i965: Move BAD_FILE from the beginning of enum register_file.
Module: Mesa
Branch: master
Commit: 5a23b31c75556fa0fe9ca53db481bbec18c2baba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a23b31c75556fa0fe9ca53db481bbec18c2baba
Author: Matt Turner
Date: Thu Oct 29 22:04:22 2015 -0700
i965: Move BAD_FILE from the beginning of enum register_file.
I'm going to begin using brw_reg's file field in backend_reg and its
derivatives, and in order to keep the hardware value for ARF as 0, we
have to do something different.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 67d623c..5632378 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -39,13 +39,13 @@
#define MAX_VGRF_SIZE 16
enum PACKED register_file {
- BAD_FILE,
GRF,
MRF,
IMM,
HW_REG, /* a struct brw_reg */
ATTR,
UNIFORM, /* prog_data->params[reg] */
+ BAD_FILE,
};
#ifdef __cplusplus
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Mesa (master): i965: Remove fixed_hw_reg field from backend_reg.
Module: Mesa
Branch: master
Commit: 94b1031703b1b5759436fe215323727cffce5f86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94b1031703b1b5759436fe215323727cffce5f86
Author: Matt Turner
Date: Sat Oct 24 15:29:03 2015 -0700
i965: Remove fixed_hw_reg field from backend_reg.
Since backend_reg now inherits brw_reg, we can use it in place of the
fixed_hw_reg field.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 93 -
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |9 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |4 +-
src/mesa/drivers/dri/i965/brw_ir_fs.h |4 +-
src/mesa/drivers/dri/i965/brw_ir_vec4.h|4 +-
.../drivers/dri/i965/brw_schedule_instructions.cpp | 50 -
src/mesa/drivers/dri/i965/brw_shader.cpp |8 +-
src/mesa/drivers/dri/i965/brw_shader.h |5 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 110 +---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 12 +--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 -
11 files changed, 139 insertions(+), 162 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 931a8fd..c2d04d9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -423,13 +423,15 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
(vf3 << 24);
}
-/** Fixed brw_reg. */
-fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
+fs_reg::fs_reg(struct brw_reg reg) :
+ backend_reg(reg)
{
- init();
this->file = HW_REG;
- this->fixed_hw_reg = fixed_hw_reg;
- this->type = fixed_hw_reg.type;
+ this->reg = 0;
+ this->reg_offset = 0;
+ this->subreg_offset = 0;
+ this->reladdr = NULL;
+ this->stride = 1;
}
bool
@@ -444,8 +446,7 @@ fs_reg::equals(const fs_reg &r) const
abs == r.abs &&
!reladdr && !r.reladdr &&
(file != HW_REG ||
-memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
- sizeof(fixed_hw_reg)) == 0) &&
+memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
(file != IMM || d == r.d) &&
stride == r.stride);
}
@@ -469,8 +470,8 @@ unsigned
fs_reg::component_size(unsigned width) const
{
const unsigned stride = (file != HW_REG ? this->stride :
-fixed_hw_reg.hstride == 0 ? 0 :
-1 << (fixed_hw_reg.hstride - 1));
+hstride == 0 ? 0 :
+1 << (hstride - 1));
return MAX2(width * stride, 1) * type_sz(type);
}
@@ -961,7 +962,6 @@ fs_visitor::vgrf(const glsl_type *const type)
brw_type_for_base_type(type));
}
-/** Fixed HW reg constructor. */
fs_reg::fs_reg(enum register_file file, int reg)
{
init();
@@ -971,7 +971,6 @@ fs_reg::fs_reg(enum register_file file, int reg)
this->stride = (file == UNIFORM ? 0 : 1);
}
-/** Fixed HW reg constructor. */
fs_reg::fs_reg(enum register_file file, int reg, enum brw_reg_type type)
{
init();
@@ -1476,10 +1475,11 @@ fs_visitor::assign_curb_setup()
struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs +
constant_nr / 8,
constant_nr % 8);
+brw_reg.abs = inst->src[i].abs;
+brw_reg.negate = inst->src[i].negate;
assert(inst->src[i].stride == 0);
- inst->src[i].file = HW_REG;
- inst->src[i].fixed_hw_reg = byte_offset(
+inst->src[i] = byte_offset(
retype(brw_reg, inst->src[i].type),
inst->src[i].subreg_offset);
}
@@ -1595,12 +1595,12 @@ fs_visitor::assign_urb_setup()
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->opcode == FS_OPCODE_LINTERP) {
assert(inst->src[1].file == HW_REG);
-inst->src[1].fixed_hw_reg.nr += urb_start;
+ inst->src[1].nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
assert(inst->src[0].file == HW_REG);
-inst->src[0].fixed_hw_reg.nr += urb_start;
+ inst->src[0].nr += urb_start;
}
}
@@ -1618,12 +1618,15 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst)
inst->src[i].reg +
inst->src[i].reg_offset;
- inst->src[i].file = HW_REG;
- inst->src[i].fixed_hw_reg =
+ struct brw_reg reg =
stride(byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type),
inst->src[i].subreg_offset),
inst->exec_size * inst->src[i].stride,
inst->exec_size, inst->src[i].stride);
+ reg.abs = inst->src[i].abs;
+ reg.negate = inst->sr
Mesa (master): i965/fs: Set stride correctly for immediates in fs_reg( brw_reg).
Module: Mesa
Branch: master
Commit: 4b0fbebf024e564c195f3ce94e1ce43a3d6442ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b0fbebf024e564c195f3ce94e1ce43a3d6442ea
Author: Matt Turner
Date: Mon Nov 2 00:25:04 2015 +
i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).
The fs_reg() constructors for immediates set stride to 0, except for
vector-immediates, which set stride to 1. This patch makes the fs_reg
constructor that takes a brw_reg do likewise, so that stride is set
correctly for cases such as fs_reg(brw_imm_v(...)).
The generator asserts that this is true (and presumably it's useful in
some optimization passes?) and the VF fs_reg constructors did this (by
virtue of the fact that it doesn't override what init() does).
In the next commit, calling this constructor with brw_imm_* will generate
an IMM file register rather than a HW_REG, making this change necessary
to avoid breakage with existing uses of brw_imm_v().
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e8ac1c2..ba42d71 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -428,6 +428,12 @@ fs_reg::fs_reg(struct brw_reg reg) :
this->subreg_offset = 0;
this->reladdr = NULL;
this->stride = 1;
+ if (this->file == IMM &&
+ (this->type != BRW_REGISTER_TYPE_V &&
+this->type != BRW_REGISTER_TYPE_UV &&
+this->type != BRW_REGISTER_TYPE_VF)) {
+ this->stride = 0;
+ }
}
bool
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Mesa (master): i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().
Module: Mesa
Branch: master
Commit: b99e1fd547035be9a6da5ee1b78b8a853c2ef3e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b99e1fd547035be9a6da5ee1b78b8a853c2ef3e0
Author: Matt Turner
Date: Mon Nov 2 00:22:29 2015 +
i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().
We use brw_imm_v() to produce type-V immediates, which generates a
brw_reg with fs_reg's .file set to HW_REG. The next commit will rid us
of HW_REGs, so we need to handle BRW_REGISTER_TYPE_V in the IMM case.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 16257a9..6e17f23 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -111,6 +111,9 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned
gen)
case BRW_REGISTER_TYPE_VF:
brw_reg = brw_imm_vf(reg->ud);
break;
+ case BRW_REGISTER_TYPE_V:
+ brw_reg = brw_imm_v(reg->ud);
+ break;
default:
unreachable("not reached");
}
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Mesa (master): i965: Combine register file field.
Module: Mesa
Branch: master
Commit: 49b3215d7076db8b9afe8998b01ef250795b5892
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49b3215d7076db8b9afe8998b01ef250795b5892
Author: Matt Turner
Date: Mon Oct 26 18:41:27 2015 -0700
i965: Combine register file field.
The first four values (2-bits) are hardware values, and VGRF, ATTR, and
UNIFORM remain values used in the IR.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h | 11 +++
src/mesa/drivers/dri/i965/brw_fs.cpp|5 ++---
src/mesa/drivers/dri/i965/brw_ir_fs.h |4 ++--
src/mesa/drivers/dri/i965/brw_ir_vec4.h |8
src/mesa/drivers/dri/i965/brw_reg.h |4 ++--
src/mesa/drivers/dri/i965/brw_shader.h | 13 -
src/mesa/drivers/dri/i965/brw_vec4.cpp | 16 ++--
7 files changed, 27 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 4735030..5044982 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1404,6 +1404,17 @@ enum PACKED brw_reg_file {
BRW_GENERAL_REGISTER_FILE = 1,
BRW_MESSAGE_REGISTER_FILE = 2,
BRW_IMMEDIATE_VALUE= 3,
+
+ ARF = BRW_ARCHITECTURE_REGISTER_FILE,
+ FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
+ MRF = BRW_MESSAGE_REGISTER_FILE,
+ IMM = BRW_IMMEDIATE_VALUE,
+
+ /* These are not hardware values */
+ VGRF,
+ ATTR,
+ UNIFORM, /* prog_data->params[reg] */
+ BAD_FILE,
};
#define BRW_HW_REG_TYPE_UD 0
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9a89872..b8c88f7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -424,7 +424,6 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
fs_reg::fs_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->subreg_offset = 0;
this->reladdr = NULL;
@@ -959,7 +958,7 @@ fs_visitor::vgrf(const glsl_type *const type)
brw_type_for_base_type(type));
}
-fs_reg::fs_reg(enum register_file file, int nr)
+fs_reg::fs_reg(enum brw_reg_file file, int nr)
{
init();
this->file = file;
@@ -968,7 +967,7 @@ fs_reg::fs_reg(enum register_file file, int nr)
this->stride = (file == UNIFORM ? 0 : 1);
}
-fs_reg::fs_reg(enum register_file file, int nr, enum brw_reg_type type)
+fs_reg::fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type)
{
init();
this->file = file;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 61e72f7..7e977e9 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -42,8 +42,8 @@ public:
explicit fs_reg(uint8_t vf[4]);
explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
fs_reg(struct brw_reg reg);
- fs_reg(enum register_file file, int nr);
- fs_reg(enum register_file file, int nr, enum brw_reg_type type);
+ fs_reg(enum brw_reg_file file, int nr);
+ fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
bool equals(const fs_reg &r) const;
bool is_contiguous() const;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index dcec5f3..110e64b 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -39,7 +39,7 @@ public:
void init();
- src_reg(register_file file, int nr, const glsl_type *type);
+ src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
src_reg();
src_reg(float f);
src_reg(uint32_t u);
@@ -108,10 +108,10 @@ public:
void init();
dst_reg();
- dst_reg(register_file file, int nr);
- dst_reg(register_file file, int nr, const glsl_type *type,
+ dst_reg(enum brw_reg_file file, int nr);
+ dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
unsigned writemask);
- dst_reg(register_file file, int nr, brw_reg_type type,
+ dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
unsigned writemask);
dst_reg(struct brw_reg reg);
dst_reg(class vec4_visitor *v, const struct glsl_type *type);
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index a2f4155..3da83b4 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -232,11 +232,11 @@ const char *brw_reg_type_letters(unsigned brw_reg_type);
*/
struct brw_reg {
enum brw_reg_type type:4;
- enum brw_reg_file file:2;
+ enum brw_reg_file file:3; /* :2 hardware format */
unsigned negate:1; /* source only */
unsigned abs:1;/* source only */
unsigned address_mode:1; /* relative addressing, hopefully! */
- unsigned pad0:2;
+ unsigned pad0:1;
uns
Mesa (master): i965: Use BRW_MRF_COMPR4 macro in more places.
Module: Mesa
Branch: master
Commit: 0eb3db117b56b081ee2674cc8940c193ffc3c41b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0eb3db117b56b081ee2674cc8940c193ffc3c41b
Author: Matt Turner
Date: Mon Nov 2 10:23:12 2015 -0800
i965: Use BRW_MRF_COMPR4 macro in more places.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_disasm.c |4 ++--
src/mesa/drivers/dri/i965/brw_eu_emit.c|4 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp |2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 76b9bed..650bdee 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -725,7 +725,7 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
/* Clear the Compr4 instruction compression bit. */
if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
- _reg_nr &= ~(1 << 7);
+ _reg_nr &= ~BRW_MRF_COMPR4;
if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (_reg_nr & 0xf0) {
@@ -1649,7 +1649,7 @@ brw_disassemble_inst(FILE *file, const struct
brw_device_info *devinfo,
if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED
&&
opcode_descs[opcode].ndst > 0 &&
brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE
&&
- brw_inst_dst_da_reg_nr(devinfo, inst) & (1 << 7)) {
+ brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) {
format(file, " compr4");
} else {
err |= control(file, "compression control", compr_ctrl,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ec04d7d..da1ddfd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -147,7 +147,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct
brw_reg dest)
const struct brw_device_info *devinfo = p->devinfo;
if (dest.file == BRW_MESSAGE_REGISTER_FILE)
- assert((dest.nr & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen));
+ assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
else if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE)
assert(dest.nr < 128);
@@ -311,7 +311,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct
brw_reg reg)
const struct brw_device_info *devinfo = p->devinfo;
if (reg.file == BRW_MESSAGE_REGISTER_FILE)
- assert((reg.nr & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen));
+ assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
else if (reg.file != BRW_ARCHITECTURE_REGISTER_FILE)
assert(reg.nr < 128);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index fa1e834..e986021 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -61,7 +61,7 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
switch (reg->file) {
case MRF:
- assert((reg->nr & ~(1 << 7)) < BRW_MAX_MRF(gen));
+ assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
/* Fallthrough */
case VGRF:
if (reg->stride == 0) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c39e854..a086b43 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1808,7 +1808,7 @@ vec4_visitor::convert_to_hw_regs()
break;
case MRF:
- assert(((dst.nr + dst.reg_offset) & ~(1 << 7)) <
BRW_MAX_MRF(devinfo->gen));
+ assert(((dst.nr + dst.reg_offset) & ~BRW_MRF_COMPR4) <
BRW_MAX_MRF(devinfo->gen));
reg = brw_message_reg(dst.nr + dst.reg_offset);
reg.type = dst.type;
reg.writemask = dst.writemask;
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Mesa (master): i965: Initialize registers.
Module: Mesa
Branch: master
Commit: dba309fc14d1ca99251c8f8115d2a26ac86f14f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dba309fc14d1ca99251c8f8115d2a26ac86f14f6
Author: Matt Turner
Date: Fri Oct 30 13:53:38 2015 -0700
i965: Initialize registers.
The test (file == BAD_FILE) works on registers for which the constructor
has not run because BAD_FILE is zero. The next commit will move
BAD_FILE in the enum so that it's no longer zero.
In the case of this->outputs, the constructor was being run implicitly,
and we were unnecessarily memsetting is to zero.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |1 -
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |9 +
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 73b09f5..7a91985 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -262,6 +262,10 @@ void
fs_visitor::nir_emit_system_values()
{
nir_system_values = ralloc_array(mem_ctx, fs_reg, SYSTEM_VALUE_MAX);
+ for (unsigned i = 0; i < SYSTEM_VALUE_MAX; i++) {
+ nir_system_values[i] = fs_reg();
+ }
+
nir_foreach_overload(nir, overload) {
assert(strcmp(overload->function->name, "main") == 0);
assert(overload->impl);
@@ -272,7 +276,11 @@ fs_visitor::nir_emit_system_values()
void
fs_visitor::nir_emit_impl(nir_function_impl *impl)
{
- nir_locals = reralloc(mem_ctx, nir_locals, fs_reg, impl->reg_alloc);
+ nir_locals = ralloc_array(mem_ctx, fs_reg, impl->reg_alloc);
+ for (unsigned i = 0; i < impl->reg_alloc; i++) {
+ nir_locals[i] = fs_reg();
+ }
+
foreach_list_typed(nir_register, reg, node, &impl->registers) {
unsigned array_elems =
reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index da7e9ca..4b9f975 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1190,7 +1190,6 @@ fs_visitor::init()
this->nir_ssa_values = NULL;
memset(&this->payload, 0, sizeof(this->payload));
- memset(this->outputs, 0, sizeof(this->outputs));
memset(this->output_components, 0, sizeof(this->output_components));
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index e0d5a14..8b6912e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -106,6 +106,9 @@ void
vec4_visitor::nir_setup_system_values()
{
nir_system_values = ralloc_array(mem_ctx, dst_reg, SYSTEM_VALUE_MAX);
+ for (unsigned i = 0; i < SYSTEM_VALUE_MAX; i++) {
+ nir_system_values[i] = dst_reg();
+ }
nir_foreach_overload(nir, overload) {
assert(strcmp(overload->function->name, "main") == 0);
@@ -118,6 +121,9 @@ void
vec4_visitor::nir_setup_inputs()
{
nir_inputs = ralloc_array(mem_ctx, src_reg, nir->num_inputs);
+ for (unsigned i = 0; i < nir->num_inputs; i++) {
+ nir_inputs[i] = dst_reg();
+ }
nir_foreach_variable(var, &nir->inputs) {
int offset = var->data.driver_location;
@@ -148,6 +154,9 @@ void
vec4_visitor::nir_emit_impl(nir_function_impl *impl)
{
nir_locals = ralloc_array(mem_ctx, dst_reg, impl->reg_alloc);
+ for (unsigned i = 0; i < impl->reg_alloc; i++) {
+ nir_locals[i] = dst_reg();
+ }
foreach_list_typed(nir_register, reg, node, &impl->registers) {
unsigned array_elems =
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Mesa (master): i965: Add and use enum brw_reg_file.
Module: Mesa
Branch: master
Commit: d74dd703f80ff40047ad8360e66ffd70b80f7230
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d74dd703f80ff40047ad8360e66ffd70b80f7230
Author: Matt Turner
Date: Fri Oct 23 13:11:44 2015 -0700
i965: Add and use enum brw_reg_file.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h| 10 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c|2 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp |5 +++--
src/mesa/drivers/dri/i965/brw_reg.h| 25
4 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 62bdb1f..4735030 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1399,10 +1399,12 @@ enum PACKED brw_predicate {
BRW_PREDICATE_ALIGN16_ALL4H = 7,
};
-#define BRW_ARCHITECTURE_REGISTER_FILE0
-#define BRW_GENERAL_REGISTER_FILE 1
-#define BRW_MESSAGE_REGISTER_FILE 2
-#define BRW_IMMEDIATE_VALUE 3
+enum PACKED brw_reg_file {
+ BRW_ARCHITECTURE_REGISTER_FILE = 0,
+ BRW_GENERAL_REGISTER_FILE = 1,
+ BRW_MESSAGE_REGISTER_FILE = 2,
+ BRW_IMMEDIATE_VALUE= 3,
+};
#define BRW_HW_REG_TYPE_UD 0
#define BRW_HW_REG_TYPE_D 1
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 775027d..ec04d7d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -92,7 +92,7 @@ gen7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg
*reg)
*/
unsigned
brw_reg_type_to_hw_type(const struct brw_device_info *devinfo,
-enum brw_reg_type type, unsigned file)
+enum brw_reg_type type, enum brw_reg_file file)
{
if (file == BRW_IMMEDIATE_VALUE) {
static const int imm_hw_types[] = {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 5fd104a..7de1669 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -33,7 +33,8 @@
#include "brw_fs.h"
#include "brw_cfg.h"
-static uint32_t brw_file_from_reg(fs_reg *reg)
+static enum brw_reg_file
+brw_file_from_reg(fs_reg *reg)
{
switch (reg->file) {
case GRF:
@@ -48,7 +49,7 @@ static uint32_t brw_file_from_reg(fs_reg *reg)
case UNIFORM:
unreachable("not reached");
}
- return 0;
+ return BRW_ARCHITECTURE_REGISTER_FILE;
}
static struct brw_reg
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index d434383..8fc2fee 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -219,7 +219,7 @@ enum PACKED brw_reg_type {
};
unsigned brw_reg_type_to_hw_type(const struct brw_device_info *devinfo,
- enum brw_reg_type type, unsigned file);
+ enum brw_reg_type type, enum brw_reg_file
file);
const char *brw_reg_type_letters(unsigned brw_reg_type);
#define REG_SIZE (8*4)
@@ -232,7 +232,7 @@ const char *brw_reg_type_letters(unsigned brw_reg_type);
*/
struct brw_reg {
enum brw_reg_type type:4;
- unsigned file:2;
+ enum brw_reg_file file:2;
unsigned nr:8;
unsigned subnr:5; /* :1 in align16 */
unsigned negate:1; /* source only */
@@ -329,7 +329,7 @@ type_is_signed(unsigned type)
* \param writemask WRITEMASK_X/Y/Z/W bitfield
*/
static inline struct brw_reg
-brw_reg(unsigned file,
+brw_reg(enum brw_reg_file file,
unsigned nr,
unsigned subnr,
unsigned negate,
@@ -378,7 +378,7 @@ brw_reg(unsigned file,
/** Construct float[16] register */
static inline struct brw_reg
-brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr)
+brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return brw_reg(file,
nr,
@@ -395,7 +395,7 @@ brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr)
/** Construct float[8] register */
static inline struct brw_reg
-brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr)
+brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return brw_reg(file,
nr,
@@ -412,7 +412,7 @@ brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr)
/** Construct float[4] register */
static inline struct brw_reg
-brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr)
+brw_vec4_reg(enum brw_reg_file file, unsigned nr, unsigned subnr)
{
return brw_reg(file,
nr,
@@ -429,7 +429,7 @@ brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr)
/** Construct float[2] register */
static inline struct brw_reg
-brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr)
+brw_vec2_reg(enum brw_reg_file file,
Mesa (master): i965: Use brw_reg's nr field to store register number.
Module: Mesa Branch: master Commit: 7638e75cf99263c1ee8e31c6cc5a319feec2c943 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7638e75cf99263c1ee8e31c6cc5a319feec2c943 Author: Matt Turner Date: Mon Oct 26 04:35:14 2015 -0700 i965: Use brw_reg's nr field to store register number. In addition to combining another field, we get replace silliness like "reg.reg" with something that actually makes sense, "reg.nr"; and no one will ever wonder again why dst.reg isn't a dst_reg. Moving the now 16-bit nr field to a 16-bit boundary decreases code size by about 3k. Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 163 ++-- .../drivers/dri/i965/brw_fs_combine_constants.cpp |8 +- .../drivers/dri/i965/brw_fs_copy_propagation.cpp | 18 +-- src/mesa/drivers/dri/i965/brw_fs_cse.cpp |2 +- src/mesa/drivers/dri/i965/brw_fs_generator.cpp |8 +- src/mesa/drivers/dri/i965/brw_fs_live_variables.h |2 +- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 34 ++-- .../drivers/dri/i965/brw_fs_register_coalesce.cpp | 22 +-- .../dri/i965/brw_fs_saturate_propagation.cpp |2 +- src/mesa/drivers/dri/i965/brw_fs_validate.cpp |4 +- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |2 +- src/mesa/drivers/dri/i965/brw_ir_fs.h |6 +- src/mesa/drivers/dri/i965/brw_ir_vec4.h|8 +- src/mesa/drivers/dri/i965/brw_reg.h| 10 +- .../drivers/dri/i965/brw_schedule_instructions.cpp | 62 src/mesa/drivers/dri/i965/brw_shader.cpp |2 +- src/mesa/drivers/dri/i965/brw_shader.h |9 -- src/mesa/drivers/dri/i965/brw_vec4.cpp | 100 ++-- .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |6 +- src/mesa/drivers/dri/i965/brw_vec4_cse.cpp |2 +- .../drivers/dri/i965/brw_vec4_live_variables.h | 12 +- .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 36 ++--- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 40 ++--- .../dri/i965/test_vec4_copy_propagation.cpp|4 +- .../dri/i965/test_vec4_register_coalesce.cpp |4 +- 25 files changed, 276 insertions(+), 290 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=7638e75cf99263c1ee8e31c6cc5a319feec2c943 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Reorganize brw_reg fields.
Module: Mesa
Branch: master
Commit: 977df90d6538ae35a5463a6b098ba974d3f0143e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=977df90d6538ae35a5463a6b098ba974d3f0143e
Author: Matt Turner
Date: Fri Oct 23 12:17:03 2015 -0700
i965: Reorganize brw_reg fields.
Put fields that are meaningless with an immediate in the same storage
with the immediate. This leaves fields type, file, nr, subnr in the
first dword where there's now extra room for expansion.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_reg.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index af2a49b..d434383 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -237,18 +237,18 @@ struct brw_reg {
unsigned subnr:5; /* :1 in align16 */
unsigned negate:1; /* source only */
unsigned abs:1;/* source only */
- unsigned vstride:4;/* source only */
- unsigned width:3; /* src only, align1 only */
- unsigned hstride:2;/* align1 only */
unsigned address_mode:1; /* relative addressing, hopefully! */
- unsigned pad0:1;
+ unsigned pad0:10;
union {
struct {
unsigned swizzle:8; /* src only, align16 only */
unsigned writemask:4;/* dest only, align16 only */
int indirect_offset:10; /* relative addressing offset */
- unsigned pad1:10;/* two dwords total */
+ unsigned vstride:4; /* source only */
+ unsigned width:3;/* src only, align1 only */
+ unsigned hstride:2; /* align1 only */
+ unsigned pad1:1;
};
float f;
@@ -357,9 +357,6 @@ brw_reg(unsigned file,
reg.subnr = subnr * type_sz(type);
reg.negate = negate;
reg.abs = abs;
- reg.vstride = vstride;
- reg.width = width;
- reg.hstride = hstride;
reg.address_mode = BRW_ADDRESS_DIRECT;
reg.pad0 = 0;
@@ -372,6 +369,9 @@ brw_reg(unsigned file,
reg.swizzle = swizzle;
reg.writemask = writemask;
reg.indirect_offset = 0;
+ reg.vstride = vstride;
+ reg.width = width;
+ reg.hstride = hstride;
reg.pad1 = 0;
return reg;
}
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Mesa (master): i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.
Module: Mesa Branch: master Commit: e42fb0c2a687cdcd6af2a590f6f5e24f64cfff3b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e42fb0c2a687cdcd6af2a590f6f5e24f64cfff3b Author: Matt Turner Date: Thu Oct 22 19:41:30 2015 -0700 i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_eu_emit.c| 52 +++--- src/mesa/drivers/dri/i965/brw_ff_gs_emit.c |2 +- src/mesa/drivers/dri/i965/brw_fs.cpp | 74 ++-- .../drivers/dri/i965/brw_fs_combine_constants.cpp |6 +- .../drivers/dri/i965/brw_fs_copy_propagation.cpp |8 +-- src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 16 ++--- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 42 +-- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |4 +- src/mesa/drivers/dri/i965/brw_reg.h| 40 +-- src/mesa/drivers/dri/i965/brw_shader.cpp | 30 src/mesa/drivers/dri/i965/brw_vec4.cpp | 40 +-- .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |6 +- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 41 ++- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 +- 14 files changed, 185 insertions(+), 178 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=e42fb0c2a687cdcd6af2a590f6f5e24f64cfff3b ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use immediate storage in inherited brw_reg.
Module: Mesa
Branch: master
Commit: 1392e45bfb396ccbfa5bb0c6063522e0550988d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1392e45bfb396ccbfa5bb0c6063522e0550988d3
Author: Matt Turner
Date: Sat Oct 24 14:55:57 2015 -0700
i965: Use immediate storage in inherited brw_reg.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 80 ++--
.../drivers/dri/i965/brw_fs_combine_constants.cpp |6 +-
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 12 +--
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 16 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 +--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |4 +-
src/mesa/drivers/dri/i965/brw_shader.cpp | 10 +--
src/mesa/drivers/dri/i965/brw_vec4.cpp | 39 +-
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 10 +--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 +-
10 files changed, 96 insertions(+), 95 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f40d05d..931a8fd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -379,7 +379,7 @@ fs_reg::fs_reg(float f)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->stride = 0;
- this->fixed_hw_reg.f = f;
+ this->f = f;
}
/** Immediate value constructor. */
@@ -389,7 +389,7 @@ fs_reg::fs_reg(int32_t i)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->stride = 0;
- this->fixed_hw_reg.d = i;
+ this->d = i;
}
/** Immediate value constructor. */
@@ -399,7 +399,7 @@ fs_reg::fs_reg(uint32_t u)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->stride = 0;
- this->fixed_hw_reg.ud = u;
+ this->ud = u;
}
/** Vector float immediate value constructor. */
@@ -408,7 +408,7 @@ fs_reg::fs_reg(uint8_t vf[4])
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
- memcpy(&this->fixed_hw_reg.ud, vf, sizeof(unsigned));
+ memcpy(&this->ud, vf, sizeof(unsigned));
}
/** Vector float immediate value constructor. */
@@ -417,7 +417,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2,
uint8_t vf3)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
- this->fixed_hw_reg.ud = (vf0 << 0) |
+ this->ud = (vf0 << 0) |
(vf1 << 8) |
(vf2 << 16) |
(vf3 << 24);
@@ -443,9 +443,10 @@ fs_reg::equals(const fs_reg &r) const
negate == r.negate &&
abs == r.abs &&
!reladdr && !r.reladdr &&
- ((file != HW_REG && file != IMM) ||
+ (file != HW_REG ||
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0) &&
+ (file != IMM || d == r.d) &&
stride == r.stride);
}
@@ -719,7 +720,7 @@ fs_inst::components_read(unsigned i) const
assert(src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
/* First/second FB write color. */
if (i < 2)
- return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.ud;
+ return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
else
return 1;
@@ -739,10 +740,10 @@ fs_inst::components_read(unsigned i) const
assert(src[8].file == IMM && src[9].file == IMM);
/* Texture coordinates. */
if (i == 0)
- return src[8].fixed_hw_reg.ud;
+ return src[8].ud;
/* Texture derivatives. */
else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL)
- return src[9].fixed_hw_reg.ud;
+ return src[9].ud;
/* Texture offset. */
else if (i == 7)
return 2;
@@ -757,7 +758,7 @@ fs_inst::components_read(unsigned i) const
assert(src[3].file == IMM);
/* Surface coordinates. */
if (i == 0)
- return src[3].fixed_hw_reg.ud;
+ return src[3].ud;
/* Surface operation source (ignored for reads). */
else if (i == 1)
return 0;
@@ -770,10 +771,10 @@ fs_inst::components_read(unsigned i) const
src[4].file == IMM);
/* Surface coordinates. */
if (i == 0)
- return src[3].fixed_hw_reg.ud;
+ return src[3].ud;
/* Surface operation source. */
else if (i == 1)
- return src[4].fixed_hw_reg.ud;
+ return src[4].ud;
else
return 1;
@@ -781,10 +782,10 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: {
assert(src[3].file == IMM &&
src[4].file == IMM);
- const unsigned op = src[4].fixed_hw_reg.ud;
+ const unsigned op = src[4].ud;
/* Surface coordinates. */
if (i == 0)
- return src[3].fixed_hw_reg.ud;
+ return src[3].ud;
/* Surface operation source. */
el
Mesa (master): i965: Delete abs/negate fields from backend_reg.
Module: Mesa
Branch: master
Commit: 433df2e03c9a066bb2975bed28b57d6e2edf0aa9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=433df2e03c9a066bb2975bed28b57d6e2edf0aa9
Author: Matt Turner
Date: Sat Oct 24 14:35:33 2015 -0700
i965: Delete abs/negate fields from backend_reg.
Instead use the ones provided by brw_reg. Also allows us to handle
HW_REGs in the negate() functions.
Reviewed-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_ir_fs.h |2 +-
src/mesa/drivers/dri/i965/brw_ir_vec4.h |2 +-
src/mesa/drivers/dri/i965/brw_shader.h |3 ---
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 4417555..c0e486e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -72,7 +72,7 @@ public:
static inline fs_reg
negate(fs_reg reg)
{
- assert(reg.file != HW_REG && reg.file != IMM);
+ assert(reg.file != IMM);
reg.negate = !reg.negate;
return reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 29642c6..2fbb043 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -90,7 +90,7 @@ swizzle(src_reg reg, unsigned swizzle)
static inline src_reg
negate(src_reg reg)
{
- assert(reg.file != HW_REG && reg.file != IMM);
+ assert(reg.file != IMM);
reg.negate = !reg.negate;
return reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index e1e89dd..73b57f4 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -82,9 +82,6 @@ struct backend_reg : public brw_reg
uint16_t reg_offset;
struct brw_reg fixed_hw_reg;
-
- bool negate;
- bool abs;
};
#endif
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Mesa (master): 28 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3694d58e6c4a39bd84e8aef0d8e67c3ae9447f33 Author: Marek Olšák Date: Thu Oct 15 23:41:35 2015 +0200 radeonsi: remove dead code after ES-GS linkage change Reviewed-by: Michel Dänzer URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d79a3449a70b35a7fd38e7b4e17cafcbc28dda0d Author: Marek Olšák Date: Thu Oct 15 23:29:00 2015 +0200 radeonsi: link ES-GS just like LS-HS This reduces the shader key for ES. Use a fixed attrib location based on (semantic name, index). The ESGS item size is determined by the physical index of the highest ES output, so it's almost always larger than before, but I think that shouldn't matter as long as the ESGS ring buffer is large enough. Reviewed-by: Michel Dänzer URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1c5f3faa9d7a227150b677469df1a5832236541 Author: Marek Olšák Date: Sun Nov 8 13:34:44 2015 +0100 radeonsi: calculate optimal GS ring sizes to fix GS hangs on Tonga I discovered that increasing the ESGS ring size fixes GS hangs on Tonga, so let's do it properly. There is now a separate init_config_gs_rings state that is not immutable, because GS rings are resized when needed. This also saves some memory. Most apps won't need more than 1MB per ring per shader engine. Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f5d911ba2b0d477bce80e4dd3ae4d9748c6f784 Author: Marek Olšák Date: Sun Nov 8 12:15:54 2015 +0100 radeonsi: rename si_update_gs_rings Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4acd856088c31ab7ebbfbe5010db1fbcca72845c Author: Marek Olšák Date: Sun Nov 8 12:12:46 2015 +0100 radeonsi: calculate ESGS_RING_ITEMSIZE in create_shader Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0cf58996197d99cc7d743b76be977cc2359dca9 Author: Marek Olšák Date: Sun Nov 8 12:05:39 2015 +0100 radeonsi: move maximum gs stream calculation into create_shader Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ab0c49f04e5039655ddc8b81cac325709b154fe Author: Marek Olšák Date: Sun Nov 8 11:49:33 2015 +0100 radeonsi: clean up small duplication in si_shader_gs Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb0d3e8a90df3f6a39a3ffc911a335554fc8cd98 Author: Marek Olšák Date: Sat Nov 7 16:30:01 2015 +0100 gallium/radeon: shorten render_cond variable names and ..._cond -> ..._invert Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70c40cc9899c1e895004c3e25c4f763af44cd17d Author: Marek Olšák Date: Sat Nov 7 16:24:47 2015 +0100 gallium/radeon: remove predicate_drawing flag Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=12596cfd4cea4cff2bc067876d5ff25c54cdc874 Author: Marek Olšák Date: Sat Nov 7 15:39:39 2015 +0100 gallium/radeon: atomize render condition (SET_PREDICATION) Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35219076227e83ad2a406942c8b009337a4746d8 Author: Marek Olšák Date: Sat Nov 7 15:00:55 2015 +0100 gallium/radeon: simplify restoring render condition after flush Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=600e212d87017db613b8068decfeab3e4bf86deb Author: Marek Olšák Date: Sat Nov 7 14:55:23 2015 +0100 gallium/radeon: don't use PREDICATION_OP_CLEAR Not setting the predication bit is sufficient. Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6eff5415e46fb43619b543368fa427334d267a71 Author: Marek Olšák Date: Sat Nov 7 14:45:58 2015 +0100 gallium/radeon: simplify disabling render condition for u_blitter just disable it by not setting the predication bit Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dd1ee6ff30fd481dd33de93e5d613d11331c1f6 Author: Marek Olšák Date: Sat Nov 7 14:36:38 2015 +0100 r600g: don't set predication on non-draw packets This has no effect. Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cc8f6c6a72b1aab7bb506deb220e04ae50d8c2b Author: Marek Olšák Date: Sat Nov 7 14:00:30 2015 +0100 gallium/radeon: inline the r600_rings structure Reviewed-by: Nicolai Hähnle URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d963abc81789870d86257956a8fc24f7c6b661b Author: Marek Olšák Date: Sat Nov 7 12:22:56
Mesa (master): mesa: minor comment fix in blend.c
Module: Mesa Branch: master Commit: 40663864d2ee46afe246c15f5c4e6e380bb81720 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40663864d2ee46afe246c15f5c4e6e380bb81720 Author: Brian Paul Date: Fri Nov 13 08:02:05 2015 -0700 mesa: minor comment fix in blend.c --- src/mesa/main/blend.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c index 20aa498..ddf7f49 100644 --- a/src/mesa/main/blend.c +++ b/src/mesa/main/blend.c @@ -639,7 +639,7 @@ _mesa_AlphaFunc( GLenum func, GLclampf ref ) * \param opcode operation. * * Verifies that \p opcode is a valid enum and updates -gl_colorbuffer_attrib::LogicOp. + * gl_colorbuffer_attrib::LogicOp. * On a change, flushes the vertices and notifies the driver via the * dd_function_table::LogicOpcode callback. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): docs: update VMware driver instructions
Module: Mesa
Branch: master
Commit: 00046393f80f2a13b21fce647f35e1a979f41d7d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00046393f80f2a13b21fce647f35e1a979f41d7d
Author: Brian Paul
Date: Fri Nov 13 07:59:42 2015 -0700
docs: update VMware driver instructions
Use a LIBDIR variable, set per-platform.
Update the Mesa configuration flags.
Run update-initramfs or dracut, update /etc/modules
Signed-off-by: Brian Paul
---
docs/vmware-guest.html | 64
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/docs/vmware-guest.html b/docs/vmware-guest.html
index 284c6c2..b495bc2 100644
--- a/docs/vmware-guest.html
+++ b/docs/vmware-guest.html
@@ -148,10 +148,33 @@ To get the latest code from git:
Building the Code
-Build libdrm: If you're on a 32-bit system, you should skip the --libdir
configure option. Note also the comment about toolchain libdrm above.
+
+Determine where the GL-related libraries reside on your system and set
+the LIBDIR environment variable accordingly.
+
+For 32-bit Ubuntu systems:
+
+ export LIBDIR=/usr/lib/i386-linux-gnu
+
+For 64-bit Ubuntu systems:
+
+ export LIBDIR=/usr/lib/x86_64-linux-gnu
+
+For 32-bit Fedora systems:
+
+ export LIBDIR=/usr/lib
+
+For 64-bit Fedora systems:
+
+ export LIBDIR=/usr/lib64
+
+
+
+
+Build libdrm:
cd $TOP/drm
- ./autogen.sh --prefix=/usr --libdir=/usr/lib64
+ ./autogen.sh --prefix=/usr --libdir=${LIBDIR}
make
sudo make install
@@ -162,12 +185,9 @@ The libxatracker library is used exclusively by the X
server to do render,
copy and video acceleration:
The following configure options doesn't build the EGL system.
-
-As before, if you're on a 32-bit system, you should skip the --libdir
-configure option.
cd $TOP/mesa
- ./autogen.sh --prefix=/usr --libdir=/usr/lib64 --with-gallium-drivers=svga
--with-dri-drivers= --enable-xa --disable-dri3
+ ./autogen.sh --prefix=/usr --libdir=${LIBDIR} --with-gallium-drivers=svga
--with-dri-drivers=swrast --enable-xa --disable-dri3 --enable-glx-tls
make
sudo make install
@@ -177,25 +197,39 @@ if they're not installed in your system. You should be
told what's missing.
-xf86-video-vmware: Now, once libxatracker is installed, we proceed with
building and replacing the current Xorg driver. First check if your system is
32- or 64-bit. If you're building for a 32-bit system, you will not be needing
the --libdir=/usr/lib64 option to autogen.
+xf86-video-vmware: Now, once libxatracker is installed, we proceed with
+building and replacing the current Xorg driver.
+First check if your system is 32- or 64-bit.
cd $TOP/xf86-video-vmware
- ./autogen.sh --prefix=/usr --libdir=/usr/lib64
+ ./autogen.sh --prefix=/usr --libdir=${LIBDIR}
make
sudo make install
+
vmwgfx kernel module. First make sure that any old version of this kernel
module is removed from the system by issuing
-
+
sudo rm /lib/modules/`uname -r`/kernel/drivers/gpu/drm/vmwgfx.ko*
-
-Then
-
+
+Build and install:
+
cd $TOP/vmwgfx
make
sudo make install
- sudo cp 00-vmwgfx.rules /etc/udev/rules.d
- sudo depmod -ae
-
+ sudo depmod -a
+
+If you're using a Ubuntu OS:
+
+ sudo update-initramfs -u
+
+If you're using a Fedora OS:
+
+ sudo dracut --force
+
+Add 'vmwgfx' to the /etc/modules file:
+
+ echo vmwgfx | sudo tee -a /etc/modules
+
Note: some distros put DRM kernel drivers in different directories.
For example, sometimes vmwgfx.ko might be found in
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Mesa (master): docs: add link to Coverity on developer utilities page
Module: Mesa Branch: master Commit: 5a5efbf804eb848553b85f498bf4c4340d748c3d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a5efbf804eb848553b85f498bf4c4340d748c3d Author: Brian Paul Date: Fri Nov 13 08:01:29 2015 -0700 docs: add link to Coverity on developer utilities page Signed-off-by: Brian Paul --- docs/utilities.html |4 1 file changed, 4 insertions(+) diff --git a/docs/utilities.html b/docs/utilities.html index 9541d30..5c0a4fd 100644 --- a/docs/utilities.html +++ b/docs/utilities.html @@ -30,6 +30,10 @@ http://www.valgrind.org";>Valgrind is a very useful tool for tracking down memory-related problems in your code. + + Coverity + provides static code analysis of Mesa. If you create an account + you can see the results and try to fix outstanding issues. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): egl/wayland: Ignore rects from SwapBuffersWithDamage
Module: Mesa
Branch: master
Commit: d1314de293e9e4a63c35f094c3893aaaed8580b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1314de293e9e4a63c35f094c3893aaaed8580b4
Author: Daniel Stone
Date: Sat Nov 7 18:25:31 2015 +
egl/wayland: Ignore rects from SwapBuffersWithDamage
eglSwapBuffersWithDamage accepts damage-region rectangles to hint the
compositor that it only needs to redraw certain areas, which was passed
through the wl_surface_damage request, as designed.
Wayland also offers a buffer transformation interface, e.g. to allow
users to render pre-rotated buffers. Unfortunately, there is no way to
query buffer transforms, and the damage region was provided in surface,
rather than buffer, co-ordinate space.
Users could in theory account for this themselves, but EGL also requires
co-ordinates to be passed in GL/mathematical co-ordinate space, with an
inversion to Wayland's natural/scanout co-ordinate space, so
transformations other than a 180-degree rotation will fail as EGL
attempts to subtract the region from (its view of the) surface height.
Pending creation and acceptance of a wl_surface.buffer_damage request,
which will accept co-ordinates in buffer co-ordinate space, pessimise to
always sending full-surface damage.
bce64c6c provides the explanation for why we send maximum-range damage,
rather than the full size of the surface: in the presence of buffer
transformations, full-surface damage may not actually cover the entire
surface.
Signed-off-by: Daniel Stone
Reviewed-by: Pekka Paalanen
Reviewed-by: Jason Ekstrand
---
src/egl/drivers/dri2/platform_wayland.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_wayland.c
b/src/egl/drivers/dri2/platform_wayland.c
index 0d161f6..a635c75 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -703,18 +703,10 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
dri2_surf->dx = 0;
dri2_surf->dy = 0;
- if (n_rects == 0) {
- wl_surface_damage(dri2_surf->wl_win->surface,
-0, 0, INT32_MAX, INT32_MAX);
- } else {
- for (i = 0; i < n_rects; i++) {
- const int *rect = &rects[i * 4];
- wl_surface_damage(dri2_surf->wl_win->surface,
- rect[0],
- dri2_surf->base.Height - rect[1] - rect[3],
- rect[2], rect[3]);
- }
- }
+ /* We deliberately ignore the damage region and post maximum damage, due to
+* https://bugs.freedesktop.org/78190 */
+ wl_surface_damage(dri2_surf->wl_win->surface,
+ 0, 0, INT32_MAX, INT32_MAX);
if (dri2_dpy->is_different_gpu) {
_EGLContext *ctx = _eglGetCurrentContext();
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