Mesa (master): i965: Clean up intel_batchbuffer_init().

2017-08-12 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: da0840246fd91134a61e35f1bd987d77111aed26
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da0840246fd91134a61e35f1bd987d77111aed26

Author: Kenneth Graunke 
Date:   Thu Aug 10 20:47:53 2017 -0700

i965: Clean up intel_batchbuffer_init().

Passing screen lets us get the kernel features, devinfo, and bufmgr,
without needing container_of.

This use of container_of could cause crashes due to issues with the
"sample" macro parameter.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102062
Reviewed-by: Tapani Pälli 
Reviewed-by: Emil Velikov 
Reviewed-by: Iago Toral Quiroga 

---

 src/mesa/drivers/dri/i965/brw_context.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16 
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |  5 ++---
 3 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 60b14571ed..2d8f34f7ef 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -934,7 +934,7 @@ brwCreateContext(gl_api api,
 
intel_fbo_init(brw);
 
-   intel_batchbuffer_init(>batch, brw->bufmgr, brw->has_llc);
+   intel_batchbuffer_init(screen, >batch);
 
if (brw->gen >= 6) {
   /* Create a new hardware context.  Using a hardware context means that
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 66b9a28129..59488a2f96 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -58,13 +58,13 @@ uint_key_hash(const void *key)
 }
 
 void
-intel_batchbuffer_init(struct intel_batchbuffer *batch,
-   struct brw_bufmgr *bufmgr,
-   bool has_llc)
+intel_batchbuffer_init(struct intel_screen *screen,
+   struct intel_batchbuffer *batch)
 {
-   struct brw_context *brw = container_of(batch, brw, batch);
+   struct brw_bufmgr *bufmgr = screen->bufmgr;
+   const struct gen_device_info *devinfo = >devinfo;
 
-   if (!has_llc) {
+   if (!devinfo->has_llc) {
   batch->cpu_map = malloc(BATCH_SZ);
   batch->map = batch->cpu_map;
   batch->map_next = batch->cpu_map;
@@ -87,14 +87,14 @@ intel_batchbuffer_init(struct intel_batchbuffer *batch,
}
 
batch->use_batch_first =
-  brw->screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST;
+  screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST;
 
/* PIPE_CONTROL needs a w/a but only on gen6 */
batch->valid_reloc_flags = EXEC_OBJECT_WRITE;
-   if (brw->gen == 6)
+   if (devinfo->gen == 6)
   batch->valid_reloc_flags |= EXEC_OBJECT_NEEDS_GTT;
 
-   intel_batchbuffer_reset(batch, bufmgr, has_llc);
+   intel_batchbuffer_reset(batch, bufmgr, devinfo->has_llc);
 }
 
 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 4661a2a9f6..99d2747f28 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -38,9 +38,8 @@ extern "C" {
 
 struct intel_batchbuffer;
 
-void intel_batchbuffer_init(struct intel_batchbuffer *batch,
-struct brw_bufmgr *bufmgr,
-bool has_llc);
+void intel_batchbuffer_init(struct intel_screen *screen,
+struct intel_batchbuffer *batch);
 void intel_batchbuffer_free(struct intel_batchbuffer *batch);
 void intel_batchbuffer_save_state(struct brw_context *brw);
 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);

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Mesa (master): i965: Guard GetBufferSubData' s streaming memcpy load with USE_SSE41

2017-08-12 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 22e1d8832c90702b4cd972e48f0db809f7c7639f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22e1d8832c90702b4cd972e48f0db809f7c7639f

Author: Kenneth Graunke 
Date:   Thu Aug 10 21:10:31 2017 -0700

i965: Guard GetBufferSubData's streaming memcpy load with USE_SSE41

This should hopefully fix build issues on 32-bit Android-x86.

v2: s/USE_SSE4_1/USE_SS41/, caught by Gražvydas Ignotas.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102050
Reviewed-by: Tapani Pälli 
Reviewed-by: Emil Velikov 

---

 src/mesa/drivers/dri/i965/intel_buffer_objects.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index ee59116828..658b1edf1c 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -342,6 +342,7 @@ brw_get_buffer_subdata(struct gl_context *ctx,
 
unsigned int map_flags = MAP_READ;
mem_copy_fn memcpy_fn = memcpy;
+#ifdef USE_SSE41
if (!intel_obj->buffer->cache_coherent && cpu_has_sse4_1) {
   /* Rather than acquire a new WB mmaping of the buffer object and pull
* it into the CPU cache, keep using the WC mmap that we have for writes,
@@ -350,6 +351,7 @@ brw_get_buffer_subdata(struct gl_context *ctx,
   map_flags |= MAP_COHERENT;
   memcpy_fn = (mem_copy_fn) _mesa_streaming_load_memcpy;
}
+#endif
 
void *map = brw_bo_map(brw, intel_obj->buffer, map_flags);
if (unlikely(!map)) {

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Mesa (master): nvc0/ir: unlink values pre- and post-call to division function

2017-08-12 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: ea22ac23e04c093f9dd0bb8f9b946e61d79824ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea22ac23e04c093f9dd0bb8f9b946e61d79824ff

Author: Ilia Mirkin 
Date:   Sat Aug 12 00:02:34 2017 -0400

nvc0/ir: unlink values pre- and post-call to division function

While technically correct, this can lead to e.g. getImmediate assuming
that it can walk up the value chain. It could be fixed to not do this,
but it seems easier and less error-prone to just not link the two values
to save on one LValue object.

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 64d743708a..c8f0701572 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -45,11 +45,10 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
 {
FlowInstruction *call;
int builtin;
-   Value *def[2];
 
bld.setPosition(i, false);
-   def[0] = bld.mkMovToReg(0, i->getSrc(0))->getDef(0);
-   def[1] = bld.mkMovToReg(1, i->getSrc(1))->getDef(0);
+   bld.mkMovToReg(0, i->getSrc(0));
+   bld.mkMovToReg(1, i->getSrc(1));
switch (i->dType) {
case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break;
case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break;
@@ -57,7 +56,7 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
   return;
}
call = bld.mkFlow(OP_CALL, NULL, CC_ALWAYS, NULL);
-   bld.mkMov(i->getDef(0), def[(i->op == OP_DIV) ? 0 : 1]);
+   bld.mkMovFromReg(i->getDef(0), i->op == OP_DIV ? 0 : 1);
bld.mkClobber(FILE_GPR, (i->op == OP_DIV) ? 0xe : 0xd, 2);
bld.mkClobber(FILE_PREDICATE, (i->dType == TYPE_S32) ? 0xf : 0x3, 0);
 

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Mesa (17.2): radv: Don't use SRGB format for image stores during resolve.

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 8b706102ebe89984e0d2dce100fb681855c8e056
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b706102ebe89984e0d2dce100fb681855c8e056

Author: Bas Nieuwenhuizen 
Date:   Sun Aug  6 01:47:09 2017 +0200

radv: Don't use SRGB format for image stores during resolve.

These seem to store very bogus results. Luckily there is some code
that converts srgb->linear already, so just making the descriptor
format UNORM should work.

Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie 
(cherry picked from commit 8286c3a49f03dc219e57d4a9ec27a4d840c5f603)

---

 src/amd/vulkan/radv_meta_resolve_cs.c |  2 +-
 src/amd/vulkan/vk_format.h| 23 +++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c 
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 1eef22ad77..832ae7b8c9 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -402,7 +402,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer 
*cmd_buffer,
 .sType = 
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 .image = 
radv_image_to_handle(dest_image),
 .viewType = 
radv_meta_get_view_type(dest_image),
-.format = 
dest_image->vk_format,
+.format = 
vk_to_non_srgb_format(dest_image->vk_format),
 .subresourceRange 
= {
 .aspectMask = 
VK_IMAGE_ASPECT_COLOR_BIT,
 .baseMipLevel = 
region->dstSubresource.mipLevel,
diff --git a/src/amd/vulkan/vk_format.h b/src/amd/vulkan/vk_format.h
index c2c7ca4ce2..43265ed3d9 100644
--- a/src/amd/vulkan/vk_format.h
+++ b/src/amd/vulkan/vk_format.h
@@ -465,4 +465,27 @@ vk_format_get_component_bits(VkFormat format,
}
 }
 
+static inline VkFormat
+vk_to_non_srgb_format(VkFormat format)
+{
+   switch(format) {
+   case VK_FORMAT_R8_SRGB :
+   return VK_FORMAT_R8_UNORM;
+   case VK_FORMAT_R8G8_SRGB:
+   return VK_FORMAT_R8G8_UNORM;
+   case VK_FORMAT_R8G8B8_SRGB:
+   return VK_FORMAT_R8G8B8_UNORM;
+   case VK_FORMAT_B8G8R8_SRGB:
+   return VK_FORMAT_B8G8R8_UNORM;
+   case VK_FORMAT_R8G8B8A8_SRGB :
+   return VK_FORMAT_R8G8B8A8_UNORM;
+   case VK_FORMAT_B8G8R8A8_SRGB:
+   return VK_FORMAT_B8G8R8A8_UNORM;
+   case VK_FORMAT_A8B8G8R8_SRGB_PACK32:
+   return VK_FORMAT_A8B8G8R8_UNORM_PACK32;
+   default:
+   return format;
+   }
+}
+
 #endif /* VK_FORMAT_H */

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Mesa (17.2): radv: Use the correct channel for alpha in resolve srgb conversion.

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 9d65214f3dd7d17403da249af9ea469027a6fe34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d65214f3dd7d17403da249af9ea469027a6fe34

Author: Bas Nieuwenhuizen 
Date:   Sun Aug  6 01:58:21 2017 +0200

radv: Use the correct channel for alpha in resolve srgb conversion.

The argument here is a bitmask, so the old code selected .xy, which
got silently truncated to .x when constructing the vec4 from components,
instead of using .w.

Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie 
(cherry picked from commit acba3a3151dbbba0ab834e062e0feb12af4873de)

---

 src/amd/vulkan/radv_meta_resolve_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c 
b/src/amd/vulkan/radv_meta_resolve_cs.c
index f13e79ef0c..d20d04231e 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -66,7 +66,7 @@ static nir_ssa_def 
*radv_meta_build_resolve_srgb_conversion(nir_builder *b,
nir_ssa_def *comp[4];
for (i = 0; i < 3; i++)
comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
-   comp[3] = nir_channels(b, input, 3);
+   comp[3] = nir_channels(b, input, 1 << 3);
return nir_vec(b, comp, 4);
 }
 

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Mesa (17.2): radv: fix f16->f32 denorm handling for SI/CIK. (v2)

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: ffd8120284e7592963ed68ffa0775b087530941b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffd8120284e7592963ed68ffa0775b087530941b

Author: Dave Airlie 
Date:   Fri Aug  4 00:17:34 2017 +0100

radv: fix f16->f32 denorm handling for SI/CIK. (v2)

This just copies the code from the -pro shaders,
and fixes the tests on CIK.

With this CIK passes the same set of conformance
tests as VI.

Fixes: 83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2))
Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 
(cherry picked from commit 3f389f75b6e9b55467aca681af09b83998ee0e46)

---

 src/amd/common/ac_nir_to_llvm.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 540976db92..5ed7e43ced 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1315,7 +1315,6 @@ static LLVMValueRef emit_f2f16(struct nir_to_llvm_context 
*ctx,
src0 = to_float(>ac, src0);
result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
 
-   /* TODO SI/CIK options here */
if (ctx->options->chip_class >= VI) {
LLVMValueRef args[2];
/* Check if the result is a denormal - and flush to 0 if so. */
@@ -1329,7 +1328,22 @@ static LLVMValueRef emit_f2f16(struct 
nir_to_llvm_context *ctx,
 
if (ctx->options->chip_class >= VI)
result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, 
result, "");
-
+   else {
+   /* for SI/CIK */
+   /* 0x3880 is smallest half float value (2^-14) in 32-bit 
float,
+* so compare the result and flush to 0 if it's smaller.
+*/
+   LLVMValueRef temp, cond2;
+   temp = emit_intrin_1f_param(>ac, "llvm.fabs",
+   ctx->f32, result);
+   cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
+LLVMBuildBitCast(ctx->builder, 
LLVMConstInt(ctx->i32, 0x3880, false), ctx->f32, ""),
+temp, "");
+   cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
+ temp, ctx->f32zero, "");
+   cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
+   result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, 
result, "");
+   }
return result;
 }
 

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Mesa (17.2): radv: Fix decompression on multisampled depth buffers

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: f0b6298c0505139bed1f15746a3f7be492d36082
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0b6298c0505139bed1f15746a3f7be492d36082

Author: Alex Smith 
Date:   Thu Aug  3 15:32:46 2017 +0100

radv: Fix decompression on multisampled depth buffers

Need to take the sample count into account in the depth decompress and
resummarize pipelines and render pass.

Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith 
Reviewed-by: Bas Nieuwenhuizen 
Cc: "17.2" 
(cherry picked from commit 2e9a13bf2205b6e96cba408e3f48f1c3fe49634a)

---

 src/amd/vulkan/radv_meta_decompress.c | 102 ++
 src/amd/vulkan/radv_private.h |   2 +-
 2 files changed, 69 insertions(+), 35 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_decompress.c 
b/src/amd/vulkan/radv_meta_decompress.c
index 7afe08fbdb..f68ce8d2b0 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -29,7 +29,9 @@
 #include "sid.h"
 
 static VkResult
-create_pass(struct radv_device *device)
+create_pass(struct radv_device *device,
+   uint32_t samples,
+   VkRenderPass *pass)
 {
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
@@ -37,7 +39,7 @@ create_pass(struct radv_device *device)
VkAttachmentDescription attachment;
 
attachment.format = VK_FORMAT_D32_SFLOAT_S8_UINT;
-   attachment.samples = 1;
+   attachment.samples = samples;
attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
attachment.initialLayout = 
VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
@@ -65,14 +67,18 @@ create_pass(struct radv_device *device)

.dependencyCount = 0,
   },
   alloc,
-  >meta_state.depth_decomp.pass);
+  pass);
 
return result;
 }
 
 static VkResult
 create_pipeline(struct radv_device *device,
-VkShaderModule vs_module_h)
+VkShaderModule vs_module_h,
+   uint32_t samples,
+   VkRenderPass pass,
+   VkPipeline *decompress_pipeline,
+   VkPipeline *resummarize_pipeline)
 {
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
@@ -129,7 +135,7 @@ create_pipeline(struct radv_device *device,
},
.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
.sType = 
VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
-   .rasterizationSamples = 1,
+   .rasterizationSamples = samples,
.sampleShadingEnable = false,
.pSampleMask = NULL,
.alphaToCoverageEnable = false,
@@ -156,7 +162,7 @@ create_pipeline(struct radv_device *device,
VK_DYNAMIC_STATE_SCISSOR,
},
},
-   .renderPass = device->meta_state.depth_decomp.pass,
+   .renderPass = pass,
.subpass = 0,
};
 
@@ -169,7 +175,7 @@ create_pipeline(struct radv_device *device,

.db_flush_stencil_inplace = true,
   },
   >meta_state.alloc,
-  
>meta_state.depth_decomp.decompress_pipeline);
+  decompress_pipeline);
if (result != VK_SUCCESS)
goto cleanup;
 
@@ -183,7 +189,7 @@ create_pipeline(struct radv_device *device,
.db_resummarize = true,
   },
   >meta_state.alloc,
-  
>meta_state.depth_decomp.resummarize_pipeline);
+  resummarize_pipeline);
if (result != VK_SUCCESS)
goto cleanup;
 
@@ -199,29 +205,31 @@ radv_device_finish_meta_depth_decomp_state(struct 
radv_device *device)
 {
struct radv_meta_state *state = >meta_state;
VkDevice device_h = radv_device_to_handle(device);
-   VkRenderPass pass_h = device->meta_state.depth_decomp.pass;
const VkAllocationCallbacks *alloc = >meta_state.alloc;
 
-   if (pass_h)
-   radv_DestroyRenderPass(device_h, pass_h,
->meta_state.alloc);
-
-

Mesa (17.2): intel/isl: Stop padding surfaces

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: dc63c715cb3f0d7dddb31345689355b1b450cdde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc63c715cb3f0d7dddb31345689355b1b450cdde

Author: Jason Ekstrand 
Date:   Mon Jul 31 08:33:22 2017 -0700

intel/isl: Stop padding surfaces

The docs contain a bunch of commentary about the need to pad various
surfaces out to multiples of something or other.  However, all of those
requirements are about avoiding GTT errors due to missing pages when the
data port or sampler accesses slightly out-of-bounds.  However, because
the kernel already fills all the empty space in our GTT with the scratch
page, we never have to worry about faulting due to OOB reads.  There are
two caveats to this:

 1) There is some potential for issues with caches here if extra data
ends up in a cache we don't expect due to OOB reads.  However,
because we always trash the entire cache whenever we need to move
anything between cache domains, this shouldn't be an issue.

 2) There is a potential issue if a surface gets placed at the very top
of the GTT by the kernel.  In this case, the hardware could
potentially end up trying to read past the top of the GTT.  If it
nicely wraps around at the 48-bit (or 32-bit) boundary, then this
shouldn't be an issue thanks to the scratch page.  If it doesn't,
then we need to come up with something to handle it.

Up until some of the GL move to ISL, having the padding code in there
just caused us to harmlessly use a bit more memory in Vulkan.  However,
now that we're using ISL sizes to validate external dma-buf images,
these padding requirements are causing us to reject otherwise valid
images due to the size of the BO being too small.

Acked-by: Kenneth Graunke 
Tested-by: Tapani Pälli 
Tested-by: Tomasz Figa 
Reviewed-by: Jordan Justen 
Cc: "17.2" 
(cherry picked from commit c15b92ce1160d742ea431062bbe4b3e818bb2aaf)

---

 src/intel/isl/isl.c | 119 +---
 1 file changed, 2 insertions(+), 117 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5e3d279b0b..d3124debfa 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1374,116 +1374,6 @@ isl_calc_row_pitch(const struct isl_device *dev,
return true;
 }
 
-/**
- * Calculate and apply any padding required for the surface.
- *
- * @param[inout] total_h_el is updated with the new height
- * @param[out] pad_bytes is overwritten with additional padding requirements.
- */
-static void
-isl_apply_surface_padding(const struct isl_device *dev,
-  const struct isl_surf_init_info *restrict info,
-  const struct isl_tile_info *tile_info,
-  uint32_t *total_h_el,
-  uint32_t *pad_bytes)
-{
-   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
-   *pad_bytes = 0;
-
-   /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
-* Formats >> Surface Padding Requirements >> Render Target and Media
-* Surfaces:
-*
-*   The data port accesses data (pixels) outside of the surface if they
-*   are contained in the same cache request as pixels that are within the
-*   surface. These pixels will not be returned by the requesting message,
-*   however if these pixels lie outside of defined pages in the GTT,
-*   a GTT error will result when the cache request is processed. In
-*   order to avoid these GTT errors, “padding” at the bottom of the
-*   surface is sometimes necessary.
-*
-* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
-* Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
-*
-*... Lots of padding requirements, all listed separately below.
-*/
-
-   /* We can safely ignore the first padding requirement, quoted below,
-* because isl doesn't do buffers.
-*
-*- [pre-BDW] For buffers, which have no inherent “height,” padding
-*  requirements are different. A buffer must be padded to the next
-*  multiple of 256 array elements, with an additional 16 bytes added
-*  beyond that to account for the L1 cache line.
-*/
-
-   /*
-*- For compressed textures [...], padding at the bottom of the surface
-*  is to an even compressed row.
-*/
-   if (isl_format_is_compressed(info->format))
-  *total_h_el = isl_align(*total_h_el, 2);
-
-   /*
-*- For cube surfaces, an additional two rows of padding are required
-*  at the bottom of the surface.
-*/
-   if (info->usage & ISL_SURF_USAGE_CUBE_BIT)
-  *total_h_el += 2;
-
-   /*
-*- For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
-*  additional padding is required. These surfaces

Mesa (17.2): configure: remove trailing "-a" in swr architecture test

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: bb6e5e5476ebaec73a17831cb5c5b883d061560e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb6e5e5476ebaec73a17831cb5c5b883d061560e

Author: Tim Rowley 
Date:   Thu Aug 10 12:58:57 2017 -0500

configure: remove trailing "-a" in swr architecture test

Fixes "configure: line 27326: test: argument expected"

CC: mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner 
(cherry picked from commit 4d9b0dcccb81ad10113d9aef52b4c84496e879f1)

---

 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 2736fbf201..8d6c9671e7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2551,7 +2551,7 @@ if test -n "$with_gallium_drivers"; then
 if test "x$HAVE_SWR_AVX" != xyes -a \
 "x$HAVE_SWR_AVX2" != xyes -a \
 "x$HAVE_SWR_KNL" != xyes -a \
-"x$HAVE_SWR_SKX" != xyes -a; then
+"x$HAVE_SWR_SKX" != xyes; then
AC_MSG_ERROR([swr enabled but no swr architectures selected])
 fi
 

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Mesa (17.2): ac: fail shader compilation if libelf is replaced by an incompatible version

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 08d49e074dc95cbe04b6090e49ba067a31bb1a84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08d49e074dc95cbe04b6090e49ba067a31bb1a84

Author: Marek Olšák 
Date:   Wed Aug  9 22:30:28 2017 +0200

ac: fail shader compilation if libelf is replaced by an incompatible version

UE4Editor has this issue.

This commit prevents hangs (release build) or assertion failures (debug
build). It doesn't fix the editor, but catastrophic scenarios are
prevented.

Cc: 17.1 17.2 
Reviewed-by: Michel Dänzer 
Reviewed-by: Samuel Pitoiset 
(cherry picked from commit 4630ede1021d49c610de1274dc9d1006b843e46b)

---

 src/amd/common/ac_binary.c  | 12 ++--
 src/amd/common/ac_binary.h  |  2 +-
 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c |  5 -
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 618b5cf8b8..1bf52c7832 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -109,7 +109,7 @@ static void parse_relocs(Elf *elf, Elf_Data *relocs, 
Elf_Data *symbols,
}
 }
 
-void ac_elf_read(const char *elf_data, unsigned elf_size,
+bool ac_elf_read(const char *elf_data, unsigned elf_size,
 struct ac_shader_binary *binary)
 {
char *elf_buffer;
@@ -118,6 +118,7 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
Elf_Data *symbols = NULL, *relocs = NULL;
size_t section_str_index;
unsigned symbol_sh_link = 0;
+   bool success = true;
 
/* One of the libelf implementations
 * (http://www.mr511.de/software/english.htm) requires calling
@@ -137,7 +138,8 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
GElf_Shdr section_header;
if (gelf_getshdr(section, _header) != _header) {
fprintf(stderr, "Failed to read ELF section header\n");
-   return;
+   success = false;
+   break;
}
name = elf_strptr(elf, section_str_index, 
section_header.sh_name);
if (!strcmp(name, ".text")) {
@@ -148,6 +150,11 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
} else if (!strcmp(name, ".AMDGPU.config")) {
section_data = elf_getdata(section, section_data);
binary->config_size = section_data->d_size;
+   if (!binary->config_size) {
+   fprintf(stderr, ".AMDGPU.config is empty!\n");
+   success = false;
+   break;
+   }
binary->config = MALLOC(binary->config_size * 
sizeof(unsigned char));
memcpy(binary->config, section_data->d_buf, 
binary->config_size);
} else if (!strcmp(name, ".AMDGPU.disasm")) {
@@ -186,6 +193,7 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
binary->global_symbol_count = 1;
binary->config_size_per_symbol = binary->config_size;
}
+   return success;
 }
 
 const unsigned char *ac_shader_binary_config_start(
diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index a784a7220c..45f554e4fe 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -83,7 +83,7 @@ struct ac_shader_config {
  * Parse the elf binary stored in \p elf_data and create a
  * ac_shader_binary object.
  */
-void ac_elf_read(const char *elf_data, unsigned elf_size,
+bool ac_elf_read(const char *elf_data, unsigned elf_size,
 struct ac_shader_binary *binary);
 
 /**
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index df37267d37..7a59c90c3e 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -148,7 +148,10 @@ unsigned si_llvm_compile(LLVMModuleRef M, struct 
ac_shader_binary *binary,
buffer_size = LLVMGetBufferSize(out_buffer);
buffer_data = LLVMGetBufferStart(out_buffer);
 
-   ac_elf_read(buffer_data, buffer_size, binary);
+   if (!ac_elf_read(buffer_data, buffer_size, binary)) {
+   fprintf(stderr, "radeonsi: cannot read an ELF shader binary\n");
+   diag.retval = 1;
+   }
 
/* Clean up */
LLVMDisposeMemoryBuffer(out_buffer);

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Mesa (17.2): nv50/ir: fix ConstantFolding with saturation

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 75f5abb82f81d9cb302c0db9862dff8c296811f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75f5abb82f81d9cb302c0db9862dff8c296811f8

Author: Karol Herbst 
Date:   Sun Jul 30 17:51:22 2017 +0200

nv50/ir: fix ConstantFolding with saturation

For mul(a, +-1) codegen can generate OP_MOV with a saturation flag
set which is ignored at emission. The same can happen with add(a, 0),
and others.

Adding an assert for detecting more of such issues.

Fixes wrongly rendered water in Hitman Absolution running under wine.
Also a few shaders in Mad Max and Alien Isolation produce such MOVs.

CC: 
Signed-off-by: Karol Herbst 
Reviewed-by: Tobias Klausmann 
[imirkin: generalize the fix for other cases]
Reviewed-by: Ilia Mirkin 
(cherry picked from commit 24a799ad35a824fba94062f9b018f603717ed145)

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 1 +
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp  | 8 
 2 files changed, 9 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 14c00bd187..58594f02c7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2006,6 +2006,7 @@ CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
 void
 CodeEmitterNVC0::emitMOV(const Instruction *i)
 {
+   assert(!i->saturate);
if (i->def(0).getFile() == FILE_PREDICATE) {
   if (i->src(0).getFile() == FILE_GPR) {
  code[0] = 0xfc01c003;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index dac3e6f814..cfc0dfc53c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1509,6 +1509,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
, int s)
default:
   return;
}
+
+   // This can get left behind some of the optimizations which simplify
+   // saturatable values.
+   if (newi->op == OP_MOV && newi->saturate) {
+  newi->saturate = 0;
+  newi->op = OP_SAT;
+   }
+
if (newi->op != op)
   foldCount++;
 }

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Mesa (17.2): radv: Only convert linear->srgb in compute resolves.

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: a57390cee01c63bb48402214f65c28298bd4c268
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a57390cee01c63bb48402214f65c28298bd4c268

Author: Bas Nieuwenhuizen 
Date:   Sun Aug  6 01:56:17 2017 +0200

radv: Only convert linear->srgb in compute resolves.

It justs works with the fragment shader resolve, so no need to do
a custom conversion. In fact with SRGB dest, it actually gives
wrong results.

Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie 
(cherry picked from commit 15e5a7a6832bba011564bfa2045fba9e833eede2)

---

 src/amd/vulkan/radv_meta.c| 46 ---
 src/amd/vulkan/radv_meta.h|  1 -
 src/amd/vulkan/radv_meta_resolve_cs.c | 46 +--
 src/amd/vulkan/radv_meta_resolve_fs.c | 38 -
 src/amd/vulkan/radv_private.h |  2 --
 5 files changed, 54 insertions(+), 79 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 263181a57f..af56f493b4 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -477,48 +477,8 @@ radv_meta_build_nir_fs_noop(void)
return b.shader;
 }
 
-static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
-   nir_ssa_def *input)
-{
-   nir_const_value v;
-   unsigned i;
-   v.u32[0] = 0x3b4d2e1c; // 0.00313080009
-
-   nir_ssa_def *cmp[3];
-   for (i = 0; i < 3; i++)
-   cmp[i] = nir_flt(b, nir_channel(b, input, i),
-nir_build_imm(b, 1, 32, v));
-
-   nir_ssa_def *ltvals[3];
-   v.f32[0] = 12.92;
-   for (i = 0; i < 3; i++)
-   ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
-nir_build_imm(b, 1, 32, v));
-
-   nir_ssa_def *gtvals[3];
-
-   for (i = 0; i < 3; i++) {
-   v.f32[0] = 1.0/2.4;
-   gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
-nir_build_imm(b, 1, 32, v));
-   v.f32[0] = 1.055;
-   gtvals[i] = nir_fmul(b, gtvals[i],
-nir_build_imm(b, 1, 32, v));
-   v.f32[0] = 0.055;
-   gtvals[i] = nir_fsub(b, gtvals[i],
-nir_build_imm(b, 1, 32, v));
-   }
-
-   nir_ssa_def *comp[4];
-   for (i = 0; i < 3; i++)
-   comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
-   comp[3] = nir_channels(b, input, 3);
-   return nir_vec(b, comp, 4);
-}
-
 void radv_meta_build_resolve_shader_core(nir_builder *b,
 bool is_integer,
-bool is_srgb,
 int samples,
 nir_variable *input_img,
 nir_variable *color,
@@ -596,10 +556,4 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 
if (outer_if)
b->cursor = nir_after_cf_node(_if->cf_node);
-
-   if (is_srgb) {
-   nir_ssa_def *newv = nir_load_var(b, color);
-   newv = radv_meta_build_resolve_srgb_conversion(b, newv);
-   nir_store_var(b, color, newv, 0xf);
-   }
 }
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index c4a81a2594..adc889bf4e 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -234,7 +234,6 @@ nir_shader *radv_meta_build_nir_fs_noop(void);
 
 void radv_meta_build_resolve_shader_core(nir_builder *b,
 bool is_integer,
-bool is_srgb,
 int samples,
 nir_variable *input_img,
 nir_variable *color,
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c 
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 832ae7b8c9..f13e79ef0c 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -31,6 +31,45 @@
 #include "sid.h"
 #include "vk_format.h"
 
+static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
+   nir_ssa_def *input)
+{
+   nir_const_value v;
+   unsigned i;
+   v.u32[0] = 0x3b4d2e1c; // 0.00313080009
+
+   nir_ssa_def *cmp[3];
+   for (i = 0; i < 3; i++)
+   cmp[i] = nir_flt(b, nir_channel(b, input, i),
+nir_build_imm(b, 1, 32, v));
+
+   nir_ssa_def *ltvals[3];
+   v.f32[0] = 12.92;
+   for (i = 0; i < 3; i++)
+   ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
+

Mesa (17.2): radeonsi/gfx9: use the VI codepath for clamping Z

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 7f5d86ebaa854ff3f60ba1a201bc2171d25f558b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f5d86ebaa854ff3f60ba1a201bc2171d25f558b

Author: Marek Olšák 
Date:   Thu Aug 10 22:29:54 2017 +0200

radeonsi/gfx9: use the VI codepath for clamping Z

This fixes corrupted shadows in Unigine Valley.
The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8
for depth.

Cc: 17.2 
Reviewed-by: Nicolai Hähnle 
(cherry picked from commit 27fef5d52d44c8684fa4e7a21bd7a4284f3688ee)

---

 src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c |  2 +-
 src/gallium/drivers/radeonsi/si_state.c   | 12 +---
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 3b50ca5341..76b8f57f23 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1400,7 +1400,7 @@ static void tex_fetch_args(
 * It's unnecessary if the original texture format was
 * Z32_FLOAT, but we don't know that here.
 */
-   if (ctx->screen->b.chip_class == VI)
+   if (ctx->screen->b.chip_class >= VI)
z = ac_build_clamp(>ac, z);
 
address[count++] = z;
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index b7f55668e0..f5d3f1b8bc 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3162,14 +3162,13 @@ si_make_texture_descriptor(struct si_screen *screen,
   uint32_t *fmask_state)
 {
struct pipe_resource *res = >resource.b.b;
-   const struct util_format_description *base_desc, *desc;
+   const struct util_format_description *desc;
unsigned char swizzle[4];
int first_non_void;
unsigned num_format, data_format, type;
uint64_t va;
 
desc = util_format_description(pipe_format);
-   base_desc = util_format_description(res->format);
 
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_[4] = {0, 0, 0, 0};
@@ -3270,15 +3269,6 @@ si_make_texture_descriptor(struct si_screen *screen,
data_format = 0;
}
 
-   /* Enable clamping for UNORM depth formats promoted to Z32F. */
-   if (screen->b.chip_class >= GFX9 &&
-   util_format_has_depth(desc) &&
-   num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
-   util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
-   /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to 
[0,1]". */
-   data_format = V_008F14_IMG_DATA_FORMAT_24_8;
-   }
-
/* S8 with Z32 HTILE needs a special format. */
if (screen->b.chip_class >= GFX9 &&
pipe_format == PIPE_FORMAT_S8_UINT &&

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Mesa (17.2): egl/x11: don't leak xfixes_query in the error path

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 59f7fdb85e363f40f94e4585561a200282f2d9b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59f7fdb85e363f40f94e4585561a200282f2d9b6

Author: Emil Velikov 
Date:   Thu Aug  3 14:34:53 2017 +0100

egl/x11: don't leak xfixes_query in the error path

If we get a xfixes v1.x we'll error out, without freeing the
xfixes_query reply.

Cc: 
Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
(cherry picked from commit c961b679fe16fc98c3d04d611abc287f1bcc07b5)

---

 src/egl/drivers/dri2/platform_x11.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index b01f739010..d6199c8b94 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -646,6 +646,7 @@ dri2_x11_connect(struct dri2_egl_display *dri2_dpy)
error != NULL || xfixes_query->major_version < 2) {
   _eglLog(_EGL_WARNING, "DRI2: failed to query xfixes version");
   free(error);
+  free(xfixes_query);
   return EGL_FALSE;
}
free(xfixes_query);

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Mesa (17.2): radv: force cs/ps/l2 flush at end of command stream. (v2)

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 1e11687029372dc0f945d5e7a088b6c3ea75d531
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e11687029372dc0f945d5e7a088b6c3ea75d531

Author: Dave Airlie 
Date:   Wed Jul 26 04:37:53 2017 +0100

radv: force cs/ps/l2 flush at end of command stream. (v2)

This seems like a workaround, but we don't see the bug on CIK/VI.

On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.*
tests, when one tests complete, the first flush at the start of the next
test causes a VM fault as we've destroyed the VM, but we end up flushing
the compute shader then, and it must still be in the process of doing
something.

Could also be a kernel difference between SI and CIK.

v2: hit this with a bigger hammer. This fixes a bunch of hangs
in the vk cts with the robustness tests.

Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Acked-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 
(cherry picked from commit 82ba384c10d598bee4786ef5f79e92a0e7b53892)

---

 src/amd/vulkan/radv_cmd_buffer.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b08781171..c73b5f453e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2233,8 +2233,11 @@ VkResult radv_EndCommandBuffer(
 {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
+   if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
+   if (cmd_buffer->device->physical_device->rad_info.chip_class == 
SI)
+   cmd_buffer->state.flush_bits |= 
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | 
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
si_emit_cache_flush(cmd_buffer);
+   }
 
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
cmd_buffer->record_fail)

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Mesa (17.2): radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 07b5c788367df13afe5027a84b2ec305f1e94e5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07b5c788367df13afe5027a84b2ec305f1e94e5a

Author: Dave Airlie 
Date:   Fri Aug  4 02:13:55 2017 +0100

radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)

This is a bug in the app, but I'd rather avoid hanging the GPU,
esp if someone is running in validation and it takes out their
development environment.

v2: get it right, reverse the polarity.

Reviewed-by: Bas Nieuwenhuizen 
Cc: 
Signed-off-by: Dave Airlie 
(cherry picked from commit 36a1b61321561634c6b243cf876c347fef73dfa4)

---

 src/amd/vulkan/radv_meta_resolve.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_resolve.c 
b/src/amd/vulkan/radv_meta_resolve.c
index 6cd0c381a5..6023e0f899 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -382,6 +382,11 @@ void radv_CmdResolveImage(
radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer);
 
assert(src_image->info.samples > 1);
+   if (src_image->info.samples <= 1) {
+   /* this causes GPU hangs if we get past here */
+   fprintf(stderr, "radv: Illegal resolve operation (src not 
multisampled), will hang GPU.");
+   return;
+   }
assert(dest_image->info.samples == 1);
 
if (src_image->info.samples >= 16) {

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Mesa (17.2): isl: Validate row pitch of stencil surfaces.

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: 17.2
Commit: 1c1653d7b0234395493872ff11206743ce40eb6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c1653d7b0234395493872ff11206743ce40eb6c

Author: Kenneth Graunke 
Date:   Wed Aug  9 11:31:48 2017 -0700

isl: Validate row pitch of stencil surfaces.

Also, silence an obnoxious finishme that started occurring for all
GL applications which use stencil after the i965 ISL conversion.

v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using
separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using
combined depth-stencil.

Cc: "17.2" 
Reviewed-by: Jason Ekstrand 
(cherry picked from commit 5563872dbfbf733ed56e1b367bc8944ca59b1c3e)

---

 src/intel/isl/isl.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6b4203d79d..133986782b 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1367,8 +1367,13 @@ isl_calc_row_pitch(const struct isl_device *dev,
!pitch_in_range(row_pitch, 
_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
   return false;
 
-   if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
-  isl_finishme("validate row pitch of stencil surfaces");
+   const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
+  _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
+  _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
+
+   if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
+   !pitch_in_range(row_pitch, stencil_pitch_bits))
+  return false;
 
  done:
*out_row_pitch = row_pitch;

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Mesa: tag mesa-17.2.0-rc4: mesa-17.2.0-rc4

2017-08-12 Thread Emil Velikov 
Module: Mesa
Branch: refs/tags/mesa-17.2.0-rc4
Tag:8c426e05476fad5f674ca276d54a972186f6ce45
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=8c426e05476fad5f674ca276d54a972186f6ce45

Tagger: Emil Velikov 
Date:   Sat Aug 12 17:12:03 2017 +0100

mesa-17.2.0-rc4
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