Re: [PATCH net-next v4 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/19/20 7:49 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
+ dp83td510->rgmii_delay);
Just to be safe, you should always write rgmii_delay, even if it is
zero. We have had too many bugs with RGMII delays which cause bad
backwards compatibility problems, so i would prefer to do a write
which might be unneeded, that find a bug here in a few years time.
OK.
+ if (ret)
+ return ret;
+ }
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
+ ret = phy_modify(phydev, DP83TD510_GEN_CFG,
+DP83TD510_FIFO_DEPTH_MASK,
+dp83td510->tx_fifo_depth);
So there is no need to set the FIFO depth for the other three RGMII
modes? Or should this also be phy_interface_is_rgmii(phydev)?
According to the data sheet the FIFO depth is for RMII.
"Fifo depth for RMII Tx fifo"
But I will ask the HW team for clarification.
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int dp83td510_of_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *of_node = dev->of_node;
You need to move this assignment to later in order to keep with
reverse christmas tree.
Well this is only used once so I will just remove the of_node declaration
+#else
+static int dp83869_of_init(struct phy_device *phydev)
+{
+ dp83td510->hi_diff_output = DP83TD510_2_4V_P2P
+ dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB
You don't have DT, so there is no fine control, but you still need to
do the basic 2ns delay as indicated by the phydev->interface value. So
i think you still need to set dp83td510->rgmii_delay depending on
which RGMII mode is requested.
The RGMII delay is fixed in the PHY. The user can either turn it on or
off. The default is 'off' which is 0.
I can explicitly set the rgmii_delay to 0 in non-OF cases.
Dan
Re: [PATCH net-next v4 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Andrew On 11/17/20 2:31 PM, Andrew Lunn wrote: On Tue, Nov 17, 2020 at 02:15:53PM -0600, Dan Murphy wrote: Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to ability Ack drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..bda1ce51836b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,12 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + max-tx-rx-p2p-microvolt: +description: | + Configures the Tx/Rx p2p differential output voltage for 10base-T1L PHYs. Does it configure, or does it limit? I _think_ this is a negotiation parameter, so the PHY might decide to do 1100mV if the link peer is near by even when max-tx-rx-p2p-microvolt has the higher value. For this device we can configure or force it to only work at 1.1v p2p otherwise 2.4 is the default. But each LP's have to be configured for the same voltage. unless auto negotiation is on then it negotiates the voltage. Dan Andrew
[PATCH net-next v4 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..d3c97bb4d820
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+enum: [ 4, 5, 6, 8 ]
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+unevaluatedProperties: false
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-rx-output-high;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.29.2
[PATCH net-next v4 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
v4 - Considerable rework of the code after secondary test setup was created.
This version also uses the handle_interrupt call back and reduces the
configuration arrays as it was determined that 80% of the array was the same.
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 505
3 files changed, 512 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..a4456e0da447
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+#define DP83TD510_PMD_DEVADDR 0x1
+
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+#define DP83TD510_CTRL_REG 0x1f
+
+#define DP83TD510_ANEG_CTRL0x200
+#define DP83TD510_PMD_CTRL 0x834
+#define DP83TD510_M_S_CTRL 0x8f6
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+#define DP83TD510_LINK_STS BIT(0)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(14)
+#define DP83TD510_AUTO_NEG_EN BIT(12)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+#define DP83TD510_2_4V BIT(12)
+#define DP83TD510_2_4V_P2P 2400
+#define DP83TD510_1_1V_P2P 1100
+#define DP83TD510_AUTO_NEG_P2P 0
+
+const int dp83td510_feature_array[4] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ u32 hi_diff_output;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_errata[] = {
+ { 0x608, 0x003b }, /* disable_0_transition */
+ { 0x862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x8
[PATCH net-next v4 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..bda1ce51836b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,12 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + max-tx-rx-p2p-microvolt: +description: | + Configures the Tx/Rx p2p differential output voltage for 10base-T1L PHYs. +enum: [ 1100, 2400 ] +default: 2400 + required: - reg -- 2.29.2
[PATCH net-next v4 1/4] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TP ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.29.2
[PATCH net-next v4 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (4): ethtool: Add 10base-T1L link mode entries dt-bindings: net: Add Rx/Tx output configuration for 10base T1L dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ethernet-phy.yaml | 6 + .../devicetree/bindings/net/ti,dp83td510.yaml | 64 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 505 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 9 files changed, 591 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.29.2
Re: [net 11/15] can: tcan4x5x: tcan4x5x_can_remove(): fix order of deregistration
Marc
On 11/15/20 11:41 AM, Marc Kleine-Budde wrote:
Change the order in tcan4x5x_can_remove() to be the exact inverse of
tcan4x5x_can_probe(). First m_can_class_unregister(), then power down the
device.
Fixes: 5443c226ba91 ("can: tcan4x5x: Add tcan4x5x driver to the kernel")
Cc: Dan Murphy
Link: http://lore.kernel.org/r/20201019154233.1262589-10-...@pengutronix.de
Signed-off-by: Marc Kleine-Budde
---
drivers/net/can/m_can/tcan4x5x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/m_can/tcan4x5x.c b/drivers/net/can/m_can/tcan4x5x.c
index f058bd9104e9..4fdb7121403a 100644
--- a/drivers/net/can/m_can/tcan4x5x.c
+++ b/drivers/net/can/m_can/tcan4x5x.c
@@ -527,10 +527,10 @@ static int tcan4x5x_can_remove(struct spi_device *spi)
{
struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
- tcan4x5x_power_enable(priv->power, 0);
-
m_can_class_unregister(priv->mcan_dev);
+ tcan4x5x_power_enable(priv->power, 0);
+
return 0;
}
Reviewed-by: Dan Murphy
Re: [net 12/15] can: m_can: m_can_handle_state_change(): fix state change
Marc
On 11/15/20 11:41 AM, Marc Kleine-Budde wrote:
From: Wu Bo
m_can_handle_state_change() is called with the new_state as an argument.
In the switch statements for CAN_STATE_ERROR_ACTIVE, the comment and the
following code indicate that a CAN_STATE_ERROR_WARNING is handled.
This patch fixes this problem by changing the case to CAN_STATE_ERROR_WARNING.
Signed-off-by: Wu Bo
Link: http://lore.kernel.org/r/20200129022330.21248-2-wubo.o...@gmail.com
Cc: Dan Murphy
Fixes: e0d1f4816f2a ("can: m_can: add Bosch M_CAN controller support")
Signed-off-by: Marc Kleine-Budde
---
drivers/net/can/m_can/m_can.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 02c5795b7393..63887e23d89c 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -665,7 +665,7 @@ static int m_can_handle_state_change(struct net_device *dev,
unsigned int ecr;
switch (new_state) {
- case CAN_STATE_ERROR_ACTIVE:
+ case CAN_STATE_ERROR_WARNING:
/* error warning state */
cdev->can.can_stats.error_warning++;
cdev->can.state = CAN_STATE_ERROR_WARNING;
@@ -694,7 +694,7 @@ static int m_can_handle_state_change(struct net_device *dev,
__m_can_get_berr_counter(dev, &bec);
switch (new_state) {
- case CAN_STATE_ERROR_ACTIVE:
+ case CAN_STATE_ERROR_WARNING:
/* error warning state */
cf->can_id |= CAN_ERR_CRTL;
cf->data[1] = (bec.txerr > bec.rxerr) ?
Reviewed-by: Dan Murphy
Re: [net 10/15] can: tcan4x5x: tcan4x5x_can_probe(): add missing error checking for devm_regmap_init()
Marc
On 11/15/20 11:41 AM, Marc Kleine-Budde wrote:
This patch adds the missing error checking when initializing the regmap
interface fails.
Fixes: 5443c226ba91 ("can: tcan4x5x: Add tcan4x5x driver to the kernel")
Cc: Dan Murphy
Link: http://lore.kernel.org/r/20201019154233.1262589-7-...@pengutronix.de
Signed-off-by: Marc Kleine-Budde
---
drivers/net/can/m_can/tcan4x5x.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/can/m_can/tcan4x5x.c b/drivers/net/can/m_can/tcan4x5x.c
index eacd428e07e9..f058bd9104e9 100644
--- a/drivers/net/can/m_can/tcan4x5x.c
+++ b/drivers/net/can/m_can/tcan4x5x.c
@@ -487,6 +487,10 @@ static int tcan4x5x_can_probe(struct spi_device *spi)
priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
&spi->dev, &tcan4x5x_regmap);
+ if (IS_ERR(priv->regmap)) {
+ ret = PTR_ERR(priv->regmap);
+ goto out_clk;
+ }
ret = tcan4x5x_power_enable(priv->power, 1);
if (ret)
Reviewed-by: Dan Murphy
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/3/20 11:18 AM, Andrew Lunn wrote:
On Tue, Nov 03, 2020 at 11:07:00AM -0600, Dan Murphy wrote:
Andrew
On 10/30/20 3:15 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int mst_slave_cfg;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
dp83td510->rgmii_delay);
+ if (ret)
+ return ret;
+ }
+ }
Hi Dan
I'm getting a bit paranoid about RGMII delays...
Not sure what this means.
See the discussion and breakage around the realtek PHY. It wrongly
implemented RGMII delays. When it was fixed, lots of board broke
because the bug in the PHY driver hid bugs in the DT.
I will have to go find that thread. Do you have a link?
Please don't use device_property_read_foo API, we don't want to give
the impression it is O.K. to stuff DT properties in ACPI
tables. Please use of_ API calls.
Hmm. Is this a new stance in DT handling for the networking tree?
If it is should I go back and rework some of my other drivers that use
device_property APIs
There is a slowly growing understanding what ACPI support in this area
means. It seems to mean that the firmware should actually do all the
setup, and the kernel should not touch the hardware configuration. But
some developers are ignoring this, and just stuffing DT properties
into ACPI tables and letting the kernel configure the hardware, if it
happens to use the device_property_read API. So i want to make it
clear that these properties are for device tree, and if you want to
use ACPI, you should do things the ACPI way.
For new code, i will be pushing for OF only calls. Older code is a bit
more tricky. There might be boards out there using ACPI, but doing it
wrongly, and stuffing OF properties into ACPI tables. We should try to
avoid breaking them.
Got it. I will move back to of_* calls
Dan
Andrew
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 11/3/20 11:21 AM, Andrew Lunn wrote:
On Tue, Nov 03, 2020 at 11:09:44AM -0600, Dan Murphy wrote:
Hello
On 10/30/20 6:03 PM, Jakub Kicinski wrote:
On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array'
was not declared. Should it be static?
I did not see this warning. Did you use W=1?
I _think_ that one is W=1. All the PHY drivers are W=1 clean, and i
want to keep it that way. And i hope to make it the default in a lot
of the network code soon.
OK I built with the W=1 before submission I did not see this but I will
try some other things.
Also this:
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#429: FILE: drivers/net/phy/dp83td510.c:371:
+ return -ENOTSUPP;
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#524: FILE: drivers/net/phy/dp83td510.c:466:
+ return -ENOTSUPP;
Same with these warnings how where they reproduced?
Same as above
ERROR: space required before the open parenthesis '('
#580: FILE: drivers/net/phy/dp83td510.c:522:
+ if(phydev->autoneg) {
ERROR: space required before the open parenthesis '('
#588: FILE: drivers/net/phy/dp83td510.c:530:
+ if(phydev->autoneg) {
These look like checkpatch.
These I missed
And please try to wrap the code on 80 chars on the non trivial lines:
What is the LoC limit for networking just for my clarification and I will
align with that.
80. I would not be too surprised to see checkpatch getting a patch to
set it to 80 for networking code.
OK I will align the lines to 80 then.
Dan
Andrew
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Hello
On 10/30/20 6:03 PM, Jakub Kicinski wrote:
On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array'
was not declared. Should it be static?
I did not see this warning. Did you use W=1?
Also this:
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#429: FILE: drivers/net/phy/dp83td510.c:371:
+ return -ENOTSUPP;
WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#524: FILE: drivers/net/phy/dp83td510.c:466:
+ return -ENOTSUPP;
Same with these warnings how where they reproduced?
ERROR: space required before the open parenthesis '('
#580: FILE: drivers/net/phy/dp83td510.c:522:
+ if(phydev->autoneg) {
ERROR: space required before the open parenthesis '('
#588: FILE: drivers/net/phy/dp83td510.c:530:
+ if(phydev->autoneg) {
And please try to wrap the code on 80 chars on the non trivial lines:
What is the LoC limit for networking just for my clarification and I
will align with that.
I know some maintainers like to keep the 80 LoC and some allow a longer
line.
Dan
Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew
On 10/30/20 3:15 PM, Andrew Lunn wrote:
+static int dp83td510_config_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int mst_slave_cfg;
+ int ret = 0;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ if (dp83td510->rgmii_delay) {
+ ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR,
+ DP83TD510_MAC_CFG_1,
dp83td510->rgmii_delay);
+ if (ret)
+ return ret;
+ }
+ }
Hi Dan
I'm getting a bit paranoid about RGMII delays...
Not sure what this means.
+static int dp83td510_read_straps(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ int strap;
+
+ strap = phy_read_mmd(phydev, DP83TD510_DEVADDR, DP83TD510_SOR_1);
+ if (strap < 0)
+ return strap;
+
+ if (strap & DP83TD510_RGMII)
+ dp83td510->is_rgmii = true;
+
+ return 0;
+};
So dp83td510->is_rgmii is the strapping configuration. So if one of
the four RGMII modes is selected, your appear to ignore which of the
four is selected, and program the hardware with the strapping?
That seems like a bad idea.
I will re-look at this code.
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int dp83td510_of_init(struct phy_device *phydev)
+{
+ struct dp83td510_private *dp83td510 = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *of_node = dev->of_node;
+ s32 rx_int_delay;
+ s32 tx_int_delay;
+ int ret;
+
+ if (!of_node)
+ return -ENODEV;
+
+ ret = dp83td510_read_straps(phydev);
+ if (ret)
+ return ret;
+
+ dp83td510->hi_diff_output = device_property_read_bool(&phydev->mdio.dev,
+
"tx-rx-output-high");
+
+ if (device_property_read_u32(&phydev->mdio.dev, "tx-fifo-depth",
+&dp83td510->tx_fifo_depth))
+ dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB;
Please don't use device_property_read_foo API, we don't want to give
the impression it is O.K. to stuff DT properties in ACPI
tables. Please use of_ API calls.
Hmm. Is this a new stance in DT handling for the networking tree?
If it is should I go back and rework some of my other drivers that use
device_property APIs
Dan
Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Andrew On 10/30/20 2:56 PM, Andrew Lunn wrote: On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote: Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. Hi Dan So this property is about the board being able to support the needed voltages? The PHY is not forced into 2.4v p2p, it just says the PHY can operate at 2.4v and the board will not melt, blow a fuse, etc? I actually think it is normal to specify the reverse. List the maximum that device can do because of board restrictions. e.g. - maximum-power-milliwatt : Maximum module power consumption Specifies the maximum power consumption allowable by a module in the slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. - max-link-speed: If present this property specifies PCI gen for link capability. Host drivers could add this as a strategy to avoid unnecessary operation for unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. - max-microvolt : The maximum voltage value supplied to the haptic motor. [The unit of the voltage is a micro] So i think this property should be max-tx-rx-p2p = <1000>; When I was re-writing the code I couldn't come up with a better property name but I like this one. I will implement it. Do you have any issue with the property being in the ethernet-phy.yaml? Dan
[PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L
Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..5cad653e143b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,11 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + tx-rx-output-high: +type: boolean +description: | + Enable the 2.4v p2p differential output voltage for 10base-T1L PHYs. + required: - reg -- 2.28.0.585.ge1cfff676549
[PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..aef949c1cfdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+enum: [ 4, 5, 6, 8 ]
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-rx-output-high;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (4): ethtool: Add 10base-T1L link mode entries dt-bindings: net: Add Rx/Tx output configuration for 10base T1L dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ethernet-phy.yaml | 5 + .../devicetree/bindings/net/ti,dp83td510.yaml | 62 ++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 681 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 9 files changed, 764 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TP ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.28.0.585.ge1cfff676549
[PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 681
3 files changed, 688 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..0d1471bdcd45
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,681 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+#define DP83TD510_PMD_DEVADDR 0x1
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_ANEG_CTRL0x200
+#define DP83TD510_PMD_CTRL 0x834
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(14)
+#define DP83TD510_AUTO_NEG_EN BIT(12)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+const int dp83td510_feature_array[3] = {
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ bool hi_diff_output;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x081a, 0x67c0 }, /* deq offset for 1V swing */
+ { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */
+ { 0x0830, 0x05a3 }, /* Enable energy lost fallback */
+ { 0x0855, 0x1b55 }, /* MSE Threshold change */
+ { 0x0831, 0x0403 }, /* energy detect threshold */
+ { 0x0856, 0x1800 }, /*
Re: [PATCH net-next v2 2/3] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
Andrew On 10/20/20 2:07 PM, Andrew Lunn wrote: Humm. Are 1v and 2.4v advertised so it can be auto negotiated? Maybe a PHY tunable is not correct? Is this voltage selection actually more like pause and EEE? [Goes and looks at the datasheet] Register 0x20E, bit 13: 1 = Advertise that the 10BASE-T1L PHY has increased transmit/ receive level ability 0 = Do not advertise that the 10BASE-T1L PHY has increased transmit/receive level ability (default) So does this mean 2.4v? This can also be strapped to a certain voltage level. The device may not have the regulators on board to drive a 2.4v signal. 1v signal AVDD is 1.8v and 2.4v the AVDD needs to be at least 3.3v This Strap defines the voltage level requested by PHY during auto negotiation. It is reflected in bit 12 of 0x20E. While using Force mode for Linkup, the strap controls the output voltage and reflects in bit 12 of 0x18F6 Bit 12 1 = Enable 2.4 Vpp operating mode 0 = Enable 1.0 Vpp operating mode So maybe this is a hybrid of tunable for master/slave and a DT for voltage level since the ability of the board to drive the signal can vary. Dan Andrew
[PATCH net-next v2 0/3] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (3): ethtool: Add 10base-T1L link mode entries dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 72 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 600 ++ drivers/net/phy/phy-core.c| 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 8 files changed, 688 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH net-next v2 3/3] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 600
3 files changed, 607 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..756497c592bc
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(2)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+enum dp83td510_mode_config {
+ DP83TD510_AUTO_NEG = 0,
+ DP83TD510_MASTER_1 = 1,
+ DP83TD510_MASTER_24 = 2,
+ DP83TD510_SLAVE_1 = 3,
+ DP83TD510_SLAVE_24 = 4,
+};
+
+const int dp83td510_feature_array[3] = {
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+};
+
+struct dp83td510_private {
+ u32 forced_mode;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0007 }, /* disable auto-neg */
+ { 0x000e, 0x0200 },
+ { 0x000d, 0x4007 },
+ { 0x000e, 0x },
+ { 0x000d, 0x0001 }, /* force master mode */
+ { 0x000e, 0x0834 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x4000 },
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x08
[PATCH net-next v2 2/3] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 72 +++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..171aed0f2503
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+ - $ref: "ethernet-phy.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+ ti,master-slave-mode:
+$ref: /schemas/types.yaml#definitions/uint32
+default: 0
+description: |
+ Force the PHY to be configured to a specific mode.
+ Force Auto Negotiation - 0
+ Force Master mode at 1v p2p - 1
+ Force Master mode at 2.4v p2p - 2
+ Force Slave mode at 1v p2p - 3
+ Force Slave mode at 2.4v p2p - 4
+enum: [ 0, 1, 2, 3, 4 ]
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next v2 1/3] ethtool: Add 10base-T1L link mode entries
Add entries for the 10base-T1L full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TPMII ]
Supported link modes: 10baseT1L/Half 10baseT1L/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT1L/Half 10baseT1L/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Full
Auto-negotiation: on
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 8d333d3084ed..616fae7f0c86 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -175,6 +175,8 @@ static const struct phy_setting settings[] = {
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
+ PHY_SETTING( 10, FULL, 10baseT1L_Full ),
+ PHY_SETTING( 10, HALF, 10baseT1L_Half ),
};
#undef PHY_SETTING
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 9ca87bc73c44..16b6ea7548d3 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
+ ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
+ ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 24036e3055a1..95f87febc742 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
__DEFINE_LINK_MODE_NAME(100, FX, Half),
__DEFINE_LINK_MODE_NAME(100, FX, Full),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Half),
+ __DEFINE_LINK_MODE_NAME(10, T1L, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index c5bcb9abc8b9..a8fab6fb1b30 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Half),
+ __DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
};
const struct nla_policy ethnl_linkmodes_set_policy[] = {
--
2.28.0.585.ge1cfff676549
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/19/20 5:04 PM, Dan Murphy wrote: Andrew On 10/19/20 4:55 PM, Andrew Lunn wrote: On Mon, Oct 19, 2020 at 04:33:18PM -0500, Dan Murphy wrote: Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Hi Dan Do you know anything about interropibility? Can a T1 and a T1L talk to each other, if suitably close? I'm wondering if this device should say it is both T1 and T1L? Or just T1L? I personally don't know about interoperability my tests were T1L to T1L but I forwarded these questions to my HW PHY team. HW team says no to interoperability. So we can just add T1L and advertise that type. The DP83TD510L capability is limited to 10Base-T1L only. Dan
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/19/20 4:55 PM, Andrew Lunn wrote: On Mon, Oct 19, 2020 at 04:33:18PM -0500, Dan Murphy wrote: Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Hi Dan Do you know anything about interropibility? Can a T1 and a T1L talk to each other, if suitably close? I'm wondering if this device should say it is both T1 and T1L? Or just T1L? I personally don't know about interoperability my tests were T1L to T1L but I forwarded these questions to my HW PHY team. Dan Andrew
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Andrew On 10/16/20 5:02 PM, Andrew Lunn wrote: On Thu, Oct 08, 2020 at 11:23:47AM -0500, Dan Murphy wrote: The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. Hi Dan I think you are going to have to add ETHTOOL_LINK_MODE_10baseT1_Full_BIT? We already have 100T1 and 1000T1, but not 10T1 :-( The data sheet says 10baseT1L. Which is not there either and seems to be the latest 802.3cg spec and has a greater max distance and used for IoT and Automotive. Dan Andrew
Re: [PATCH net-next 1/2] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
Florian Thanks for the review On 10/8/20 12:11 PM, Florian Fainelli wrote: On 10/8/2020 9:23 AM, Dan Murphy wrote: The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index ..0f0eac77a11a --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + +maintainers: + - Dan Murphy + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. Those two properties are already defined as part of Documentation/devicetree/bindings/net/ethernet-phy.yaml, so you can reference that binding, too. OK I referenced the ethernet-controller.yaml for the delay. I am wondering if we should add rx/tx-fifo-depth to the ethernet-phy.yaml as well. That way PHYs only have to reference ethernet-phy.yaml. Or maybe remove the internal-delay from the ethernet-phy.yaml and reference the ethernet-controller.yaml in the ethernet-phy.yaml so we don't have to maintain duplicate properties + + ti,master-slave-mode: + $ref: /schemas/types.yaml#definitions/uint32 + default: 0 + description: | + Force the PHY to be configured to a specific mode. + Force Auto Negotiation - 0 + Force Master mode at 1v p2p - 1 + Force Master mode at 2.4v p2p - 2 + Force Slave mode at 1v p2p - 3 + Force Slave mode at 2.4v p2p - 4 If you accept different values you should be indicating which values are supported with an enumeration. Ah yes forgot the min/max
Re: [PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
Heiner
On 10/8/20 11:51 AM, Heiner Kallweit wrote:
On 08.10.2020 18:23, Dan Murphy wrote:
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
+static struct phy_driver dp83td510_driver[] = {
+ {
+ PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
+ .name = "TI DP83TD510E",
+ .probe = dp83td510_probe,
+ .config_init= dp83td510_config_init,
+ .soft_reset = dp83td510_phy_reset,
+ .features = PHY_BASIC_FEATURES,
Per default phylib uses genphy_read_abilities() to auto-detect
the features. Doesn't your PHY support the needed clause 22
standard registers? Or are they incorrectly populated?
Maybe better than setting PHY_BASIC_FEATURES and then removing
unsuported features in dp83td510_config_init() would be to
implement phy_driver callback get_features. Then you can set
the supported fatures directly.
Thanks for the review. I will have to look at this maybe the call back
will be better.
I will probably post v2 after net-next opens for 5.10.
I wanted to get some reviews on this patch before net-next closes for
the merge window.
Dan
[PATCH net-next 0/2] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Dan Dan Murphy (2): dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 583 ++ 4 files changed, 660 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
[PATCH net-next 1/2] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY
The DP83TD510 is a 10M single twisted pair Ethernet PHY
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
new file mode 100644
index ..0f0eac77a11a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83TD510 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and
+ RGMII interfaces.
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83td510e.pdf
+
+properties:
+ reg:
+maxItems: 1
+
+ tx-fifo-depth:
+description: |
+ Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble
+ depths. The valid nibble depths are 4, 5, 6 and 8.
+default: 5
+
+ rx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 30ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY has a range of -4 to 4ns
+ relative to transmit data.
+
+ ti,master-slave-mode:
+$ref: /schemas/types.yaml#definitions/uint32
+default: 0
+description: |
+ Force the PHY to be configured to a specific mode.
+ Force Auto Negotiation - 0
+ Force Master mode at 1v p2p - 1
+ Force Master mode at 2.4v p2p - 2
+ Force Slave mode at 1v p2p - 3
+ Force Slave mode at 2.4v p2p - 4
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+tx-fifo-depth = <5>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
--
2.28.0.585.ge1cfff676549
[PATCH net-next 2/2] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY
The DP83TD510E is an ultra-low power Ethernet physical layer transceiver
that supports 10M single pair cable.
The device supports both 2.4-V p2p and 1-V p2p output voltage as defined
by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via
the device tree or the device is defaulted to auto negotiation to
determine the proper p2p voltage.
Signed-off-by: Dan Murphy
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile| 1 +
drivers/net/phy/dp83td510.c | 583
3 files changed, 590 insertions(+)
create mode 100644 drivers/net/phy/dp83td510.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..017252e1504c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -302,6 +302,12 @@ config DP83869_PHY
Currently supports the DP83869 PHY. This PHY supports copper and
fiber connections.
+config DP83TD510_PHY
+ tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY"
+ help
+ Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single
+ pair Ethernet connection.
+
config VITESSE_PHY
tristate "Vitesse PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..bf62ce211eb4 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o
obj-$(CONFIG_DP83867_PHY) += dp83867.o
obj-$(CONFIG_DP83869_PHY) += dp83869.o
obj-$(CONFIG_DP83TC811_PHY)+= dp83tc811.o
+obj-$(CONFIG_DP83TD510_PHY)+= dp83td510.o
obj-$(CONFIG_FIXED_PHY)+= fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
new file mode 100644
index ..0cce9063fd1c
--- /dev/null
+++ b/drivers/net/phy/dp83td510.c
@@ -0,0 +1,583 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Driver for the Texas Instruments DP83TD510 PHY
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DP83TD510E_PHY_ID 0x2180
+#define DP83TD510_DEVADDR_AN 0x7
+#define DP83TD510_DEVADDR 0x1f
+
+#define DP83TD510_MII_REG 0x0
+#define DP83TD510_PHY_STAT 0x10
+#define DP83TD510_GEN_CFG 0x11
+#define DP83TD510_INT_REG1 0x12
+#define DP83TD510_INT_REG2 0x13
+#define DP83TD510_MAC_CFG_10x17
+
+#define DP83TD510_SOR_10x467
+
+#define DP83TD510_HW_RESET BIT(15)
+#define DP83TD510_SW_RESET BIT(14)
+
+/* GEN CFG bits */
+#define DP83TD510_INT_OE BIT(0)
+#define DP83TD510_INT_EN BIT(1)
+
+/* INT REG 1 bits */
+#define DP83TD510_INT1_ESD_EN BIT(3)
+#define DP83TD510_INT1_LINK_EN BIT(5)
+#define DP83TD510_INT1_RHF_EN BIT(7)
+#define DP83TD510_INT1_ESD BIT(11)
+#define DP83TD510_INT1_LINKBIT(13)
+#define DP83TD510_INT1_RHF BIT(15)
+
+/* INT REG 2 bits */
+#define DP83TD510_INT2_POR_EN BIT(0)
+#define DP83TD510_INT2_POL_EN BIT(1)
+#define DP83TD510_INT2_PAGE_EN BIT(5)
+#define DP83TD510_INT2_POR BIT(8)
+#define DP83TD510_INT2_POL BIT(9)
+#define DP83TD510_INT2_PAGEBIT(13)
+
+/* MAC CFG bits */
+#define DP83TD510_RX_CLK_SHIFT BIT(12)
+#define DP83TD510_TX_CLK_SHIFT BIT(11)
+
+#define DP83TD510_MASTER_MODE BIT(2)
+#define DP83TD510_2_4V BIT(7)
+#define DP83TD510_RGMIIBIT(8)
+
+#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5)
+#define DP83TD510_FIFO_DEPTH_4_B_NIB 0
+#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5)
+#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6)
+#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6))
+
+enum dp83td510_mode_config {
+ DP83TD510_AUTO_NEG = 0,
+ DP83TD510_MASTER_1 = 1,
+ DP83TD510_MASTER_24 = 2,
+ DP83TD510_SLAVE_1 = 3,
+ DP83TD510_SLAVE_24 = 4,
+};
+
+struct dp83td510_private {
+ u32 forced_mode;
+ u32 tx_fifo_depth;
+ u32 rgmii_delay;
+ bool is_rgmii;
+};
+
+struct dp83td510_init_reg {
+ int reg;
+ int val;
+};
+
+static struct dp83td510_init_reg dp83td510_master_1_0[] = {
+ { 0x000d, 0x0007 }, /* disable auto-neg */
+ { 0x000e, 0x0200 },
+ { 0x000d, 0x4007 },
+ { 0x000e, 0x },
+ { 0x000d, 0x0001 }, /* force master mode */
+ { 0x000e, 0x0834 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x4000 },
+ { 0x000d, 0x0001 }, /* force 1.0v swing */
+ { 0x000e, 0x08f6 },
+ { 0x000d, 0x4001 },
+ { 0x000e, 0x },
+ { 0x0608, 0x003b }, /* disable_0_transition */
+ { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */
+ { 0x081a, 0x67c0 }, /* deq offset for 1V swing */
+ { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */
+ { 0x0830, 0x05a3 }, /* Enable energy lost fallback */
+ { 0x08
[PATCH net-next 0/2] DP83TD510 Single Pair 10Mbps Ethernet PHY
Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Dan Dan Murphy (2): dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ti,dp83td510.yaml | 70 +++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 583 ++ 4 files changed, 660 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549
Re: [PATCH][next] net: phy: dp83869: fix unsigned comparisons against less than zero values
Colin
On 10/2/20 11:54 AM, Colin King wrote:
From: Colin Ian King
Currently the comparisons of u16 integers value and sopass_val with
less than zero for error checking is always false because the values
are unsigned. Fix this by making these variables int. This does not
affect the shift and mask operations performed on these variables
Addresses-Coverity: ("Unsigned compared against zero")
Fixes: 49fc23018ec6 ("net: phy: dp83869: support Wake on LAN")
Signed-off-by: Colin Ian King
---
drivers/net/phy/dp83869.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 0aee5f645b71..cf6dec7b7d8e 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -305,7 +305,7 @@ static int dp83869_set_wol(struct phy_device *phydev,
static void dp83869_get_wol(struct phy_device *phydev,
struct ethtool_wolinfo *wol)
{
- u16 value, sopass_val;
+ int value, sopass_val;
wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
WAKE_MAGICSECURE);
Wonder why this was not reported before as the previous comparison issue
reported by zero day.
Acked-by: Dan Murphy
Re: [PATCH ethtool v3 1/3] Add missing 400000base modes for dump_link_caps
Michal
On 9/28/20 11:37 AM, Michal Kubecek wrote:
On Mon, Sep 28, 2020 at 09:44:01AM -0500, Dan Murphy wrote:
Commit 63130d0b00040 ("update link mode tables") missed adding in the
40base link_caps to the array.
Signed-off-by: Dan Murphy
---
I'm sorry, I only found these patches shortly after I pushed similar
update as I needed updated UAPI headers for new format descriptions.
Is there an action I need to take here?
[RESEND PATCH net-next v5 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 292 ++ 1 file changed, 292 insertions(+) -- 2.28.0.585.ge1cfff676549
[RESEND PATCH net-next v5 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index de68e56faf3d..0aee5f645b71 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
struct dp83869_private *dp83869
[RESEND PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
v5 - Fixed 0-day warning for u16, removed defconfig
drivers/net/phy/dp83869.c | 176 ++
1 file changed, 176 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 81899bc99add..de68e56faf3d 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -104,6 +112,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -177,6 +193,163 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ int val_rxcfg, val_micr;
+ u8 *mac;
+ int ret;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ if (val_rxcfg < 0)
+ return val_rxcfg;
+
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+ if (val_micr < 0)
+ return val_micr;
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC ||
+ wol->wolopts & WAKE_MAGICSECURE) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD1,
+ mac[1] << 8 | mac[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD2,
+ mac[3] << 8 | mac[2]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD3,
+ mac[5] << 8 | mac[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) |
wol->sopass[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) |
wol->sopass[2]);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) |
wol->sopass[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol-
Re: [PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
Hello On 9/28/20 9:46 AM, Dan Murphy wrote: This adds WoL support on TI DP83869 for magic, magic secure, unicast and broadcast. Signed-off-by: Dan Murphy --- v5 - Fixed 0-day warning for u16 arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + I have to repost this patch as this got added when updating the patches when I was testing. Dan
[PATCH net-next v5 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and broadcast. Signed-off-by: Dan Murphy --- v5 - Fixed 0-day warning for u16 arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + drivers/net/phy/dp83869.c | 176 ++ 2 files changed, 2511 insertions(+) create mode 100644 arch/arm/configs/ti_sdk_omap2_debug_defconfig diff --git a/arch/arm/configs/ti_sdk_omap2_debug_defconfig b/arch/arm/configs/ti_sdk_omap2_debug_defconfig new file mode 100644 index ..e340e0cdc7e3 --- /dev/null +++ b/arch/arm/configs/ti_sdk_omap2_debug_defconfig @@ -0,0 +1,2335 @@ +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PERF_EVENTS=y +CONFIG_MACH_ARTPEC6=y +CONFIG_MACH_ASPEED_G6=y +CONFIG_SOC_SAMA5D2=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +CONFIG_ARCH_BCM_HR2=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_63XX=y +CONFIG_MACH_BERLIN_BG2=y +CONFIG_MACH_BERLIN_BG2CD=y +CONFIG_MACH_BERLIN_BG2Q=y +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX51=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_LS1021A=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_VF610=y +CONFIG_ARCH_MILBEAUT_M10V=y +CONFIG_ARCH_MMP=y +CONFIG_MACH_MMP2_DT=y +CONFIG_MACH_MMP3_DT=y +CONFIG_MACH_ARMADA_370=y +CONFIG_MACH_ARMADA_375=y +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_39X=y +CONFIG_MACH_ARMADA_XP=y +CONFIG_MACH_DOVE=y +CONFIG_MACH_SPEAR1310=y +CONFIG_MACH_SPEAR1340=y +CONFIG_SMP=y +CONFIG_EFI=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y +CONFIG_ARM_ZYNQ_CPUIDLE=y +CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_TRUSTED_FOUNDATIONS=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_EFI_VARS=m +CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_ESP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NET_DSA=m +CONFIG_CAN_AT91=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_SUN4I=y +CONFIG_CAN_XILINXCAN=y +CONFIG_CAN_RCAR=m +CONFIG_CAN_MCP251X=y +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MVEBU=y +CONFIG_PCI_TEGRA=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PCIE_RCAR=y +CONFIG_OMAP_OCP2SCP=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_VF610_NFC=y +CONFIG_MTD_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_ASPEED_SMC=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VIRTIO_BLK=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_ATMEL_TCLIB=y +CONFIG_ICS932S401=y +CONFIG_ATMEL_SSC=m +CONFIG_QCOM_COINCELL=m +CONFIG_APDS9802ALS=y +CONFIG_ISL29003=y +CONFIG_BLK_DEV_SR=y +CONFIG_AHCI_BRCM=y +CONFIG_AHCI_DM816=y +CONFIG_AHCI_ST=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_SUNXI=y +CONFIG_AHCI_TEGRA=y +CONFIG_SATA_HIGHBANK=y +CONFIG_SATA_MV=y +CONFIG_SATA_RCAR=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_SUN4I_EMAC=y +CONFIG_BGMAC_BCMA=y +CONFIG_MACB=y +CONFIG_NET_CALXEDA_XGMAC=y +CONFIG_FTGMAC100=m +CONFIG_GIANFAR=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_MV643XX_ETH=y +CONFIG_MVNETA=y +CONFIG_PXA168_ETH=m +CONFIG_KS8851=y +CONFIG_R8169=y +CONFIG_SH_ETH=y +CONFIG_SMSC911X=y +CONFIG_SNI_AVE=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_XILINX_EMACLITE=y +CONFIG_AT803X_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_SMSC75XX=y +CONFIG_BRCMFMAC=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_RT2X00=m +CONFIG_RT2800USB=m +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_TEGRA=y +CONFIG_KEYBOARD_PXA27x=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_ST_KEYSCAN=y +CONFIG_KEYBOARD_SPEAR=y +CONFIG_KEYBOARD_CROS_EC=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=y +CONFIG_TOUCHSCREEN_ADC=m
[PATCH net-next v5 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index de68e56faf3d..0aee5f645b71 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
struct dp83869_private *dp83869
[PATCH net-next v5 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature arch/arm/configs/ti_sdk_omap2_debug_defconfig | 2335 + drivers/net/phy/dp83869.c | 292 +++ 2 files changed, 2627 insertions(+) create mode 100644 arch/arm/configs/ti_sdk_omap2_debug_defconfig -- 2.28.0.585.ge1cfff676549
[PATCH ethtool v3 2/3] update UAPI header copies
Update to kernel commit 55f13311785c
Signed-off-by: Dan Murphy
---
uapi/linux/ethtool.h | 2 ++
uapi/linux/ethtool_netlink.h | 19 ++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/uapi/linux/ethtool.h b/uapi/linux/ethtool.h
index 847ccd0b1fce..052689bcc90c 100644
--- a/uapi/linux/ethtool.h
+++ b/uapi/linux/ethtool.h
@@ -1615,6 +1615,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT = 87,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT = 88,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/uapi/linux/ethtool_netlink.h b/uapi/linux/ethtool_netlink.h
index cebdb52e6a05..c022883cdb22 100644
--- a/uapi/linux/ethtool_netlink.h
+++ b/uapi/linux/ethtool_netlink.h
@@ -79,6 +79,7 @@ enum {
ETHTOOL_MSG_TSINFO_GET_REPLY,
ETHTOOL_MSG_CABLE_TEST_NTF,
ETHTOOL_MSG_CABLE_TEST_TDR_NTF,
+ ETHTOOL_MSG_TUNNEL_INFO_GET_REPLY,
/* add new constants above here */
__ETHTOOL_MSG_KERNEL_CNT,
@@ -91,9 +92,12 @@ enum {
#define ETHTOOL_FLAG_COMPACT_BITSETS (1 << 0)
/* provide optional reply for SET or ACT requests */
#define ETHTOOL_FLAG_OMIT_REPLY(1 << 1)
+/* request statistics, if supported by the driver */
+#define ETHTOOL_FLAG_STATS (1 << 2)
#define ETHTOOL_FLAG_ALL (ETHTOOL_FLAG_COMPACT_BITSETS | \
- ETHTOOL_FLAG_OMIT_REPLY)
+ ETHTOOL_FLAG_OMIT_REPLY | \
+ ETHTOOL_FLAG_STATS)
enum {
ETHTOOL_A_HEADER_UNSPEC,
@@ -376,12 +380,25 @@ enum {
ETHTOOL_A_PAUSE_AUTONEG,/* u8 */
ETHTOOL_A_PAUSE_RX, /* u8 */
ETHTOOL_A_PAUSE_TX, /* u8 */
+ ETHTOOL_A_PAUSE_STATS, /* nest - _PAUSE_STAT_*
*/
/* add new constants above here */
__ETHTOOL_A_PAUSE_CNT,
ETHTOOL_A_PAUSE_MAX = (__ETHTOOL_A_PAUSE_CNT - 1)
};
+enum {
+ ETHTOOL_A_PAUSE_STAT_UNSPEC,
+ ETHTOOL_A_PAUSE_STAT_PAD,
+
+ ETHTOOL_A_PAUSE_STAT_TX_FRAMES,
+ ETHTOOL_A_PAUSE_STAT_RX_FRAMES,
+
+ /* add new constants above here */
+ __ETHTOOL_A_PAUSE_STAT_CNT,
+ ETHTOOL_A_PAUSE_STAT_MAX = (__ETHTOOL_A_PAUSE_STAT_CNT - 1)
+};
+
/* EEE */
enum {
--
2.28.0.585.ge1cfff676549
[PATCH ethtool v3 1/3] Add missing 400000base modes for dump_link_caps
Commit 63130d0b00040 ("update link mode tables") missed adding in the
40base link_caps to the array.
Signed-off-by: Dan Murphy
---
ethtool.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/ethtool.c b/ethtool.c
index 4f93c0f96985..974b14063de2 100644
--- a/ethtool.c
+++ b/ethtool.c
@@ -659,6 +659,16 @@ static void dump_link_caps(const char *prefix, const char
*an_prefix,
"20baseDR4/Full" },
{ 0, ETHTOOL_LINK_MODE_20baseCR4_Full_BIT,
"20baseCR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_40baseKR4_Full_BIT,
+ "40baseKR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_40baseSR4_Full_BIT,
+ "40baseSR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT,
+ "40baseLR4_ER4_FR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_40baseDR4_Full_BIT,
+ "40baseDR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_40baseCR4_Full_BIT,
+ "40baseCR4/Full" },
};
int indent;
int did1, new_line_pend;
--
2.28.0.585.ge1cfff676549
[PATCH ethtool v3 3/3] Update link mode tables for fiber
Update the link mode tables to include 100base Fx Full and Half duplex
modes.
Signed-off-by: Dan Murphy
---
ethtool.8.in | 2 ++
ethtool.c | 6 ++
netlink/settings.c | 2 ++
3 files changed, 10 insertions(+)
diff --git a/ethtool.8.in b/ethtool.8.in
index d0921949b37e..7c6e23e28ffa 100644
--- a/ethtool.8.in
+++ b/ethtool.8.in
@@ -794,6 +794,8 @@ lB l lB.
0x80 40baseLR4_ER4_FR4 Full
0x100 40baseDR4 Full
0x200 40baseCR4 Full
+0x400 100baseFX Half
+0x800 100baseFX Full
.TE
.TP
.BI phyad \ N
diff --git a/ethtool.c b/ethtool.c
index 974b14063de2..39a1862a72a4 100644
--- a/ethtool.c
+++ b/ethtool.c
@@ -463,6 +463,8 @@ static void init_global_link_mode_masks(void)
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
};
static const enum ethtool_link_mode_bit_indices
additional_advertised_flags_bits[] = {
@@ -669,6 +671,10 @@ static void dump_link_caps(const char *prefix, const char
*an_prefix,
"40baseDR4/Full" },
{ 0, ETHTOOL_LINK_MODE_40baseCR4_Full_BIT,
"40baseCR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ "100baseFx/Half" },
+ { 1, ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+ "100baseFx/Full" },
};
int indent;
int did1, new_line_pend;
diff --git a/netlink/settings.c b/netlink/settings.c
index 3059d4d0d0b7..41a2e5af1945 100644
--- a/netlink/settings.c
+++ b/netlink/settings.c
@@ -162,6 +162,8 @@ static const struct link_mode_info link_modes[] = {
[ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_40baseDR4_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_40baseCR4_Full_BIT] = __REAL(40),
+ [ETHTOOL_LINK_MODE_100baseFX_Half_BIT] = __HALF_DUPLEX(100),
+ [ETHTOOL_LINK_MODE_100baseFX_Full_BIT] = __REAL(100),
};
const unsigned int link_modes_count = ARRAY_SIZE(link_modes);
--
2.28.0.585.ge1cfff676549
[PATCH ethtool v2 2/2] Update link mode tables for fiber
Update the link mode tables to include 100base Fx Full and Half duplex
modes.
Signed-off-by: Dan Murphy
---
ethtool.c | 6 ++
netlink/settings.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/ethtool.c b/ethtool.c
index ab9b4577cbce..2f71fa92bb09 100644
--- a/ethtool.c
+++ b/ethtool.c
@@ -463,6 +463,8 @@ static void init_global_link_mode_masks(void)
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
};
static const enum ethtool_link_mode_bit_indices
additional_advertised_flags_bits[] = {
@@ -659,6 +661,10 @@ static void dump_link_caps(const char *prefix, const char
*an_prefix,
"20baseDR4/Full" },
{ 0, ETHTOOL_LINK_MODE_20baseCR4_Full_BIT,
"20baseCR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ "100baseFx/Half" },
+ { 1, ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+ "100baseFx/Full" },
};
int indent;
int did1, new_line_pend;
diff --git a/netlink/settings.c b/netlink/settings.c
index 3059d4d0d0b7..41a2e5af1945 100644
--- a/netlink/settings.c
+++ b/netlink/settings.c
@@ -162,6 +162,8 @@ static const struct link_mode_info link_modes[] = {
[ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_40baseDR4_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_40baseCR4_Full_BIT] = __REAL(40),
+ [ETHTOOL_LINK_MODE_100baseFX_Half_BIT] = __HALF_DUPLEX(100),
+ [ETHTOOL_LINK_MODE_100baseFX_Full_BIT] = __REAL(100),
};
const unsigned int link_modes_count = ARRAY_SIZE(link_modes);
--
2.28.0.585.ge1cfff676549
[PATCH ethtool v2 1/2] update UAPI header copies
Update to kernel commit 55f13311785c
Signed-off-by: Dan Murphy
---
uapi/linux/ethtool.h | 2 ++
uapi/linux/ethtool_netlink.h | 19 ++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/uapi/linux/ethtool.h b/uapi/linux/ethtool.h
index 847ccd0b1fce..052689bcc90c 100644
--- a/uapi/linux/ethtool.h
+++ b/uapi/linux/ethtool.h
@@ -1615,6 +1615,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT = 87,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT = 88,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/uapi/linux/ethtool_netlink.h b/uapi/linux/ethtool_netlink.h
index cebdb52e6a05..c022883cdb22 100644
--- a/uapi/linux/ethtool_netlink.h
+++ b/uapi/linux/ethtool_netlink.h
@@ -79,6 +79,7 @@ enum {
ETHTOOL_MSG_TSINFO_GET_REPLY,
ETHTOOL_MSG_CABLE_TEST_NTF,
ETHTOOL_MSG_CABLE_TEST_TDR_NTF,
+ ETHTOOL_MSG_TUNNEL_INFO_GET_REPLY,
/* add new constants above here */
__ETHTOOL_MSG_KERNEL_CNT,
@@ -91,9 +92,12 @@ enum {
#define ETHTOOL_FLAG_COMPACT_BITSETS (1 << 0)
/* provide optional reply for SET or ACT requests */
#define ETHTOOL_FLAG_OMIT_REPLY(1 << 1)
+/* request statistics, if supported by the driver */
+#define ETHTOOL_FLAG_STATS (1 << 2)
#define ETHTOOL_FLAG_ALL (ETHTOOL_FLAG_COMPACT_BITSETS | \
- ETHTOOL_FLAG_OMIT_REPLY)
+ ETHTOOL_FLAG_OMIT_REPLY | \
+ ETHTOOL_FLAG_STATS)
enum {
ETHTOOL_A_HEADER_UNSPEC,
@@ -376,12 +380,25 @@ enum {
ETHTOOL_A_PAUSE_AUTONEG,/* u8 */
ETHTOOL_A_PAUSE_RX, /* u8 */
ETHTOOL_A_PAUSE_TX, /* u8 */
+ ETHTOOL_A_PAUSE_STATS, /* nest - _PAUSE_STAT_*
*/
/* add new constants above here */
__ETHTOOL_A_PAUSE_CNT,
ETHTOOL_A_PAUSE_MAX = (__ETHTOOL_A_PAUSE_CNT - 1)
};
+enum {
+ ETHTOOL_A_PAUSE_STAT_UNSPEC,
+ ETHTOOL_A_PAUSE_STAT_PAD,
+
+ ETHTOOL_A_PAUSE_STAT_TX_FRAMES,
+ ETHTOOL_A_PAUSE_STAT_RX_FRAMES,
+
+ /* add new constants above here */
+ __ETHTOOL_A_PAUSE_STAT_CNT,
+ ETHTOOL_A_PAUSE_STAT_MAX = (__ETHTOOL_A_PAUSE_STAT_CNT - 1)
+};
+
/* EEE */
enum {
--
2.28.0.585.ge1cfff676549
[PATCH net-next v4 2/2] net: phy: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
v4 - Fixed error from E2BIG to EINVAL
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 975b64b4b6c4..8d4440326432 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -120,6 +122,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -350,6 +364,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -EINVAL;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
[PATCH net-next v4 0/2] DP83869 WoL and Speed optimization
Hello Add the WoL and Speed Optimization (aka downshift) support for the DP83869 Ethernet PHY. Dan Dan Murphy (2): net: phy: dp83869: support Wake on LAN net: phy: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 292 ++ 1 file changed, 292 insertions(+) -- 2.28.0
[PATCH net-next v4 1/2] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
v4 - Added checking error on phy_read
drivers/net/phy/dp83869.c | 176 ++
1 file changed, 176 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 81899bc99add..975b64b4b6c4 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -104,6 +112,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -177,6 +193,163 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ u16 val_rxcfg, val_micr;
+ u8 *mac;
+ int ret;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ if (val_rxcfg < 0)
+ return val_rxcfg;
+
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+ if (val_micr < 0)
+ return val_micr;
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC ||
+ wol->wolopts & WAKE_MAGICSECURE) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD1,
+ mac[1] << 8 | mac[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD2,
+ mac[3] << 8 | mac[2]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFPMD3,
+ mac[5] << 8 | mac[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) |
wol->sopass[0]);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) |
wol->sopass[2]);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+ DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) |
wol->sopass[4]);
+ if (ret)
+ return ret;
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol-
[PATCH net-next v2 1/3] ethtool: Add 100base-FX link mode entries
Add entries for the 100base-FX full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ FIBRE ]
Supported link modes: 100baseFX/Half 100baseFX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: 100baseFX/Half 100baseFX/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: off
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
v2 - Updated ethtool example in the commit message no other functional changes
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index ff8e14b01eeb..de5b869139d7 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -160,6 +160,8 @@ static const struct phy_setting settings[] = {
PHY_SETTING(100, FULL,100baseT_Full ),
PHY_SETTING(100, FULL,100baseT1_Full),
PHY_SETTING(100, HALF,100baseT_Half ),
+ PHY_SETTING(100, HALF,100baseFX_Half),
+ PHY_SETTING(100, FULL,100baseFX_Full),
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index b4f2d134e713..9ca87bc73c44 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1617,6 +1617,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT = 87,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT = 88,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index ed19573fccd7..24036e3055a1 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -192,6 +192,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, LR4_ER4_FR4, Full),
__DEFINE_LINK_MODE_NAME(40, DR4, Full),
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
+ __DEFINE_LINK_MODE_NAME(100, FX, Half),
+ __DEFINE_LINK_MODE_NAME(100, FX, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index 7044a2853886..29dcd675b65a 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -272,6 +272,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, LR4_ER4_FR4, Full),
__DEFINE_LINK_MODE_PARAMS(40, DR4, Full),
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(100, FX, Half),
+ __DEFINE_LINK_MODE_PARAMS(100, FX, Full),
};
static const struct nla_policy
--
2.28.0
[PATCH net-next v2 3/3] net: phy: dp83822: Update the fiber advertisement for speed
Update the fiber advertisement for speed and duplex modes with the
100base-FX full and half linkmode entries.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83822.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 732c8bec7452..c162c9551bd1 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -110,9 +110,8 @@
#define DP83822_RX_ER_SHIFT8
#define MII_DP83822_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
- ADVERTISED_FIBRE | ADVERTISED_BNC | \
- ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
- ADVERTISED_100baseT_Full)
+ ADVERTISED_FIBRE | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause)
struct dp83822_private {
bool fx_signal_det_low;
@@ -406,6 +405,14 @@ static int dp83822_config_init(struct phy_device *phydev)
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->advertising);
/* Auto neg is not supported in fiber mode */
bmcr = phy_read(phydev, MII_BMCR);
--
2.28.0
[PATCH net-next v2 0/3] 100base Fx link modes
Hello As per patch https://lore.kernel.org/patchwork/patch/1300241/ the link modes for 100base FX full and half duplex modes did not exist. Adding these link modes to the core and ethtool allow devices like the DP83822, DP83869 and Broadcomm PHYs to properly advertise the correct mode for Fiber 100Mbps. Corresponding user land ethtool patches are available but rely on these patches to be applied first. Dan Dan Murphy (3): ethtool: Add 100base-FX link mode entries net: dp83869: Add ability to advertise Fiber connection net: phy: dp83822: Update the fiber advertisement for speed drivers/net/phy/dp83822.c| 13 +-- drivers/net/phy/dp83869.c| 73 drivers/net/phy/phy-core.c | 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 6 files changed, 92 insertions(+), 4 deletions(-) -- 2.28.0
[PATCH net-next v2 2/3] net: dp83869: Add ability to advertise Fiber connection
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 6b98d74b5102..81899bc99add 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,10 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_FIBRE | \
+ ADVERTISED_Pause | \
+ ADVERTISED_Asym_Pause)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULTMII_DP83869_BMCR_DEFAULT
@@ -118,6 +122,28 @@ struct dp83869_private {
int mode;
};
+static int dp83869_read_status(struct phy_device *phydev)
+{
+ struct dp83869_private *dp83869 = phydev->priv;
+ int ret;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
+ if (phydev->link) {
+ if (dp83869->mode == DP83869_RGMII_100_BASE)
+ phydev->speed = SPEED_100;
+ } else {
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ }
+ }
+
+ return 0;
+}
+
static int dp83869_ack_interrupt(struct phy_device *phydev)
{
int err = phy_read(phydev, MII_DP83869_ISR);
@@ -295,6 +321,51 @@ static int dp83869_configure_rgmii(struct phy_device
*phydev,
return ret;
}
+static int dp83869_configure_fiber(struct phy_device *phydev,
+ struct dp83869_private *dp83869)
+{
+ int bmcr;
+ int ret;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
+ linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
+
+ if (dp83869->mode == DP83869_RGMII_1000_BASE) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+phydev->supported);
+ } else {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->supported);
+
+ /* Auto neg is not supported in 100base FX mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ /* Update advertising from supported */
+ linkmode_or(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ return 0;
+}
+
static int dp83869_configure_mode(struct phy_device *phydev,
struct dp83869_private *dp83869)
{
@@ -384,6 +455,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
break;
case DP83869_RGMII_1000_BASE:
case DP83869_RGMII_100_BASE:
+ ret = dp83869_configure_fiber(phydev, dp83869);
break;
default:
return -EINVAL;
@@ -494,6 +566,7 @@ static struct phy_driver dp83869_driver[] = {
/* IRQ related */
.ack_interrupt = dp83869_ack_interrupt,
.config_intr= dp83869_config_intr,
+ .read_status= dp83869_read_status,
.suspend= genphy_suspend,
.resume = genphy_resume,
--
2.28.0
Re: [PATCH net-next 1/3] ethtool: Add 100base-FX link mode entries
Andrew On 9/15/20 6:29 PM, Dan Murphy wrote: Andrew On 9/15/20 3:21 PM, Andrew Lunn wrote: On Tue, Sep 15, 2020 at 01:17:06PM -0500, Dan Murphy wrote: Add entries for the 100base-FX full and half duplex supported modes. $ ethtool eth0 Supported ports: [ TP MII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 100baseFX/Half 100baseFX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 100baseFX/Half 100baseFX/Full I thought this PHY could not switch between TP and Fibre. It has a strap which decides? So i would expect the supported modes to be either BaseT or BaseFX. Not both. Same for Advertised? Andrew I found that the phy-device was setting all these bits in phy_init in features_init. My first pass was to clear all these bits as well because the PHY was still advertising these modes. But you are right this PHY cannot switch without strapping. I can clear these bits. I re-read your reply and this is just an example. This patch really has nothing to do with any PHY as it is just adding in the new link modes. Unless you comment wanted me to remove the TP and advertised modes from the example in the commit message? Dan Dan
Re: [PATCH net-next v4 5/5] ravb: Add support for explicit internal clock delay configuration
Geert
On 9/17/20 8:57 AM, Geert Uytterhoeven wrote:
Some EtherAVB variants support internal clock delay configuration, which
can add larger delays than the delays that are typically supported by
the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
properties).
Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode. This caused issues with PHY drivers that
implement PHY internal delays properly[1]. Hence a backwards-compatible
workaround was added by masking the PHY mode[2].
Add proper support for explicit configuration of the MAC internal clock
delays using the new "[rt]x-internal-delay-ps" properties.
Fall back to the old handling if none of these properties is present.
[1] Commit bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for
the KSZ9031 PHY")
[2] Commit 9b23203c32ee02cd ("ravb: Mask PHY mode to avoid inserting
delays twice").
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Sergei Shtylyov
Reviewed-by: Florian Fainelli
---
v4:
- Add Reviewed-by,
v3:
- No changes,
v2:
- Add Reviewed-by,
- Split long line,
- Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps",
- Use 1 instead of true when assigning to a single-bit bitfield.
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 36 ++--
2 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h
b/drivers/net/ethernet/renesas/ravb.h
index e5ca12ce93c730a9..7453b17a37a2c8d0 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1038,6 +1038,7 @@ struct ravb_private {
unsigned wol_enabled:1;
unsigned rxcidm:1; /* RX Clock Internal Delay Mode */
unsigned txcidm:1; /* TX Clock Internal Delay Mode */
+ unsigned rgmii_override:1; /* Deprecated rgmii-*id behavior */
int num_tx_desc;/* TX descriptors per packet */
};
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 59dadd971345e0d1..aa120e3f1e4d4da5 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1034,11 +1034,8 @@ static int ravb_phy_init(struct net_device *ndev)
pn = of_node_get(np);
}
- iface = priv->phy_interface;
- if (priv->chip_id != RCAR_GEN2 && phy_interface_mode_is_rgmii(iface)) {
- /* ravb_set_delay_mode() takes care of internal delay mode */
- iface = PHY_INTERFACE_MODE_RGMII;
- }
+ iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
+: priv->phy_interface;
phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
of_node_put(pn);
if (!phydev) {
@@ -1989,20 +1986,41 @@ static const struct soc_device_attribute
ravb_delay_mode_quirk_match[] = {
};
/* Set tx and rx clock internal delay modes */
-static void ravb_parse_delay_mode(struct net_device *ndev)
+static void ravb_parse_delay_mode(struct device_node *np, struct net_device
*ndev)
{
struct ravb_private *priv = netdev_priv(ndev);
+ bool explicit_delay = false;
+ u32 delay;
+
+ if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 1800, according to DT bindings */
+ priv->rxcidm = !!delay;
+ explicit_delay = true;
+ }
+ if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 2000, according to DT bindings */
+ priv->txcidm = !!delay;
+ explicit_delay = true;
+ }
There are helper functions for this
s32 phy_get_internal_delay(struct phy_device *phydev, struct device
*dev, const int *delay_values, int size, bool is_rx)
Re: [PATCH net-next 2/3] net: dp83869: Add ability to advertise Fiber connection
Andrew On 9/16/20 5:13 PM, Andrew Lunn wrote: On Wed, Sep 16, 2020 at 03:54:34PM -0500, Dan Murphy wrote: Andrew On 9/15/20 3:17 PM, Andrew Lunn wrote: + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, +phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, +phydev->supported); + + /* Auto neg is not supported in 100base FX mode */ Hi Dan If it does not support auto neg, how do you decide to do half duplex? I don't see any code here which allows the user to configure it. Ethtool has the provisions to set the duplex and speed right?. What i'm getting at is you say you support ETHTOOL_LINK_MODE_100baseFX_Full_BIT & ETHTOOL_LINK_MODE_100baseFX_Half_BIT. If there is no auto neg in FX mode, i'm questioning how these two different modes code be used? I'm guessing the PHY defaults to ETHTOOL_LINK_MODE_100baseFX_Full_BIT? How does the user set it to ETHTOOL_LINK_MODE_100baseFX_Half_BIT? The user can use ethtool to set the speed and duplex. And ethtool uses the IOCTLs to configure the device. So if the user creates their own HAL then they can use those IOCTLs as well. The data sheet indicates "In fiber mode, the speed is not decided through auto-negotiation. Both sides of the link must be configured to the same operating speed." The only call back I see which is valid is config_aneg which would still require a user space tool to set the needed link modes. Correct. Maybe all you need to do is point me at the code in the driver which actually sets the PHY into half duplex in FX mode when the user asks for it. Is it just clearing BMCR_FULLDPLX? Here is the full flow when setting the speed and duplex mode from the Ethtool or when the IOCTL's are called to update the PHY phy_ethtool_ksettings_set updates the phydev->speed and phydev->duplex Since Auto Neg is disabled the call to genphy_setup_forced is done in the __genphy_config_aneg in phy_device. genphy_setup_forced updates the BMCR with the updated values. So IMO there is no need to populate the config_aneg call back to root@am335x-evm:~# ./ethtool -s eth0 speed 10 duplex half [ 92.098491] phy_ethtool_ksettings_set [ 92.102247] phy_ethtool_ksettings_set: speed 10 duplex 0 [ 92.107755] phy_sanitize_settings [ 92.111085] phy_config_aneg [ 92.113930] genphy_config_aneg [ 92.116997] __genphy_config_aneg [ 92.120237] genphy_setup_forced [ 92.123419] genphy_setup_forced: Update the BMCR root@am335x-evm:~# ./ethtool -s eth0 speed 100 duplex full [ 102.693105] phy_ethtool_ksettings_set [ 102.697029] phy_ethtool_ksettings_set: speed 100 duplex 1 [ 102.702462] phy_sanitize_settings [ 102.705892] phy_config_aneg [ 102.708702] genphy_config_aneg [ 102.711770] __genphy_config_aneg [ 102.715051] genphy_setup_forced [ 102.718209] genphy_setup_forced: Update the BMCR I am hoping this answers your question. Dan
Re: [PATCH net-next 2/3] net: dp83869: Add ability to advertise Fiber connection
Andrew On 9/15/20 3:17 PM, Andrew Lunn wrote: + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, +phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, +phydev->supported); + + /* Auto neg is not supported in 100base FX mode */ Hi Dan If it does not support auto neg, how do you decide to do half duplex? I don't see any code here which allows the user to configure it. Ethtool has the provisions to set the duplex and speed right?. The only call back I see which is valid is config_aneg which would still require a user space tool to set the needed link modes. I could implement the config_aneg to call genphy_setup_forced if auto neg is disabled but that function just writes the BMCR which is already updated and if auto neg is enabled it would just call genphy_check_and_restart_aneg. I verified the ethtool path with the DP83822 by reading the BMCR and ethtool displayed the correct advertisement root@am335x-evm:~# ethtool -s eth0 speed 100 duplex full root@am335x-evm:~# ethtool eth0 Settings for eth0: Supported ports: [ TP MII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 100baseT/Full root@am335x-evm:~# ethtool -s eth0 speed 10 duplex half root@am335x-evm:~# ethtool eth0 Settings for eth0: Supported ports: [ TP MII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 10baseT/Half root@am335x-evm:~# ./mdio-test g eth0 0 0x root@am335x-evm:~# ethtool -s eth0 speed 100 duplex full root@am335x-evm:~# ./mdio-test g eth0 0 0x2100 root@am335x-evm:~# ethtool -s eth0 speed 10 duplex half root@am335x-evm:~# ./mdio-test g eth0 0 0x root@am335x-evm:~# ethtool -s eth0 speed 10 duplex full root@am335x-evm:~# ./mdio-test g eth0 0 0x0100 root@am335x-evm:~# ethtool eth0 Settings for eth0: Supported ports: [ TP MII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 10baseT/Full Dan
Re: [PATCH net-next 1/3] ethtool: Add 100base-FX link mode entries
Andrew On 9/15/20 3:21 PM, Andrew Lunn wrote: On Tue, Sep 15, 2020 at 01:17:06PM -0500, Dan Murphy wrote: Add entries for the 100base-FX full and half duplex supported modes. $ ethtool eth0 Supported ports: [ TPMII FIBRE ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 100baseFX/Half 100baseFX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 100baseFX/Half 100baseFX/Full I thought this PHY could not switch between TP and Fibre. It has a strap which decides? So i would expect the supported modes to be either BaseT or BaseFX. Not both. Same for Advertised? Andrew I found that the phy-device was setting all these bits in phy_init in features_init. My first pass was to clear all these bits as well because the PHY was still advertising these modes. But you are right this PHY cannot switch without strapping. I can clear these bits. Dan
Re: [PATCH net-next 1/3] ethtool: Add 100base-FX link mode entries
Andrew
On 9/15/20 3:10 PM, Andrew Lunn wrote:
On Tue, Sep 15, 2020 at 01:17:06PM -0500, Dan Murphy wrote:
@@ -160,6 +160,8 @@ static const struct phy_setting settings[] = {
PHY_SETTING(100, FULL,100baseT_Full ),
PHY_SETTING(100, FULL,100baseT1_Full),
PHY_SETTING(100, HALF,100baseT_Half ),
+ PHY_SETTING(100, HALF,100baseFX_Half),
+ PHY_SETTING(100, FULL,100baseFX_Full),
Hi Dan
Does 100baseFX_Half make an sense? My understanding of 802.3 section
26 is that it is always a pair, not a single fibre where you might
need CSMA/CD?
I actually questioned that too and looked it up
I found these and thought they could be viable
http://www.certiology.com/tech-terms/network/100base-fx.html
"The 100Base-FX can be used in a maximum length of 412 meters if being
used in
half-duplex connections or as 2 kilometer lengths in the case of
full-duplex transmissions over optical fiber."
https://www.cnet.com/products/half-duplex-100basefx-interface-pb7/
Of course I never have seen one myself
Dan
Andrew
[PATCH net-next 0/3] 100base Fx link modes
Hello As per patch https://lore.kernel.org/patchwork/patch/1300241/ the link modes for 100base FX full and half duplex modes did not exist. Adding these link modes to the core and ethtool allow devices like the DP83822, DP83869 and Broadcomm PHYs to properly advertise the correct mode for Fiber 100Mbps. Corresponding user land ethtool patches are available but rely on these patches to be applied first. Dan Dan Murphy (3): ethtool: Add 100base-FX link mode entries net: dp83869: Add ability to advertise Fiber connection net: phy: dp83822: Update the fiber advertisement for speed drivers/net/phy/dp83822.c| 13 +-- drivers/net/phy/dp83869.c| 73 drivers/net/phy/phy-core.c | 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 6 files changed, 92 insertions(+), 4 deletions(-) -- 2.28.0
[PATCH net-next 3/3] net: phy: dp83822: Update the fiber advertisement for speed
Update the fiber advertisement for speed and duplex modes with the
100base-FX full and half linkmode entries.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83822.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 732c8bec7452..c162c9551bd1 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -110,9 +110,8 @@
#define DP83822_RX_ER_SHIFT8
#define MII_DP83822_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
- ADVERTISED_FIBRE | ADVERTISED_BNC | \
- ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
- ADVERTISED_100baseT_Full)
+ ADVERTISED_FIBRE | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause)
struct dp83822_private {
bool fx_signal_det_low;
@@ -406,6 +405,14 @@ static int dp83822_config_init(struct phy_device *phydev)
phydev->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->advertising);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->advertising);
/* Auto neg is not supported in fiber mode */
bmcr = phy_read(phydev, MII_BMCR);
--
2.28.0
[PATCH net-next 1/3] ethtool: Add 100base-FX link mode entries
Add entries for the 100base-FX full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ TPMII FIBRE ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
100baseFX/Half 100baseFX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
100baseFX/Half 100baseFX/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: off
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x (0)
Link detected: yes
Signed-off-by: Dan Murphy
---
drivers/net/phy/phy-core.c | 4 +++-
include/uapi/linux/ethtool.h | 2 ++
net/ethtool/common.c | 2 ++
net/ethtool/linkmodes.c | 2 ++
4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index ff8e14b01eeb..de5b869139d7 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync.
"
"If a speed or mode has been added please update
phy_speed_to_str "
"and the PHY settings array.\n");
@@ -160,6 +160,8 @@ static const struct phy_setting settings[] = {
PHY_SETTING(100, FULL,100baseT_Full ),
PHY_SETTING(100, FULL,100baseT1_Full),
PHY_SETTING(100, HALF,100baseT_Half ),
+ PHY_SETTING(100, HALF,100baseFX_Half),
+ PHY_SETTING(100, FULL,100baseFX_Full),
/* 10M */
PHY_SETTING( 10, FULL, 10baseT_Full ),
PHY_SETTING( 10, HALF, 10baseT_Half ),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index b4f2d134e713..9ca87bc73c44 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1617,6 +1617,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseLR4_ER4_FR4_Full_BIT = 87,
ETHTOOL_LINK_MODE_40baseDR4_Full_BIT = 88,
ETHTOOL_LINK_MODE_40baseCR4_Full_BIT = 89,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index ed19573fccd7..24036e3055a1 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -192,6 +192,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(40, LR4_ER4_FR4, Full),
__DEFINE_LINK_MODE_NAME(40, DR4, Full),
__DEFINE_LINK_MODE_NAME(40, CR4, Full),
+ __DEFINE_LINK_MODE_NAME(100, FX, Half),
+ __DEFINE_LINK_MODE_NAME(100, FX, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index 7044a2853886..29dcd675b65a 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -272,6 +272,8 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(40, LR4_ER4_FR4, Full),
__DEFINE_LINK_MODE_PARAMS(40, DR4, Full),
__DEFINE_LINK_MODE_PARAMS(40, CR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(100, FX, Half),
+ __DEFINE_LINK_MODE_PARAMS(100, FX, Full),
};
static const struct nla_policy
--
2.28.0
[PATCH net-next 2/3] net: dp83869: Add ability to advertise Fiber connection
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 6b98d74b5102..81899bc99add 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,10 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_FIBRE | \
+ ADVERTISED_Pause | \
+ ADVERTISED_Asym_Pause)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULTMII_DP83869_BMCR_DEFAULT
@@ -118,6 +122,28 @@ struct dp83869_private {
int mode;
};
+static int dp83869_read_status(struct phy_device *phydev)
+{
+ struct dp83869_private *dp83869 = phydev->priv;
+ int ret;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
+ if (phydev->link) {
+ if (dp83869->mode == DP83869_RGMII_100_BASE)
+ phydev->speed = SPEED_100;
+ } else {
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ }
+ }
+
+ return 0;
+}
+
static int dp83869_ack_interrupt(struct phy_device *phydev)
{
int err = phy_read(phydev, MII_DP83869_ISR);
@@ -295,6 +321,51 @@ static int dp83869_configure_rgmii(struct phy_device
*phydev,
return ret;
}
+static int dp83869_configure_fiber(struct phy_device *phydev,
+ struct dp83869_private *dp83869)
+{
+ int bmcr;
+ int ret;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
+ linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
+
+ if (dp83869->mode == DP83869_RGMII_1000_BASE) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+phydev->supported);
+ } else {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+phydev->supported);
+
+ /* Auto neg is not supported in 100base FX mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ /* Update advertising from supported */
+ linkmode_or(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ return 0;
+}
+
static int dp83869_configure_mode(struct phy_device *phydev,
struct dp83869_private *dp83869)
{
@@ -384,6 +455,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
break;
case DP83869_RGMII_1000_BASE:
case DP83869_RGMII_100_BASE:
+ ret = dp83869_configure_fiber(phydev, dp83869);
break;
default:
return -EINVAL;
@@ -494,6 +566,7 @@ static struct phy_driver dp83869_driver[] = {
/* IRQ related */
.ack_interrupt = dp83869_ack_interrupt,
.config_intr= dp83869_config_intr,
+ .read_status= dp83869_read_status,
.suspend= genphy_suspend,
.resume = genphy_resume,
--
2.28.0
[PATCH 0/1] Adding 100base FX support
Hello I am adding the 100base Fx support for the ethtool. There are a few PHYs that support the Fiber connection and the ethtool should be able to properly display that the PHY supports the 100base-FX Full and Half Duplex modes. I am adding this support in the ethtool first and then submit the fiber bits into the kernel. If the kernel needs to be updated first then I can prepare those patches and reference them. Dan Dan Murphy (1): ethtool: Add 100BaseFX half and full duplex link modes ethtool.c| 6 ++ netlink/settings.c | 2 ++ uapi/linux/ethtool.h | 2 ++ 3 files changed, 10 insertions(+) -- 2.28.0
[PATCH 1/1] ethtool: Add 100BaseFX half and full duplex link modes
The kernel can now indicate if the PHY supports operating over a
fiber cable at 100Mbps either Full or Half duplex.
Signed-off-by: Dan Murphy
---
ethtool.c| 6 ++
netlink/settings.c | 2 ++
uapi/linux/ethtool.h | 2 ++
3 files changed, 10 insertions(+)
diff --git a/ethtool.c b/ethtool.c
index 606af3e6b48f..84ad21467206 100644
--- a/ethtool.c
+++ b/ethtool.c
@@ -443,6 +443,8 @@ static void init_global_link_mode_masks(void)
ETHTOOL_LINK_MODE_20baseCR4_Full_BIT,
ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
};
static const enum ethtool_link_mode_bit_indices
additional_advertised_flags_bits[] = {
@@ -639,6 +641,10 @@ static void dump_link_caps(const char *prefix, const char
*an_prefix,
"20baseDR4/Full" },
{ 0, ETHTOOL_LINK_MODE_20baseCR4_Full_BIT,
"20baseCR4/Full" },
+ { 0, ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ "100baseFx/Half" },
+ { 1, ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
+ "100baseFx/Full" },
};
int indent;
int did1, new_line_pend;
diff --git a/netlink/settings.c b/netlink/settings.c
index 935724e799da..a11c85756ca6 100644
--- a/netlink/settings.c
+++ b/netlink/settings.c
@@ -147,6 +147,8 @@ static const struct link_mode_info link_modes[] = {
[ETHTOOL_LINK_MODE_40baseDR8_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_40baseCR8_Full_BIT] = __REAL(40),
[ETHTOOL_LINK_MODE_FEC_LLRS_BIT]= __SPECIAL(FEC),
+ [ETHTOOL_LINK_MODE_100baseFX_Half_BIT] = __HALF_DUPLEX(100),
+ [ETHTOOL_LINK_MODE_100baseFX_Full_BIT] = __REAL(100),
};
const unsigned int link_modes_count = ARRAY_SIZE(link_modes);
diff --git a/uapi/linux/ethtool.h b/uapi/linux/ethtool.h
index a1cfbe2ef40f..5c58555fecb4 100644
--- a/uapi/linux/ethtool.h
+++ b/uapi/linux/ethtool.h
@@ -1598,6 +1598,8 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_40baseDR8_Full_BIT = 72,
ETHTOOL_LINK_MODE_40baseCR8_Full_BIT = 73,
ETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
+ ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
--
2.28.0
Re: [PATCH net-next v3 2/3] net: phy: dp83869: support Wake on LAN
Andrew
On 9/10/20 1:02 PM, Andrew Lunn wrote:
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
struct dp83869_private *dp83869 = phydev->priv;
Overall this code looks quite similar to dp83867, is there no way to
factor this out?
Factor what out? Yes the DP83867 and DP83869 are very similar in registers
and bitmaps. They just differ in their feature sets.
The WoL code was copied and pasted to the 869 and I would like to keep the
two files as similar as I can as it will be easier to fix and find bugs.
It will be even easier if they shared the same code. You could create
a library of functions, like bcm-phy-lib.c.
If I do that I would want to add in the DP83822 and the DP83811 as well
even though the SOP and Data registers are different the code is the same.
I can just pass in the register numbers in.
That will have to be something I refactor later as it will rip up at
least 4 TI drivers if not more.
Dan
Re: [PATCH net-next v3 1/3] net: dp83869: Add ability to advertise Fiber connection
Hello
On 9/7/20 9:29 AM, Andrew Lunn wrote:
On Sat, Sep 05, 2020 at 11:17:55AM -0700, Jakub Kicinski wrote:
On Thu, 3 Sep 2020 06:42:57 -0500 Dan Murphy wrote:
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
Some comments, I'm not very phy-knowledgeable so bear with me
(hopefully PHY maintainers can correct me, too).
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..48a68474f89c 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,11 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
I'm not actually sure myself what the semantics of port type advertise
bits are, but if this is fiber why advertise TP and do you really have
BNC connectors? :S
Hi Jakub
Normally, we start with a base of ETHTOOL_LINK_MODE_TP_BIT,
ETHTOOL_LINK_MODE_MII_BIT and then use genphy_read_abilities() to read
the standard registers in the PHY to determine what the PHY
supports. The PHY driver has the ability of provide its own function
to get the supported features, which is happening here. As far as i
remember, there is no standard way to indicate a PHY is doing Fibre,
not copper.
I agree that TP and BMC make no sense here, since my understanding is
that the device only supports Fibre when strapped for Fibre. It cannot
swap to TP, and it has been at least 20 years since i last had a BNC
cable in my hands.
In this context, i've no idea what MII means.
I will remove the TP and BNC.
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
You say 100Base-FX, yet you advertise 100Base-T?
100Base-FX does not actually exist in ADVERTISED_X form. I guess this
is historical. It was not widely supported, the broadcom PHYs appear
to support it, but not much else. We were also running out of bits to
represent these ADVERTISED_X values. Now that we have changed to linux
bitmaps and have unlimited number of bits, it makes sense to add it.
The note in the ethtool.h says
/* Last allowed bit for __ETHTOOL_LINK_MODE_LEGACY_MASK is bit
* 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
* macro for bits > 31. The only way to use indices > 31 is to
* use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
*/
Which was added by Heiner
I guess I would prefer to add this in a separate patchset once I figure
out how the ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API works
@@ -383,7 +389,37 @@ static int dp83869_configure_mode(struct phy_device
*phydev,
break;
case DP83869_RGMII_1000_BASE:
+ break;
case DP83869_RGMII_100_BASE:
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ phy_modify_changed(phydev, MII_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE);
This only accesses standard registers, should it perhaps be a helper in
the kernel's phy code?
I suspect the PHY is not following the standard when strapped to
fibre.
No its a bit wonky in that respect.
Dan
Re: [PATCH net-next v3 3/3] net: dp83869: Add speed optimization feature
Jakub
On 9/8/20 12:47 PM, Jakub Kicinski wrote:
On Tue, 8 Sep 2020 09:07:22 -0500 Dan Murphy wrote:
On 9/5/20 1:38 PM, Jakub Kicinski wrote:
On Thu, 3 Sep 2020 06:42:59 -0500 Dan Murphy wrote:
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -E2BIG;
ERANGE
This is not checking a range but making sure it is not bigger then 8.
IMO I would use ERANGE if the check was a boundary check for upper and
lower bounds.
Yeah, ERANGE is not perfect, but the strerror for E2BIG is
"Argument list too long" - IDK if users seeing that will know that it
means the value is too large. Perhaps we should stick to EINVAL?
EINVAL works for me to.
Dan
Re: [PATCH net-next v3 2/3] net: phy: dp83869: support Wake on LAN
Jakub
Thanks for the review
On 9/5/20 1:34 PM, Jakub Kicinski wrote:
On Thu, 3 Sep 2020 06:42:58 -0500 Dan Murphy wrote:
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 48a68474f89c..5045df9515a5 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS10x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG0x0170
#define DP83869_OP_MODE 0x01df
#define DP83869_FX_CTRL 0x0c00
@@ -105,6 +113,14 @@
#define DP83869_OP_MODE_MII BIT(5)
#define DP83869_SGMII_RGMII_BRIDGEBIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -156,6 +172,115 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ u16 val_rxcfg, val_micr;
+ u8 *mac;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
In the previous patch you checked if phy_read() failed, here you don't.
I will add it back
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD1,
+ (mac[1] << 8 | mac[0]));
parenthesis unnecessary
OK
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD2,
+ (mac[3] << 8 | mac[2]));
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD3,
+ (mac[5] << 8 | mac[4]));
Why only program mac addr for wake_magic, does magic_secure or unicast
not require it?
Unicast and broadcast are the ways to send the magic packet.
Magic secure is programmed below into the SOP (secure on pass) registers
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) | wol->sopass[0]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) | wol->sopass[2]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) | wol->sopass[4]);
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol->wolopts & WAKE_UCAST)
+ val_rxcfg |= DP83869_WOL_UCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_UCAST_EN;
+
+ if (wol->wolopts & WAKE_BCAST)
+ val_rxcfg |= DP83869_WOL_BCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_BCAST_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_ENH_MAC;
+ val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
+ }
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFC
Re: [PATCH net-next v3 3/3] net: dp83869: Add speed optimization feature
Jakub
On 9/5/20 1:38 PM, Jakub Kicinski wrote:
On Thu, 3 Sep 2020 06:42:59 -0500 Dan Murphy wrote:
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -E2BIG;
ERANGE
This is not checking a range but making sure it is not bigger then 8.
IMO I would use ERANGE if the check was a boundary check for upper and
lower bounds.
Dan
[PATCH net-next v2] net: phy: dp83867: Fix various styling and space issues
Fix spacing issues reported for misaligned switch..case and extra new
lines.
Also updated the file header to comply with networking commet style.
Reviewed-by: Florian Fainelli
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83867.c | 45 ++-
1 file changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index f3c04981b8da..ca26ccc6dfa4 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/*
- * Driver for the Texas Instruments DP83867 PHY
+/* Driver for the Texas Instruments DP83867 PHY
*
* Copyright (C) 2015 Texas Instruments Inc.
*/
@@ -113,7 +112,6 @@
#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
-
/* IO_MUX_CFG bits */
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX0x0
@@ -384,22 +382,22 @@ static int dp83867_set_downshift(struct phy_device
*phydev, u8 cnt)
DP83867_DOWNSHIFT_EN);
switch (cnt) {
- case DP83867_DOWNSHIFT_1_COUNT:
- count = DP83867_DOWNSHIFT_1_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_2_COUNT:
- count = DP83867_DOWNSHIFT_2_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_4_COUNT:
- count = DP83867_DOWNSHIFT_4_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_8_COUNT:
- count = DP83867_DOWNSHIFT_8_COUNT_VAL;
- break;
- default:
- phydev_err(phydev,
- "Downshift count must be 1, 2, 4 or 8\n");
- return -EINVAL;
+ case DP83867_DOWNSHIFT_1_COUNT:
+ count = DP83867_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_2_COUNT:
+ count = DP83867_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_4_COUNT:
+ count = DP83867_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_8_COUNT:
+ count = DP83867_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
}
val = DP83867_DOWNSHIFT_EN;
@@ -411,7 +409,7 @@ static int dp83867_set_downshift(struct phy_device *phydev,
u8 cnt)
}
static int dp83867_get_tunable(struct phy_device *phydev,
- struct ethtool_tunable *tuna, void *data)
+ struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
@@ -422,7 +420,7 @@ static int dp83867_get_tunable(struct phy_device *phydev,
}
static int dp83867_set_tunable(struct phy_device *phydev,
- struct ethtool_tunable *tuna, const void *data)
+ struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
@@ -524,11 +522,10 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->io_impedance = -1; /* leave at default */
dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
- "ti,dp83867-rxctrl-strap-quirk");
+
"ti,dp83867-rxctrl-strap-quirk");
dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
- "ti,sgmii-ref-clock-output-enable");
-
+
"ti,sgmii-ref-clock-output-enable");
dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
--
2.28.0
Re: [PATCH net] net: phy: dp83867: Fix various styling and space issues
Florian On 9/3/20 11:34 AM, Florian Fainelli wrote: On 9/3/2020 7:15 AM, Dan Murphy wrote: Fix spacing issues reported for misaligned switch..case and extra new lines. Also updated the file header to comply with networking commet style. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83867.c | 47 ++- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index cd7032628a28..f182a8d767c6 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Driver for the Texas Instruments DP83867 PHY +/* Driver for the Texas Instruments DP83867 PHY * * Copyright (C) 2015 Texas Instruments Inc. */ @@ -35,7 +34,7 @@ #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) -#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) +#define DP83867_CFG4_SGMII_ANEG_TIMER_2US BIT(5) Now the definitions are inconsistent, you would want to drop this one and stick to the existing style. OK I was a little conflicted making that change due to the reasons you mentioned. But if that is an acceptable warning I am ok with it. The rest of the changes look good, so with that fixed, and the subject correct to "net-next" (this is no bug fix material), you can add: I will have to reapply this to the net-next to make sure it applies cleanly there. But not an issue. Dan Reviewed-by: Florian Fainelli
[PATCH net-next v3 0/3] DP83869 Feature additions
Hello Adding features to the DP83869 PHY. These features are also supported in other TI PHYs like the DP83867 and DP83822. Fiber Advertisement: The DP83869 supports a 100Base-FX connection. When this mode is selected the driver needs to advertise that this PHY supports fiber. WoL: The PHY also supports Wake on Lan feature with SecureOn password. Downshift: Speed optimization or AKA downshift is also supported by this PHY. Dan Dan Murphy (3): net: dp83869: Add ability to advertise Fiber connection net: phy: dp83869: support Wake on LAN net: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 280 ++ 1 file changed, 280 insertions(+) -- 2.28.0
[PATCH net-next v3 2/3] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 48a68474f89c..5045df9515a5 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -105,6 +113,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -156,6 +172,115 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ u16 val_rxcfg, val_micr;
+ u8 *mac;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD1,
+ (mac[1] << 8 | mac[0]));
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD2,
+ (mac[3] << 8 | mac[2]));
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD3,
+ (mac[5] << 8 | mac[4]));
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) | wol->sopass[0]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) | wol->sopass[2]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) | wol->sopass[4]);
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol->wolopts & WAKE_UCAST)
+ val_rxcfg |= DP83869_WOL_UCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_UCAST_EN;
+
+ if (wol->wolopts & WAKE_BCAST)
+ val_rxcfg |= DP83869_WOL_BCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_BCAST_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_ENH_MAC;
+ val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
+ }
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
+ phy_write(phydev, MII_DP83869_MICR, val_micr);
+
+ return 0;
+}
+
+static void dp83869_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u16 value, sopass_val;
+
+ wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
+ WAKE_MAGICSECURE);
+ wol->wolopts = 0;
+
+ value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+
+ if (value & DP83869_W
[PATCH net-next v3 1/3] net: dp83869: Add ability to advertise Fiber connection
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..48a68474f89c 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,11 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULTMII_DP83869_BMCR_DEFAULT
@@ -300,6 +305,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
{
int phy_ctrl_val;
int ret;
+ int bmcr;
if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
@@ -383,7 +389,37 @@ static int dp83869_configure_mode(struct phy_device
*phydev,
break;
case DP83869_RGMII_1000_BASE:
+ break;
case DP83869_RGMII_100_BASE:
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ phy_modify_changed(phydev, MII_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE);
break;
default:
return -EINVAL;
--
2.28.0
[PATCH net] net: phy: dp83867: Fix various styling and space issues
Fix spacing issues reported for misaligned switch..case and extra new
lines.
Also updated the file header to comply with networking commet style.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83867.c | 47 ++-
1 file changed, 22 insertions(+), 25 deletions(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index cd7032628a28..f182a8d767c6 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/*
- * Driver for the Texas Instruments DP83867 PHY
+/* Driver for the Texas Instruments DP83867 PHY
*
* Copyright (C) 2015 Texas Instruments Inc.
*/
@@ -35,7 +34,7 @@
#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
-#define DP83867_CFG4_SGMII_ANEG_TIMER_2US(1 << 5)
+#define DP83867_CFG4_SGMII_ANEG_TIMER_2USBIT(5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
#define DP83867_RGMIICTL 0x0032
@@ -113,7 +112,6 @@
#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
-
/* IO_MUX_CFG bits */
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX0x0
@@ -384,22 +382,22 @@ static int dp83867_set_downshift(struct phy_device
*phydev, u8 cnt)
DP83867_DOWNSHIFT_EN);
switch (cnt) {
- case DP83867_DOWNSHIFT_1_COUNT:
- count = DP83867_DOWNSHIFT_1_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_2_COUNT:
- count = DP83867_DOWNSHIFT_2_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_4_COUNT:
- count = DP83867_DOWNSHIFT_4_COUNT_VAL;
- break;
- case DP83867_DOWNSHIFT_8_COUNT:
- count = DP83867_DOWNSHIFT_8_COUNT_VAL;
- break;
- default:
- phydev_err(phydev,
- "Downshift count must be 1, 2, 4 or 8\n");
- return -EINVAL;
+ case DP83867_DOWNSHIFT_1_COUNT:
+ count = DP83867_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_2_COUNT:
+ count = DP83867_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_4_COUNT:
+ count = DP83867_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83867_DOWNSHIFT_8_COUNT:
+ count = DP83867_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
}
val = DP83867_DOWNSHIFT_EN;
@@ -411,7 +409,7 @@ static int dp83867_set_downshift(struct phy_device *phydev,
u8 cnt)
}
static int dp83867_get_tunable(struct phy_device *phydev,
- struct ethtool_tunable *tuna, void *data)
+ struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
@@ -422,7 +420,7 @@ static int dp83867_get_tunable(struct phy_device *phydev,
}
static int dp83867_set_tunable(struct phy_device *phydev,
- struct ethtool_tunable *tuna, const void *data)
+ struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
@@ -524,11 +522,10 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->io_impedance = -1; /* leave at default */
dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
- "ti,dp83867-rxctrl-strap-quirk");
+
"ti,dp83867-rxctrl-strap-quirk");
dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
- "ti,sgmii-ref-clock-output-enable");
-
+
"ti,sgmii-ref-clock-output-enable");
dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
--
2.28.0
[PATCH net-next v3 3/3] net: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
v3 - Fixed checkpatch format issues
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 5045df9515a5..5d0130cf5a44 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -121,6 +123,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -281,6 +295,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -E2BIG;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static int dp83869_config_port_mirroring(struct phy_device *phydev)
{
Re: [PATCH net-next v2 3/3] net: dp83869: Add speed optimization feature
Jakub
On 9/2/20 9:06 PM, Jakub Kicinski wrote:
On Wed, 2 Sep 2020 15:34:44 -0500 Dan Murphy wrote:
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
there seems to be lots of checkpatch warnings here:
ERROR: switch and case should be at the same indent
#111: FILE: drivers/net/phy/dp83869.c:342:
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
[...]
+ case DP83869_DOWNSHIFT_2_COUNT:
[...]
+ case DP83869_DOWNSHIFT_4_COUNT:
[...]
+ case DP83869_DOWNSHIFT_8_COUNT:
[...]
+ default:
CHECK: Alignment should match open parenthesis
#139: FILE: drivers/net/phy/dp83869.c:370:
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
CHECK: Alignment should match open parenthesis
#150: FILE: drivers/net/phy/dp83869.c:381:
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
WARNING: please, no spaces at the start of a line
#168: FILE: drivers/net/phy/dp83869.c:669:
+ ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,$
ERROR: code indent should use tabs where possible
#169: FILE: drivers/net/phy/dp83869.c:670:
+DP83869_DOWNSHIFT_EN);$
WARNING: please, no spaces at the start of a line
#169: FILE: drivers/net/phy/dp83869.c:670:
+DP83869_DOWNSHIFT_EN);$
WARNING: please, no spaces at the start of a line
#170: FILE: drivers/net/phy/dp83869.c:671:
+ if (ret)$
WARNING: suspect code indent for conditional statements (7, 15)
#170: FILE: drivers/net/phy/dp83869.c:671:
+ if (ret)
+ return ret;
ERROR: code indent should use tabs where possible
#171: FILE: drivers/net/phy/dp83869.c:672:
+ return ret;$
WARNING: please, no spaces at the start of a line
#171: FILE: drivers/net/phy/dp83869.c:672:
+ return ret;$
total: 3 errors, 5 warnings, 2 checks, 152 lines checked
I will fix these.
Dan
[PATCH net-next v2 2/3] net: phy: dp83869: support Wake on LAN
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 48a68474f89c..5045df9515a5 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -27,6 +28,13 @@
#define DP83869_RGMIICTL 0x0032
#define DP83869_STRAP_STS1 0x006e
#define DP83869_RGMIIDCTL 0x0086
+#define DP83869_RXFCFG 0x0134
+#define DP83869_RXFPMD10x0136
+#define DP83869_RXFPMD20x0137
+#define DP83869_RXFPMD30x0138
+#define DP83869_RXFSOP10x0139
+#define DP83869_RXFSOP20x013A
+#define DP83869_RXFSOP30x013B
#define DP83869_IO_MUX_CFG 0x0170
#define DP83869_OP_MODE0x01df
#define DP83869_FX_CTRL0x0c00
@@ -105,6 +113,14 @@
#define DP83869_OP_MODE_MIIBIT(5)
#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
+/* RXFCFG bits*/
+#define DP83869_WOL_MAGIC_EN BIT(0)
+#define DP83869_WOL_PATTERN_EN BIT(1)
+#define DP83869_WOL_BCAST_EN BIT(2)
+#define DP83869_WOL_UCAST_EN BIT(4)
+#define DP83869_WOL_SEC_EN BIT(5)
+#define DP83869_WOL_ENH_MACBIT(7)
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -156,6 +172,115 @@ static int dp83869_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83869_MICR, micr_status);
}
+static int dp83869_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *ndev = phydev->attached_dev;
+ u16 val_rxcfg, val_micr;
+ u8 *mac;
+
+ val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+ val_micr = phy_read(phydev, MII_DP83869_MICR);
+
+ if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
+ WAKE_BCAST)) {
+ val_rxcfg |= DP83869_WOL_ENH_MAC;
+ val_micr |= MII_DP83869_MICR_WOL_INT_EN;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ mac = (u8 *)ndev->dev_addr;
+
+ if (!is_valid_ether_addr(mac))
+ return -EINVAL;
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD1,
+ (mac[1] << 8 | mac[0]));
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD2,
+ (mac[3] << 8 | mac[2]));
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFPMD3,
+ (mac[5] << 8 | mac[4]));
+
+ val_rxcfg |= DP83869_WOL_MAGIC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
+ }
+
+ if (wol->wolopts & WAKE_MAGICSECURE) {
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP1,
+ (wol->sopass[1] << 8) | wol->sopass[0]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP2,
+ (wol->sopass[3] << 8) | wol->sopass[2]);
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFSOP3,
+ (wol->sopass[5] << 8) | wol->sopass[4]);
+
+ val_rxcfg |= DP83869_WOL_SEC_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_SEC_EN;
+ }
+
+ if (wol->wolopts & WAKE_UCAST)
+ val_rxcfg |= DP83869_WOL_UCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_UCAST_EN;
+
+ if (wol->wolopts & WAKE_BCAST)
+ val_rxcfg |= DP83869_WOL_BCAST_EN;
+ else
+ val_rxcfg &= ~DP83869_WOL_BCAST_EN;
+ } else {
+ val_rxcfg &= ~DP83869_WOL_ENH_MAC;
+ val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
+ }
+
+ phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
+ phy_write(phydev, MII_DP83869_MICR, val_micr);
+
+ return 0;
+}
+
+static void dp83869_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u16 value, sopass_val;
+
+ wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
+ WAKE_MAGICSECURE);
+ wol->wolopts = 0;
+
+ value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
+
+ if (value & DP83869_W
[PATCH net-next v2 3/3] net: dp83869: Add speed optimization feature
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 5045df9515a5..06a228dac92b 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
@@ -20,6 +21,7 @@
#define MII_DP83869_PHYCTRL0x10
#define MII_DP83869_MICR 0x12
#define MII_DP83869_ISR0x13
+#define DP83869_CFG2 0x14
#define DP83869_CTRL 0x1f
#define DP83869_CFG4 0x1e
@@ -121,6 +123,18 @@
#define DP83869_WOL_SEC_EN BIT(5)
#define DP83869_WOL_ENH_MACBIT(7)
+/* CFG2 bits */
+#define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9))
+#define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
+#define DP83869_DOWNSHIFT_1_COUNT_VAL 0
+#define DP83869_DOWNSHIFT_2_COUNT_VAL 1
+#define DP83869_DOWNSHIFT_4_COUNT_VAL 2
+#define DP83869_DOWNSHIFT_8_COUNT_VAL 3
+#define DP83869_DOWNSHIFT_1_COUNT 1
+#define DP83869_DOWNSHIFT_2_COUNT 2
+#define DP83869_DOWNSHIFT_4_COUNT 4
+#define DP83869_DOWNSHIFT_8_COUNT 8
+
enum {
DP83869_PORT_MIRRORING_KEEP,
DP83869_PORT_MIRRORING_EN,
@@ -281,6 +295,99 @@ static void dp83869_get_wol(struct phy_device *phydev,
wol->wolopts = 0;
}
+static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val, cnt, enable, count;
+
+ val = phy_read(phydev, DP83869_CFG2);
+ if (val < 0)
+ return val;
+
+ enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
+ cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_1_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_2_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_4_COUNT;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT_VAL:
+ count = DP83869_DOWNSHIFT_8_COUNT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ int val, count;
+
+ if (cnt > DP83869_DOWNSHIFT_8_COUNT)
+ return -E2BIG;
+
+ if (!cnt)
+ return phy_clear_bits(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN);
+
+ switch (cnt) {
+ case DP83869_DOWNSHIFT_1_COUNT:
+ count = DP83869_DOWNSHIFT_1_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_2_COUNT:
+ count = DP83869_DOWNSHIFT_2_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_4_COUNT:
+ count = DP83869_DOWNSHIFT_4_COUNT_VAL;
+ break;
+ case DP83869_DOWNSHIFT_8_COUNT:
+ count = DP83869_DOWNSHIFT_8_COUNT_VAL;
+ break;
+ default:
+ phydev_err(phydev,
+ "Downshift count must be 1, 2, 4 or 8\n");
+ return -EINVAL;
+ }
+
+ val = DP83869_DOWNSHIFT_EN;
+ val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
+
+ return phy_modify(phydev, DP83869_CFG2,
+ DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
+ val);
+}
+
+static int dp83869_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int dp83869_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return dp83869_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+
[PATCH net-next v2 1/3] net: dp83869: Add ability to advertise Fiber connection
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..48a68474f89c 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,11 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULTMII_DP83869_BMCR_DEFAULT
@@ -300,6 +305,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
{
int phy_ctrl_val;
int ret;
+ int bmcr;
if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
@@ -383,7 +389,37 @@ static int dp83869_configure_mode(struct phy_device
*phydev,
break;
case DP83869_RGMII_1000_BASE:
+ break;
case DP83869_RGMII_100_BASE:
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ phy_modify_changed(phydev, MII_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE,
+ MII_DP83869_FIBER_ADVERTISE);
break;
default:
return -EINVAL;
--
2.28.0
[PATCH net-next v2 0/3] DP83869 Feature additions
Hello Adding features to the DP83869 PHY. These features are also supported in other TI PHYs like the DP83867 and DP83822. Fiber Advertisement: (This is v2 fixing the return of phy_modify) The DP83869 supports a 100Base-FX connection. When this mode is selected the driver needs to advertise that this PHY supports fiber. WoL: The PHY also supports Wake on Lan feature with SecureOn password. Downshift: Speed optimization or AKA downshift is also supported by this PHY. Dan Murphy (3): net: dp83869: Add ability to advertise Fiber connection net: phy: dp83869: support Wake on LAN net: dp83869: Add speed optimization feature drivers/net/phy/dp83869.c | 280 ++ 1 file changed, 280 insertions(+) -- 2.28.0
[PATCH net] net: dp83867: Fix WoL SecureOn password
Fix the registers being written to as the values were being over written
when writing the same registers.
Fixes: caabee5b53f5 ("net: phy: dp83867: support Wake on LAN")
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83867.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index f3c04981b8da..cd7032628a28 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -215,9 +215,9 @@ static int dp83867_set_wol(struct phy_device *phydev,
if (wol->wolopts & WAKE_MAGICSECURE) {
phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
(wol->sopass[1] << 8) | wol->sopass[0]);
- phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
(wol->sopass[3] << 8) | wol->sopass[2]);
- phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
(wol->sopass[5] << 8) | wol->sopass[4]);
val_rxcfg |= DP83867_WOL_SEC_EN;
--
2.28.0
Re: [PATCH net-next] net: dp83869: Add ability to advertise Fiber connection
On 9/2/20 8:25 AM, Dan Murphy wrote:
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..1acf498832f1 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,11 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
@@ -300,6 +305,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
{
int phy_ctrl_val;
int ret;
+ int bmcr;
if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
@@ -383,7 +389,36 @@ static int dp83869_configure_mode(struct phy_device
*phydev,
break;
case DP83869_RGMII_1000_BASE:
+ break;
case DP83869_RGMII_100_BASE:
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+ ret = phy_modify_changed(phydev, MII_ADVERTISE,
+MII_DP83869_FIBER_ADVERTISE,
+MII_DP83869_FIBER_ADVERTISE);
This is not correct after some testing find that this fails to init
since ret will be non-zero on success
Dan
[PATCH net-next] net: dp83869: Add ability to advertise Fiber connection
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.
Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83869.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..1acf498832f1 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -52,6 +52,11 @@
BMCR_FULLDPLX | \
BMCR_SPEED1000)
+#define MII_DP83869_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
+
/* This is the same bit mask as the BMCR so re-use the BMCR default */
#define DP83869_FX_CTRL_DEFAULTMII_DP83869_BMCR_DEFAULT
@@ -300,6 +305,7 @@ static int dp83869_configure_mode(struct phy_device *phydev,
{
int phy_ctrl_val;
int ret;
+ int bmcr;
if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
@@ -383,7 +389,36 @@ static int dp83869_configure_mode(struct phy_device
*phydev,
break;
case DP83869_RGMII_1000_BASE:
+ break;
case DP83869_RGMII_100_BASE:
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ phydev->autoneg = AUTONEG_DISABLE;
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->advertising);
+
+ if (bmcr & BMCR_ANENABLE) {
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (ret < 0)
+ return ret;
+ }
+ ret = phy_modify_changed(phydev, MII_ADVERTISE,
+MII_DP83869_FIBER_ADVERTISE,
+MII_DP83869_FIBER_ADVERTISE);
break;
default:
return -EINVAL;
--
2.28.0
Re: [PATCH] can: m_can_platform: don't call m_can_class_suspend in runtime suspend
Lucase On 8/11/20 3:15 AM, Lucas Stach wrote: 0704c5743694 (can: m_can_platform: remove unnecessary m_can_class_resume() call) removed the m_can_class_resume() call in the runtime resume path to get rid of a infinite recursion, so the runtime resume now only handles the device clocks. Unfortunately it did not remove the complementary m_can_class_suspend() call in the runtime suspend function, so those paths are now unbalanced, which causes the pinctrl state to get stuck on the "sleep" state, which breaks all CAN functionality on SoCs where this state is defined. Remove the m_can_class_suspend() call to fix this. Fixes: 0704c5743694 (can: m_can_platform: remove unnecessary m_can_class_resume() call) Not sure about this wrap around for the fixes in the commit msg. Otherwise Acked-by: Dan Murphy Signed-off-by: Lucas Stach --- drivers/net/can/m_can/m_can_platform.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 38ea5e600fb8..e6d0cb9ee02f 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -144,8 +144,6 @@ static int __maybe_unused m_can_runtime_suspend(struct device *dev) struct net_device *ndev = dev_get_drvdata(dev); struct m_can_classdev *mcan_class = netdev_priv(ndev); - m_can_class_suspend(dev); - clk_disable_unprepare(mcan_class->cclk); clk_disable_unprepare(mcan_class->hclk);
Re: [PATCH v2] can: m_can: Set device to software init mode before closing
Faiz On 8/25/20 12:54 AM, Faiz Abbas wrote: There might be some requests pending in the buffer when the interface close sequence occurs. In some devices, these pending requests might lead to the module not shutting down properly when m_can_clk_stop() is called. Therefore, move the device to init state before potentially powering it down. Signed-off-by: Faiz Abbas --- changes since v1: Rebased to latest mainline drivers/net/can/m_can/m_can.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 02c5795b7393..d0c458f7f6e1 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1414,6 +1414,9 @@ static void m_can_stop(struct net_device *dev) /* disable all interrupts */ m_can_disable_all_interrupts(cdev); + /* Set init mode to disengage from the network */ + m_can_config_endisable(cdev, true); + /* set the state as STOPPED */ cdev->can.state = CAN_STATE_STOPPED; } Acked-by: Dan Murphy
[PATCH net-next v3 2/2] net: phy: DP83822: Add ability to advertise Fiber connection
The DP83822 can be configured to use a Fiber connection. The strap
register is read to determine if the device has been configured to use
a fiber connection. With the fiber connection the PHY can be configured
to detect whether the fiber connection is active by either a high signal
or a low signal.
Fiber mode is only applicable to the DP83822 so rework the PHY match
table so that non-fiber PHYs can still use the same driver but not call
or use any of the fiber features.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83822.c | 225 --
1 file changed, 218 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 37643c468e19..732c8bec7452 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -23,16 +23,31 @@
#define DP83822_DEVADDR0x1f
+#define MII_DP83822_CTRL_2 0x0a
+#define MII_DP83822_PHYSTS 0x10
#define MII_DP83822_PHYSCR 0x11
#define MII_DP83822_MISR1 0x12
#define MII_DP83822_MISR2 0x13
+#define MII_DP83822_FCSCR 0x14
#define MII_DP83822_RCSR 0x17
#define MII_DP83822_RESET_CTRL 0x1f
#define MII_DP83822_GENCFG 0x465
+#define MII_DP83822_SOR1 0x467
+
+/* GENCFG */
+#define DP83822_SIG_DET_LOWBIT(0)
+
+/* Control Register 2 bits */
+#define DP83822_FX_ENABLE BIT(14)
#define DP83822_HW_RESET BIT(15)
#define DP83822_SW_RESET BIT(14)
+/* PHY STS bits */
+#define DP83822_PHYSTS_DUPLEX BIT(2)
+#define DP83822_PHYSTS_10 BIT(1)
+#define DP83822_PHYSTS_LINKBIT(0)
+
/* PHYSCR Register Fields */
#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
@@ -83,6 +98,28 @@
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
+/* SOR1 mode */
+#define DP83822_STRAP_MODE10
+#define DP83822_STRAP_MODE2BIT(0)
+#define DP83822_STRAP_MODE3BIT(1)
+#define DP83822_STRAP_MODE4GENMASK(1, 0)
+
+#define DP83822_COL_STRAP_MASK GENMASK(11, 10)
+#define DP83822_COL_SHIFT 10
+#define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
+#define DP83822_RX_ER_SHIFT8
+
+#define MII_DP83822_FIBER_ADVERTISE(ADVERTISED_TP | ADVERTISED_MII | \
+ ADVERTISED_FIBRE | ADVERTISED_BNC | \
+ ADVERTISED_Pause |
ADVERTISED_Asym_Pause | \
+ ADVERTISED_100baseT_Full)
+
+struct dp83822_private {
+ bool fx_signal_det_low;
+ int fx_enabled;
+ u16 fx_sd_enable;
+};
+
static int dp83822_ack_interrupt(struct phy_device *phydev)
{
int err;
@@ -197,6 +234,7 @@ static void dp83822_get_wol(struct phy_device *phydev,
static int dp83822_config_intr(struct phy_device *phydev)
{
+ struct dp83822_private *dp83822 = phydev->priv;
int misr_status;
int physcr_status;
int err;
@@ -208,13 +246,16 @@ static int dp83822_config_intr(struct phy_device *phydev)
misr_status |= (DP83822_RX_ERR_HF_INT_EN |
DP83822_FALSE_CARRIER_HF_INT_EN |
- DP83822_ANEG_COMPLETE_INT_EN |
- DP83822_DUP_MODE_CHANGE_INT_EN |
- DP83822_SPEED_CHANGED_INT_EN |
DP83822_LINK_STAT_INT_EN |
DP83822_ENERGY_DET_INT_EN |
DP83822_LINK_QUAL_INT_EN);
+ if (!dp83822->fx_enabled)
+ misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
+ DP83822_DUP_MODE_CHANGE_INT_EN |
+ DP83822_SPEED_CHANGED_INT_EN;
+
+
err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
if (err < 0)
return err;
@@ -224,14 +265,16 @@ static int dp83822_config_intr(struct phy_device *phydev)
return misr_status;
misr_status |= (DP83822_JABBER_DET_INT_EN |
- DP83822_WOL_PKT_INT_EN |
DP83822_SLEEP_MODE_INT_EN |
- DP83822_MDI_XOVER_INT_EN |
DP83822_LB_FIFO_INT_EN |
DP83822_PAGE_RX_INT_EN |
- DP83822_ANEG_ERR_INT_EN |
DP83822_EEE_ERROR_CHANGE_INT_EN);
+ if (!dp83822->fx_enabled)
+ misr_status |= DP83822_MDI_XOVER_INT_EN |
+ DP83822_ANEG_ERR_INT_EN |
+ DP83822_WOL_PKT_INT_EN;
+
err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
if (err < 0)
return
[PATCH net-next v3 1/2] dt-bindings: net: dp83822: Add TI dp83822 phy
Add a dt binding for the TI dp83822 ethernet phy device.
Reviewed-by: Rob Herring
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83822.yaml | 80 +++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml
b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
new file mode 100644
index ..55913534cbc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83822.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83822 ethernet PHY
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
+ provides all of the physical layer functions needed to transmit and receive
+ data over standard, twisted-pair cables or to connect to an external,
+ fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
+ connect to a MAC through a standard MII, RMII, or RGMII interface
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83822i.pdf
+
+allOf:
+ - $ref: "ethernet-phy.yaml#"
+
+properties:
+ reg:
+maxItems: 1
+
+ ti,link-loss-low:
+type: boolean
+description: |
+ DP83822 PHY in Fiber mode only.
+ Sets the DP83822 to detect a link drop condition when the signal goes
+ high. If not set then link drop will occur when the signal goes low.
+ This property is only applicable if the fiber mode support is strapped
+ to on.
+
+ ti,fiber-mode:
+type: boolean
+description: |
+ DP83822 PHY only.
+ If present the DP83822 PHY is configured to operate in fiber mode
+ Fiber mode support can also be strapped. If the strap pin is not set
+ correctly or not set at all then this boolean can be used to enable it.
+ If the fiber mode is not strapped then signal detection for the PHY
+ is disabled.
+ In fiber mode, auto-negotiation is disabled and the PHY can only work in
+ 100base-fx (full and half duplex) modes.
+
+ rx-internal-delay-ps:
+description: |
+ DP83822 PHY only.
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ DP83822 PHY only.
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
+ to transmit data.
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
+
+...
--
2.28.0
[PATCH net-next v3 0/2] Enable Fiber on DP83822 PHY
Hello The DP83822 Ethernet PHY has the ability to connect via a Fiber port. The derivative PHYs DP83825 and DP83826 do not have this ability. In fiber mode the DP83822 disables auto negotiation and has a fixed 100Mbps speed with support for full or half duplex modes. A devicetree binding was added to set the signal polarity for the fiber connection. This property is only applicable if the FX_EN strap is set in hardware other wise the signal loss detection is disabled on the PHY. If the FX_EN is not strapped the device can be configured to run in fiber mode via the device tree. All be it the PHY will not perform signal loss detection. v2 review from a long time ago can be found here - https://lore.kernel.org/patchwork/patch/1270958/ Dan Dan Murphy (2): dt-bindings: net: dp83822: Add TI dp83822 phy net: phy: DP83822: Add ability to advertise Fiber connection .../devicetree/bindings/net/ti,dp83822.yaml | 80 +++ drivers/net/phy/dp83822.c | 225 +- 2 files changed, 298 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml -- 2.28.0
Re: [PATCH] net: dp83869: Fix RGMII internal delay configuration
Andrew
On 8/26/20 7:58 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:57:35PM -0500, Dan Murphy wrote:
Andrew
On 8/25/20 8:37 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
RGMII Transmit/Receive Clock Delay
0x0 = RGMII transmit clock is shifted with respect to transmit/receive
data.
0x1 = RGMII transmit clock is aligned with respect to transmit/receive
data.
This commit fixes the inversed behavior of these bits
Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
I Daniel
I would like to see some sort of response from Dan Murphy about this.
Daniel had sent this privately to me and I encouraged him to send it in for
review.
Unfortunately he did not cc me on the patch he sent to the list.
You should be able to reply to this email with a Reviewed-by: and
patchwork will do the right thing.
Yep. I gave my ack on v2 of the patch set
Dan
Andrew
Re: [PATCH v2] net: dp83869: Fix RGMII internal delay configuration
Hello
On 8/26/20 12:00 AM, Daniel Gorsulowski wrote:
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
RGMII Transmit/Receive Clock Delay
0x0 = RGMII transmit clock is shifted with respect to transmit/receive
data.
0x1 = RGMII transmit clock is aligned with respect to transmit/receive
data.
This commit fixes the inversed behavior of these bits
Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
Signed-off-by: Daniel Gorsulowski
---
v2: fixed indentation and commit style
drivers/net/phy/dp83869.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 58103152c601..6b98d74b5102 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev)
return ret;
val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
- val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
-DP83869_RGMII_RX_CLK_DELAY_EN);
+ val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
+ DP83869_RGMII_RX_CLK_DELAY_EN);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
- val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
- DP83869_RGMII_RX_CLK_DELAY_EN);
+ val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
+DP83869_RGMII_RX_CLK_DELAY_EN);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
- val |= DP83869_RGMII_TX_CLK_DELAY_EN;
+ val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
- val |= DP83869_RGMII_RX_CLK_DELAY_EN;
+ val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
val);
With the exception on bot knowing what net tree this goes to via the subject
Acked-by: Dan Murphy
Re: [PATCH] net: dp83869: Fix RGMII internal delay configuration
Andrew
On 8/25/20 8:37 AM, Andrew Lunn wrote:
On Tue, Aug 25, 2020 at 02:07:21PM +0200, Daniel Gorsulowski wrote:
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
RGMII Transmit/Receive Clock Delay
0x0 = RGMII transmit clock is shifted with respect to transmit/receive
data.
0x1 = RGMII transmit clock is aligned with respect to transmit/receive
data.
This commit fixes the inversed behavior of these bits
Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
I Daniel
I would like to see some sort of response from Dan Murphy about this.
Daniel had sent this privately to me and I encouraged him to send it in
for review.
Unfortunately he did not cc me on the patch he sent to the list.
But reviewing it off the list it looks fine to me
Dan
Re: [PATCH net-next v2 2/2] net: phy: DP83822: Add ability to advertise Fiber connection
Andrew On 7/11/20 1:45 PM, Andrew Lunn wrote: +#define MII_DP83822_FIBER_ADVERTISE(SUPPORTED_AUI | SUPPORTED_FIBRE | \ +SUPPORTED_BNC | SUPPORTED_Pause | \ +SUPPORTED_Asym_Pause | \ +SUPPORTED_100baseT_Full) + + /* Setup fiber advertisement */ + err = phy_modify_changed(phydev, MII_ADVERTISE, +ADVERTISE_1000XFULL | +ADVERTISE_1000XPAUSE | +ADVERTISE_1000XPSE_ASYM, +MII_DP83822_FIBER_ADVERTISE); That looks very odd. SUPPORTED_AUI #define has nothing to do with MII_ADVERTISE register. It is not a bit you can read/write in that register. ACK removed the SUPPORTED_AUI. I also going to update the MII_DP83822_FIBER_ADVERTISE defines from SUPPORTED_* to ADVERTISED_* Dan Andrew
Re: [PATCH net-next v2 2/2] net: phy: DP83822: Add ability to advertise Fiber connection
Andrew
On 7/11/20 1:54 PM, Andrew Lunn wrote:
@@ -302,6 +357,48 @@ static int dp83822_config_init(struct phy_device *phydev)
}
}
+ if (dp83822->fx_enabled) {
+ err = phy_modify(phydev, MII_DP83822_CTRL_2,
+DP83822_FX_ENABLE, 1);
+ if (err < 0)
+ return err;
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_ANENABLE) {
+ err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (err < 0)
+ return err;
+ }
+ phydev->autoneg = AUTONEG_DISABLE;
You should also be removing ETHTOOL_LINK_MODE_Autoneg_BIT from
phydev->supported, to make it clear autoneg is not supported. Assuming
genphy_read_abilities() cannot figure this out for itself.
In our testing we are finding that it cannot determine that for itself
so I will have to clear the bit.
Dan
[PATCH net-next v2 0/2] DP83822 Fiber enablement
Hello The DP83822 Ethernet PHY has the ability to connect via a Fiber port. The derivative PHYs DP83825 and DP83826 do not have this ability. In fiber mode the DP83822 disables auto negotiation and has a fixed 100Mbps speed with support for full or half duplex modes. A devicetree binding was added to set the signal polarity for the fiber connection. This property is only applicable if the FX_EN strap is set in hardware other wise the signal loss detection is disabled on the PHY. If the FX_EN is not strapped the device can be configured to run in fiber mode via the device tree. All be it the PHY will not perfomr signal loss detection. Dan Dan Murphy (2): dt-bindings: net: dp83822: Add TI dp83822 phy net: phy: DP83822: Add ability to advertise Fiber connection .../devicetree/bindings/net/ti,dp83822.yaml | 80 + drivers/net/phy/dp83822.c | 161 ++ 2 files changed, 241 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml -- 2.27.0
[PATCH net-next v2 1/2] dt-bindings: net: dp83822: Add TI dp83822 phy
Add a dt binding for the TI dp83822 ethernet phy device.
CC: Rob Herring
Signed-off-by: Dan Murphy
---
.../devicetree/bindings/net/ti,dp83822.yaml | 80 +++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml
b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
new file mode 100644
index ..55913534cbc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83822.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI DP83822 ethernet PHY
+
+maintainers:
+ - Dan Murphy
+
+description: |
+ The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
+ provides all of the physical layer functions needed to transmit and receive
+ data over standard, twisted-pair cables or to connect to an external,
+ fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
+ connect to a MAC through a standard MII, RMII, or RGMII interface
+
+ Specifications about the Ethernet PHY can be found at:
+http://www.ti.com/lit/ds/symlink/dp83822i.pdf
+
+allOf:
+ - $ref: "ethernet-phy.yaml#"
+
+properties:
+ reg:
+maxItems: 1
+
+ ti,link-loss-low:
+type: boolean
+description: |
+ DP83822 PHY in Fiber mode only.
+ Sets the DP83822 to detect a link drop condition when the signal goes
+ high. If not set then link drop will occur when the signal goes low.
+ This property is only applicable if the fiber mode support is strapped
+ to on.
+
+ ti,fiber-mode:
+type: boolean
+description: |
+ DP83822 PHY only.
+ If present the DP83822 PHY is configured to operate in fiber mode
+ Fiber mode support can also be strapped. If the strap pin is not set
+ correctly or not set at all then this boolean can be used to enable it.
+ If the fiber mode is not strapped then signal detection for the PHY
+ is disabled.
+ In fiber mode, auto-negotiation is disabled and the PHY can only work in
+ 100base-fx (full and half duplex) modes.
+
+ rx-internal-delay-ps:
+description: |
+ DP83822 PHY only.
+ Setting this property to a non-zero number sets the RX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
+ to receive data.
+
+ tx-internal-delay-ps:
+description: |
+ DP83822 PHY only.
+ Setting this property to a non-zero number sets the TX internal delay
+ for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
+ to transmit data.
+
+required:
+ - reg
+
+examples:
+ - |
+mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+rx-internal-delay-ps = <1>;
+tx-internal-delay-ps = <1>;
+ };
+};
+
+...
--
2.27.0
[PATCH net-next v2 2/2] net: phy: DP83822: Add ability to advertise Fiber connection
The DP83822 can be configured to use a Fiber connection. The strap
register is read to determine if the device has been configured to use
a fiber connection. With the fiber connection the PHY can be configured
to detect whether the fiber connection is active by either a high signal
or a low signal.
Fiber mode is only applicable to the DP83822 so rework the PHY match
table so that non-fiber PHYs can still use the same driver but not call
or use any of the fiber features.
Signed-off-by: Dan Murphy
---
drivers/net/phy/dp83822.c | 161 ++
1 file changed, 161 insertions(+)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 37643c468e19..b797e3d2a4e5 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -23,16 +23,29 @@
#define DP83822_DEVADDR0x1f
+#define MII_DP83822_CTRL_2 0x0a
+#define MII_DP83822_PHYSTS 0x10
#define MII_DP83822_PHYSCR 0x11
#define MII_DP83822_MISR1 0x12
#define MII_DP83822_MISR2 0x13
#define MII_DP83822_RCSR 0x17
#define MII_DP83822_RESET_CTRL 0x1f
#define MII_DP83822_GENCFG 0x465
+#define MII_DP83822_SOR1 0x467
+
+/* GENCFG */
+#define DP83822_SIG_DET_LOWBIT(0)
+
+/* Control Register 2 bits */
+#define DP83822_FX_ENABLE BIT(14)
#define DP83822_HW_RESET BIT(15)
#define DP83822_SW_RESET BIT(14)
+/* PHY STS bits */
+#define DP83822_PHYSTS_DUPLEX BIT(2)
+#define DP83822_PHYSTS_10 BIT(1)
+
/* PHYSCR Register Fields */
#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
@@ -83,6 +96,21 @@
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
+/* SOR1 bits */
+#define DP83822_FX_EN_STRAPBIT(11)
+#define DP83822_FX_SD_EN_STRAP BIT(8)
+
+#define MII_DP83822_FIBER_ADVERTISE(SUPPORTED_AUI | SUPPORTED_FIBRE | \
+SUPPORTED_BNC | SUPPORTED_Pause | \
+SUPPORTED_Asym_Pause | \
+SUPPORTED_100baseT_Full)
+
+struct dp83822_private {
+ bool fx_signal_det_low;
+ int fx_enabled;
+ u16 fx_sd_enable;
+};
+
static int dp83822_ack_interrupt(struct phy_device *phydev)
{
int err;
@@ -270,13 +298,40 @@ static int dp8382x_disable_wol(struct phy_device *phydev)
MII_DP83822_WOL_CFG, value);
}
+static int dp83822_read_status(struct phy_device *phydev)
+{
+ int status = phy_read(phydev, MII_DP83822_PHYSTS);
+ int ret;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (status < 0)
+ return status;
+
+ if (status & DP83822_PHYSTS_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (status & DP83822_PHYSTS_10)
+ phydev->speed = SPEED_10;
+ else
+ phydev->speed = SPEED_100;
+
+ return 0;
+}
+
static int dp83822_config_init(struct phy_device *phydev)
{
+ struct dp83822_private *dp83822 = phydev->priv;
struct device *dev = &phydev->mdio.dev;
int rgmii_delay;
s32 rx_int_delay;
s32 tx_int_delay;
int err = 0;
+ int bmcr;
if (phy_interface_is_rgmii(phydev)) {
rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
@@ -302,6 +357,48 @@ static int dp83822_config_init(struct phy_device *phydev)
}
}
+ if (dp83822->fx_enabled) {
+ err = phy_modify(phydev, MII_DP83822_CTRL_2,
+DP83822_FX_ENABLE, 1);
+ if (err < 0)
+ return err;
+
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+phydev->advertising);
+
+ /* Auto neg is not supported in fiber mode */
+ bmcr = phy_read(phydev, MII_BMCR);
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_ANENABLE) {
+ err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+ if (err < 0)
+ return err;
+ }
+ phydev->autoneg = AUTONEG_DISABLE;
+
+ /* Setup fiber advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ADVERTISE_1000XFULL |
+ADVERTISE_1000XPAUSE |
+ADVERTISE_1000XPSE_ASYM,
+M
