Several ACPI entries were missing from the bios and the new controllers
need to be initialized properly.
Furthermore COM2 is not being emulated, so Mac OS X broke trying to
initialize it.
The HPET ACPI table parts are optional.
This patch is against the bochsbios. Should this rather be sent to the
bochs ML?
Index: acpi-dsdt.dsl
===
RCS file: /cvsroot/bochs/bochs/bios/acpi-dsdt.dsl,v
retrieving revision 1.1
diff -u -r1.1 acpi-dsdt.dsl
--- acpi-dsdt.dsl 28 Sep 2006 18:56:20 - 1.1
+++ acpi-dsdt.dsl 8 Jan 2008 14:05:34 -
@@ -25,6 +25,93 @@
0x1 // OEM Revision
)
{
+OperationRegion (GNVS, SystemMemory, 0x7EEDBC10, 0x0100)
+Field (GNVS, AnyAcc, Lock, Preserve)
+{
+OSYS, 16,
+SMIF, 8,
+PRM0, 8,
+PRM1, 8,
+SCIF, 8,
+PRM2, 8,
+PRM3, 8,
+LCKF, 8,
+PRM4, 8,
+PRM5, 8,
+P80D, 32,
+LIDS, 8,
+PWRS, 8,
+DBGS, 8,
+Offset (0x14),
+ACTT, 8,
+PSVT, 8,
+TC1V, 8,
+TC2V, 8,
+TSPV, 8,
+CRTT, 8,
+DTSE, 8,
+DTS1, 8,
+DTS2, 8,
+DTSF, 8,
+BNUM, 8,
+B0SC, 8,
+B1SC, 8,
+B2SC, 8,
+B0SS, 8,
+B1SS, 8,
+B2SS, 8,
+Offset (0x28),
+APIC, 8,
+MPEN, 8,
+PPCS, 8,
+PPCM, 8,
+Offset (0x32),
+NATP, 8,
+CMAP, 8,
+CMBP, 8,
+LPTP, 8,
+FDCP, 8,
+CMCP, 8,
+CIRP, 8,
+Offset (0x3C),
+IGDS, 8,
+TLST, 8,
+CADL, 8,
+PADL, 8,
+CSTE, 16,
+NSTE, 16,
+SSTE, 16,
+NDID, 8,
+DID1, 32,
+DID2, 32,
+DID3, 32,
+DID4, 32,
+DID5, 32,
+BDSP, 8,
+PTY1, 8,
+PTY2, 8,
+PSCL, 8,
+TVF1, 8,
+TVF2, 8,
+Offset (0x67),
+BLCS, 8,
+BRTL, 8,
+ALSE, 8,
+ALAF, 8,
+LLOW, 8,
+LHIH, 8,
+Offset (0x6E),
+EMAE, 8,
+EMAP, 16,
+EMAL, 16,
+Offset (0x74),
+MEFE, 8,
+Offset (0x82),
+GTF0, 56,
+GTF2, 56,
+IDEM, 8
+}
+
Scope (\)
{
/* CMOS memory access */
@@ -47,11 +134,114 @@
{
DBGL, 32,
}
+
+/* PIC mode setting */
+Name (PICF, 0x00)
+Method (_PIC, 1, NotSerialized)
+{
+Store(Arg0, PICF)
+}
+Name (SSDT, Package (0x0C)
+{
+CPU0IST ,
+0x7EEB8C10,
+0x026C,
+CPU1IST ,
+0x7EEB8F10,
+0x0087,
+CPU0CST ,
+0x7EEB8910,
+0x02A0,
+CPU1CST ,
+0x7EEB7F10,
+0x0085
+})
+Name (CFGD, 0x011B49B1)
+Name (\PDC0, 0x8000)
+Name (\PDC1, 0x8000)
+Name (\SDTL, 0x00)
}
+Scope (\_PR)
+{
+Processor (CPU0, 0x00, 0x0680, 0x06) {}
+/* Processor (CPU1, 0x01, 0x0410, 0x06) {} */
+}
/* PCI Bus definition */
Scope(\_SB) {
+OperationRegion (XXX, SystemIO, 0x300, 0x01)
+Method (_INI, 0, NotSerialized)
+{
+Store (0x1, XXX)
+If (CondRefOf (_OSI, Local0))
+{
+If (_OSI (Darwin))
+{
+Store (0x2710, OSYS)
+}
+}
+
+Store (0x35, SMIF)
+}
+Device (HPET)
+{
+Name (_HID, EisaId (PNP0103))
+Name (_CID, 0x010CD041)
+Name (BUF0, ResourceTemplate ()
+{
+IRQNoFlags ()
+{0}
+IRQNoFlags ()
+{8}
+Memory32Fixed (ReadOnly,
+0xFED0, // Address Base
+0x0400, // Address Length
+_Y16)
+})
+Method (_STA, 0, NotSerialized)
+{
+Return (0x0F)
+}
+
+Method (_CRS, 0, Serialized)
+{
+
+Return (BUF0)
+}
+}
+
+Device (SMC)
+{
+Name (_HID, EisaId (APP0001))
+Name (_CID,
