[Qemu-devel] qemu cpu-exec.c exec-all.h exec.c translate-all.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/12/11 19:35:45 Modified files: . : cpu-exec.c exec-all.h exec.c translate-all.c Log message: Fix code generation buffer overflow reported by TeLeMan CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.128r2=1.129 http://cvs.savannah.gnu.org/viewcvs/qemu/exec-all.h?cvsroot=qemur1=1.72r2=1.73 http://cvs.savannah.gnu.org/viewcvs/qemu/exec.c?cvsroot=qemur1=1.117r2=1.118 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-all.c?cvsroot=qemur1=1.23r2=1.24
[Qemu-devel] qemu cpu-exec.c translate-all.c target-sh4/cpu....
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/12/02 06:10:04 Modified files: . : cpu-exec.c translate-all.c target-sh4 : cpu.h op.c translate.c Log message: SH4 delay slot code update, by Magnus Damm. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.126r2=1.127 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-all.c?cvsroot=qemur1=1.22r2=1.23 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/cpu.h?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op.c?cvsroot=qemur1=1.8r2=1.9 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/translate.c?cvsroot=qemur1=1.20r2=1.21
[Qemu-devel] qemu cpu-exec.c hw/sh7750.c hw/sh_intc.c hw/sh_...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/12/02 06:18:25 Modified files: . : cpu-exec.c hw : sh7750.c sh_intc.c sh_intc.h target-sh4 : cpu.h helper.c op.c Log message: SH4: system emulator interrupt update, by Magnus Damm. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.127r2=1.128 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sh7750.c?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sh_intc.c?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sh_intc.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/cpu.h?cvsroot=qemur1=1.13r2=1.14 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/helper.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op.c?cvsroot=qemur1=1.9r2=1.10
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Paul Brook pbrook 07/11/23 02:11:10 Modified files: . : cpu-exec.c Log message: Fix TB chaining for exceptions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.125r2=1.126
[Qemu-devel] qemu cpu-exec.c vl.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Fabrice Bellard bellard 07/11/11 20:14:28 Modified files: . : cpu-exec.c vl.c Log message: removed warning CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.123r2=1.124 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.360r2=1.361
[Qemu-devel] qemu cpu-exec.c target-i386/cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Fabrice Bellard bellard 07/11/11 22:16:57 Modified files: . : cpu-exec.c target-i386: cpu.h Log message: consistent types for cpu_x86_fsave and cpu_x86_frstor CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.124r2=1.125 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/cpu.h?cvsroot=qemur1=1.54r2=1.55
[Qemu-devel] qemu cpu-exec.c target-sparc/cpu.h target-sparc...
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/11/07 17:03:37 Modified files: . : cpu-exec.c target-sparc : cpu.h helper.c op_helper.c translate.c Log message: CPU specific boot mode (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.120r2=1.121 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemur1=1.56r2=1.57 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/helper.c?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op_helper.c?cvsroot=qemur1=1.50r2=1.51 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemur1=1.78r2=1.79
[Qemu-devel] qemu cpu-exec.c exec-all.h exec.c gdbstub.c sof...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/10/08 13:16:15 Modified files: . : cpu-exec.c exec-all.h exec.c gdbstub.c softmmu_header.h vl.c vl.h Log message: CRIS support in toplevel, by Edgar E. Iglesias. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.118r2=1.119 http://cvs.savannah.gnu.org/viewcvs/qemu/exec-all.h?cvsroot=qemur1=1.66r2=1.67 http://cvs.savannah.gnu.org/viewcvs/qemu/exec.c?cvsroot=qemur1=1.107r2=1.108 http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemur1=1.65r2=1.66 http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_header.h?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.346r2=1.347 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.275r2=1.276
[Qemu-devel] qemu cpu-exec.c target-i386/helper.c target-i38...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/09/27 01:52:01 Modified files: . : cpu-exec.c target-i386: helper.c translate.c Log message: SVM VINTR fix, by Alexander Graf. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.117r2=1.118 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/helper.c?cvsroot=qemur1=1.88r2=1.89 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/translate.c?cvsroot=qemur1=1.71r2=1.72
[Qemu-devel] qemu cpu-exec.c hw/sun4m.c target-sparc/cpu.h t...
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/09/24 19:44:09 Modified files: . : cpu-exec.c hw : sun4m.c target-sparc : cpu.h helper.c op_helper.c translate.c Log message: CPU boot mode CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.116r2=1.117 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemur1=1.49r2=1.50 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemur1=1.49r2=1.50 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/helper.c?cvsroot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op_helper.c?cvsroot=qemur1=1.38r2=1.39 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemur1=1.69r2=1.70
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/09/19 05:37:57 Modified files: . : cpu-exec.c Log message: Improve PowerPC target implementation, using computed hflags as TB flags. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.113r2=1.114
[Qemu-devel] qemu cpu-exec.c gdbstub.c monitor.c translate-a...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/09/06 00:18:15 Modified files: . : cpu-exec.c gdbstub.c monitor.c translate-all.c hw : mips_r4k.c mips_timer.c linux-user : main.c signal.c syscall.c target-mips: cpu.h exec.h fop_template.c helper.c op.c op_helper.c op_template.c translate.c translate_init.c Log message: Partial support for 34K multithreading, not functional yet. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.110r2=1.111 http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemur1=1.62r2=1.63 http://cvs.savannah.gnu.org/viewcvs/qemu/monitor.c?cvsroot=qemur1=1.77r2=1.78 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-all.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_timer.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.118r2=1.119 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/signal.c?cvsroot=qemur1=1.39r2=1.40 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall.c?cvsroot=qemur1=1.117r2=1.118 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.42r2=1.43 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemur1=1.30r2=1.31 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/fop_template.c?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.69r2=1.70 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.56r2=1.57 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.95r2=1.96 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate_init.c?cvsroot=qemur1=1.19r2=1.20
[Qemu-devel] qemu cpu-exec.c target-alpha/exec.h target-arm/...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/06/03 17:44:37 Modified files: . : cpu-exec.c target-alpha : exec.h target-arm : exec.h target-i386: exec.h helper.c target-m68k: exec.h target-mips: exec.h op_helper.c target-ppc : exec.h op_helper.c target-sh4 : op_helper.c target-sparc : exec.h Log message: Clean up of some target specifics in exec.c/cpu-exec.c. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.106r2=1.107 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/exec.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/exec.h?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/exec.h?cvsroot=qemur1=1.31r2=1.32 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/helper.c?cvsroot=qemur1=1.82r2=1.83 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/exec.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemur1=1.29r2=1.30 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.51r2=1.52 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.20r2=1.21 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op_helper.c?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/exec.h?cvsroot=qemur1=1.18r2=1.19
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/06/03 18:45:55 Modified files: . : cpu-exec.c Log message: Some more regs_to_env/envs_to_regs cleanup. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.107r2=1.108
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/06/03 18:52:16 Modified files: . : cpu-exec.c Log message: Add comment. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.108r2=1.109
[Qemu-devel] qemu cpu-exec.c target-m68k/cpu.h target-m68k/h...
CVSROOT:/sources/qemu Module name:qemu Changes by: Paul Brook pbrook 07/05/29 14:57:59 Modified files: . : cpu-exec.c target-m68k: cpu.h helper.c op.c qregs.def translate.c Log message: ColdFire EMAC support. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.105r2=1.106 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/helper.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/op.c?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/qregs.def?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/translate.c?cvsroot=qemur1=1.12r2=1.13
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/12 16:57:43 Modified files: . : cpu-exec.c Log message: Update debug output. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.103r2=1.104
[Qemu-devel] qemu cpu-exec.c vl.h hw/openpic.c hw/ppc.c hw/p...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/04/09 22:45:36 Modified files: . : cpu-exec.c vl.h hw : openpic.c ppc.c ppc_chrp.c ppc_prep.c target-ppc : cpu.h helper.c translate_init.c Log message: Implement embedded IRQ controller for PowerPC 6xx/740 750. Fix PowerPC external interrupt input handling and lowering. Fix OpenPIC output pins management. Fix multiples bugs in OpenPIC IRQ management. Fix OpenPIC CPU(s) reset function. Fix Mac99 machine to properly route OpenPIC outputs to the PowerPC input pins. Fix PREP machine to properly route i8259 output to the PowerPC external interrupt pin. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.99r2=1.100 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.208r2=1.209 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/openpic.c?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.14r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.31r2=1.32 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.33r2=1.34 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.36r2=1.37 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.40r2=1.41 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.8r2=1.9
[Qemu-devel] qemu cpu-exec.c target-i386/cpu.h target-i386/h...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/03/31 20:28:52 Modified files: . : cpu-exec.c target-i386: cpu.h helper.c Log message: Generate double and triple faults, by Bernhard Kauer. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.97r2=1.98 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/cpu.h?cvsroot=qemur1=1.41r2=1.42 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/helper.c?cvsroot=qemur1=1.74r2=1.75
[Qemu-devel] qemu cpu-exec.c vl.h hw/openpic.c hw/ppc.c hw/p...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/03/30 09:38:04 Modified files: . : cpu-exec.c vl.h hw : openpic.c ppc.c ppc_chrp.c ppc_prep.c target-ppc : cpu.h helper.c Log message: New model for PowerPC CPU hardware interrupt events: move all PowerPC specific code into target-ppc/helper.c to avoid polluting the common code in cpu-exec.c. This makes implementation of new features (ie embedded PowerPC timers, critical interrupts, ...) easier. This also avoid hardcoding the IRQ callback in the OpenPIC controller, making it more easily reusable and allowing cascading. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.95r2=1.96 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.196r2=1.197 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/openpic.c?cvsroot=qemur1=1.9r2=1.10 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.31r2=1.32 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.35r2=1.36
[Qemu-devel] qemu cpu-exec.c dyngen-exec.h hw/mips_int.c tar...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/03/30 16:44:54 Modified files: . : cpu-exec.c dyngen-exec.h hw : mips_int.c target-mips: cpu.h helper.c op.c op_helper.c translate.c Log message: Sanitize mips exception handling. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.96r2=1.97 http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen-exec.h?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_int.c?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.27r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.41r2=1.42
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/03/19 20:39:50 Modified files: . : cpu-exec.c Log message: Fix call to generated code on SPARC, by Juergen Keil. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.94r2=1.95 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Fabrice Bellard bellard 07/02/05 21:41:46 Modified files: . : cpu-exec.c Log message: Make cpu_signal_handler work on Mac OS X/Darwin x86 CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.92r2=1.93 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/02/02 03:57:10 Modified files: . : cpu-exec.c Log message: Use target_ulong type for emulator registers. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.90r2=1.91 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c target-arm/cpu.h target-i386/cp...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/01/31 12:16:51 Modified files: . : cpu-exec.c target-arm : cpu.h target-i386: cpu.h target-m68k: cpu.h target-ppc : cpu.h target-sh4 : cpu.h target-sparc : cpu.h Log message: siginfo fix for Darwin/Mac OS X, by Pierre d'Herbemont. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.89r2=1.90 http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/cpu.h?cvsroot=qemur1=1.18r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/cpu.h?cvsroot=qemur1=1.39r2=1.40 http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.24r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/cpu.h?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemur1=1.26r2=1.27 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c hw/ne2000.c hw/smc91c111.c hw/u...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 06/12/07 18:28:42 Modified files: . : cpu-exec.c hw : ne2000.c smc91c111.c unin_pci.c target-sh4 : README.sh4 Log message: Spelling fixes, thanks to Stefan Weil. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ne2000.c?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/smc91c111.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/unin_pci.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/README.sh4?cvsroot=qemur1=1.1r2=1.2 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Paul Brook pbrook 06/07/29 19:09:31 Modified files: . : cpu-exec.c Log message: Arm host build fix. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.83r2=1.84 ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c gdbstub.c linux-user/main.c tar...
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook pbrook 06/06/18 19:12:54
Modified files:
. : cpu-exec.c gdbstub.c
linux-user : main.c
target-sh4 : cpu.h exec.h op.c translate.c
Log message:
SH bugfixes.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.81r2=1.82
http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemur1=1.38r2=1.39
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.87r2=1.88
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/cpu.h?cvsroot=qemur1=1.2r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/exec.h?cvsroot=qemur1=1.2r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op.c?cvsroot=qemur1=1.2r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/translate.c?cvsroot=qemur1=1.5r2=1.6
Patches:
Index: cpu-exec.c
===
RCS file: /sources/qemu/qemu/cpu-exec.c,v
retrieving revision 1.81
retrieving revision 1.82
diff -u -b -r1.81 -r1.82
--- cpu-exec.c 17 Jun 2006 19:58:24 - 1.81
+++ cpu-exec.c 18 Jun 2006 19:12:54 - 1.82
@@ -47,7 +47,7 @@
longjmp(env-jmp_env, 1);
}
#endif
-#ifndef TARGET_SPARC
+#if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
#define reg_T2
#endif
Index: gdbstub.c
===
RCS file: /sources/qemu/qemu/gdbstub.c,v
retrieving revision 1.38
retrieving revision 1.39
diff -u -b -r1.38 -r1.39
--- gdbstub.c 17 Jun 2006 18:30:42 - 1.38
+++ gdbstub.c 18 Jun 2006 19:12:54 - 1.39
@@ -504,7 +504,12 @@
int i;
#define SAVE(x) *ptr++=tswapl(x)
- for (i = 0; i 16; i++) SAVE(env-gregs[i]);
+ if ((env-sr (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
+ for (i = 0; i 8; i++) SAVE(env-gregs[i + 16]);
+ } else {
+ for (i = 0; i 8; i++) SAVE(env-gregs[i]);
+ }
+ for (i = 8; i 16; i++) SAVE(env-gregs[i]);
SAVE (env-pc);
SAVE (env-pr);
SAVE (env-gbr);
@@ -527,7 +532,12 @@
int i;
#define LOAD(x) (x)=*ptr++;
- for (i = 0; i 16; i++) LOAD(env-gregs[i]);
+ if ((env-sr (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
+ for (i = 0; i 8; i++) LOAD(env-gregs[i + 16]);
+ } else {
+ for (i = 0; i 8; i++) LOAD(env-gregs[i]);
+ }
+ for (i = 8; i 16; i++) LOAD(env-gregs[i]);
LOAD (env-pc);
LOAD (env-pr);
LOAD (env-gbr);
Index: linux-user/main.c
===
RCS file: /sources/qemu/qemu/linux-user/main.c,v
retrieving revision 1.87
retrieving revision 1.88
diff -u -b -r1.87 -r1.88
--- linux-user/main.c 17 Jun 2006 19:58:24 - 1.87
+++ linux-user/main.c 18 Jun 2006 19:12:54 - 1.88
@@ -1370,14 +1370,14 @@
switch (trapnr) {
case 0x160:
ret = do_syscall(env,
- env-gregs[0x13],
- env-gregs[0x14],
- env-gregs[0x15],
- env-gregs[0x16],
- env-gregs[0x17],
- env-gregs[0x10],
+ env-gregs[3],
+ env-gregs[4],
+ env-gregs[5],
+ env-gregs[6],
+ env-gregs[7],
+ env-gregs[0],
0);
-env-gregs[0x10] = ret;
+env-gregs[0] = ret;
env-pc += 2;
break;
case EXCP_DEBUG:
Index: target-sh4/cpu.h
===
RCS file: /sources/qemu/qemu/target-sh4/cpu.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- target-sh4/cpu.h14 Jun 2006 15:02:05 - 1.2
+++ target-sh4/cpu.h18 Jun 2006 19:12:54 - 1.3
@@ -45,7 +45,9 @@
#define FPSCR_PR (1 19)
#define FPSCR_DN (1 18)
-#define DELAY_SLOT (1 0)
+#define DELAY_SLOT (1 0) /* Must be the same as SR_T. */
+/* This flag is set if the next insn is a delay slot for a conditional jump.
+ The dynamic value of the DELAY_SLOT determines whether the jup is taken. */
#define DELAY_SLOT_CONDITIONAL (1 1)
/* Those are used in contexts only */
#define BRANCH (1 2)
Index: target-sh4/exec.h
===
RCS file: /sources/qemu/qemu/target-sh4/exec.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- target-sh4/exec.h 14 Jun 2006 15:02:05 - 1.2
+++ target-sh4/exec.h 18 Jun 2006 19:12:54 - 1.3
@@ -26,7 +26,7 @@
register struct CPUSH4State *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
-register uint32_t T2 asm(AREG3);
+//register uint32_t T2 asm(AREG3);
#define FT0 (env-ft0)
#define
[Qemu-devel] qemu cpu-exec.c linux-user/main.c target-sh4/he...
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook pbrook 06/06/17 19:58:25
Modified files:
. : cpu-exec.c
linux-user : main.c
target-sh4 : helper.c translate.c
Log message:
SH usermode fault handling.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemur1=1.80r2=1.81
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.86r2=1.87
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/helper.c?cvsroot=qemur1=1.1r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/translate.c?cvsroot=qemur1=1.3r2=1.4
Patches:
Index: cpu-exec.c
===
RCS file: /sources/qemu/qemu/cpu-exec.c,v
retrieving revision 1.80
retrieving revision 1.81
diff -u -b -r1.80 -r1.81
--- cpu-exec.c 14 Jun 2006 17:32:25 - 1.80
+++ cpu-exec.c 17 Jun 2006 19:58:24 - 1.81
@@ -1172,7 +1172,6 @@
a virtual CPU fault */
cpu_restore_state(tb, env, pc, puc);
}
-if (ret == 1) {
#if 0
printf(PF exception: NIP=0x%08x error=0x%x %p\n,
env-nip, env-error_code, tb);
@@ -1180,11 +1179,7 @@
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
-//do_raise_exception_err(env-exception_index,
env-error_code);
-} else {
-/* activate soft MMU for this block */
-cpu_resume_from_signal(env, puc);
-}
+cpu_loop_exit();
/* never comes here */
return 1;
}
Index: linux-user/main.c
===
RCS file: /sources/qemu/qemu/linux-user/main.c,v
retrieving revision 1.86
retrieving revision 1.87
diff -u -b -r1.86 -r1.87
--- linux-user/main.c 17 Jun 2006 18:30:42 - 1.86
+++ linux-user/main.c 17 Jun 2006 19:58:24 - 1.87
@@ -1362,7 +1362,7 @@
void cpu_loop (CPUState *env)
{
int trapnr, ret;
-//target_siginfo_t info;
+target_siginfo_t info;
while (1) {
trapnr = cpu_sh4_exec (env);
@@ -1380,6 +1380,20 @@
env-gregs[0x10] = ret;
env-pc += 2;
break;
+case EXCP_DEBUG:
+{
+int sig;
+
+sig = gdb_handlesig (env, TARGET_SIGTRAP);
+if (sig)
+ {
+info.si_signo = sig;
+info.si_errno = 0;
+info.si_code = TARGET_TRAP_BRKPT;
+queue_signal(info.si_signo, info);
+ }
+}
+break;
default:
printf (Unhandled trap: 0x%x\n, trapnr);
cpu_dump_state(env, stderr, fprintf, 0);
Index: target-sh4/helper.c
===
RCS file: /sources/qemu/qemu/target-sh4/helper.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- target-sh4/helper.c 27 Apr 2006 21:00:31 - 1.1
+++ target-sh4/helper.c 17 Jun 2006 19:58:24 - 1.2
@@ -28,6 +28,38 @@
#include cpu.h
#include exec-all.h
+#if defined(CONFIG_USER_ONLY)
+
+void do_interrupt (CPUState *env)
+{
+ env-exception_index = -1;
+}
+
+int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
+int is_user, int is_softmmu)
+{
+env-tea = address;
+switch (rw) {
+case 0:
+env-exception_index = 0x0a0;
+break;
+case 1:
+env-exception_index = 0x0c0;
+break;
+case 2:
+env-exception_index = 0x0a0;
+break;
+}
+return 1;
+}
+
+target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+{
+return addr;
+}
+
+#else /* !CONFIG_USER_ONLY */
+
#define MMU_OK 0
#define MMU_ITLB_MISS(-1)
#define MMU_ITLB_MULTIPLE(-2)
@@ -396,3 +428,14 @@
return tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
}
+
+target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+{
+target_ulong physical;
+int prot;
+
+get_physical_address(env, physical, prot, addr, PAGE_READ, 0);
+return physical;
+}
+
+#endif
Index: target-sh4/translate.c
===
RCS file: /sources/qemu/qemu/target-sh4/translate.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- target-sh4/translate.c 17 Jun 2006 18:48:31 - 1.3
+++ target-sh4/translate.c 17 Jun 2006 19:58:25 - 1.4
@@ -144,22 +144,6 @@
return env;
}
-#ifdef CONFIG_USER_ONLY
-target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
-{
-return addr;
-}
-#else
-target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
-{
-target_ulong physical;
-int prot;
-
-
[Qemu-devel] qemu ./cpu-exec.c target-mips/helper.c
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/05/22 22:03:52 Modified files: . : cpu-exec.c target-mips: helper.c Log message: mips cleanup (Thiemo Seufer) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.78tr2=1.79r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-mips/helper.c.diff?tr1=1.10tr2=1.11r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu ./cpu-exec.c ./vl.c ./vl.h hw/integratorcp...
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Paul Brook [EMAIL PROTECTED] 06/02/20 00:33:36 Modified files: . : cpu-exec.c vl.c vl.h hw : integratorcp.c linux-user : main.c target-arm : cpu.h helper.c op.c op_helper.c translate.c Log message: Add Arm926 core support. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.73tr2=1.74r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/vl.c.diff?tr1=1.164tr2=1.165r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/vl.h.diff?tr1=1.104tr2=1.105r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/integratorcp.c.diff?tr1=1.5tr2=1.6r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/linux-user/main.c.diff?tr1=1.78tr2=1.79r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-arm/cpu.h.diff?tr1=1.15tr2=1.16r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-arm/helper.c.diff?tr1=1.3tr2=1.4r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-arm/op.c.diff?tr1=1.19tr2=1.20r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-arm/op_helper.c.diff?tr1=1.4tr2=1.5r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/target-arm/translate.c.diff?tr1=1.39tr2=1.40r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c exec-all.h exec.c kqemu.c
CVSROOT:/sources/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/02/08 22:43:39 Modified files: . : cpu-exec.c exec-all.h exec.c kqemu.c Log message: optional support for kernel code virtualization CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.72tr2=1.73r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/exec-all.h.diff?tr1=1.44tr2=1.45r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/exec.c.diff?tr1=1.72tr2=1.73r1=textr2=text http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/kqemu.c.diff?tr1=1.8tr2=1.9r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/12/05 19:59:05 Modified files: . : cpu-exec.c Log message: MIPS halt support - MIPS static state fix (Daniel Jacobowitz) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.69tr2=1.70r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu ./cpu-exec.c target-arm/cpu.h target-arm/o...
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/26 10:46:39 Modified files: . : cpu-exec.c target-arm : cpu.h op.c translate.c Log message: ARM CPU suspend/halt (Paul Brook) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.65tr2=1.66r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-arm/cpu.h.diff?tr1=1.12tr2=1.13r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-arm/op.c.diff?tr1=1.16tr2=1.17r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-arm/translate.c.diff?tr1=1.32tr2=1.33r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] qemu ./cpu-exec.c ./monitor.c target-ppc/helper...
On Wed, 2005-11-23 at 17:05 -0500, Fabrice Bellard wrote: CVSROOT: /cvsroot/qemu Module name: qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/23 22:05:28 Modified files: . : cpu-exec.c monitor.c target-ppc : helper.c translate.c Log message: halt state support for ppc CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.63tr2=1.64r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/monitor.c.diff?tr1=1.42tr2=1.43r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/helper.c.diff?tr1=1.28tr2=1.29r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/translate.c.diff?tr1=1.39tr2=1.40r1=textr2=text One should beware before merging this patch in its local repository. It was rejected in the past and is broken for many reasons: - MSR_POW bit _does not_ mean enter halt state. It means enable power management. What the PowerPC core would do when this bit is set is implementation dependant. For example, PowerPC 750 (the one currently emulated by Qemu targets) will enter halt state only if some bits in the HID0 SPR are set. - the cpu state cannot be changed outside of the PowerPC emulation code. Setting the MSR_POW bit to zero is buggy because we loose useful information to decide wether the CPU has to go back in running state (if it's really halted) or has to ignore the raised exception. -- J. Mayer [EMAIL PROTECTED] Never organized ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/26 18:43:28 Modified files: . : cpu-exec.c Log message: fixed warning CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.66tr2=1.67r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu ./cpu-exec.c ./monitor.c target-ppc/cpu.h ...
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/26 20:15:14 Modified files: . : cpu-exec.c monitor.c target-ppc : cpu.h helper.c Log message: specialize the power save code for 7x0 CPUs CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.67tr2=1.68r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/monitor.c.diff?tr1=1.43tr2=1.44r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/cpu.h.diff?tr1=1.22tr2=1.23r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/helper.c.diff?tr1=1.29tr2=1.30r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu ./cpu-exec.c ./monitor.c target-ppc/helper...
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/23 22:05:28 Modified files: . : cpu-exec.c monitor.c target-ppc : helper.c translate.c Log message: halt state support for ppc CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.63tr2=1.64r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/monitor.c.diff?tr1=1.42tr2=1.43r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/helper.c.diff?tr1=1.28tr2=1.29r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/translate.c.diff?tr1=1.39tr2=1.40r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c exec-all.h exec.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/11/20 10:35:40 Modified files: . : cpu-exec.c exec-all.h exec.c Log message: make the TB cache independent of MMU mappings (faster MMU context switches and needed for SMP support) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.60tr2=1.61r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/exec-all.h.diff?tr1=1.39tr2=1.40r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/exec.c.diff?tr1=1.67tr2=1.68r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/08/21 09:43:38 Modified files: . : cpu-exec.c Log message: Fix interrupt masking (Ralf Baechle CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.59tr2=1.60r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu cpu-exec.c dyngen-exec.h vl.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/24 15:11:38 Modified files: . : cpu-exec.c dyngen-exec.h vl.c Log message: s390 bits CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.58tr2=1.59r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/dyngen-exec.h.diff?tr1=1.25tr2=1.26r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/vl.c.diff?tr1=1.131tr2=1.132r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu ./cpu-exec.c target-mips/op_helper.c
CVSROOT:/cvsroot/qemu Module name:qemu Branch: Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 15:16:15 Modified files: . : cpu-exec.c target-mips: op_helper.c Log message: soft irq are just irqs (Ralf Baechle) CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/cpu-exec.c.diff?tr1=1.57tr2=1.58r1=textr2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-mips/op_helper.c.diff?tr1=1.1tr2=1.2r1=textr2=text ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
