[U-Boot] [PATCH 1/4] drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c | 17 ++
drivers/ddr/fsl/interactive.c | 51 -
drivers/ddr/fsl/main.c|2 +-
drivers/ddr/fsl/util.c| 28 +++---
include/fsl_ddr.h |4 +---
5 files changed, 89 insertions(+), 13 deletions(-)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 690e73d..9ccddef 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -313,7 +313,10 @@ static void set_timing_cfg_0(const unsigned int ctrl_num,
#ifdef CONFIG_SYS_FSL_DDR4
/* tXP=max(4nCK, 6ns) */
int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
- trwt_mclk = 2;
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
+
+ /* for faster clock, need more time for data setup */
+ trwt_mclk = (data_rate/100 1900) ? 3 : 2;
twrt_mclk = 1;
act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
pre_pd_exit_mclk = act_pd_exit_mclk;
@@ -338,7 +341,7 @@ static void set_timing_cfg_0(const unsigned int ctrl_num,
*/
txp = max((int)mclk_ps * 3, (mclk_ps 1540 ? 7500 : 6000));
- ip_rev = fsl_ddr_get_version();
+ ip_rev = fsl_ddr_get_version(ctrl_num);
if (ip_rev = 0x40700) {
/*
* MRS_CYC = max(tMRD, tMOD)
@@ -544,7 +547,7 @@ static void set_timing_cfg_1(const unsigned int ctrl_num,
* we need set extend bit for it at
* TIMING_CFG_3[EXT_CASLAT]
*/
- if (fsl_ddr_get_version() = 0x40400)
+ if (fsl_ddr_get_version(ctrl_num) = 0x40400)
caslat_ctrl = 2 * cas_latency - 1;
else
caslat_ctrl = (cas_latency - 1) 1;
@@ -1114,12 +1117,16 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t
*ddr,
unsigned short esdmode4 = 0;/* Extended SDRAM mode 4 */
unsigned short esdmode5;/* Extended SDRAM mode 5 */
- esdmode5 = 0x0400; /* Data mask enabled */
+ esdmode5 = 0x0500; /* Data mask enabled */
ddr-ddr_sdram_mode_9 = (0
| ((esdmode4 0x) 16)
| ((esdmode5 0x) 0)
);
+
+ /* only mode_9 use 0x500, others use 0x400 */
+ esdmode5 = 0x0400; /* Data mask enabled */
+
debug(FSLDDR: ddr_sdram_mode_9) = 0x%08x\n, ddr-ddr_sdram_mode_9);
if (unq_mrs_en) { /* unique mode registers are supported */
for (i = 1; i CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -2349,7 +2356,7 @@ compute_fsl_memctl_config_regs(const unsigned int
ctrl_num,
set_ddr_cdr1(ddr, popts);
set_ddr_cdr2(ddr, popts);
set_ddr_sdram_cfg(ddr, popts, common_dimm);
- ip_rev = fsl_ddr_get_version();
+ ip_rev = fsl_ddr_get_version(ctrl_num);
if (ip_rev 0x40400)
unq_mrs_en = 1;
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 32ba6d8..57d14e8 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -205,6 +205,8 @@ static void
lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
sizeof((dimm_params_t *)0)-x, 0}
+#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
+ sizeof((dimm_params_t *)0)-x, 1}
static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
@@ -220,6 +222,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t
*pinfo,
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(mirrored_dimm),
DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
@@ -274,7 +277,27 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t
*pinfo,
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
#endif
-
+#ifdef CONFIG_SYS_FSL_DDR4
+ DIMM_PARM_HEX(dq_mapping[0]),
+ DIMM_PARM_HEX(dq_mapping[1]),
+ DIMM_PARM_HEX(dq_mapping[2]),
+ DIMM_PARM_HEX(dq_mapping[3]),
+ DIMM_PARM_HEX(dq_mapping[4]),
+ DIMM_PARM_HEX(dq_mapping[5]),
+ DIMM_PARM_HEX(dq_mapping[6]),
+ DIMM_PARM_HEX(dq_mapping[7]),
+ DIMM_PARM_HEX(dq_mapping[8]),
+ DIMM_PARM_HEX(dq_mapping[9]),
+
[U-Boot] [PATCH 3/4] driver/ddr/fsl: Add built-in memory test for DDR4 driver
Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable ddr_bist is checked before starting test.
It takes a while (several seconds) depending on system memory size.
Signed-off-by: York Sun york...@freescale.com
---
README |3 ++
drivers/ddr/fsl/fsl_ddr_gen4.c | 73
2 files changed, 76 insertions(+)
diff --git a/README b/README
index b0124d6..f473515 100644
--- a/README
+++ b/README
@@ -4904,6 +4904,9 @@ Low Level (hardware related) configuration options:
- CONFIG_FSL_DDR_SYNC_REFRESH
Enable sync of refresh for multiple controllers.
+- CONFIG_FSL_DDR_BIST
+ Enable built-in memory test for Freescale DDR controllers.
+
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d9fce7d..1d67983 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -36,6 +36,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
defined(CONFIG_SYS_FSL_ERRATUM_A008514)
u32 *eddrtqcr1;
#endif
+#ifdef CONFIG_FSL_DDR_BIST
+ u32 mtcr, err_detect, err_sbe;
+ u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
+#endif
+#ifdef CONFIG_FSL_DDR_BIST
+ char buffer[CONFIG_SYS_CBSIZE];
+#endif
switch (ctrl_num) {
case 0:
@@ -309,4 +316,70 @@ step2:
ddr_out32(ddr-sdram_cfg_2, temp_sdram_cfg);
}
#endif
+
+#ifdef CONFIG_FSL_DDR_BIST
+#define BIST_PATTERN1 0x
+#define BIST_PATTERN2 0x0
+#define BIST_CR0x8001
+#define BIST_CR_EN 0x8000
+#define BIST_CR_STAT 0x0001
+#define CTLR_INTLV_MASK0x2000
+ /* Perform build-in test on memory. Three-way interleaving is not yet
+* supported by this code. */
+ if (getenv_f(ddr_bist, buffer, CONFIG_SYS_CBSIZE) = 0) {
+ puts(Running BIST test. This will take a while...);
+ cs0_config = ddr_in32(ddr-cs0_config);
+ if (cs0_config CTLR_INTLV_MASK) {
+ cs0_bnds = ddr_in32(cs0_bnds);
+ cs1_bnds = ddr_in32(cs1_bnds);
+ cs2_bnds = ddr_in32(cs2_bnds);
+ cs3_bnds = ddr_in32(cs3_bnds);
+ /* set bnds to non-interleaving */
+ ddr_out32(cs0_bnds, (cs0_bnds 0xfffefffe) 1);
+ ddr_out32(cs1_bnds, (cs1_bnds 0xfffefffe) 1);
+ ddr_out32(cs2_bnds, (cs2_bnds 0xfffefffe) 1);
+ ddr_out32(cs3_bnds, (cs3_bnds 0xfffefffe) 1);
+ }
+ ddr_out32(ddr-mtp1, BIST_PATTERN1);
+ ddr_out32(ddr-mtp2, BIST_PATTERN1);
+ ddr_out32(ddr-mtp3, BIST_PATTERN2);
+ ddr_out32(ddr-mtp4, BIST_PATTERN2);
+ ddr_out32(ddr-mtp5, BIST_PATTERN1);
+ ddr_out32(ddr-mtp6, BIST_PATTERN1);
+ ddr_out32(ddr-mtp7, BIST_PATTERN2);
+ ddr_out32(ddr-mtp8, BIST_PATTERN2);
+ ddr_out32(ddr-mtp9, BIST_PATTERN1);
+ ddr_out32(ddr-mtp10, BIST_PATTERN2);
+ mtcr = BIST_CR;
+ ddr_out32(ddr-mtcr, mtcr);
+ timeout = 100;
+ while (timeout 0 (mtcr BIST_CR_EN)) {
+ mdelay(1000);
+ timeout--;
+ mtcr = ddr_in32(ddr-mtcr);
+ }
+ if (timeout = 0)
+ puts(Timeout\n);
+ else
+ puts(Done\n);
+ err_detect = ddr_in32(ddr-err_detect);
+ err_sbe = ddr_in32(ddr-err_sbe);
+ if (mtcr BIST_CR_STAT) {
+ printf(BIST test failed on controller %d.\n,
+ ctrl_num);
+ }
+ if (err_detect || (err_sbe 0x)) {
+ printf(ECC error detected on controller %d.\n,
+ ctrl_num);
+ }
+
+ if (cs0_config CTLR_INTLV_MASK) {
+ /* restore bnds registers */
+ ddr_out32(cs0_bnds, cs0_bnds);
+ ddr_out32(cs1_bnds, cs1_bnds);
+ ddr_out32(cs2_bnds, cs2_bnds);
+ ddr_out32(cs3_bnds, cs3_bnds);
+ }
+ }
+#endif
}
--
1.7.9.5
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[U-Boot] [PATCH 4/4] driver/ddr/fsl: Add workaround for DDR erratum A008511
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 96 +++-
include/fsl_ddr_sdram.h|2 +
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 1d67983..49e4688 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -11,6 +11,22 @@
#include fsl_immap.h
#include fsl_ddr.h
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ ddr_out32(ptr, value);
+
+ while (ddr_in32(ptr) bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout = 0)
+ puts(Error: A007865 wait for clear timeout.\n);
+}
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
+
#if (CONFIG_CHIP_SELECTS_PER_CTRL 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
@@ -36,6 +52,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
defined(CONFIG_SYS_FSL_ERRATUM_A008514)
u32 *eddrtqcr1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+ u32 temp32, mr6;
+#endif
#ifdef CONFIG_FSL_DDR_BIST
u32 mtcr, err_detect, err_sbe;
u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
@@ -221,6 +240,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
ddr_setbits32(ddr-debug[28], 0x9 20);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+ /* Part 1 of 2 */
+ /* This erraum only applies to verion 5.2.0 */
+ if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
+ /* Disable DRAM VRef training */
+ ddr_out32(ddr-ddr_cdr2,
+ regs-ddr_cdr2 ~DDR_CDR2_VREF_TRAIN_EN);
+ /* Disable deskew */
+ ddr_out32(ddr-debug[28], 0x400);
+ /* Disable D_INIT */
+ ddr_out32(ddr-sdram_cfg_2,
+ regs-ddr_sdram_cfg_2 ~SDRAM_CFG2_D_INIT);
+ ddr_out32(ddr-debug[25], 0x9000);
+ }
+#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
@@ -268,6 +302,66 @@ step2:
mb();
isb();
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+ /* Part 2 of 2 */
+ /* This erraum only applies to verion 5.2.0 */
+ if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
+ /* Wait for idle */
+ timeout = 200;
+ while (!(ddr_in32(ddr-debug[1]) 0x2)
+ (timeout 0)) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout = 0) {
+ printf(Controler %d timeout, debug_2 = %x\n,
+ ctrl_num, ddr_in32(ddr-debug[1]));
+ }
+ /* Set VREF */
+ for (i = 0; i CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs-cs[i].config SDRAM_CS_CONFIG_EN))
+ continue;
+
+ mr6 = (regs-ddr_sdram_mode_10 16) |
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL(i) |
+MD_CNTL_MD_SEL(6) |
+0x0020;
+ temp32 = mr6 | 0xc0;
+ set_wait_for_bits_clear(ddr-sdram_md_cntl,
+ temp32, MD_CNTL_MD_EN);
+ udelay(1);
+ debug(MR6 = 0x%08x\n, temp32);
+ temp32 = mr6 | 0xf0;
+ set_wait_for_bits_clear(ddr-sdram_md_cntl,
+ temp32, MD_CNTL_MD_EN);
+ udelay(1);
+ debug(MR6 = 0x%08x\n, temp32);
+ temp32 = mr6 | 0x70;
+ set_wait_for_bits_clear(ddr-sdram_md_cntl,
+ temp32, MD_CNTL_MD_EN);
+ udelay(1);
+ debug(MR6 = 0x%08x\n, temp32);
+ }
+ ddr_out32(ddr-sdram_md_cntl, 0);
+ ddr_out32(ddr-debug[28], 0); /* Enable deskew */
+ ddr_out32(ddr-debug[1], 0x400); /* restart deskew */
+ /* wait for idle */
+ timeout = 200;
+ while
Re: [U-Boot] am335x: GPMC: reading speed with prefetch mode
On 03/19/2015 04:13 PM, Yegor Yefremov wrote: Strange. Have tried with nand read command, but still the same result with and without CONFIG_NAND_OMAP_GPMC_PREFETCH : [2.150655 0.001006] NAND read: device 0 offset 0x26, size 0x120 [15.978943 13.828288] 18874368 bytes read: OK What about adding some debug prints to the prefetch setup function and see if it is executed at all? Daniel, do you have the numbers? Images size and load time? What can I expect? I don't currently have the setup at hand, sorry. But the number I recall from an email conversation back then is: The time from power-on, loading SPL, loading U-Boot, leeching a 6MB uImage, jumping into it waiting for the console to start dumping the kernel boot messages was less than 5 seconds in total. Thanks, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] am335x: GPMC: reading speed with prefetch mode
On Thu, Mar 19, 2015 at 2:56 PM, Daniel Mack dan...@zonque.org wrote: Hi, On 03/19/2015 02:41 PM, Yegor Yefremov wrote: I've got v2015.04-rc4 running on my custom am335x (600MHz) based board. My 8-bit NAND chip: [17.297793 0.004021] omap-gpmc 5000.gpmc: GPMC revision 6.0 [17.303850 0.006057] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda [17.309706 0.005856] nand: Micron MT29F2G08ABAEAWP [17.312823 0.003117] nand: 256MiB, SLC, page size: 2048, OOB size: 64 [17.317311 0.004488] nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme I need to load about 17Mb FIT image from UBIFS partition. In Linux it takes about 7 seconds: # time cp /mnt/kernel-fit.itb /tmp/ real0m 7.12s user0m 0.00s sys 0m 6.89s But U-Boot needs about twice the time: On my boards, I didn't load the uImage through UBIFS but directly from the raw mtdblock device. That might make a significant difference, depending on how UBIFS is implemented in U-Boot. For performance tests, I recommend you compare the numbers using 'dd' from the mtdblock device under Linux, and 'nand read.i' from U-Boot. Linux will, however, still be faster due to DMA, which is unsuable from U-Boot due to the lack of interrupt handlers. But in my tests, enabling the prefetch mode in U-Boot gave me a speed-up of roughly factor 2 IIRC. Strange. Have tried with nand read command, but still the same result with and without CONFIG_NAND_OMAP_GPMC_PREFETCH : [2.150655 0.001006] NAND read: device 0 offset 0x26, size 0x120 [15.978943 13.828288] 18874368 bytes read: OK As if I would missing some important configuration. Daniel, do you have the numbers? Images size and load time? What can I expect? Yegor ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] fsl-ch3/README: Add description for NOR flash layout (firmware images)
From: Bhupesh Sharma bhupesh.sha...@freescale.com This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com --- arch/arm/cpu/armv8/fsl-lsch3/README | 25 + 1 file changed, 25 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index cc47466..99fc39a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -8,3 +8,28 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. + +Flash Layout + +A typical layout of various images (including Linux and other firmware images) +is shown below considering a 32MB NOR flash device: + + - + | linux | + - 0x0120_ + | Debug Server| + - 0x00C0_ + | AIOP SW | + - 0x0070_ + | MC FW | + - 0x006C_ + | MC Data Path Layout | + - 0x0020_ + | BootLoader | + - 0x_1000 + | PBI | + - 0x_0080 + | RCW | + - 0x_ + + 32-MB NOR flash layout -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/8] driver/i2c/mxc: Add I2C3 and I2C4 for LS2085A
LS2085A uses mxc I2C driver and has four I2C buses.
Signed-off-by: York Sun york...@freescale.com
CC: Heiko Schocher h...@denx.de
---
drivers/i2c/mxc_i2c.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index fc5ee35..02a173e 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -114,6 +114,9 @@ static u16 i2c_clk_div[50][2] = {
#ifndef CONFIG_SYS_MXC_I2C3_SPEED
#define CONFIG_SYS_MXC_I2C3_SPEED 10
#endif
+#ifndef CONFIG_SYS_MXC_I2C4_SPEED
+#define CONFIG_SYS_MXC_I2C4_SPEED 10
+#endif
#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
#define CONFIG_SYS_MXC_I2C1_SLAVE 0
@@ -124,6 +127,9 @@ static u16 i2c_clk_div[50][2] = {
#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
#define CONFIG_SYS_MXC_I2C3_SLAVE 0
#endif
+#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
+#define CONFIG_SYS_MXC_I2C4_SLAVE 0
+#endif
/*
@@ -545,10 +551,18 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init,
mxc_i2c_probe,
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
- defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102XA) ||\
+ defined(CONFIG_LS2085A)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C3_SPEED,
CONFIG_SYS_MXC_I2C3_SLAVE, 2)
#endif
+#ifdef CONFIG_LS2085A
+U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
+mxc_i2c_read, mxc_i2c_write,
+mxc_i2c_set_bus_speed,
+CONFIG_SYS_MXC_I2C4_SPEED,
+CONFIG_SYS_MXC_I2C4_SLAVE, 3)
+#endif
--
1.7.9.5
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[U-Boot] [PATCH] cmd_mem: Store last address/size/etc as ulong
From: Scott Wood scottw...@freescale.com Otherwise the high 32 bits get truncated on 64-bit U-boot. Signed-off-by: Scott Wood scottw...@freescale.com CC: Simon Glass s...@chromium.org --- common/cmd_mem.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index bcb3ee3..62a0404 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -35,9 +35,9 @@ static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. * Memory modify remembered values are different from display memory. */ -static uintdp_last_addr, dp_last_size; -static uintdp_last_length = 0x40; -static uintmm_last_addr, mm_last_size; +static ulong dp_last_addr, dp_last_size; +static ulong dp_last_length = 0x40; +static ulong mm_last_addr, mm_last_size; static ulong base_address = 0; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] drivers/net/e1000.c: Cleanup whitespace
From: Minghuan Lian minghuan.l...@freescale.com
The patch removes unnecessary whitespace to fix checkpatch's
warning: unnecessary whitespace before a quoted newline
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
CC: Joe Hershberger joe.hershber...@ni.com
---
drivers/net/e1000.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index cd44222..e747d97 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -2174,7 +2174,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
DEBUGOUT(Error, did not detect valid phy.\n);
return ret_val;
}
- DEBUGOUT(Phy ID = %x \n, hw-phy_id);
+ DEBUGOUT(Phy ID = %x\n, hw-phy_id);
/* Set PHY to class A mode (if necessary) */
ret_val = e1000_set_phy_mode(hw);
@@ -3485,11 +3485,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* some sticky (latched) bits.
*/
if (e1000_read_phy_reg(hw, PHY_STATUS, mii_status_reg) 0) {
- DEBUGOUT(PHY Read Error \n);
+ DEBUGOUT(PHY Read Error\n);
return -E1000_ERR_PHY;
}
if (e1000_read_phy_reg(hw, PHY_STATUS, mii_status_reg) 0) {
- DEBUGOUT(PHY Read Error \n);
+ DEBUGOUT(PHY Read Error\n);
return -E1000_ERR_PHY;
}
@@ -5152,7 +5152,7 @@ e1000_poll(struct eth_device *nic)
if (!(le32_to_cpu(rd-status)) E1000_RXD_STAT_DD)
return 0;
- /*DEBUGOUT(recv: packet len=%d \n, rd-length); */
+ /* DEBUGOUT(recv: packet len=%d\n, rd-length); */
/* Packet received, make sure the data are re-loaded from RAM. */
len = le32_to_cpu(rd-length);
invalidate_dcache_range((unsigned long)packet,
--
1.7.9.5
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[U-Boot] [PATCH 01/28] armv8/fsl-lsch3: Implement workaround for erratum A008585
Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/generic_timer.c | 11 +++
arch/arm/include/asm/arch-fsl-lsch3/config.h |1 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv8/generic_timer.c
b/arch/arm/cpu/armv8/generic_timer.c
index 223b95e..8e60bae 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -25,7 +25,18 @@ unsigned long get_tbclk(void)
unsigned long timer_read_counter(void)
{
unsigned long cntpct;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+ /* This erratum number needs to be confirmed to match ARM document */
+ unsigned long temp;
+#endif
isb();
asm volatile(mrs %0, cntpct_el0 : =r (cntpct));
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+ asm volatile(mrs %0, cntpct_el0 : =r (temp));
+ while (temp != cntpct) {
+ asm volatile(mrs %0, cntpct_el0 : =r (cntpct));
+ asm volatile(mrs %0, cntpct_el0 : =r (temp));
+ }
+#endif
return cntpct;
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 1d2a7fa..2d461d9 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -120,6 +120,7 @@
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
--
1.7.9.5
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[U-Boot] [PATCH 04/28] armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz. This is
common to the SoC, not board specific.
Signed-off-by: York Sun york...@freescale.com
---
README |8
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 24
board/freescale/ls2085a/ls2085a.c | 18 --
include/configs/ls2085a_common.h |6 +-
4 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/README b/README
index f473515..776ebf4 100644
--- a/README
+++ b/README
@@ -690,6 +690,14 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ COUNTER_FREQUENCY
+ Generic timer clock source frequency.
+
+ COUNTER_FREQUENCY_REAL
+ Generic timer clock source frequency if the real clock is
+ different from COUNTER_FREQUENCY, and can only be determined
+ at run time.
+
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 94fd147..e985181 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -395,3 +395,27 @@ int arch_early_init_r(void)
return 0;
}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+ unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+ /* Update with accurate clock frequency */
+ asm volatile(msr cntfrq_el0, %0 : : r (cntfrq) : memory);
+#endif
+
+ /* Enable timebase for all clusters.
+* It is safe to do so even some clusters are not enabled.
+*/
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+* This is a global setting.
+*/
+ out_le32(cntcr, 0x1);
+
+ return 0;
+}
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,24 +55,6 @@ int dram_init(void)
return 0;
}
-int timer_init(void)
-{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
-
- /* Enable timebase for all clusters.
-* It is safe to do so even some clusters are not enabled.
-*/
- out_le32(cltbenr, 0xf);
-
- /* Enable clock for timer
-* This is a global setting.
-*/
- out_le32(cntcr, 0x1);
-
- return 0;
-}
-
/*
* Board specific reset that is system reset.
*/
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 339337d..b47cf68 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -72,7 +72,11 @@
#define CONFIG_DP_DDR_NUM_CTRLS1
/* Generic Timer Definitions */
-#define COUNTER_FREQUENCY 1200/* 12MHz */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY 2500/* 25MHz */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
--
1.7.9.5
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[U-Boot] [PATCH 02/28] armv8/ls2085a: Update common header file
From: Prabhakar Kushwaha prabha...@freescale.com ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable loadb command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Signed-off-by: Scott Wood scottw...@freescale.com Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 ++ include/configs/ls2085a_common.h | 142 ++ include/configs/ls2085a_emu.h| 62 +++ include/configs/ls2085a_simu.h | 117 + 4 files changed, 222 insertions(+), 110 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 2d461d9..518e59c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -108,6 +108,16 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x260) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x270) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x10ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x12ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x14ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x16ULL + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -119,6 +129,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #endif diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index eb7b9b2..339337d 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -23,7 +23,7 @@ #define CONFIG_ARCH_MISC_INIT /* Link Definitions */ -#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SYS_TEXT_BASE 0x3010 #ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH @@ -47,8 +47,6 @@ #define CONFIG_SYS_FSL_DDR3/* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ @@ -72,7 +70,6 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS1 -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 1200/* 12MHz */ @@ -84,8 +81,6 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_MXC_I2C1_SPEED 4000 -#define CONFIG_SYS_MXC_I2C2_SPEED 4000 /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -99,8 +94,7 @@ /* IFC */ #define CONFIG_FSL_IFC -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + /* * During booting, CS0 needs to be at the region of 0x3000, i.e. the IFC * address 0. But this region is limited to 256MB. To accommodate bigger NOR @@ -114,125 +108,55 @@ #define CONFIG_SYS_FLASH_BASE_PHYS 0x8000 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define
[U-Boot] [PATCH 05/28] armv8/ls2085a: Add support for reset request
From: pankaj chauhan pankaj.chau...@freescale.com
Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: pankaj chauhan pankaj.chau...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 +++
board/freescale/ls2085a/ls2085a.c |7 ---
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index e985181..0e5aa5c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -419,3 +419,14 @@ int timer_init(void)
return 0;
}
+
+void reset_cpu(ulong addr)
+{
+ u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+ u32 val;
+
+ /* Raise RESET_REQ_B */
+ val = in_le32(rstcr);
+ val |= 0x02;
+ out_le32(rstcr, val);
+}
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index bd016e9..19f5a7b 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,13 +55,6 @@ int dram_init(void)
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(ulong addr)
-{
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
--
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[U-Boot] [PATCH 06/28] armv8/fsl-lsch3: Set nodes in DVM domain
From: Scott Wood scottw...@freescale.com This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |9 + arch/arm/include/asm/arch-fsl-lsch3/config.h |6 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 886576e..1787168 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -15,6 +15,15 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* Add fully-coherent masters to DVM domain */ + ldr x1, =CCI_MN_BASE + ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] + str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] +1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] + mvn x0, x3 + tst x0, x3 /* Wait for domain addition to complete */ + b.ne1b + /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 518e59c..9121452 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -118,6 +118,12 @@ #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x14ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x16ULL +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE0x0400 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/28] armv8/fsl-lsch3: Use correct compatible for serial clock fixup
From: Scott Wood scottw...@freescale.com The serial nodes in the fsl-lsch3 device trees have compatible = fsl,ns16550, ns16550a -- so don't look for ns16550. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/arm/cpu/armv8/fsl-lsch3/fdt.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 7eb9b6a..42c5b58 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -62,7 +62,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, ns16550, + do_fixup_by_compat_u32(blob, fsl,ns16550, clock-frequency, CONFIG_SYS_NS16550_CLK, 1); #endif } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/28] armv8/ls2085a: Add workaround for USB erratum A-008751
From: Scott Wood scottw...@freescale.com
Without this USB may not work according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 11 +++
arch/arm/include/asm/arch-fsl-lsch3/config.h |5 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 242a865..17700ef 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -7,8 +7,19 @@
#include common.h
#include fsl_ifc.h
#include asm/arch-fsl-lsch3/soc.h
+#include asm/io.h
+
+static void erratum_a008751(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
+#endif
+}
void fsl_lsch3_early_init_f(void)
{
+ erratum_a008751();
init_early_memctl_regs(); /* tighten IFC timing */
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 9121452..a81e3ed 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -124,6 +124,10 @@
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+/* Supplemental Configuration */
+#define SCFG_BASE 0x01fc
+#define SCFG_USB3PRM1CR0x000
+
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@@ -138,6 +142,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
--
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[U-Boot] [PATCH 08/28] fsl-lsch3: Introduce place for common early SoC init
From: Scott Wood scottw...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/Makefile |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c| 14 ++
arch/arm/include/asm/arch-fsl-lsch3/soc.h |8
board/freescale/ls2085a/ls2085a.c |4 ++--
4 files changed, 25 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index f920eeb..6542590 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -6,6 +6,7 @@
obj-y += cpu.o
obj-y += lowlevel.o
+obj-y += soc.o
obj-y += speed.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
new file mode 100644
index 000..242a865
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fsl_ifc.h
+#include asm/arch-fsl-lsch3/soc.h
+
+void fsl_lsch3_early_init_f(void)
+{
+ init_early_memctl_regs(); /* tighten IFC timing */
+}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
new file mode 100644
index 000..16b723d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+void fsl_lsch3_early_init_f(void);
+
diff --git a/board/freescale/ls2085a/ls2085a.c
b/board/freescale/ls2085a/ls2085a.c
index 19f5a7b..dd0acf2 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -15,6 +15,7 @@
#include fsl_debug_server.h
#include fsl-mc/fsl_mc.h
#include environment.h
+#include asm/arch-fsl-lsch3/soc.h
DECLARE_GLOBAL_DATA_PTR;
@@ -31,8 +32,7 @@ int board_init(void)
int board_early_init_f(void)
{
- init_early_memctl_regs(); /* tighten IFC timing */
-
+ fsl_lsch3_early_init_f();
return 0;
}
--
1.7.9.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/28] armv8: Add SerDes framework for LayerScape Architecture
From: Minghuan Lian minghuan.l...@freescale.com
Add support of SerDes framework for LayerScape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/Makefile |1 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.c |4 +
.../fsl-lsch3/fsl_lsch3_serdes.c} | 78 ++---
arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117
arch/arm/include/asm/arch-fsl-lsch3/config.h |4 +
arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 +++
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h |5 +
include/configs/ls2085a_common.h |5 +
8 files changed, 237 insertions(+), 44 deletions(-)
copy arch/arm/cpu/{armv7/ls102xa/fsl_ls1_serdes.c =
armv8/fsl-lsch3/fsl_lsch3_serdes.c} (51%)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index 6542590..9f7815b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -8,5 +8,6 @@ obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 595dbd1..caa48f2 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -12,6 +12,7 @@
#include asm/arch-fsl-lsch3/immap_lsch3.h
#include fsl_debug_server.h
#include fsl-mc/fsl_mc.h
+#include asm/arch/fsl_serdes.h
#include cpu.h
#include mp.h
#include speed.h
@@ -415,6 +416,9 @@ int arch_early_init_r(void)
if (rv)
printf(Did not wake secondary cores\n);
+#ifdef CONFIG_SYS_HAS_SERDES
+ fsl_serdes_init();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
similarity index 51%
copy from arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
copy to arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
index 9b78acb..78b9210 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -1,32 +1,31 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier:GPL-2.0+
*/
#include common.h
-#include asm/arch/fsl_serdes.h
-#include asm/arch/immap_ls102xa.h
-#include asm/errno.h
#include asm/io.h
-#include fsl_ls1_serdes.h
+#include asm/errno.h
+#include asm/arch/fsl_serdes.h
+#include asm/arch-fsl-lsch3/immap_lsch3.h
#ifdef CONFIG_SYS_FSL_SRDS_1
-static u64 serdes1_prtcl_map;
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
-static u64 serdes2_prtcl_map;
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
int is_serdes_configured(enum srds_prtcl device)
{
- u64 ret = 0;
+ int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
- ret |= (1ULL device) serdes1_prtcl_map;
+ ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- ret |= (1ULL device) serdes2_prtcl_map;
+ ret |= serdes2_prtcl_map[device];
#endif
return !!ret;
@@ -35,20 +34,20 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 cfg = in_be32(gur-rcwsr[4]);
+ u32 cfg = in_le32(gur-rcwsr[28]);
int i;
switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1
case FSL_SRDS_1:
- cfg = RCWSR4_SRDS1_PRTCL_MASK;
- cfg = RCWSR4_SRDS1_PRTCL_SHIFT;
+ cfg = FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ cfg = FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
case FSL_SRDS_2:
- cfg = RCWSR4_SRDS2_PRTCL_MASK;
- cfg = RCWSR4_SRDS2_PRTCL_SHIFT;
+ cfg = FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ cfg = FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
break;
#endif
default:
@@ -56,7 +55,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
break;
}
/* Is serdes enabled at all? */
- if (unlikely(cfg == 0))
+ if (cfg == 0)
return -ENODEV;
for (i = 0; i SRDS_MAX_LANES; i++) {
@@ -67,14 +66,16 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV;
}
-u64
[U-Boot] [PATCH 17/28] armv8/fsl-lsch3: Enable system error aborts
From: Scott Wood scottw...@freescale.com This lets us see the problems (close to) when they happen, rather than Linux hanging when it enables them prior to having a working console. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c |4 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 07064a3..22b5fb2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -263,6 +263,10 @@ int arch_cpu_init(void) __asm_invalidate_tlb_all(); early_mmu_setup(); set_sctlr(get_sctlr() | CR_C); + + /* Enable system error aborts */ + asm volatile(msr daifclr, #4 : : : memory); + return 0; } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/28] net/memac_phy: reuse driver for little endian SoCs
From: Shaohui Xie shaohui@freescale.com
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
Signed-off-by: Shaohui Xie shaohui@freescale.com
CC: Joe Hershberger joe.hershber...@ni.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h |1 +
drivers/net/Makefile |1 +
drivers/net/fm/eth.c |2 +-
drivers/net/fm/memac.c|2 +-
drivers/net/fm/memac_phy.c| 62 ++---
drivers/net/vsc9953.c |2 +-
{arch/powerpc/include/asm = include}/fsl_memac.h |0
7 files changed, 46 insertions(+), 24 deletions(-)
rename {arch/powerpc/include/asm = include}/fsl_memac.h (100%)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 98db1ef..684c70f 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -109,6 +109,7 @@
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5497934..d871093 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,4 +66,5 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o
xilinx_ll_temac_mdio.o \
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
+obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 1d1089d..a7a5c69 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -15,7 +15,7 @@
#include phy.h
#include asm/fsl_dtsec.h
#include asm/fsl_tgec.h
-#include asm/fsl_memac.h
+#include fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 60e898c..81a64bf 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,7 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_memac.h
+#include fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index a155d89..4ab78e6 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -10,9 +10,28 @@
#include miiphy.h
#include phy.h
#include asm/io.h
-#include asm/fsl_memac.h
+#include fsl_memac.h
#include fm_eth.h
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+#define memac_out_32(a, v) out_le32(a, v)
+#define memac_clrbits_32(a, v) clrbits_le32(a, v)
+#define memac_setbits_32(a, v) setbits_le32(a, v)
+#else
+#define memac_out_32(a, v) out_be32(a, v)
+#define memac_clrbits_32(a, v) clrbits_be32(a, v)
+#define memac_setbits_32(a, v) setbits_be32(a, v)
+#endif
+
+static u32 memac_in_32(u32 *reg)
+{
+#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+ return in_le32(reg);
+#else
+ return in_be32(reg);
+#endif
+}
+
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
@@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr,
int dev_addr,
if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */
dev_addr = regnum 0x1f;
- clrbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
+ memac_clrbits_32(regs-mdio_stat, MDIO_STAT_ENC);
} else
- setbits_be32(regs-mdio_stat, MDIO_STAT_ENC);
+ memac_setbits_32(regs-mdio_stat, MDIO_STAT_ENC);
/* Wait till the bus is free */
- while ((in_be32(regs-mdio_stat)) MDIO_STAT_BSY)
+ while ((memac_in_32(regs-mdio_stat)) MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
- out_be32(regs-mdio_ctl, mdio_ctl);
+ memac_out_32(regs-mdio_ctl, mdio_ctl);
/* Set the register address */
if (c45)
- out_be32(regs-mdio_addr, regnum 0x);
+ memac_out_32(regs-mdio_addr, regnum 0x);
/* Wait till the bus is free */
- while ((in_be32(regs-mdio_stat)) MDIO_STAT_BSY)
+ while ((memac_in_32(regs-mdio_stat)) MDIO_STAT_BSY)
;
/* Write the value to the register */
- out_be32(regs-mdio_data, MDIO_DATA(value));
+ memac_out_32(regs-mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write
[U-Boot] [PATCH 14/28] drivers/fsl-mc: Changed MC firmware loading for new boot architecture
From: J. German Rivera german.riv...@freescale.com
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables mcboottimeout for MC boot timeout in milliseconds,
mcmemsize for MC DRAM block size. Check MC boot status before calling
flib functions.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/README |8 +
drivers/net/fsl-mc/mc.c | 494 ++-
include/configs/ls2085a_common.h|6 +-
include/configs/ls2085a_emu.h | 13 +-
include/configs/ls2085a_simu.h |5 +
5 files changed, 395 insertions(+), 131 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index 99fc39a..f781620 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -33,3 +33,11 @@ is shown below considering a 32MB NOR flash device:
- 0x_
32-MB NOR flash layout
+
+Environment Variables
+=
+mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize: MC DRAM block size. If this variable is not defined, the value
+ CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 2a2b0af..c5c44bc 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -3,7 +3,6 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
-
#include errno.h
#include asm/io.h
#include fsl-mc/fsl_mc.h
@@ -15,14 +14,64 @@
#include fsl-mc/fsl_dpio.h
#include fsl-mc/fsl_qbman_portal.h
+#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
+#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
+
+#define MC_MEM_SIZE_ENV_VARmcmemsize
+#define MC_BOOT_TIMEOUT_ENV_VARmcboottimeout
+
DECLARE_GLOBAL_DATA_PTR;
static int mc_boot_status;
struct fsl_mc_io *dflt_mc_io = NULL;
uint16_t dflt_dprc_handle = 0;
struct fsl_dpbp_obj *dflt_dpbp = NULL;
struct fsl_dpio_obj *dflt_dpio = NULL;
-uint16_t dflt_dpio_handle = NULL;
+uint16_t dflt_dpio_handle = 0;
+
+#ifdef DEBUG
+void dump_ram_words(const char *title, void *addr)
+{
+ int i;
+ uint32_t *words = addr;
+
+ printf(Dumping beginning of %s (%p):\n, title, addr);
+ for (i = 0; i 16; i++)
+ printf(%#x , words[i]);
+
+ printf(\n);
+}
+void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
+{
+ printf(MC CCSR registers:\n
+ reg_gcr1 %#x\n
+ reg_gsr %#x\n
+ reg_sicbalr %#x\n
+ reg_sicbahr %#x\n
+ reg_sicapr %#x\n
+ reg_mcfbalr %#x\n
+ reg_mcfbahr %#x\n
+ reg_mcfapr %#x\n
+ reg_psr %#x\n,
+ mc_ccsr_regs-reg_gcr1,
+ mc_ccsr_regs-reg_gsr,
+ mc_ccsr_regs-reg_sicbalr,
+ mc_ccsr_regs-reg_sicbahr,
+ mc_ccsr_regs-reg_sicapr,
+ mc_ccsr_regs-reg_mcfbalr,
+ mc_ccsr_regs-reg_mcfbahr,
+ mc_ccsr_regs-reg_mcfapr,
+ mc_ccsr_regs-reg_psr);
+}
+#else
+
+#define dump_ram_words(title, addr)
+#define dump_mc_ccsr_regs(mc_ccsr_regs)
+
+#endif /* DEBUG */
+
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
/**
* Copying MC firmware or DPL image to DDR
*/
@@ -31,6 +80,7 @@ static int mc_copy_image(const char *title,
{
debug(%s copied to address %p\n, title, (void *)mc_ram_addr);
memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+ flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
return 0;
}
@@ -92,22 +142,254 @@ int parse_mc_firmware_fit_image(const void
**raw_image_addr,
return 0;
}
+#endif
+
+/*
+ * Calculates the values to be used to specify the address range
+ * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
+ * It returns the highest 512MB-aligned address within the given
+ * address range, in '*aligned_base_addr', and the number of 256 MiB
+ * blocks in it, in 'num_256mb_blocks'.
+ */
+static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
+ size_t mc_ram_size,
+ u64 *aligned_base_addr,
+ u8 *num_256mb_blocks)
+{
+ u64 addr;
+ u16 num_blocks;
+
+ if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
+ printf(fsl-mc: ERROR: invalid MC private RAM size (%lu)\n,
+ mc_ram_size);
+ return -EINVAL;
+ }
+
+ num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+ if (num_blocks 1 || num_blocks
[U-Boot] [PATCH 07/28] armv8/fsl-lsch3: Update early MMU table
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 56 +---
common/board_r.c |6
2 files changed, 45 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 0e5aa5c..595dbd1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -25,8 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Level 0 IA[39], table address @0
- * Level 1 IA[31:30], table address @01000, 0x2000
- * Level 2 IA[29:21], table address @0x3000
+ * Level 1 IA[31:30], table address @0x1000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000, 0x4000
+ * Address above 0x5000 is free for other purpose.
*/
#define SECTION_SHIFT_L0 39UL
@@ -61,12 +62,12 @@ static inline void early_mmu_setup(void)
{
int el;
u64 i;
- u64 section_l1t0, section_l1t1, section_l2;
+ u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1;
u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
- u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
-
+ u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+ u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
level0_table[0] =
(u64)level1_table_0 | PMD_TYPE_TABLE;
@@ -80,21 +81,25 @@ static inline void early_mmu_setup(void)
*/
section_l1t0 = 0;
section_l1t1 = BLOCK_SIZE_L0;
- section_l2 = 0;
+ section_l2t0 = 0;
+ section_l2t1 = CONFIG_SYS_FLASH_BASE;
for (i = 0; i 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
MT_DEVICE_NGNRNE);
set_pgtable_section(level1_table_1, i, section_l1t1,
MT_NORMAL);
- set_pgtable_section(level2_table, i, section_l2,
+ set_pgtable_section(level2_table_0, i, section_l2t0,
+ MT_DEVICE_NGNRNE);
+ set_pgtable_section(level2_table_1, i, section_l2t1,
MT_DEVICE_NGNRNE);
section_l1t0 += BLOCK_SIZE_L1;
section_l1t1 += BLOCK_SIZE_L1;
- section_l2 += BLOCK_SIZE_L2;
+ section_l2t0 += BLOCK_SIZE_L2;
+ section_l2t1 += BLOCK_SIZE_L2;
}
level1_table_0[0] =
- (u64)level2_table | PMD_TYPE_TABLE;
+ (u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[1] =
0x4000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_DEVICE_NGNRNE);
@@ -105,17 +110,34 @@ static inline void early_mmu_setup(void)
0xc000 | PMD_SECT_AF | PMD_TYPE_SECT |
PMD_ATTRINDX(MT_NORMAL);
- /* Rewrite table to enable cache */
- set_pgtable_section(level2_table,
+ /* Rewerite table to enable cache for OCRAM */
+ set_pgtable_section(level2_table_0,
CONFIG_SYS_FSL_OCRAM_BASE SECTION_SHIFT_L2,
CONFIG_SYS_FSL_OCRAM_BASE,
MT_NORMAL);
- for (i = CONFIG_SYS_IFC_BASE SECTION_SHIFT_L2;
-i (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
- SECTION_SHIFT_L2; i++) {
- section_l2 = i SECTION_SHIFT_L2;
- set_pgtable_section(level2_table, i,
- section_l2, MT_NORMAL);
+
+#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) defined(CONFIG_SYS_NOR_AMASK_EARLY)
+ /* Rewrite table to enable cache for two entries (4MB) */
+ section_l2t1 = CONFIG_SYS_IFC_BASE;
+ set_pgtable_section(level2_table_0,
+ section_l2t1 SECTION_SHIFT_L2,
+ section_l2t1,
+ MT_NORMAL);
+ section_l2t1 += BLOCK_SIZE_L2;
+ set_pgtable_section(level2_table_0,
+ section_l2t1 SECTION_SHIFT_L2,
+ section_l2t1,
+ MT_NORMAL);
+#endif
+
+ /* Create a mapping for 256MB IFC region to final flash location */
+
[U-Boot] [PATCH 11/28] driver/ldpaa_eth: Update ldpaa ethernet driver
From: Prabhakar Kushwaha prabha...@freescale.com
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev-state is set as ETH_STATE_INIT So take care net_dev-state as
ETH_STATE_INIT in ldpaa_eth_stop.
Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.
Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.
Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.
Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: pankaj chauhan pankaj.chau...@freescale.com
Signed-off-by: Roy Pledge roy.ple...@freescale.com
---
drivers/net/ldpaa_eth/ldpaa_eth.c | 62 +++--
1 file changed, 38 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index b79942f..9015e4f 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -15,6 +15,7 @@
#include ldpaa_eth.h
+#undef CONFIG_PHYLIB
static int init_phy(struct eth_device *dev)
{
/*TODO for external PHY */
@@ -33,8 +34,6 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
struct qbman_release_desc releasedesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
- invalidate_dcache_all();
-
fd_addr = ldpaa_fd_get_addr(fd);
fd_offset = ldpaa_fd_get_offset(fd);
fd_length = ldpaa_fd_get_len(fd);
@@ -62,6 +61,7 @@ static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
NetReceive((uint8_t *)(fd_addr) + fd_offset, fd_length);
error:
+ flush_dcache_range(fd_addr, fd_addr + LDPAA_ETH_RX_BUFFER_SIZE);
qbman_release_desc_clear(releasedesc);
qbman_release_desc_set_bpid(releasedesc, dflt_dpbp-dpbp_attr.bpid);
do {
@@ -76,22 +76,29 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev-priv;
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
- int i = 5, err = 0, status;
+ int i = 5, err = 0, status, loop = 20;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
- qbman_pull_desc_clear(pulldesc);
- qbman_pull_desc_set_numframes(pulldesc, 1);
- qbman_pull_desc_set_fq(pulldesc, priv-rx_dflt_fqid);
-
while (--i) {
+ qbman_pull_desc_clear(pulldesc);
+ qbman_pull_desc_set_numframes(pulldesc, 1);
+ qbman_pull_desc_set_fq(pulldesc, priv-rx_dflt_fqid);
+
err = qbman_swp_pull(swp, pulldesc);
if (err 0) {
printf(Dequeue frames error:0x%08x\n, err);
continue;
}
- dq = qbman_swp_dqrr_next(swp);
+ do {
+ loop--;
+ dq = qbman_swp_dqrr_next(swp);
+
+ if (!loop)
+ break;
+ } while (!dq);
+
if (dq) {
/* Check for valid frame. If not sent a consume
* confirmation to QBMAN otherwise give it to NADK
@@ -128,7 +135,6 @@ static void ldpaa_eth_tx_conf(struct ldpaa_eth_priv *priv,
struct qbman_release_desc releasedesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
- invalidate_dcache_all();
fd_addr = ldpaa_fd_get_addr(fd);
@@ -159,22 +165,29 @@ static int ldpaa_eth_pull_dequeue_tx_conf(struct
ldpaa_eth_priv *priv)
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int err = 0;
- int i = 5, status;
+ int i = 5, status, loop = 20;
static struct qbman_pull_desc pulldesc;
struct qbman_swp *swp = dflt_dpio-sw_portal;
- qbman_pull_desc_clear(pulldesc);
- qbman_pull_desc_set_numframes(pulldesc, 1);
- qbman_pull_desc_set_fq(pulldesc, priv-tx_conf_fqid);
-
while (--i) {
+ qbman_pull_desc_clear(pulldesc);
+ qbman_pull_desc_set_numframes(pulldesc, 1);
+ qbman_pull_desc_set_fq(pulldesc, priv-tx_conf_fqid);
+
err = qbman_swp_pull(swp, pulldesc);
if (err 0) {
printf(Dequeue TX conf frames error:0x%08x\n, err);
continue;
}
- dq = qbman_swp_dqrr_next(swp);
+ do {
+ loop--;
+ dq = qbman_swp_dqrr_next(swp);
+
+ if (!loop)
+
[U-Boot] [PATCH 19/28] armv8/ls2085aqds: Add support of LS2085AQDS platform
The LS2080AQDS is an evaluatoin platform that supports the LS2080A
family SoCs. This patch add basic support of the platform.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
arch/arm/Kconfig | 11 +
arch/arm/cpu/armv8/fsl-lsch3/README| 70 -
board/freescale/{ls1021aqds = ls2085aqds}/Kconfig |9 +-
board/freescale/ls2085aqds/MAINTAINERS |7 +
board/freescale/ls2085aqds/Makefile|8 +
board/freescale/ls2085aqds/README | 129 +
board/freescale/{ls2085a = ls2085aqds}/ddr.c | 126 -
board/freescale/{ls2085a = ls2085aqds}/ddr.h | 28 +-
board/freescale/ls2085aqds/ls2085aqds.c| 287
.../ls2085aqds_qixis.h}| 19 +-
...qds_ddr4_nor_defconfig = ls2085aqds_defconfig} |2 +-
include/configs/ls2085a_common.h | 38 ++-
include/configs/ls2085aqds.h | 283 +++
include/fsl_ddr_sdram.h|1 +
14 files changed, 902 insertions(+), 116 deletions(-)
copy board/freescale/{ls1021aqds = ls2085aqds}/Kconfig (54%)
create mode 100644 board/freescale/ls2085aqds/MAINTAINERS
create mode 100644 board/freescale/ls2085aqds/Makefile
create mode 100644 board/freescale/ls2085aqds/README
copy board/freescale/{ls2085a = ls2085aqds}/ddr.c (64%)
copy board/freescale/{ls2085a = ls2085aqds}/ddr.h (63%)
create mode 100644 board/freescale/ls2085aqds/ls2085aqds.c
copy board/freescale/{ls1021aqds/ls1021aqds_qixis.h =
ls2085aqds/ls2085aqds_qixis.h} (53%)
copy configs/{ls1021aqds_ddr4_nor_defconfig = ls2085aqds_defconfig} (66%)
create mode 100644 include/configs/ls2085aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b9ebee1..f4a7851 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -648,6 +648,16 @@ config TARGET_LS2085A_SIMU
select ARM64
select ARMV8_MULTIENTRY
+config TARGET_LS2085AQDS
+ bool Support ls2085aqds
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2085AQDS platform
+ The LS2085A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS2085A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool Support ls1021aqds
select CPU_V7
@@ -793,6 +803,7 @@ source board/denx/m53evk/Kconfig
source board/embest/mx6boards/Kconfig
source board/esg/ima3-mx53/Kconfig
source board/freescale/ls2085a/Kconfig
+source board/freescale/ls2085aqds/Kconfig
source board/freescale/ls1021aqds/Kconfig
source board/freescale/ls1021atwr/Kconfig
source board/freescale/mx23evk/Kconfig
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index f781620..817ea1b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -11,28 +11,82 @@ for example LS2085A.
Flash Layout
-A typical layout of various images (including Linux and other firmware images)
-is shown below considering a 32MB NOR flash device:
+
+(1) A typical layout of various images (including Linux and other firmware
images)
+ is shown below considering a 32MB NOR flash device present on most
+ pre-silicon platforms (simulator and emulator):
-
- | linux |
+ | FIT Image |
+ | (linux + DTB + RFS) |
- 0x0120_
- | Debug Server|
+ | Debug Server FW |
- 0x00C0_
- | AIOP SW |
+ | AIOP FW |
- 0x0070_
| MC FW |
- 0x006C_
- | MC Data Path Layout |
+ | MC DPL Blob |
- 0x0020_
- | BootLoader |
+ | BootLoader + Env|
- 0x_1000
| PBI |
- 0x_0080
| RCW |
- 0x_
- 32-MB NOR flash layout
+ 32-MB NOR flash layout for pre-silicon platforms (simulator and
emulator)
+
+(2) A typical layout of various images (including Linux and other firmware
images)
+is shown below considering a 128MB NOR flash device present on QDS
+boards:
+ - 0x5_8800_ ---
+ | .. Unused .. (7M) | |
+ - 0x5_8790_ |
+ | FIT Image (linux + DTB + RFS) (40M) |
[U-Boot] [PATCH 18/28] driver/ldpaa: Add support of WRIOP static data structure
From: Prabhakar Kushwaha prabha...@freescale.com
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c |7 +-
arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 24
drivers/net/ldpaa_eth/Makefile|2 +-
drivers/net/ldpaa_eth/ldpaa_eth.h |4 -
drivers/net/ldpaa_eth/ldpaa_wriop.c | 146 +
include/fsl-mc/ldpaa_wriop.h | 70 ++
7 files changed, 250 insertions(+), 6 deletions(-)
create mode 100644 drivers/net/ldpaa_eth/ldpaa_wriop.c
create mode 100644 include/fsl-mc/ldpaa_wriop.h
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
index 78b9210..02ca126 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -9,6 +9,7 @@
#include asm/errno.h
#include asm/arch/fsl_serdes.h
#include asm/arch-fsl-lsch3/immap_lsch3.h
+#include fsl-mc/ldpaa_wriop.h
#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
@@ -86,8 +87,12 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32
sd_prctl_shift,
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
if (unlikely(lane_prtcl = SERDES_PRCTL_COUNT))
debug(Unknown SerDes lane protocol %d\n, lane_prtcl);
- else
+ else {
serdes_prtcl_map[lane_prtcl] = 1;
+#ifdef CONFIG_FSL_MC_ENET
+ wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+#endif
+ }
}
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 684c70f..403b2ef 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -38,6 +38,9 @@
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B8)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA)
/* SP (Cortex-A5) related */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index 91cf68b..d6bee60 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -47,6 +47,30 @@ struct ccsr_gur {
u32 devdisr5; /* Device disable control 5 */
u32 devdisr6; /* Device disable control 6 */
u32 devdisr7; /* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x0001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x0002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x0004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x0008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x0010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x0020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x0040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x0080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x0100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x0200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x0400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x0800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x1000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x2000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x4000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x8000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x0001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x0002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x0004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x0008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x0010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x0020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x0040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x0080
u8 res_08c[0x90-0x8c];
u32 coredisru; /* uppper portion for support of 64 cores */
u32 coredisrl; /* lower portion for support of 64 cores */
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 3b1a60b..d32d67e 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Layerscape LDPAA driver
+obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
diff --git
[U-Boot] [PATCH 16/28] armv8/fsl-ch3: Add support to print RCW configuration
From: Bhupesh Sharma bhupesh.sha...@freescale.com
This patch adds support to print out the Reset Configuration Word
information.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index caa48f2..07064a3 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -371,6 +371,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@@ -394,6 +395,19 @@ int print_cpuinfo(void)
printf( DP-DDR: %-4s MHz, strmhz(buf, sysinfo.freq_ddrbus2));
puts(\n);
+ /* Display the RCW, so that no one gets confused as to what RCW
+* we're actually using for this boot.
+*/
+ puts(Reset Configuration Word (RCW):);
+ for (i = 0; i ARRAY_SIZE(gur-rcwsr); i++) {
+ u32 rcw = in_le32(gur-rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf(\n %02x:, i * 4);
+ printf( %08x, rcw);
+ }
+ puts(\n);
+
return 0;
}
#endif
--
1.7.9.5
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[U-Boot] [PATCH 13/28] net/phy/cortina: Fix compilation warning
From: pankaj chauhan pankaj.chau...@freescale.com
Fix comilation warning which is emitted when
firmware address is more than 32 bit.
Signed-off-by: pankaj chauhan pankaj.chau...@freescale.com
CC: Joe Hershberger joe.hershber...@ni.com
---
drivers/net/phy/cortina.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 254f056..3a2b3bb 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -186,8 +186,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
while (*addr != 0x0a) {
line_temp[i++] = *addr++;
if (0x50 i) {
- printf(Not found Cortina PHY ucode at 0x%x\n,
- CONFIG_CORTINA_FW_ADDR);
+ printf(Not found Cortina PHY ucode at 0x%p\n,
+ (char *)CONFIG_CORTINA_FW_ADDR);
return;
}
}
--
1.7.9.5
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[U-Boot] [PATCH 24/28] armv8/ls2085aqds: NAND boot support
From: Scott Wood scottw...@freescale.com
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper
nand boot RCW and flash to the beginning of NAND.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/arm/Kconfig |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c| 48 +
arch/arm/cpu/armv8/{u-boot.lds = u-boot-spl.lds} | 74 +
arch/arm/include/asm/arch-fsl-lsch3/config.h |9 +++
arch/arm/lib/crt0_64.S|7 ++
board/freescale/ls2085aqds/ddr.c |4 ++
common/spl/spl.c |2 +-
common/spl/spl_nand.c |2 +-
configs/ls2085aqds_nand_defconfig |4 ++
drivers/misc/fsl_ifc.c| 12
drivers/mtd/nand/fsl_ifc_spl.c|2 +-
include/configs/ls2085a_common.h | 29
include/configs/ls2085aqds.h | 50 --
13 files changed, 193 insertions(+), 51 deletions(-)
copy arch/arm/cpu/armv8/{u-boot.lds = u-boot-spl.lds} (57%)
create mode 100644 configs/ls2085aqds_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7478eb4..46a48a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,7 @@ config TARGET_LS2085AQDS
bool Support ls2085aqds
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef..ca00108 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
#include common.h
#include fsl_ifc.h
+#include nand.h
+#include spl.h
#include asm/arch-fsl-lsch3/soc.h
#include asm/io.h
+#include asm/global_data.h
+
+DECLARE_GLOBAL_DATA_PTR;
static void erratum_a008751(void)
{
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
#endif
}
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+ u32 val;
+
+ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+ val = ~DCFG_PORSR1_RCW_SRC;
+ val |= DCFG_PORSR1_RCW_SRC_NOR;
+ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
+ erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+ board_early_init_f();
+ timer_init();
+ env_init();
+ gd-baudrate = getenv_ulong(baudrate, 10, CONFIG_BAUDRATE);
+
+ serial_init();
+ console_init_f();
+ dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
similarity index 57%
copy from arch/arm/cpu/armv8/u-boot.lds
copy to arch/arm/cpu/armv8/u-boot-spl.lds
index 4c1..4df339c 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -5,80 +5,68 @@
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, ga...@denx.de
*
+ * (C) Copyright 2010
+ * Texas Instruments, www.ti.com
+ * Aneesh V ane...@ti.com
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
OUTPUT_FORMAT(elf64-littleaarch64, elf64-littleaarch64,
elf64-littleaarch64)
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
- . = 0x;
-
- . = ALIGN(8);
- .text :
- {
+ .text : {
+ . = ALIGN(8);
*(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
- }
+ } .sram
- . = ALIGN(8);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } .sram
- . = ALIGN(8);
.data : {
+ . = ALIGN(8);
*(.data*)
- }
+ } .sram
- . = ALIGN(8);
-
- . = .;
-
- . = ALIGN(8);
.u_boot_list : {
+ . = ALIGN(8);
KEEP(*(SORT(.u_boot_list*)));
- }
-
-
[U-Boot] [PATCH 27/28] ls2085a: esdhc: Add esdhc support for ls2085a
From: Yangbo Lu yangbo...@freescale.com
This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 +++
arch/arm/cpu/armv8/fsl-lsch3/fdt.c |7 +
arch/arm/include/asm/arch-fsl-lsch3/config.h |2 ++
drivers/mmc/fsl_esdhc.c | 36 --
include/configs/ls2085a_common.h |5 ++--
include/configs/ls2085aqds.h | 19 +-
include/configs/ls2085ardb.h | 11 +++-
include/fsl_esdhc.h |4 +++
8 files changed, 88 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 22b5fb2..e738c49 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -13,6 +13,9 @@
#include fsl_debug_server.h
#include fsl-mc/fsl_mc.h
#include asm/arch/fsl_serdes.h
+#ifdef CONFIG_FSL_ESDHC
+#include fsl_esdhc.h
+#endif
#include cpu.h
#include mp.h
#include speed.h
@@ -416,6 +419,13 @@ int print_cpuinfo(void)
}
#endif
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int error = 0;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index 42c5b58..d370023 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -7,6 +7,9 @@
#include common.h
#include libfdt.h
#include fdt_support.h
+#ifdef CONFIG_FSL_ESDHC
+#include fsl_esdhc.h
+#endif
#include mp.h
#ifdef CONFIG_MP
@@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, fsl,ns16550,
clock-frequency, CONFIG_SYS_NS16550_CLK, 1);
#endif
+
+#if defined(CONFIG_FSL_ESDHC)
+ fdt_fixup_esdhc(blob, bd);
+#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 77c20ab..ca8d38c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -31,6 +31,7 @@
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x0030)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x0031)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x0037)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x0114)
#define CONFIG_SYS_IFC_ADDR(CONFIG_SYS_IMMR + 0x0124)
#define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR +
0x011C0500)
#define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR +
0x011C0600)
@@ -110,6 +111,7 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_ESDHC_LE
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5e270d..7528b9d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd-resp_type MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102XA)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
+ defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -183,7 +184,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc-priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg-esdhc_base;
-
+#ifdef CONFIG_LS2085A
+ dma_addr_t addr;
+#endif
uint wml_value;
wml_value = data-blocksize/4;
@@ -194,8 +197,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(regs-wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+ addr = virt_to_phys((void *)(data-dest));
+ if (upper_32_bits(addr))
+ printf(Error found for upper 32 bits\n);
+ else
+ esdhc_write32(regs-dsaddr, lower_32_bits(addr));
+#else
esdhc_write32(regs-dsaddr, (u32)data-dest);
#endif
+#endif
} else {
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
flush_dcache_range((ulong)data-src,
@@ -212,8 +223,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(regs-wml, WML_WR_WML_MASK,
wml_value 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+
[U-Boot] [PATCH 03/28] armv8/fsl-lsch3: Fix platform clock calculation
Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/speed.c |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 72cd999..2b140cd 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info)
sys_info-freq_systembus *= (in_le32(gur-rcwsr[0])
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT)
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+ /* Platform clock is half of platform PLL */
+ sys_info-freq_systembus /= 2;
sys_info-freq_ddrbus *= (in_le32(gur-rcwsr[0])
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT)
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info)
offsetof(struct ccsr_clk_cluster_group,
pllngsr[i%3].gsr));
ratio[i] = (in_le32(offset) 1) 0x3f;
- if (ratio[i] 4)
- freq_c_pll[i] = sysclk * ratio[i];
- else
- freq_c_pll[i] = sys_info-freq_systembus * ratio[i];
+ freq_c_pll[i] = sysclk * ratio[i];
}
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 26/28] armv8/ls2085ardb: Enable NAND SPL support
From: Scott Wood scottw...@freescale.com
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or qixis_reset nand
command.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/arm/Kconfig |1 +
board/freescale/ls2085ardb/ddr.c |4
configs/ls2085ardb_nand_defconfig |4
include/configs/ls2085ardb.h | 40 -
4 files changed, 44 insertions(+), 5 deletions(-)
create mode 100644 configs/ls2085ardb_nand_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 46a48a0..7cbbf37 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config TARGET_LS2085ARDB
bool Support ls2085ardb
select ARM64
select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
help
Support for Freescale LS2085ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
index 6cd5e8b..8d71ae1 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -147,9 +147,13 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL) !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
puts(Initializing DDRusing SPD\n);
dram_size = fsl_ddr_sdram();
+#endif
return dram_size;
}
diff --git a/configs/ls2085ardb_nand_defconfig
b/configs/ls2085ardb_nand_defconfig
new file mode 100644
index 000..39ba8c5
--- /dev/null
+++ b/configs/ls2085ardb_nand_defconfig
@@ -0,0 +1,4 @@
++S:CONFIG_SYS_EXTRA_OPTIONS=SYS_FSL_DDR4,NAND
++S:CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS2085ARDB=y
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 24400e4..34aa3e5 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -139,11 +139,13 @@ unsigned long get_board_sys_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK0x04
+#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_RST_CTL_RESET0x31
#define QIXIS_RST_CTL_RESET_EN 0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RCW_SRC_NAND 0x119
#defineQIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
@@ -169,6 +171,33 @@ unsigned long get_board_sys_clk(void);
FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3 0x0
+#if defined(CONFIG_SPL) defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (1536 * 1024)
+#define CONFIG_ENV_SECT_SIZE 0x2
+#define CONFIG_ENV_SIZE0x2000
+#define CONFIG_SPL_PAD_TO 0x7ff40
+#define CONFIG_SYS_NAND_U_BOOT_OFFS(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE(512 * 1024)
+#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
@@ -187,6 +216,12 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR(CONFIG_SYS_FLASH_BASE +
0x20)
+#define CONFIG_ENV_SECT_SIZE 0x2
+#define CONFIG_ENV_SIZE0x2000
+#endif
+
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR0x580D0ULL
@@ -232,11 +267,6 @@ unsigned long get_board_sys_clk(void);
#define
[U-Boot] [PATCH 23/28] driver/ifc: Add 64KB page support
From: Jaiprakash Singh b44...@freescale.com
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh b44...@freescale.com
Change-Id: I64800b3ed1a32c77ae3f2ac007e289e3078c2c09
---
arch/arm/cpu/armv7/ls102xa/clock.c|4 +-
arch/arm/cpu/armv8/fsl-lsch3/speed.c |4 +-
arch/powerpc/cpu/mpc85xx/cpu_init_early.c |8 +--
arch/powerpc/cpu/mpc85xx/speed.c |4 +-
board/freescale/bsc9132qds/bsc9132qds.c |4 +-
board/freescale/c29xpcie/c29xpcie.c |4 +-
board/freescale/p1010rdb/p1010rdb.c |5 +-
board/freescale/p1010rdb/spl.c|4 +-
drivers/mtd/nand/fsl_ifc_nand.c | 53 ++
drivers/mtd/nand/fsl_ifc_spl.c| 23 ++--
include/fsl_ifc.h | 84 +++--
11 files changed, 126 insertions(+), 71 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
index 8f80c61..7a337e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -20,7 +20,7 @@ void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
@@ -74,7 +74,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_be32(ifc_regs-ifc_ccr);
+ ccr = in_be32(ifc_regs.gregs-ifc_ccr);
ccr = ((ccr IFC_CCR_CLK_DIV_MASK) IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info-freq_localbus = sys_info-freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 2b140cd..cac4f92 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -26,7 +26,7 @@ void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_le32(ifc_regs-ifc_ccr);
+ ccr = in_le32(ifc_regs.gregs-ifc_ccr);
ccr = ((ccr IFC_CCR_CLK_DIV_MASK) IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info-freq_localbus = sys_info-freq_systembus / ccr;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5ca9bf5..235a635 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_A003399_NOR_WORKAROUND
void setup_ifc(void)
{
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
@@ -70,9 +70,9 @@ void setup_ifc(void)
#endif
/* Change flash's physical address */
- ifc_out32((ifc_regs-cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
- ifc_out32((ifc_regs-csor_cs[0].csor), CONFIG_SYS_CSOR0);
- ifc_out32((ifc_regs-amask_cs[0].amask), CONFIG_SYS_AMASK0);
+ ifc_out32((ifc_regs.gregs-cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+ ifc_out32((ifc_regs.gregs-csor_cs[0].csor), CONFIG_SYS_CSOR0);
+ ifc_out32((ifc_regs.gregs-amask_cs[0].amask), CONFIG_SYS_AMASK0);
return ;
}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e24b857..321ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
- struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
@@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_FSL_IFC)
- ccr = ifc_in32(ifc_regs-ifc_ccr);
+ ccr = ifc_in32(ifc_regs.gregs-ifc_ccr);
[U-Boot] [PATCH 21/28] drivers/fsl-mc: Autoload AOIP image from NOR flash
From: J. German Rivera german.riv...@freescale.com
Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Change-Id: I19e23d983e7f947a4398e0421600057e0d7be6a3
[York Sun: This is a debug commit. Will drop once AIOP is loaded by Linux]
---
drivers/net/fsl-mc/mc.c | 24
include/configs/ls2085a_common.h |2 ++
include/configs/ls2085aqds.h |3 +++
include/configs/ls2085ardb.h |3 +++
4 files changed, 32 insertions(+)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c5c44bc..e6f6d55 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -298,6 +298,24 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
return 0;
}
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+{
+ void *aiop_img;
+
+ /*
+* Load the MC AIOP image in the MC private DRAM block:
+*/
+
+ aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+ mc_copy_image(MC AIOP image,
+ (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+ mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+
+ return 0;
+}
+#endif
+
/**
* Return the MC boot timeout value in milliseconds
*/
@@ -454,6 +472,12 @@ int mc_init(void)
if (error != 0)
goto out;
+#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+ error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
+ if (error != 0)
+ goto out;
+#endif
+
debug(mc_ccsr_regs %p\n, mc_ccsr_regs);
dump_mc_ccsr_regs(mc_ccsr_regs);
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 95a5e56..3fee92a 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -164,6 +164,8 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET0x00F0
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH0x2
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET0x00F2
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x20
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x1f80
/* Carve out a DDR region which will not be used by u-boot/Linux */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 70162e7..961e4dd 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -218,6 +218,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x58080ULL
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
+
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 5f7ea7b..24400e4 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -201,6 +201,9 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x58080ULL
+#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
+#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x58090ULL
+
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
--
1.7.9.5
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[U-Boot] [PATCH 22/28] board/ls2085qds: Add support ethernet
From: Prabhakar Kushwaha prabha...@freescale.com
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link type
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Change-Id: I6d79a9633f3e31b3c23c839b9e9660ee59f0cc0c
---
board/freescale/ls2085aqds/Makefile |1 +
board/freescale/ls2085aqds/eth.c | 380 +
board/freescale/ls2085aqds/ls2085aqds.c | 13 -
board/freescale/ls2085aqds/ls2085aqds_qixis.h |4 +
drivers/net/ldpaa_eth/Makefile|1 +
drivers/net/ldpaa_eth/ls2085a.c | 83 ++
include/configs/ls2085aqds.h | 19 ++
7 files changed, 488 insertions(+), 13 deletions(-)
create mode 100644 board/freescale/ls2085aqds/eth.c
create mode 100644 drivers/net/ldpaa_eth/ls2085a.c
diff --git a/board/freescale/ls2085aqds/Makefile
b/board/freescale/ls2085aqds/Makefile
index f174f33..da69a7d 100644
--- a/board/freescale/ls2085aqds/Makefile
+++ b/board/freescale/ls2085aqds/Makefile
@@ -6,3 +6,4 @@
obj-y += ls2085aqds.o
obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
new file mode 100644
index 000..5ba4770
--- /dev/null
+++ b/board/freescale/ls2085aqds/eth.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include netdev.h
+#include asm/io.h
+#include asm/arch/fsl_serdes.h
+#include asm/arch-fsl-lsch3/immap_lsch3.h
+#include fsl_mdio.h
+#include malloc.h
+#include fm_eth.h
+#include fsl-mc/ldpaa_wriop.h
+
+#include ../common/qixis.h
+
+#include ls2085aqds_qixis.h
+
+
+#ifdef CONFIG_FSL_MC_ENET
+ /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 - Lanes A, B, C, D, E, F, G, H
+ * Bank 2 - Lanes A,B, C, D, E, F, G, H
+ */
+
+ /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+
+static u8 lane_to_slot_fsm2[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+ SGMII_CARD_PORT1_PHY_ADDR,
+ SGMII_CARD_PORT2_PHY_ADDR,
+ SGMII_CARD_PORT3_PHY_ADDR,
+ SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0x
+#define EMI1_SLOT1 0
+#define EMI1_SLOT2 1
+#define EMI1_SLOT3 2
+#define EMI1_SLOT4 3
+#define EMI1_SLOT5 4
+#define EMI1_SLOT6 5
+#define EMI2 6
+#define SFP_TX 1
+
+static const char * const mdio_names[] = {
+ LS2085A_QDS_MDIO0,
+ LS2085A_QDS_MDIO1,
+ LS2085A_QDS_MDIO2,
+ LS2085A_QDS_MDIO3,
+ LS2085A_QDS_MDIO4,
+ LS2085A_QDS_MDIO5,
+ DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls2085a_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf(No bus for muxval %x\n, muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf(No bus by name %s\n, name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+{
+ u8 brdcfg9;
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ brdcfg9 = ~BRDCFG9_SFPTX_MASK;
+ brdcfg9 |= (muxval BRDCFG9_SFPTX_SHIFT);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls2085a_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval = 5) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 = ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+int devad, int regnum)
+{
+ struct ls2085a_qds_mdio *priv = bus-priv;
+
+ ls2085a_qds_mux_mdio(priv-muxval);
+
+ return priv-realbus-read(priv-realbus, addr, devad, regnum);
+}
+
+static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls2085a_qds_mdio *priv = bus-priv;
+
+ ls2085a_qds_mux_mdio(priv-muxval);
+
+ return priv-realbus-write(priv-realbus, addr, devad, regnum, value);
+}
+
+static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls2085a_qds_mdio *priv = bus-priv;
+
+ return
[U-Boot] [PATCH 28/28] armv8/fsl-lsch3: Implement workaround for I2C issue
This erratum requires setting GLITCH_EN bit in debug register.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index ca00108..4d9df20 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -37,11 +37,41 @@ static void erratum_rcw_src(void)
#endif
}
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+static void erratum_i2c(void)
+{
+ u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+ ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+ writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
void fsl_lsch3_early_init_f(void)
{
erratum_a008751();
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
+ erratum_i2c();
}
#ifdef CONFIG_SPL_BUILD
--
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[U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2080ARDB is a evaluation platform that supports LS2080A
family SoCs. This patch add sbasic support for the platform.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Change-Id: I7744b17f074488989de998ab7d487c437cc8eedf
---
arch/arm/Kconfig | 11 +++
arch/arm/cpu/armv8/fsl-lsch3/README|4 +-
board/freescale/{ls2085aqds = ls2085ardb}/Kconfig |6 +-
board/freescale/ls2085ardb/MAINTAINERS |7 ++
.../freescale/{ls2085aqds = ls2085ardb}/Makefile |2 +-
board/freescale/{ls2085aqds = ls2085ardb}/README | 46
board/freescale/{ls2085aqds = ls2085ardb}/ddr.c |0
board/freescale/{ls2085aqds = ls2085ardb}/ddr.h |6 +-
.../ls2085aqds.c = ls2085ardb/ls2085ardb.c} | 54 +++
.../ls2085ardb_qixis.h}| 12 +---
...qds_ddr4_nor_defconfig = ls2085ardb_defconfig} |2 +-
include/configs/{ls2085aqds.h = ls2085ardb.h} | 73
12 files changed, 80 insertions(+), 143 deletions(-)
copy board/freescale/{ls2085aqds = ls2085ardb}/Kconfig (66%)
create mode 100644 board/freescale/ls2085ardb/MAINTAINERS
copy board/freescale/{ls2085aqds = ls2085ardb}/Makefile (81%)
copy board/freescale/{ls2085aqds = ls2085ardb}/README (73%)
copy board/freescale/{ls2085aqds = ls2085ardb}/ddr.c (100%)
copy board/freescale/{ls2085aqds = ls2085ardb}/ddr.h (93%)
copy board/freescale/{ls2085aqds/ls2085aqds.c = ls2085ardb/ls2085ardb.c} (76%)
copy board/freescale/{ls2085aqds/ls2085aqds_qixis.h =
ls2085ardb/ls2085ardb_qixis.h} (61%)
copy configs/{ls1021aqds_ddr4_nor_defconfig = ls2085ardb_defconfig} (66%)
copy include/configs/{ls2085aqds.h = ls2085ardb.h} (80%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4a7851..7478eb4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
+config TARGET_LS2085ARDB
+ bool Support ls2085ardb
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2085ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2085A
+ LayerScape Architecture processor.
+
config TARGET_LS1021AQDS
bool Support ls1021aqds
select CPU_V7
@@ -804,6 +814,7 @@ source board/embest/mx6boards/Kconfig
source board/esg/ima3-mx53/Kconfig
source board/freescale/ls2085a/Kconfig
source board/freescale/ls2085aqds/Kconfig
+source board/freescale/ls2085ardb/Kconfig
source board/freescale/ls1021aqds/Kconfig
source board/freescale/ls1021atwr/Kconfig
source board/freescale/mx23evk/Kconfig
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index 817ea1b..4f36e2a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -38,7 +38,7 @@ Flash Layout
32-MB NOR flash layout for pre-silicon platforms (simulator and
emulator)
(2) A typical layout of various images (including Linux and other firmware
images)
-is shown below considering a 128MB NOR flash device present on QDS
+is shown below considering a 128MB NOR flash device present on QDS and RDB
boards:
- 0x5_8800_ ---
| .. Unused .. (7M) | |
@@ -86,7 +86,7 @@ Flash Layout
| RCW and PBI (1M)| |
- 0x5_8000_ ---
- 128-MB NOR flash layout for QDS board
+ 128-MB NOR flash layout for QDS and RDB boards
Environment Variables
=
diff --git a/board/freescale/ls2085aqds/Kconfig
b/board/freescale/ls2085ardb/Kconfig
similarity index 66%
copy from board/freescale/ls2085aqds/Kconfig
copy to board/freescale/ls2085ardb/Kconfig
index deb640d..85a3dcd 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2085ardb/Kconfig
@@ -1,8 +1,8 @@
-if TARGET_LS2085AQDS
+if TARGET_LS2085ARDB
config SYS_BOARD
- default ls2085aqds
+ default ls2085ardb
config SYS_VENDOR
default freescale
@@ -11,6 +11,6 @@ config SYS_SOC
default fsl-lsch3
config SYS_CONFIG_NAME
- default ls2085aqds
+ default ls2085ardb
endif
diff --git a/board/freescale/ls2085ardb/MAINTAINERS
b/board/freescale/ls2085ardb/MAINTAINERS
new file mode 100644
index 000..436039f
--- /dev/null
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M: Prabhakar Kushwaha prabha...@freescale.com
+S: Maintained
+F: board/freescale/ls2085ardb/
+F:
[U-Boot] [PATCH 25/28] freescale/qixis: Add support for booting from NAND
From: Scott Wood scottw...@freescale.com
Use qixis_reset nand to reset the board to boot from NAND.
Signed-off-by: Scott Wood scottw...@freescale.com
---
board/freescale/common/qixis.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index a49e300..9f6b0e7 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -138,24 +138,23 @@ void qixis_bank_reset(void)
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
-/* Set the boot bank to the power-on default bank */
-void clear_altbank(void)
+static void __maybe_unused set_lbmap(int lbmap)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
- reg = (reg ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
+ reg = (reg ~QIXIS_LBMAP_MASK) | lbmap;
QIXIS_WRITE(brdcfg[0], reg);
}
-/* Set the boot bank to the alternate bank */
-void set_altbank(void)
+static void __maybe_unused set_rcw_src(int rcw_src)
{
u8 reg;
- reg = QIXIS_READ(brdcfg[0]);
- reg = (reg ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
- QIXIS_WRITE(brdcfg[0], reg);
+ reg = QIXIS_READ(dutcfg[1]);
+ reg = (reg ~1) | (rcw_src 1);
+ QIXIS_WRITE(dutcfg[1], reg);
+ QIXIS_WRITE(dutcfg[0], (rcw_src 1) 0xff);
}
static void qixis_dump_regs(void)
@@ -201,11 +200,22 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
int i;
if (argc = 1) {
- clear_altbank();
+ set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], altbank) == 0) {
- set_altbank();
+ set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
+ } else if (strcmp(argv[1], nand) == 0) {
+#ifdef QIXIS_LBMAP_NAND
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_NAND);
+ set_rcw_src(QIXIS_RCW_SRC_NAND);
+ QIXIS_WRITE(rcfg_ctl, 0x20);
+ QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+ printf(Not implemented\n);
+#endif
} else if (strcmp(argv[1], watchdog) == 0) {
static char *period[9] = {2s, 4s, 8s, 16s, 32s,
1min, 2min, 4min, 8min};
@@ -244,6 +254,7 @@ U_BOOT_CMD(
Reset the board using the FPGA sequencer,
- hard reset to default bank\n
qixis_reset altbank - reset to alternate bank\n
+ qixis_reset nand - reset to nand\n
qixis watchdog watchdog_period - set the watchdog period\n
period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n
qixis_reset dump - display the QIXIS registers\n
--
1.7.9.5
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