Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable
Hi Bin Bin Meng 於 2019年4月23日 週二 下午8:19寫道： > > On Tue, Apr 23, 2019 at 8:14 PM Bin Meng wrote: > > > > Hi Rick, > > > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > > > From: Rick Chen > > > > > > > typo in the commit title: seletable -> selectable OK > > > > > In smp flow this two features only can be enabled when U-Boot > > > > this->these OK > > > > > boot from ram. It shall be disabled when U-Boot boot from flash. > > > > boot->boots OK > > > > > > > > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select > > BTW: is it possible to use a single option for such feature, like > CONFIG_XIP? Basically these two options are used for the same reason. Yes. This is my initial idea. But I worry the connection seem a little weak. But if you say so, I will do it as you say. Thanks Rick > > > > this two features. Their default value will say YES for booting > > > > this->these > > > > > from ram. > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable
On Tue, Apr 23, 2019 at 8:14 PM Bin Meng wrote: > > Hi Rick, > > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote: > > > > From: Rick Chen > > > > typo in the commit title: seletable -> selectable > > > In smp flow this two features only can be enabled when U-Boot > > this->these > > > boot from ram. It shall be disabled when U-Boot boot from flash. > > boot->boots > > > > > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select BTW: is it possible to use a single option for such feature, like CONFIG_XIP? Basically these two options are used for the same reason. > > this two features. Their default value will say YES for booting > > this->these > > > from ram. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable
Hi Rick,
On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
>
> From: Rick Chen
>
typo in the commit title: seletable -> selectable
> In smp flow this two features only can be enabled when U-Boot
this->these
> boot from ram. It shall be disabled when U-Boot boot from flash.
boot->boots
>
> Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
> this two features. Their default value will say YES for booting
this->these
> from ram.
>
> AE350 will encounter the the write failure problem since
> hart_lottery and available_harts_lock was not in ram address
was->is
> but in flash address when booing from flash.
booing->booting
>
> This patch can help to fix the failure problem when AE350 was
was->is
> booting from flash by disable this two features.
disable->disabling
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> arch/riscv/Kconfig | 21 +
> arch/riscv/cpu/cpu.c | 4
> arch/riscv/cpu/start.S | 9 -
> arch/riscv/include/asm/global_data.h | 2 ++
> arch/riscv/lib/asm-offsets.c | 2 ++
> arch/riscv/lib/smp.c | 2 ++
> 6 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ae8ff7b..4354396 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -162,6 +162,27 @@ config SBI_IPI
> default y if RISCV_SMODE
> depends on SMP
>
> +config HART_LOTTERY
> + bool "Hart lottery support"
nits: I would use "hart"
> + default y
> + depends on SMP
> + help
> + This will upport hart lottery, all harts have changce to become
upport->support, changce->chance
> + main hart. But if you say N here, hart 0 will be the main hart.
> + It only can be enabled when U-Boot boot from ram, but shall be
boot->boots
> + disabled when boot from flash.
boot->booting
> +
> +config AVAILABLE_HARTS
> + bool "available harts support"
> + default y
> + depends on SMP
> + depends on HART_LOTTERY
> + help
> + This will help to record active harts and compare with dts' cpus.
> + So it will not send ipi to in-active harts.
in-active->inactive
> + It only can be enabled when U-Boot boot from ram, but shall be
boot->boots
> + disabled when boot from flash.
boot->booting
> +
> config STACK_SIZE_SHIFT
> int
> default 13
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c32de8a..0add783 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -16,13 +16,17 @@
> * before the bss section is available.
> */
> phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
> +#ifdef CONFIG_HART_LOTTERY
> u32 hart_lottery __attribute__((section(".data"))) = 0;
> +#endif
>
> +#ifdef CONFIG_AVAILABLE_HARTS
> /*
> * The main hart running U-Boot has acquired available_harts_lock until it
> has
> * finished initialization of global data.
> */
> u32 available_harts_lock = 1;
> +#endif
>
> static inline bool supports_extension(char ext)
> {
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index a4433fb..d030d4a 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -98,6 +98,7 @@ call_board_init_f_0:
> mv sp, a0
> #endif
>
> +#ifdef CONFIG_HART_LOTTERY
> /*
> * Pick hart to initialize global data and run U-Boot. The other harts
> * wait for initialization to complete.
> @@ -106,6 +107,9 @@ call_board_init_f_0:
> li s2, 1
> amoswap.w s2, t1, 0(t0)
> bnezs2, wait_for_gd_init
> +#else
> + bneztp, secondary_hart_loop
> +#endif
>
> la t0, prior_stage_fdt_address
> SREGs1, 0(t0)
> @@ -115,6 +119,7 @@ call_board_init_f_0:
> /* save the boot hart id to global_data */
> SREGtp, GD_BOOT_HART(gp)
>
> +#ifdef CONFIG_AVAILABLE_HARTS
> la t0, available_harts_lock
> fence rw, w
> amoswap.w zero, zero, 0(t0)
> @@ -135,13 +140,15 @@ wait_for_gd_init:
>
> fence rw, w
> amoswap.w zero, zero, 0(t0)
> +#endif
>
> +#ifdef CONFIG_HART_LOTTERY
> /*
> * Continue on hart lottery winner, others branch to
> * secondary_hart_loop.
> */
> bnezs2, secondary_hart_loop
> -
This blank line should not be deleted.
> +#endif
> /* Enable cache */
> jal icache_enable
> jal dcache_enable
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index dffcd45..e2e8b65 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -27,7 +27,9 @@ struct arch_global_data {
> #ifdef CONFIG_SMP
> struct ipi_data ipi[CONFIG_NR_CPUS];
> #endif
> +#ifdef CONFIG_AVAILABLE_HARTS
> ulong available_harts;
> +#endif
> };
[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable
From: Rick Chen
In smp flow this two features only can be enabled when U-Boot
boot from ram. It shall be disabled when U-Boot boot from flash.
Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
this two features. Their default value will say YES for booting
from ram.
AE350 will encounter the the write failure problem since
hart_lottery and available_harts_lock was not in ram address
but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.
Signed-off-by: Rick Chen
Cc: Greentime Hu
---
arch/riscv/Kconfig | 21 +
arch/riscv/cpu/cpu.c | 4
arch/riscv/cpu/start.S | 9 -
arch/riscv/include/asm/global_data.h | 2 ++
arch/riscv/lib/asm-offsets.c | 2 ++
arch/riscv/lib/smp.c | 2 ++
6 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..4354396 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,27 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
+config HART_LOTTERY
+ bool "Hart lottery support"
+ default y
+ depends on SMP
+ help
+ This will upport hart lottery, all harts have changce to become
+ main hart. But if you say N here, hart 0 will be the main hart.
+ It only can be enabled when U-Boot boot from ram, but shall be
+ disabled when boot from flash.
+
+config AVAILABLE_HARTS
+ bool "available harts support"
+ default y
+ depends on SMP
+ depends on HART_LOTTERY
+ help
+ This will help to record active harts and compare with dts' cpus.
+ So it will not send ipi to in-active harts.
+ It only can be enabled when U-Boot boot from ram, but shall be
+ disabled when boot from flash.
+
config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0add783 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,13 +16,17 @@
* before the bss section is available.
*/
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifdef CONFIG_HART_LOTTERY
u32 hart_lottery __attribute__((section(".data"))) = 0;
+#endif
+#ifdef CONFIG_AVAILABLE_HARTS
/*
* The main hart running U-Boot has acquired available_harts_lock until it has
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
+#endif
static inline bool supports_extension(char ext)
{
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..d030d4a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv sp, a0
#endif
+#ifdef CONFIG_HART_LOTTERY
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+ bneztp, secondary_hart_loop
+#endif
la t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
+#ifdef CONFIG_AVAILABLE_HARTS
la t0, available_harts_lock
fence rw, w
amoswap.w zero, zero, 0(t0)
@@ -135,13 +140,15 @@ wait_for_gd_init:
fence rw, w
amoswap.w zero, zero, 0(t0)
+#endif
+#ifdef CONFIG_HART_LOTTERY
/*
* Continue on hart lottery winner, others branch to
* secondary_hart_loop.
*/
bnezs2, secondary_hart_loop
-
+#endif
/* Enable cache */
jal icache_enable
jal dcache_enable
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index dffcd45..e2e8b65 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
+#ifdef CONFIG_AVAILABLE_HARTS
ulong available_harts;
+#endif
};
#include
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..3ebda97 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifdef CONFIG_AVAILABLE_HARTS
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
return 0;
}
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..4de7ea2 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
