@@ -1612,6 +1613,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN: -o - | FileCheck
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/80409
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https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/80409
According to the C++ standard, `dynamic_cast` of pointers either returns a
pointer (7.6.1.7) or results in undefined behavior (11.9.5). This patch marks
`__dynamic_cast` as `willreturn` to remove unused calls.
dtcxzyw wrote:
> I guess Zaamo + Zacas is technically a way one could implement atomics
> without LR/SC?
The Zacas extension depends upon the A extension.
https://github.com/llvm/llvm-project/pull/77424
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dtcxzyw wrote:
Ping?
https://github.com/llvm/llvm-project/pull/68882
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@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 |
FileCheck %s
dtcxzyw wrote:
Can we split `rv32a-invalid.s` into two files? I think it is better than
duplicating tests for new extensions.
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/76338
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68485
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dtcxzyw wrote:
> Can you please fix or revert
> https://lab.llvm.org/buildbot/#/builders/74/builds/24592 ?
Should be fixed by
https://github.com/llvm/llvm-project/commit/7e405eb722e40c79b7726201d0f76b5dab34ba0f.
https://lab.llvm.org/buildbot/#/builders/74/builds/24613
dtcxzyw wrote:
> > Yeah, we should skip this inference for functions with the sanitize_memory
> > attribute.
>
> I will post a patch later.
Candidate patch: https://github.com/llvm/llvm-project/pull/76691
https://github.com/llvm/llvm-project/pull/76553
dtcxzyw wrote:
> Yeah, we should skip this inference for functions with the sanitize_memory
> attribute.
I will post a patch later.
https://github.com/llvm/llvm-project/pull/76553
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dtcxzyw wrote:
> Can you please fix or revert
> https://lab.llvm.org/buildbot/#/builders/74/builds/24592 ?
Thank you for reporting this! I will check the error log.
https://github.com/llvm/llvm-project/pull/76553
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https://github.com/llvm/llvm-project/pull/76553
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https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
dtcxzyw wrote:
> Failed Tests (3):
LLVM :: CodeGen/BPF/loop-exit-cond.ll
LLVM :: CodeGen/NVPTX/nvvm-reflect-opaque.ll
LLVM :: CodeGen/NVPTX/nvvm-reflect.ll
https://github.com/llvm/llvm-project/pull/76553
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dtcxzyw wrote:
> There are lld test failures.
Done.
https://github.com/llvm/llvm-project/pull/76553
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https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
@@ -0,0 +1,112 @@
+// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck
-check-prefix=RVI20U32 %s
+// RVI20U32: "-target-cpu" "generic-rv32"
+// RVI20U32: "-target-feature" "-a"
+// RVI20U32: "-target-feature" "-c"
+// RVI20U32: "-target-feature" "-d"
+// RVI20U32:
@@ -206,6 +210,17 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
};
+static const RISCVProfile SupportedProfiles[] = {
+{"rvi20u32", "rv32i"},
dtcxzyw wrote:
Profile names
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76553
This patch deduces `noundef` attributes for return values.
IIUC, a function returns `noundef` values iff all of its return values are
guaranteed not to be `undef` or `poison`.
Definition of `noundef` from
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/76372
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dtcxzyw wrote:
> There is a failing clang test.
Fixed.
https://github.com/llvm/llvm-project/pull/76372
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https://github.com/llvm/llvm-project/pull/76372
>From 5ceb22715cdcfc52b77b451110295ea083c09327 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 26 Dec 2023 05:10:06 +0800
Subject: [PATCH] [FuncAttrs] Infer `norecurse` for funcs with calls to
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76338
>From a646e872e72bab7b143db7496adfeb633b882dc4 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 25 Dec 2023 01:39:27 +0800
Subject: [PATCH] Revert "InstCombine: Fold is.fpclass(x, fcInf) to fabs+fcmp"
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/76289
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https://github.com/llvm/llvm-project/pull/76256
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https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76289
This patch adds support for `__riscv_clmulr_32/64` in `riscv_bitmanip.h`.
It also fixes the extension requirements of `clmul/clmulh`.
Thank @Liaoshihua for reporting this!
>From
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76286
This patch replaces `__builtin_riscv_cpop_32/64` with `__builtin_popcount(ll)`
because `__builtin_riscv_cpop_32/64` is not implemented in clang.
Thank @Liaoshihua for reporting this!
It is an alternative to
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76256
This patch adds support for `__builtin_riscv_cpop_32/64`, which are used by
`riscv_bitmanip.h`.
See also
dtcxzyw wrote:
> arrayidx
We should teach `foldCmpLoadFromIndexedGlobal` to handle constant GEPs with i8
source element type.
https://github.com/llvm/llvm-project/pull/68882
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dtcxzyw wrote:
> @nikic Could you please have a look at
> [dtcxzyw/llvm-opt-benchmark#17](https://github.com/dtcxzyw/llvm-opt-benchmark/pull/17)?
> One regression:
>
> ```
> diff --git a/bench/brotli/optimized/compound_dictionary.c.ll
> b/bench/brotli/optimized/compound_dictionary.c.ll
>
dtcxzyw wrote:
An unique regression:
```
diff --git a/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll
b/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll
index 534c0a07..85a097fc 100644
--- a/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll
+++
dtcxzyw wrote:
> @dtcxzyw GitHub can't display the diff, and struggles to clone the repo. Can
> you share the diffs for just the mentioned files?
I have posted the diff between optimized IRs.
https://github.com/llvm/llvm-project/pull/68882
___
dtcxzyw wrote:
Another example:
```
diff --git a/bench/hermes/optimized/Sorting.cpp.ll
b/bench/hermes/optimized/Sorting.cpp.ll
index 1a808c47..e03089ca 100644
--- a/bench/hermes/optimized/Sorting.cpp.ll
+++ b/bench/hermes/optimized/Sorting.cpp.ll
@@ -41,20 +41,22 @@ if.end:
dtcxzyw wrote:
@nikic Could you please have a look at
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/17?
One regression:
```
diff --git a/bench/brotli/optimized/compound_dictionary.c.ll
b/bench/brotli/optimized/compound_dictionary.c.ll
index 21fd37fd..b9894810 100644
---
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68485
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dtcxzyw wrote:
I guess you should split it into patch series.
+ [ ] MC support (and docs)
+ [ ] Sched support
+ [ ] ISel support
+ [ ] Builtin intrinsic support in clang
https://github.com/llvm/llvm-project/pull/74824
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https://github.com/dtcxzyw approved this pull request.
The regression in `Shootout-C++-ary2` may be caused by ThinLTO. But I think it
is OK to go ahead and merge :)
https://github.com/llvm/llvm-project/pull/73662
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dtcxzyw wrote:
Looks like the regression in `DILATE` has been addressed.
Could you please have a look at
`MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode`?
https://github.com/llvm/llvm-project/pull/73662
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dtcxzyw wrote:
Could you please rebase this patch on
https://github.com/llvm/llvm-project/pull/74246 and add a test for
https://github.com/llvm/llvm-project/issues/74242?
https://github.com/llvm/llvm-project/pull/73662
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dtcxzyw wrote:
My CI detected some significant regressions caused by this patch:
https://github.com/dtcxzyw/llvm-ci/pull/839#issuecomment-1836976355
https://github.com/llvm/llvm-project/pull/73662
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https://github.com/dtcxzyw approved this pull request.
The implementation looks good to me. Waiting for the result of my CI.
https://github.com/dtcxzyw/llvm-ci/actions/runs/7066692655
@goldsteinn Any comments?
https://github.com/llvm/llvm-project/pull/73662
@@ -75,7 +75,8 @@ define void @idom_sign_bit_check_edge_dominates_select(i64
%a, i64 %b) {
; CHECK: land.lhs.true:
; CHECK-NEXT:br label [[LOR_END:%.*]]
; CHECK: lor.rhs:
-; CHECK-NEXT:[[CMP3_NOT:%.*]] = icmp eq i64 [[A]], [[B:%.*]]
+; CHECK-NEXT:
@@ -0,0 +1,74 @@
+//===- DomConditionCache.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -2840,6 +2841,46 @@ static Instruction *matchFunnelShift(Instruction ,
InstCombinerImpl ) {
return nullptr;
FShiftArgs = {ShVal0, ShVal1, ShAmt};
+ } else if (isa(Or0) || isa(Or1)) {
+// If there are two 'or' instructions concat variables in opposite order,
https://github.com/dtcxzyw closed
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https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
Do you have the access to merge PR?
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
My command: `bin/opt -S -O3 -print-changed min_max.ll`
Then I got IR after the SROA pass :)
https://github.com/llvm/llvm-project/pull/70845
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https://github.com/dtcxzyw commented:
LGTM
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,111 @@
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
+;; short vecreduce_smin_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i <
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@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
dtcxzyw wrote:
> Oh nice, I'm running into something similar in #71657. Are all these dead
> ADDIs coming from the backwards local postpass?
Yes. I believe this PR can address the issue.
https://github.com/llvm/llvm-project/pull/65934
___
@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
```
define i16 @vecreduce_smin_v2i16(i32 %n, ptr %v) {
entry:
br label %for.cond
for.cond:
%p.0 = phi i16 [ 0, %entry ], [ %conv8, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc,
https://github.com/dtcxzyw requested changes to this pull request.
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
```suggestion
; RUN: opt < %s -O3 -S | FileCheck %s
```
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
Could you please:
1. Convert this IR into SSA form as @nikic mentioned.
2. Drop unused attributes.
3. Re-generate tests with `llvm/utils/update_test_checks.py`.
https://github.com/dtcxzyw edited
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dtcxzyw wrote:
Reduced test case: https://godbolt.org/z/d4ETPhbno
https://github.com/llvm/llvm-project/pull/71534
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@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: define
https://github.com/dtcxzyw requested changes to this pull request.
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@@ -0,0 +1,126 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
+
+define signext i16 @vecreduce_smax_v2i16(i32 noundef %0, ptr noundef %1) #0 {
dtcxzyw wrote:
Could you please reduce the test case and move it into `InstCombine`?
https://github.com/dtcxzyw edited
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@@ -5587,11 +5587,20 @@ Instruction
*InstCombinerImpl::foldICmpWithZextOrSext(ICmpInst ) {
return new ICmpInst(ICmp.getPredicate(), Builder.CreateOr(X, Y),
Constant::getNullValue(X->getType()));
+ // Treat "zext nneg" as "sext"
+
https://github.com/dtcxzyw approved this pull request.
LGTM. Thanks!
We can improve the compile time by adding `nneg` flag during the zext creation
(e.g., `cttz(zext(x)) -> zext nneg(cttz(x))`).
https://github.com/llvm/llvm-project/pull/71534
___
dtcxzyw wrote:
Please also update existing uses in `lldb`.
Buildbot failure: https://lab.llvm.org/buildbot/#/builders/68/builds/63101
https://github.com/llvm/llvm-project/pull/71029
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https://github.com/llvm/llvm-project/pull/70294
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From 1222b8bda348af58f4921a45d8cddca726875bb9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
Ping. @preames Any more comments?
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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dtcxzyw wrote:
Rebased on top of #70241.
https://github.com/llvm/llvm-project/pull/70232
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70232
>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu
Co-authored-by:
dtcxzyw wrote:
Any more questions about XiangShan? If there is no question, I will merge this
PR tomorrow.
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
You can find the full implementation of `zicbom` and `zicboz` here:
https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25.
cc @poemonsense
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
> Can you separate out the basic processor definition (using NoSchedModel), and
> a patch which adds the scheduling model? We can at least get the processor
> definition landed while we iterate on the scheduling related pieces.
>
> edit: For clarity, I'm requesting that the
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70232
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan processor
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/69252
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 6e34e74e8e8046aaa086869e8a8aecb781dd3b3b Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67917
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@@ -6411,6 +6411,41 @@ static Value *simplifyBinaryIntrinsic(Function *F, Value
*Op0, Value *Op1,
return Constant::getNullValue(ReturnType);
break;
}
+ case Intrinsic::ptrmask: {
+if (isa(Op0) || isa(Op1))
+ return PoisonValue::get(Op0->getType());
+
+
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/69252
This patch handles formatting of real and imaginary parts of complex lvalue.
Fixes #69218.
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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Author: Yingwei Zheng
Date: 2023-10-13T15:19:35+08:00
New Revision: 411ceacf4351bd3af9db75b859063864b19e71e1
URL:
https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1
DIFF:
https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1.diff
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/67915
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dtcxzyw wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/65934
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dtcxzyw wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/65934
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