camel-cdr wrote:
Ah, thanks, that works.
How can support for behavior be detected?
The intrinsic spec says:
> The `__riscv_v_intrinsic` macro is the C macro to test the compiler's support
> for the RISC-V "V" extension intrinsics.
and recommends using:
```c
#ifdef __riscv_v_intrinsic
#include
camel-cdr wrote:
FYI, the example code you shown doesn't compile anymore:
https://godbolt.org/z/ooTWEGejf
This feature is quite important, without it we can't compile in RVV by default
in a lot of libraries, e.g. simdutf, flac, ...
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/llvm/llvm-project/pull/90392
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@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*-
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See
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camel-cdr wrote:
The execution unit layout does not match the current XiangShan master. Has the
final execution unit layout been decided on?
[earlier
camel-cdr wrote:
Has the target architecture been finalized? (As in what it should be, not
necessarily the rtl)
Just yesterday, there was a significant change in vector execution units:
