[clang] [clang] Default to -fno-sized-deallocation for AIX (PR #97076)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/97076 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/97383 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [NFC][RISCV] Simplify the dynamic linker construction logic (PR #97383)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/97383 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

@@ -306,7 +306,7 @@ // RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s // RV32-XSEP: error: invalid arch name 'rv32ixabc_', -// RV32-XSEP: extension name missing after separator '_' +// R

[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/97506 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/97799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/97799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental for bf16 extensions (PR #97996)

@@ -271,7 +271,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zalasr`` LLVM implements the `0.0.5 draft specification `__. -``experimental-zfbfmin``, ``experimental-zvfbfmin``

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

wangpc-pp wrote: > @JinjinLi868 are you still working on this? I can ask him. Is this PR blocking some of your works on float16/bf16? https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

wangpc-pp wrote: > What's the status of backend support for the large code model? That would > presumably be a prerequisite to landing this. It was just merged: https://github.com/llvm/llvm-project/pull/70308. https://github.com/llvm/llvm-project/pull/107817 ___

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/103709 These two extensions add addtional instructions for carryless multiplication with 32-bits elements and Vector-Scalar GCM instructions. Please see https://github.com/riscv/riscv-isa-manual/pull/1306. >From 0b

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `1.0 release specification `__. +``experimental

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/102155 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -754,6 +754,17 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e +: RISCVExperimentalExtensio

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/103709 >From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Wed, 14 Aug 2024 15:14:36 +0800 Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and

[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/87966 Remove them from experimental. See also: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc >From 5b312a80cdc3396e3e35d906176f56349392d437 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date:

[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/87966 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args, options::OPT_fno_relaxed_template_template_args); - // -fsized-deallocation is off by default,

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/83774 >From 1e556e00e59377c76c168293d6c2678f7a874742 Mon Sep 17 00:00:00 2001 From: wangpc Date: Fri, 14 Jul 2023 10:38:14 +0800 Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14 onwards Si

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: htt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH 1/2] [RISCV] Add B extension It seems that we have `B` extension again:

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From 169ef33f585b964d9af7a7628919271245f318fc Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH 1/3] [RISCV] Add B extension It seems that we have `B` extension again:

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

@@ -704,6 +705,12 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s // CHECK-ZACAS-EXT: __riscv_zacas 100{{$}} +// RUN: %clang --target=riscv32 -march=rv32izama16b -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

wangpc-pp wrote: > Filed https://gitlab.kitware.com/cmake/cmake/-/issues/26031 So this is a cmake bug, not clang's, right? https://github.com/llvm/llvm-project/pull/90373 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

wangpc-pp wrote: Spacemit K1 is the name of the product/SoC or whatever you call it. The processor definitions in the RISCV backend are focusing on the CPU core. For Spacemit K1, its name should be `X60`? I don't know…… https://github.com/llvm/llvm-project/pull/94564 ___

[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

@@ -381,3 +381,14 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/94578 `riscv_atomics.h` contains all builtins for atomics. >From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 6 Jun 2024 13:48:34 +0800 Subject: [PATCH] =?UTF-8?

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp converted_to_draft https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/94578 >From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 6 Jun 2024 13:48:34 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp ready_for_review https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp unassigned https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp unassigned https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomics.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/94578 >From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 6 Jun 2024 13:48:34 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/94578 >From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 6 Jun 2024 13:48:34 +0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

wangpc-pp wrote: The description needs to be revised. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

wangpc-pp wrote: > lr/sc builtins are extremely fragile: there's no reasonable way for the > compiler to guarantee that the sc is placed in such a way that it will > eventually succeed. I think the user should have enough knowledges about lr/sc to make the logic reasonable. If we don't provid

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

wangpc-pp wrote: If we are talking about the necessariness of adding these intrinsics, please refer to the ARM implementations in DPDK (https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h).We want to use https://github.com/llvm/llvm-p

[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

@@ -86,8 +86,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, // and other features (ex. mirco architecture feature) from mcpu if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { StringRef CPU = A->getValue(); -if (CPU == "nat

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From 9ab05b9f68def57e9abb9d5ac65293b84aacc95a Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: htt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94313 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/94313 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/95953 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

@@ -358,3 +358,21 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-sc

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

@@ -358,3 +358,21 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-sc

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/wangpc-pp approved this pull request. LGTM with nits. https://github.com/llvm/llvm-project/pull/95953 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/95953 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/96283 `riscv_atomic.h` contains all builtins for atomics. Currently, we suppoprt builtins for Zawrs extension. Doc: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/79 >From 4b597ebf69de59d62e5587a27cedf2b12e

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From a780efe3e297fe59c5521ea5387dda12905a4423 Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: htt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

wangpc-pp wrote: Ping. The B extension has been ratified and I hava rebased this PR. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add B extension (PR #76893)

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() { } static constexpr StringLiteral CombineIntoExts[] = { -{"zk"},{"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"}, -{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"}, +{"b"}, {"zk"},{"zkn"}, {"zks"}, {"zvkn

[clang] [llvm] [RISCV] Add Smcsrind and Sscsrind extension (PR #93952)

wangpc-pp wrote: > Specification link: https://github.com/riscvarchive/riscv-indirect-csr-access You may need to update link to https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc. https://github.com/llvm/llvm-project/pull/93952 ___

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

wangpc-pp wrote: > This broke building clang on Windows with PGO: > > ``` > FAILED: bin/clang-repl.exe lib/clang-repl.lib > cmd.exe /C "cmd.exe /C "D:\task_171745452431588\fetches\cmake\bin\cmake.exe > -E __create_def > D:\task_171745452431588\fetches\llvm-project\build\stage2\build\tools\cla

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

wangpc-pp wrote: This seems to be a breaking change, do we need to create issue in https://github.com/riscv-non-isa/rvv-intrinsic-doc? https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://list

[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] Reland "[clang] Enable sized deallocation by default in C++14 onwards" (PR #90373)

wangpc-pp wrote: > What kind of detail are you looking for? Mainly about the commands of cmake building. Does this failure bind to a buildbot? And can @AaronBallman @vitalybuka @vgvassilev help me to figure this out? https://github.com/llvm/llvm-project/pull/90373 _

[clang] [llvm] [RISCV] Add B extension (PR #76893)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893 >From ac2c10240160783ebbd65332230c8c294fef2442 Mon Sep 17 00:00:00 2001 From: wangpc Date: Thu, 4 Jan 2024 13:05:53 +0800 Subject: [PATCH] [RISCV] Add B extension It seems that we have `B` extension again: htt

[clang] [llvm] [RISCV] Add B extension (PR #76893)

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() { } static constexpr StringLiteral CombineIntoExts[] = { -{"zk"},{"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"}, -{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"}, +{"b"}, {"zk"},{"zkn"}, {"zks"}, {"zvkn

[clang] [llvm] [RISCV] Add B extension (PR #76893)

@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() { } static constexpr StringLiteral CombineIntoExts[] = { -{"zk"},{"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"}, -{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"}, +{"b"}, {"zk"},{"zkn"}, {"zks"}, {"zvkn

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

wangpc-pp wrote: Can you add it to RVA23 profile? https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284 https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing lis

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

wangpc-pp wrote: > Can you add it to RVA23 profile? > > https://github.com/llvm/llvm-project/blob/f71e25bb669d662f98823d6d81b3f918538c9239/llvm/lib/Support/RISCVISAInfo.cpp#L250-L284 Never mind, it's an optional extension. https://github.com/llvm/llvm-project/pull/88474 ___

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

@@ -7238,10 +7238,15 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args, options::OPT_fno_relaxed_template_template_args); - // -fsized-deallocation is off by default,

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

wangpc-pp wrote: Has KunMingHu's RTl been finalized (IIRC, we have developing vector unit)? And can we have different doc for different generations of XiangShan? https://github.com/llvm/llvm-project/pull/89359 ___ cfe-commits mailing list cfe-commits@

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

wangpc-pp wrote: Ping. https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/83774 >From f84c6c7a108d179ffa7f5ec423d852cb667e0f33 Mon Sep 17 00:00:00 2001 From: wangpc Date: Fri, 14 Jul 2023 10:38:14 +0800 Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards Since C

[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

@@ -1,12 +1,12 @@ -//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser *- C++ -*-===// wangpc-pp wrote: We shouldn't remove `*- C++ -*` here I think, it's for editors like Emacs. https://github.com/llvm/llvm-project/pull/89684 _

[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

https://github.com/wangpc-pp commented: I think this patch doesn't need to be stacked on #89335. https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

@@ -0,0 +1,194 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-feature +fullbf16 -S -emit-llvm %s -o - | FileCheck %s wangpc-pp wrote: ```sugges

[clang] [lld] [llvm] [RISCV] Split code that tablegen needs out of RISCVISAInfo. (PR #89684)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/89684 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/101046 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/83774 >From 2ed73672a548b77a36675343b420ef57266e46ab Mon Sep 17 00:00:00 2001 From: wangpc Date: Fri, 14 Jul 2023 10:38:14 +0800 Subject: [PATCH] [clang] Enable sized deallocation by default in C++14 onwards Since C

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

wangpc-pp wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

wangpc-pp wrote: > Do you see any disadvantage to going back to adding a feature for the > profiles? Of course not, I will revise this patch tomorrow. Thanks for discussing this! (I missed the sync-up meeting because I forgot the daylight saving...) https://github.com/llvm/llvm-project/pull/84

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } + wangpc-pp wro

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

@@ -0,0 +1,165 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm \ +// RUN: %s -o - | opt -S -passes=mem2reg | FileCheck %s + +// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16( +// CHECK-SAME: bfloat noundef [[A:%.*]]) #

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

@@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm \ +// RUN: %s -o - | opt -S -passes=mem2reg | FileCheck %s + +// CHECK-LABEL: define dso_local half @test_convert_from_bf16_to_fp16( +// CHECK-SAME: bfloat noundef [[A:%.*]]) #[

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

wangpc-pp wrote: > Lets revert #90299 to recover bots before the weekend. > Many thanks for reverting it and fixing one of the failures! https://github.com/llvm/llvm-project/pull/83774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://l

[clang] [clang-tools-extra] [libcxx] [clang] Enable sized deallocation by default in C++14 onwards (PR #83774)

wangpc-pp wrote: > This change is also causing a failure on our internal Windows builder, and a > public Windows bot: > https://lab.llvm.org/buildbot/#/builders/119/builds/17634 > ``` > 88.872 [191/66/4550] Linking CXX executable bin\clang-repl.exe > FAILED: bin/clang-repl.exe > cmd.exe /C "cd

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