[coreboot] MacBook development

Wondering if support for 3, 1 / 4, 1 / 5, 2 is in the works. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ME hacking @ BlackHat

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 09/22/2017 03:30 PM, Rene Shuster wrote: > > https://www.blackhat.com/eu-17/briefings/schedule/index.html#how-to-hack-a-turned-off-computer-or-running-unsigned-code-in-intel-management-engine-8668 We've been aware of this for a couple of days now

[coreboot] ME hacking @ BlackHat

https://www.blackhat.com/eu-17/briefings/schedule/index.html#how-to-hack-a-turned-off-computer-or-running-unsigned-code-in-intel-management-engine-8668 -- Tech III * AppControl * Endpoint Protection * Server Maintenance Buncombe County Schools Technology Department Network Group ComicSans Awarene

Re: [coreboot] ECC’17: Fund developer travel costs

Hello, On 22.09.2017 08:44, Paul Menzel wrote: Dear coreboot folks, The European coreboot conference 2017 is around the corner and starts on October 26th. Are there developers who need funding of their travel costs? Are there any plans to raise funds for travel costs? I have seen companies gi

[coreboot] New Defects reported by Coverity Scan for coreboot

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 5 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 1381373: Control flow issues (MISSING_BREAK) /src/d

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

Verified payload was built using code based on EDK2 code commit: >commit c1b0828b3ba8fa203033ede0c3329c0d5573719e >Author: Zhang, Chao B >Date: Wed Jan 25 12:50:55 2017 +0800 > >SecurityPkg: Tcg2Dxe: Update PCR[4] measure logic .. from git repo at https://github.com/tia

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

I can confirm coreboot has no issue to support 64 bit UEFI payload, it's already verified. Can you please provide more information of your coreboot/payload? Like, coreboot revision/commit ID, payload revision/commid ID, FSP revision, platform details (CRB or OEM platform) etc. On Thu, Sep 21, 201

Re: [coreboot] ECC’17: Fund developer travel costs

We can also help out to finding cheap hotels if needed. In order to do so, please contact Justine Spalik: justine.spa...@9elements.com On 22.09.2017 08:44, Paul Menzel wrote: > Dear coreboot folks, > > > The Eur

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

Hi Mariusz, which revision of EDK2 do you use? I used SVN 35017 Thanks. Regards, Melissa Yi BIOS Lead Engineer Celestica(Shanghai) R&D Center, China www.celestica.com Solid Partners, Flexible Solutions 2017-09-22 15:16 GMT+08:00 Szafranski, MariuszX < mariuszx.szafran...@intel.com>: > Hi

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

I have looked into the log. I see that INTEL FSP (for what I know) works correctly. It entered bunch of phases (now there are many, NOT only three). Anyway, scary stuff, directly taken from INTEL BIOS development, and tailored as "FSP" per say. I also see that MRC passed (there is in total 6 GB of

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

Hi, It was tested on Denverton_NS platform using mainly 64bit UEFI payload. 32bit UEFI payload was tested also. Both UEFI payload versions should behave similarly when built from same source code using same coreboot configs. I didn`t noticed difference between 32 and 64 versions. BR, Mariusz F