https://bugs.dpdk.org/show_bug.cgi?id=507
Bug ID: 507
Summary: virtio perf decrease and interrupt abnormal
Product: DPDK
Version: 20.08
Hardware: x86
OS: Linux
Status: UNCONFIRMED
Severity: normal
-DALLOW_EXPERIMENTAL_API is always set for in-tree compilation.
See https://git.dpdk.org/dpdk/commit/?id=acec04c4b2f5
Fixes: 322bd6e70272 ("net/bnxt: add port representor infrastructure")
Signed-off-by: David Marchand
---
drivers/net/bnxt/Makefile | 1 -
1 file changed, 1 deletion(-)
diff --gi
-DALLOW_EXPERIMENTAL_API is always set for in-tree compilation since
https://git.dpdk.org/dpdk/commit/?id=acec04c4b2f5
Warn people not to copy/paste this flag that was needed before.
Signed-off-by: David Marchand
---
devtools/checkpatches.sh | 8
1 file changed, 8 insertions(+)
diff -
On Wed, Jul 15, 2020 at 2:49 PM Aaron Conole wrote:
> David Marchand writes:
>
> > abidiff can provide some more information about the ABI difference it
> > detected.
> > In all cases, a discussion on the mailing must happen but we can give
> > some hints to know if this is a problem with the scr
There are several drivers which duplicate bit generation macro.
Introduce a generic bit macros so that such drivers avoid redefining
same in multiple drivers.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
Acked-by: Morten Brørup
---
Changelog:
v4->v5:
- Addressed comments from Morten Brøru
mlx5 PCI Device supports multiple classes of devices such as net, vdpa,
and/or regex.
To support these multiple classes, change mlx5_class to a
bitmap values so that if users asks to enable multiple of them, all
supported classes can be parsed.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
-
This series introduces mlx5 bus to support multiple class of devices
for a single PCI device.
Motivation and example
--
mlx5 PCI device supports multiple class of devices such as net, vdpa
and regex devices.
Currently only one pmd (either net or vdpa) can bind to this device.
Currently mlx5_common uses CLASS priority to initialize
common code before initializing the PMD.
However mlx5_common is not really a class, it is the pre-initialization
code needed for the PMDs.
In subsequent patch a needed initialization sequence is:
(a) Initialize bus (say pci)
(b) Initialize co
Following two errors are reported when compiled with
gcc (GCC) 8.3.1 20191121 (Red Hat 8.3.1-5).
drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a prototype [-Werror=strict-prototypes]
drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a
Add mlx5 PCI bus which enables multiple mlx5 drivers to bind to single
pci device.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
---
Changelog:
v5->v6:
- Updated Makefile for parallel shared build support
v4->v5:
- Merged maintainers update patch with this patch
v2->v3:
- Addressed commen
Create a mlx5 bus driver framework for invoking drivers of
multiple classes who have registered with the mlx5_pci bus
driver.
Validate user class arguments for supported class combinations.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
---
Changelog:
v3->v4:
- Fixed dma_map error unwinding
Enable class driver to match with the mlx5 pci devices.
Migrate mlx5 net PMD and vdpa PMD to start using mlx5 common class
driver.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
---
Changelog:
v2->v3:
- Avoid static table
v1->v2:
- Migreate API from rte_driver to rte_pci_driver
---
drivers
Use RTE_PRIO_COMMON for mlx5 common initialization and use
RTE_PRIO_CLASS for mlx5 net, vdpa PMDs.
This enables to do following initialization sequence.
(a) Initialize bus (say pci)
(b) Initialize common code of a driver (mlx5_common)
(c) Register mlx5 class PMDs (mlx5 net, mlx5 vdpa)
Information
Acked-by: Jeff Guo
On 7/16/2020 2:33 PM, alvinx.zh...@intel.com wrote:
From: Alvin Zhang
If a VF request PF to allocate more number of queue pairs, the PF will
free the queue pairs which have been allocated and reset the VF. So,
VF should stop to work until all the process is done. This patch
Now that mlx5_pci bus does the check for enabled classes and performs
probe(), remove() of associated classes, individual class driver
does not need to check if other driver is enabled.
Signed-off-by: Parav Pandit
Acked-by: Matan Azrad
---
Changelog:
v2->v3:
- Removed empty line
v1->v2:
- New
The hash for ipv6 nat-t esp should be enable as ipv4 nat-t esp.
Fixes: dadf70e5c30a (net/ice: enable additional input set for RSS hash)
Signed-off-by: Jeff Guo
---
drivers/net/ice/ice_hash.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/ice_hash.c b/drive
Enable GTPU SESSION flag usage to fix GTPU IP hash issue.
Signed-off-by: Jeff Guo
---
drivers/net/ice/base/ice_flow.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index d1b8a0534..00af44ab9 1006
Hi,
On 7/16/20 4:26 AM, Xia, Chenbo wrote:
> Hi Adrian,
>
>> -Original Message-
>> From: Adrian Moreno
>> Sent: Thursday, July 16, 2020 1:18 AM
>> To: dev@dpdk.org
>> Cc: maxime.coque...@redhat.com; Wang, Zhihong ;
>> amore...@redhat.com; Xia, Chenbo
>> Subject: [PATCH 2/5] net/virtio:
PMD flow priority is different from application flow priority. Flow
rules with higher match granularity assigned higher PMD priority. Also
PMD splits internally RSS flows according to flow RSS layer.
Final PMD flow rule priority derived from the last match item network
level, after PMD adjusts fl
On Thu, Jul 9, 2020 at 3:49 PM Lukasz Wojciechowski
wrote:
>
> Following flags were still present in the common_base config,
> but they were not used anywhere in the code:
> * CONFIG_RTE_LIBRTE_ACL_DEBUG
> * CONFIG_RTE_LIBRTE_NFP_DEBUG_TX
> * CONFIG_RTE_LIBRTE_NFP_DEBUG_RX
> * CONFIG_RTE_LIBRTE_PM
On 7/16/20 5:15 AM, Xia, Chenbo wrote:
> Hi Adrian,
>
>> -Original Message-
>> From: Adrian Moreno
>> Sent: Thursday, July 16, 2020 1:18 AM
>> To: dev@dpdk.org
>> Cc: maxime.coque...@redhat.com; Wang, Zhihong ;
>> amore...@redhat.com; Xia, Chenbo
>> Subject: [PATCH 3/5] net/virtio: ad
This series adds lookaside IPsec support in OCTEON TX2 PMD.
Features supported:
* IPv4
* ESP
* Tunnel mode
* AES-128/192/256-GCM
v3:
* Fixed PMD documentation and release notes updates
* Squashed enqueue and dequeue patches
* Removed unused code
v2:
* Updated PMD documentation and release notes
This patch moves capabilities initialization into probe.
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_cryptodev.c | 2 ++
drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c | 9 ++---
drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h | 8 +++-
dr
This patch adds lookaside IPsec SA context definitions.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_cryptodev_sec.h | 58 +
drivers/crypto/octeontx2/otx2_ipsec_po.h | 110 ++
drivers/crypto/octeontx2/otx2_security.
This patch moves otx2_sec_session structure to otx2_security.h
to make it common for inline and lookaside protocol.
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_security.h | 20
drivers/net/octeontx2/otx2_ethdev_sec.c| 1 +
drivers/net/octeontx2/ot
This patch registers security operations with cryptodev.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
doc/guides/cryptodevs/features/octeontx2.ini | 1 +
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 3 +-
drivers/cr
This patch adds lookaside IPsec capabilities.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_cryptodev.c | 1 +
.../octeontx2/otx2_cryptodev_capabilities.c | 101 ++
.../octeontx2/otx2_cryptodev_capabilities.h | 13 +++
From: Vamsi Attunuru
This patch adds lookaside IPsec callback functions.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 34 +--
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/octeo
From: Vamsi Attunuru
This patch creates session for lookaside IPsec.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 468 +-
drivers/crypto/octeontx2/otx2_ipsec_po.h | 295 +++
drivers/crypto/octeont
From: Vamsi Attunuru
This patch adds lookaside IPsec enqueue and dequeue routines.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Tejasree Kondoj
---
doc/guides/cryptodevs/octeontx2.rst | 21 +++
doc/guides/rel_notes/release_20_08.rst| 5 +
drivers/crypto/octeontx2/otx2_cry
On 7/16/20 5:31 AM, Xia, Chenbo wrote:
> Hi Adrian,
>
>> -Original Message-
>> From: Adrian Moreno
>> Sent: Thursday, July 16, 2020 1:18 AM
>> To: dev@dpdk.org
>> Cc: maxime.coque...@redhat.com; Wang, Zhihong ;
>> amore...@redhat.com; Xia, Chenbo
>> Subject: [PATCH 4/5] net/virtio: ad
> -Original Message-
> From: Dharmappa, Savinay
> Sent: Wednesday, July 15, 2020 7:28 PM
> To: Dharmappa, Savinay ; Singh, Jasvinder
> ; dev@dpdk.org
> Subject: [RFC PATCH 0/2] Enable dyynamic configuration of subport
> bandwidth profile
>
> DPDK sched library allows runtime configurat
> This series adds lookaside IPsec support in OCTEON TX2 PMD.
>
> Features supported:
> * IPv4
> * ESP
> * Tunnel mode
> * AES-128/192/256-GCM
>
> v3:
> * Fixed PMD documentation and release notes updates
> * Squashed enqueue and dequeue patches
> * Removed unused code
>
> v2:
> * Updated PMD do
> -Original Message-
> From: Dharmappa, Savinay
> Sent: Wednesday, July 15, 2020 7:28 PM
> To: Dharmappa, Savinay ; Singh, Jasvinder
> ; dev@dpdk.org
> Subject: [RFC PATCH 1/2] sched: add dynamic config of subport bandwidth
> profile
>
> This patch modifies the subport level data struc
Hi Adrian,
> -Original Message-
> From: Adrian Moreno
> Sent: Thursday, July 16, 2020 3:34 PM
> To: Xia, Chenbo ; dev@dpdk.org
> Cc: maxime.coque...@redhat.com; Wang, Zhihong ;
> Li, Miao
> Subject: Re: [PATCH 2/5] net/virtio: add DEVICE_NEEDS_RESET status bit
>
> Hi,
>
> On 7/16/20 4:
> -Original Message-
> From: Dharmappa, Savinay
> Sent: Wednesday, July 15, 2020 7:28 PM
> To: Dharmappa, Savinay ; Singh, Jasvinder
> ; dev@dpdk.org
> Subject: [RFC PATCH 2/2] example/qos_sched: subport bandwidth profile
> config
>
> qos sched application uses the new apis introduced
On Thu, Jul 16, 2020 at 9:53 AM Adrian Moreno wrote:
> >> +if (ret > UINT8_MAX) {
> >> +PMD_INIT_LOG(ERR, "Invalid VHOST_USER_GET_STATUS
> >> response 0x%" PRIx64 "\n", ret);
> >
> > There's a coding style issue here:
> > CHECK:CAMELCASE: Avoid CamelCase:
> > Could you fix this?
>
The accurate packet Tx scheduling on timestamps was introduced [1].
This patchset provides the feature implementation on mlx5 PMD side.
[1] http://patches.dpdk.org/patch/73742/
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
v3: - 32-bit systems rte_atomic128_cmp_exchange() fix
This patch introduces the new devargs:
tx_pp - enables accurate packet send scheduling on mbuf timestamps
in the PMD. On the device start if "rte_dynflag_timestamp"
dynamic flag is registered and this devarg non-zero value is
specified, the driver initializes all necessary internal
infrast
The master and representors might be created over the multiport
Infiniband devices and the UAR resource allocated for sibling
ports might belong to the same underlying Infiniband device.
Hardware requires the write access to the UAR must be performed
as atomic 64-bit write, on 32-bit systems this i
This patch prepares the common part of the mlx5 PMDs to
support packet send scheduling on mbuf timestamps:
- the DevX routine to query the packet pacing HCA capabilities
- packet pacing Send Queue attributes support
- the hardware related definitions
Signed-off-by: Viacheslav Ovsiienko
Ack
This patch creates the special completion queue providing
reference completions to schedule packet send from
other transmitting queues.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/Makefile| 1 +
drivers/net/mlx5/linux/mlx5_os.c | 3 +
drivers/net/m
This is preparation step before moving the Tx queue creation
to the DevX approach. Some features require the shared UAR
for Tx queues and scheduling completion queues, the patch
manages the shared UAR.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.c | 14 ++
The dedicated Rearm Queue is needed to fire the work requests to
the Clock Queue in realtime. The Clock Queue should never stop,
otherwise the clock synchronization mignt be broken and packet
send scheduling would fail. The Rearm Queue uses cross channel
SEND_EN/WAIT operations to provides the requ
Service routine is invoked periodically on Rearm Queue
completion interrupts, typically once per some milliseconds
(1-16) to track clock jitter and wander in robust fashion.
It performs the following:
- fetches the completed CQEs for Rearm Queue
- restarts Rearm Queue on errors
- pushes new reques
To provide the packet send schedule on mbuf timestamp the Tx
queue must be attached to the same UAR as Clock Queue is.
UAR is special hardware related resource mapped to the host
memory and provides doorbell registers, the assigning UAR
to the queue being created is provided via DevX API only.
Sig
Tested-by: Xiao Qimai
Regards,
Xiao Qimai
> -Original Message-
> From: dev On Behalf Of patrick...@intel.com
> Sent: Wednesday, July 15, 2020 11:59 PM
> To: dev@dpdk.org; maxime.coque...@redhat.com; Xia, Chenbo
>
> Cc: Wang, Yinan ; Fu, Patrick
> Subject: [dpdk-dev] [PATCH v1] vhost:
This patch allocates the Packet Pacing context from the kernel,
configures one according to requested pace send scheduling
granularuty and assigns to Clock Queue.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h | 2 ++
drivers/net/mlx5/mlx5_txpp.c | 7
The application provides timestamps in Tx mbuf as clocks,
the hardware performs scheduling on Clock Queue completion index
match. This patch introduces the timestamp-to-completion-index
inline routine.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5.h |
This patch adds send scheduling on timestamps into tx_burst
routine template. The feature is controlled by static configuration
flag, the actual routines supporting the new feature are generated
over this updated template.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/ne
The mlx5 PMD exposes the following new introduced
extended statistics counter to report the errors
of packet send scheduling on timestamps:
- txpp_err_miss_int - rearm queue interrupt was not handled
was not handled in time and service routine might miss
the completions
- txpp_err_rea
The new static control flag is introduced to control
routine generating from template, enabling the scheduling
on timestamps.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5_rxtx.c | 97 +++-
drivers/net/mlx5/mlx5_txq.c
The fields to support send scheduling on dynamic timestamp
field are introduced and initialized on device start.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5_rxtx.h| 4
drivers/net/mlx5/mlx5_trigger.c | 2 ++
drivers/net/mlx5/mlx5_txq.c | 32
If send schedule feature is engaged there is the Clock Queue
created, that reports reliable the current device clock counter
value. The device clock counter can be read directly from the
Clock Queue CQE.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/net/mlx5/linux/mlx5_o
> -Original Message-
> From: Sun, Chenmin
> Sent: Thursday, July 16, 2020 7:04 AM
> To: Zhang, Qi Z ; Xing, Beilei
> Cc: dev@dpdk.org; Sun, Chenmin
> Subject: [PATCH V2] net/i40e: fix fdir cannot receive rx writeback issue
>
> From: Chenmin Sun
>
> This patch fixes the fdir cannot
The DevX routine to read/write NIC registers via DevX API is added.
This is the preparation step to check timestamp modes and units
and gather the extended statistics.
Signed-off-by: Viacheslav Ovsiienko
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_devx_cmds.c| 60
The ConnectX-6DX supports the timestamps in various formats,
the new realtime format is introduced - the upper 32-bit word
of timestamp contains the UTC seconds and the lower 32-bit word
contains the nanoseconds. This patch detects what format is
configured in the NIC and performs the conversion ac
On 7/16/20 10:18 AM, David Marchand wrote:
> On Thu, Jul 16, 2020 at 9:53 AM Adrian Moreno wrote:
+if (ret > UINT8_MAX) {
+PMD_INIT_LOG(ERR, "Invalid VHOST_USER_GET_STATUS
response 0x%" PRIx64 "\n", ret);
>>>
>>> There's a coding style issue here:
>>> CHECK:CAMELC
> -Original Message-
> From: David Marchand
> Sent: Thursday, July 16, 2020 3:43 PM
> To: Lukasz Wojciechowski
> Cc: tho...@monjalon.net; dev ; Ruifeng Wang
>
> Subject: Re: [dpdk-dev] [PATCH v3 2/4] config: remove unused config flags
>
> On Thu, Jul 9, 2020 at 3:49 PM Lukasz Wojciecho
> -Original Message-
> From: Gregory Etelson
> Sent: Thursday, July 16, 2020 10:40 AM
> Subject: [PATCH] net/mlx5: fix tunnel PMD flow prioriry
>
> PMD flow priority is different from application flow priority. Flow
> rules with higher match granularity assigned higher PMD priority. A
Hi,
> -Original Message-
> From: Morten Brørup
> Sent: Thursday, July 16, 2020 12:03 AM
> To: Zhao1, Wei ; Guo, Jia
> Cc: dev@dpdk.org; Thomas Monjalon ; Yigit, Ferruh
> ; Andrew Rybchenko
> Subject: ixgbe vector rx does not conform to rte_eth_rx_burst() API
>
> Wei, Jeff,
>
> For th
As tx mbuf is not set for some advanced descriptors, if there is no
mbuf checking before rte_pktmbuf_free_seg() function be called on
the process of tx done clean up, that will casue a segfault. So add
a NULL pointer check to fix it.
Bugzilla ID: 501
Fixes: 8d907d2b79f7 (net/igb: free consumed Tx
As tx mbuf is not set for some advanced descriptors, if there is no
mbuf checking before rte_pktmbuf_free_seg() function be called on
the process of tx done clean up, that will cause a segfault. So add
a NULL pointer check to fix it.
Bugzilla ID: 501
Fixes: 8d907d2b79f7 (net/igb: free consumed Tx
Hi Nicholas,
> Subject: [PATCH v1] baseband/fpga_5gnr_fec: add companion PF config App
>
> Adding companion application to configure HW Device from the PF.
> Then the device can be accessed through BBDEV from VF (or PF).
>
> Signed-off-by: Nicolas Chautru
> ---
I believe this patch is for next
Hi Adrian,
> -Original Message-
> From: Adrian Moreno
> Sent: Thursday, July 16, 2020 3:43 PM
> To: Xia, Chenbo ; dev@dpdk.org
> Cc: maxime.coque...@redhat.com; Wang, Zhihong
> Subject: Re: [PATCH 3/5] net/virtio: add VIRTIO_SET_STATUS support to Virtio-
> user
>
>
>
> On 7/16/20 5:15
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Zhao1, Wei
> Sent: Thursday, July 16, 2020 10:50 AM
>
> Hi,
>
> > -Original Message-
> > From: Morten Brørup
> > Sent: Thursday, July 16, 2020 12:03 AM
> > To: Zhao1, Wei ; Guo, Jia
> > Cc: dev@dpdk.org; Thomas Monjalon ; Yigit,
> F
> -Original Message-
> From: Guo, Jia
> Sent: Thursday, July 16, 2020 3:31 PM
> To: Zhang, Qi Z ; Yang, Qiming
> Cc: dev@dpdk.org; Su, Simei ; Guo, Jia
>
> Subject: [dpdk-dev] net/ice/base: fix GTPU IP hash issue
>
> Enable GTPU SESSION flag usage to fix GTPU IP hash issue.
>
> Sign
> -Original Message-
> From: dev On Behalf Of Jeff Guo
> Sent: Thursday, July 16, 2020 3:31 PM
> To: Zhang, AlvinX ; Yang, Qiming
>
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v5] net/i40e: fix qps configuration in VF
>
> Acked-by: Jeff Guo
>
> On 7/16/2020 2
Reviewed-by: Wei Zhao
> -Original Message-
> From: Guo, Jia
> Sent: Thursday, July 16, 2020 4:54 PM
> To: Zhao1, Wei
> Cc: bmcf...@redhat.com; dev@dpdk.org; Guo, Jia
> Subject: [dpdk-dev] net/e1000: fix segfault on tx done clean up
>
> As tx mbuf is not set for some advanced descrip
Currently, for MLX5 PMD, once millions of flows created, the memory
consumption of the flows are also very huge. For the system with limited
memory, it means the system need to reserve most of the memory as huge
page memory to serve the flows in advance. And other normal applications
will have no c
Add the internal mlx5 memory management functions:
mlx5_malloc_mem_select();
mlx5_memory_stat_dump();
mlx5_rellaocate();
mlx5_malloc();
mlx5_free();
User will be allowed to manage memory from system or from rte memory
with the unified functions.
In this case, for the system with limited memory w
Currently, for MLX5 PMD, once millions of flows created, the memory
consumption of the flows are also very huge. For the system with limited
memory, it means the system need to reserve most of the memory as huge
page memory to serve the flows in advance. And other normal applications
will have no c
This commit allocates the control path memory from unified malloc
function.
The objects be changed:
1. hlist;
2. rss key;
3. vlan vmwa;
4. indexed pool;
5. fdir objects;
6. meter profile;
7. flow counter pool;
8. hrxq and indirect table;
9. flow object cache resources;
10. temporary resources in
This commit allocates the miscellaneous configuration objects from the
unified malloc function.
Signed-off-by: Suanming Mou
Acked-by: Matan Azrad
---
drivers/net/mlx5/linux/mlx5_ethdev_os.c | 8 +---
drivers/net/mlx5/linux/mlx5_os.c| 26 +-
drivers/net/mlx5/
This commit allocateis the control path objects memory from the unified
malloc function.
These objects are all used during the instances initialize, it will not
affect the data path.
Signed-off-by: Suanming Mou
Acked-by: Matan Azrad
---
drivers/common/mlx5/linux/mlx5_glue.c | 13 +++---
driver
This commit allocates the data path object page and B-tree table memory
from unified malloc function with explicit flag MLX5_MEM_RTE.
Signed-off-by: Suanming Mou
Acked-by: Matan Azrad
---
drivers/common/mlx5/mlx5_common.c| 10 ++
drivers/common/mlx5/mlx5_common_mr.c | 31 +++
This commit allocates the Rx/Tx queue objects from unified malloc
function.
Signed-off-by: Suanming Mou
Acked-by: Matan Azrad
---
drivers/net/mlx5/mlx5_rxq.c | 37 ++---
drivers/net/mlx5/mlx5_txq.c | 44 +---
2 files change
> -Original Message-
> From: Guo, Jia
> Sent: Thursday, July 16, 2020 3:29 PM
> To: Zhang, Qi Z ; Yang, Qiming
> Cc: dev@dpdk.org; Su, Simei ; Guo, Jia
>
> Subject: [dpdk-dev v1] net/ice: fix ipv6 nat-t esp issue
>
> The hash for ipv6 nat-t esp should be enable as ipv4 nat-t esp.
>
As tx mbuf is not set for some advanced descriptors, if there is no
mbuf checking before rte_pktmbuf_free_seg() function be called on
the process of tx done clean up, that will cause a segfault. So add
a NULL pointer check to fix it.
Bugzilla ID: 501
Fixes: 8d907d2b79f7 (net/igb: free consumed Tx
On Sat, Jul 11, 2020 at 12:28 AM Nicolas Chautru
wrote:
[snip]
> +#define SYS_DIR "/sys/bus/pci/devices"
> +#define CUR_DIR "."
> +#define PREV_DIR ".."
> +
> +#define DRIVER_LINK "driver"
> +#define DEVICE_FILE "device"
> +#define VENDOR_FILE "vendor"
> +#define BAR0_FILE"resource0"
> +#
On 7/16/20 10:58 AM, Xia, Chenbo wrote:
> Hi Adrian,
>
>> -Original Message-
>> From: Adrian Moreno
>> Sent: Thursday, July 16, 2020 3:43 PM
>> To: Xia, Chenbo ; dev@dpdk.org
>> Cc: maxime.coque...@redhat.com; Wang, Zhihong
>> Subject: Re: [PATCH 3/5] net/virtio: add VIRTIO_SET_STATUS
On 13/07/20 08:13 -0700, Manish Chopra wrote:
> This is merely copy of latest linux/pci_regs.h in
> order to avoid dependency of dpdk on user headers.
>
I guess this dependency is an issue on non-linux systems, when you must
use those defines in a generic implementation. Can you confirm this is
t
Re-CCing dev@dpdk.org as it was removed from the reply.
On 13/07/20 08:13 -0700, Manish Chopra wrote:
> This is merely copy of latest linux/pci_regs.h in
> order to avoid dependency of dpdk on user headers.
>
I guess this dependency is an issue on non-linux systems, when you must
use those defin
On 16/07/20 12:08 +0200, Gaëtan Rivet wrote:
> Re-CCing dev@dpdk.org as it was removed from the reply.
>
> On 13/07/20 08:13 -0700, Manish Chopra wrote:
> > This is merely copy of latest linux/pci_regs.h in
> > order to avoid dependency of dpdk on user headers.
> >
>
> I guess this dependency is
On 2020-07-15 18:21, Stephen Hemminger wrote:
> On Wed, 15 Jul 2020 10:17:09 +
> Mattias Rönnblom wrote:
>
>> On 2020-07-14 22:51, Stephen Hemminger wrote:
>>> On Tue, 14 Jul 2020 18:59:59 +
>>> Honnappa Nagarahalli wrote:
>>>
>> Hi.
> Hey,
>
>> In
Add deprecation note for making changes in data structures and APIs
in order to allow dynamic configuration of subport bandwidth profile.
These changes are aligned as suggested in the RFC[1].
https://mails.dpdk.org/archives/dev/2020-July/175161.html
Signed-off-by: Savinay Dharmappa
---
doc/guid
On Thu, Jul 16, 2020 at 3:48 PM Gaëtan Rivet wrote:
>
> On 16/07/20 12:08 +0200, Gaëtan Rivet wrote:
> > Re-CCing dev@dpdk.org as it was removed from the reply.
> >
> > On 13/07/20 08:13 -0700, Manish Chopra wrote:
> > > This is merely copy of latest linux/pci_regs.h in
> > > order to avoid depend
Hello,
On Thu, Jul 16, 2020 at 6:58 AM Phil Yang wrote:
>
> Add information about possible optimizations using C11 atomic built-ins.
We are missing a review on this doc update.
Thanks.
--
David Marchand
>
> Signed-off-by: Phil Yang
> Signed-off-by: Honnappa Nagarahalli
> ---
> doc/guides
The following sequences was working fine on mlx5:
rte_eth_dev_configure(portid, ...);
for (queueid = 0; queueid < nb_txq; queueid++)
rte_eth_tx_queue_setup(portid, queueid, ...);
for (queueid = 0; queueid < nb_rxq; queueid++)
rte_eth_rx_queue_setup(portid, queueid, ...);
/
On Thu, Jul 16, 2020 at 6:58 AM Phil Yang wrote:
>
> In order to deprecate the rte_atomic and rte_smp barrier APIs, prevent
> the patches from using these APIs in the converted modules and compilers
> __sync built-ins in all modules.
builtins* for the whole patch.
>
> The converted modules:
> l
Hi Ruifeng,
On 16/07/2020 06:19, Ruifeng Wang wrote:
Coverity complains about unchecked return value of rte_rcu_qsbr_dq_enqueue.
By default, defer queue size is big enough to hold all tbl8 groups. When
enqueue fails, return error to the user to indicate system issue.
Coverity issue: 360832
Fixe
Hi Adrian,
> -Original Message-
> From: Adrian Moreno
> Sent: Thursday, July 16, 2020 5:51 PM
> To: Xia, Chenbo ; dev@dpdk.org
> Cc: maxime.coque...@redhat.com; Wang, Zhihong
> Subject: Re: [PATCH 3/5] net/virtio: add VIRTIO_SET_STATUS support to Virtio-
> user
>
>
>
> On 7/16/20 10:5
16/07/2020 12:27, Jerin Jacob:
> On Thu, Jul 16, 2020 at 3:48 PM Gaëtan Rivet wrote:
> >
> > On 16/07/20 12:08 +0200, Gaëtan Rivet wrote:
> > > Re-CCing dev@dpdk.org as it was removed from the reply.
> > >
> > > On 13/07/20 08:13 -0700, Manish Chopra wrote:
> > > > This is merely copy of latest li
16/07/2020 12:48, David Marchand:
> On Thu, Jul 16, 2020 at 6:58 AM Phil Yang wrote:
> > check_forbidden_additions() { #
> > res=0
> > + c11_atomics_dir="lib/librte_distributor lib/librte_hash
> > lib/librte_kni
> > +lib/librte_lpm lib/librte_rcu lib/librte
On Thu, Jul 16, 2020 at 6:16 AM Phil Yang wrote:
>
> David Marchand writes:
>
> > Subject: Re: [PATCH v4 1/2] mbuf: use C11 atomic built-ins for refcnt
> > operations
> >
> > On Thu, Jul 9, 2020 at 5:59 PM Phil Yang wrote:
> > >
> > > Use C11 atomic built-ins with explicit ordering instead of rt
On Thu, Jul 09, 2020 at 11:58:50PM +0800, Phil Yang wrote:
> Use C11 atomic built-ins with explicit ordering instead of rte_atomic
> ops which enforce unnecessary barriers on aarch64.
>
> Signed-off-by: Phil Yang
> Reviewed-by: Ruifeng Wang
Acked-by: Olivier Matz
Thanks
This patch updates the minimum driver version that supports
Intel QuickAssist device D15xx.
Signed-off-by: Adam Dybkowski
---
doc/guides/cryptodevs/qat.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 931a
This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).
Adam Dybkowski (2):
common/qat: support GEN2 QAT device 200xx
doc: update QAT PMD release notes
doc/guides/cryptodevs/qat.rst | 7 +--
doc/guides/rel_notes/release_
This patch separates QAT PMD paragraphs in the release notes
into three parts, for QAT Symmetric Crypto PMD, QAT Asymmetric
Crypto PMD and QAT Compression PMD.
Signed-off-by: Adam Dybkowski
---
doc/guides/rel_notes/release_20_08.rst | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).
Signed-off-by: Adam Dybkowski
---
doc/guides/cryptodevs/qat.rst | 7 +--
doc/guides/rel_notes/release_20_08.rst | 2 ++
drivers/common/qat/qat_device.c| 6 +-
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