This is how it is calculated in coreboot
https://review.coreboot.org:4430/cgit/coreboot.git/tree/src/lib/cbfs.c?id=refs/heads/master#n268
___FMAP__COREBOOT_BASE and ___FMAP__COREBOOT_SIZE are based on values
available in fmd files (depending on 8MB/16Mb coreboot).
#grep -r FMAP__COREBOOT_BASE
24.03.2017 20:32, Gailu Singh пишет:
>>> Could you please reference the solution for future users with the same
> problem?
> Sure. Infect I should have detailed it without asking. Sorry for that.
>
> Solution can be referenced to following thread in coreboot mailing list
> that provide details of
>>Could you please reference the solution for future users with the same
problem?
Sure. Infect I should have detailed it without asking. Sorry for that.
Solution can be referenced to following thread in coreboot mailing list
that provide details of memory mapping on the board answered by Adrian
Hi Matthias,
The patches I send to the mailing list do not support the Intel UARTs
right now, because they only match for OXSemi IDs. One has to add a
similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs.
I have changed the ns8250_pci_mmio_iter and enabled two debug print in
On Fri, Mar 24, 2017, 10:17 Gailu Singh wrote:
> It was indeed the ROM mapping issue. solved now. Thank you so much Andrei.
>
Could you please reference the solution for future users with the same
problem?
>
> On Fri, Mar 17, 2017 at 7:29 PM, Gailu Singh
It was indeed the ROM mapping issue. solved now. Thank you so much Andrei.
On Fri, Mar 17, 2017 at 7:29 PM, Gailu Singh wrote:
> >>Any chance ROM is mapped somewhere else in your case?
> I need to check, this may be a case.
>
> On Fri, Mar 17, 2017 at 7:16 PM, Andrei