Dhinakaran Pandiyan writes:
> Now that drm_vblank_count() returns all bits of the vblank count, update
> drm_crtc_arm_vblank_event() so that it queues the correct sequence.
> Otherwise, this leads to prolonged waits for a vblank sequence when the
> current count is >=2^32.
The summary for this p
Dhinakaran Pandiyan writes:
> drm_vblank_count() has a u32 type returning what is a 64-bit vblank
> count.
It looks like a general review of the 64-bit widening patch is needed.
* drm_crtc_accurate_vblank_count has a 32-bit return, and uses a 32-bit
temporary
* drm_wait_one_vblank uses a 32-
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: Fix return from
guc_log_relay_file_create
URL : https://patchwork.freedesktop.org/series/37382/
State : success
== Summary ==
Series 37382v1 series starting with [1/3] drm/i915/guc: Fix return from
guc_log_relay_file_creat
On some systems like skl-gvtdvm, SSE4.1 movntdqa might not be available.
movntdqa is needed for efficient capture of the logs from uncached GuC
log buffer. GuC init was tied with this support and other setup needed
for interrupt based GuC log capture like relay channel/file support and
uncached map
guc_log_relay_file_create will return -EEXIST if we invoke
relay_late_setup_files multiple times as part of i915_guc_log_control.
However this is to be not cosidered as fail and need to return 0.
This was mistakenly introduced in the below commit. Fix it.
Fixes: 70deeaddc6e6 "drm/i915/guc: Fix loc
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.h | 4 ++--
drivers/gpu/drm/i915/intel_guc_log.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..53037b5 100644
== Series Details ==
Series: tests/kms_frontbuffer_tracking: Including DRRS test coverage
URL : https://patchwork.freedesktop.org/series/37334/
State : success
== Summary ==
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
Test kms_cursor_legacy:
== Series Details ==
Series: drm/i915: Flush ggtt writes through the old fenced vma before changing
fences
URL : https://patchwork.freedesktop.org/series/37355/
State : warning
== Summary ==
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
fail ->
On Tue, Jan 30, 2018 at 08:44:46AM +, Jani Nikula wrote:
> On Mon, 29 Jan 2018, Jani Nikula wrote:
> > On Mon, 29 Jan 2018, Lionel Landwerlin
> > wrote:
> >> On 29/01/18 09:02, Chris Wilson wrote:
> >>> Quoting Lionel Landwerlin (2018-01-29 08:33:46)
> This reverts commit 5b54eddd3920e9
On Tue, Jan 30, 2018 at 09:06:14AM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-01-29 21:40:27)
> > On Mon, Jan 29, 2018 at 08:45:24PM +, Chris Wilson wrote:
> > > Quoting Srivatsa, Anusha (2018-01-29 20:17:25)
> > > >
> > > >
> > > > >-Original Message-
> > > > >From: Vivi
On Tue, Jan 30, 2018 at 08:46:49PM +, Ville Syrjälä wrote:
> On Tue, Jan 30, 2018 at 12:42:12PM -0800, Rodrigo Vivi wrote:
> > On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote:
> > > On Mon, 29 Jan 2018, Rodrigo Vivi wrote:
> > > > On CNL SKUs that uses port F, max DP rate is 8.1G
== Series Details ==
Series: drm/i915: Optimize drop-caches
URL : https://patchwork.freedesktop.org/series/37351/
State : failure
== Summary ==
Test drv_suspend:
Subgroup fence-restore-untiled:
pass -> DMESG-WARN (shard-snb) fdo#102365
Test prime_self_import:
Almost forgot to respond to this one!
Reviewed-by: Lyude Paul
On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Allow encoders to customize their hotplug processing by moving the
> intel_hpd_irq_event() code into an encoder hotplug vfunc. Currently
> only SDVO n
Reviewed-by: Lyude Paul
On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> LSPCON likes to throw short HPDs during the enable seqeunce prior to the
> link being trained. These obviously result in the channel CR/EQ check
> failing and thus we schedule a pointless h
Reviewed-by: Lyude Paul
On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> intel_dp->channel_eq_status is used in exactly one function, and we
> don't need it to persist between calls. So just go back to using a
> local variable instead.
>
> Signed-off-by: Ville
On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Doing link retraining from the short pulse handler is problematic since
> that might introduce deadlocks with MST sideband processing. Currently
> we don't retrain MST links from this code, but we want to change tha
== Series Details ==
Series: drm/i915: Fix Limited Range Color Handling (rev4)
URL : https://patchwork.freedesktop.org/series/35725/
State : failure
== Summary ==
Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip -> PASS (shard-snb)
Test kms_vblank:
On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The LG 4k TV I have doesn't deassert HPD when I turn the TV off, but
> when I turn it back on it will pulse the HPD line. By that time it has
> forgotten everything we told it about scrambling and the clock ratio.
>
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE
timeouts during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37344/
State : failure
== Summary ==
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pas
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : failure
== Summary ==
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-b-planes:
dmesg-warn -> PASS (shard-snb)
Test perf_pmu:
== Series Details ==
Series: series starting with [1/7] drm/i915: Don't set cursor pipe select bits
on g4x+
URL : https://patchwork.freedesktop.org/series/37362/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK in
On Tue, Jan 30, 2018 at 12:42:12PM -0800, Rodrigo Vivi wrote:
> On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote:
> > On Mon, 29 Jan 2018, Rodrigo Vivi wrote:
> > > On CNL SKUs that uses port F, max DP rate is 8.1G for all
> > > ports when we have the elevated voltage (higher than 0.85
On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote:
> On Mon, 29 Jan 2018, Rodrigo Vivi wrote:
> > On CNL SKUs that uses port F, max DP rate is 8.1G for all
> > ports when we have the elevated voltage (higher than 0.85V).
> >
> > v2: Make commit message more generic.
> > v3: Move conditi
== Series Details ==
Series: tests/kms_frontbuffer_tracking: Including DRRS test coverage
URL : https://patchwork.freedesktop.org/series/37334/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
3f820260ce660cdff7fb803237c57554a29498c0 tests/kms_atomic_transiti
From: Ville Syrjälä
Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865
cursor defines consistently, and move the pipe CSC enable bit next
to the other non-845/865 cursor defines.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++---
d
From: Ville Syrjälä
We disable trickle feed whenever possible, except for the cursors
on SNB/IVB. Let's try disabling it there too if for no other reason
than consistency.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Ville Syrjälä
WaDoubleCursorLP3Latency was meant for pre-production hardware.
Drop it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b92ea1db
From: Ville Syrjälä
Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere.
Cc: Hans de Goede
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dsi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/
From: Ville Syrjälä
Like we do for encoder let's make the plane->get_hw_state() return
the pipe to which the plane is currently attached. We don't currently
allow planes to move between the pipes, but perhaps one day we will.
In either case this makes the code more uniform and perhaps makes
inte
From: Ville Syrjälä
i965 and g4x still have the pipe select bits in the plane control
registers, they're just hardcoded to select a specific pipe. However
plane C on i965 can still move between the pipes, thus we should
program the pipe select bits on i965 if we want to expose plane C
some day.
From: Ville Syrjälä
G4x cursor control registers still allow us to write to the pipe select
bits even though cursors are supposed to be fixed to a specific pipe.
Bspec tells us that we should only ever write 0 to these bits. Let's
follow that recommendation. On ilk+ the bits become hardwired to 0
On Tue, Jan 30, 2018 at 08:05:41PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
> another SKU.
> URL : https://patchwork.freedesktop.org/series/37309/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915
== Series Details ==
Series: drm/i915: Add a new modparam for customized ring multiplier (rev2)
URL : https://patchwork.freedesktop.org/series/35535/
State : failure
== Summary ==
Series 35535v2 drm/i915: Add a new modparam for customized ring multiplier
https://patchwork.freedesktop.org/api/1
On Tue, Jan 30, 2018 at 03:23:32PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, December 22, 2017 9:43 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
> >Syrjala, Ville ;
On Tue, Jan 30, 2018 at 07:52:14PM +, Pandiyan, Dhinakaran wrote:
>
> On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote:
> > From: "Kumar, Mahesh"
> >
> > Platforms before Gen11 were sharing lanes between port-A & port-E.
> > This limitation is no more there.
> >
> > Changes since V1:
>
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/37309/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Using index info to reconstruct a
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : success
== Summary ==
Series 37341v1 ICL mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/
fi-bdw-5557u total:288 pass:267 dwarn:0
== Series Details ==
Series: series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts
during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37338/
State : success
== Summary ==
Warning: bzip CI_DRM_3701/shard-glkb6/results1.json.bz2 wasn't in correct JSON
for
On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote:
> From: "Kumar, Mahesh"
>
> Platforms before Gen11 were sharing lanes between port-A & port-E.
> This limitation is no more there.
>
> Changes since V1:
> - optimize the code (Shashank/Jani)
> - create helper function to get max lanes (vi
== Series Details ==
Series: drm/i915: Flush ggtt writes through the old fenced vma before changing
fences
URL : https://patchwork.freedesktop.org/series/37355/
State : success
== Summary ==
Series 37355v1 drm/i915: Flush ggtt writes through the old fenced vma before
changing fences
https://
== Series Details ==
Series: drm/i915: Optimize drop-caches
URL : https://patchwork.freedesktop.org/series/37351/
State : success
== Summary ==
Series 37351v1 drm/i915: Optimize drop-caches
https://patchwork.freedesktop.org/api/1.0/series/37351/revisions/1/mbox/
Test debugfs_test:
Sub
Quoting Lis, Tomasz (2018-01-30 18:47:55)
>
>
> On 2018-01-27 21:28, Chris Wilson wrote:
> > If we remove some hardcoded assumptions about the preempt context having
> > a fixed id, reserved from use by normal user contexts, we may only
> > allocate the i915_gem_context when required. Then the su
On 2018-01-27 21:28, Chris Wilson wrote:
If we remove some hardcoded assumptions about the preempt context having
a fixed id, reserved from use by normal user contexts, we may only
allocate the i915_gem_context when required. Then the subsequent
decisions on using preemption reduce to having th
== Series Details ==
Series: drm/i915: Fix Limited Range Color Handling (rev4)
URL : https://patchwork.freedesktop.org/series/35725/
State : success
== Summary ==
Series 35725v4 drm/i915: Fix Limited Range Color Handling
https://patchwork.freedesktop.org/api/1.0/series/35725/revisions/4/mbox/
A known issue that ring frequency transition would lead to
a full system stall had impacted the media performance when
the GT frequency is lower than IA freqency and there's heavy
GT workload while having low IA workload. In this case, the
ring frequency will be toggled between GT and IA frequency.
== Series Details ==
Series: drm/i915: Use the correct maximum in skl_compute_plane_wm (rev2)
URL : https://patchwork.freedesktop.org/series/37342/
State : failure
== Summary ==
Applying: drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm
error: sha1 information is lacking or u
== Series Details ==
Series: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS
URL : https://patchwork.freedesktop.org/series/37345/
State : failure
== Summary ==
Applying: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS
Using index info to reconstruct a base tree...
M drivers/gp
== Series Details ==
Series: drm/i915: Restore HDCP DRM_INFO when with no downstream (rev2)
URL : https://patchwork.freedesktop.org/series/36921/
State : failure
== Summary ==
Applying: drm/i915: Restore HDCP DRM_INFO when with no downstream
error: Failed to merge in the changes.
Using index i
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE
timeouts during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37344/
State : success
== Summary ==
Series 37344v1 series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : success
== Summary ==
Series 37341v1 ICL mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_ent
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : warning
== Summary ==
Test perf:
Subgroup enable-disable:
fail -> PASS (shard-apl) fdo#103715
Subgroup b
== Series Details ==
Series: series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts
during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37338/
State : success
== Summary ==
Series 37338v1 series starting with [1/3] drm/i915/bxt, glk: Increase PCODE
timeou
Regards
Shashank
On 1/30/2018 3:53 PM, Jani Nikula wrote:
On Tue, 30 Jan 2018, Shashank Sharma wrote:
From: "Sharma, Shashank"
Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR for
== Series Details ==
Series: drm/i915: Enable debugobjects for request validation (rev3)
URL : https://patchwork.freedesktop.org/series/37240/
State : success
== Summary ==
Series 37240v3 drm/i915: Enable debugobjects for request validation
https://patchwork.freedesktop.org/api/1.0/series/3724
This is a precautionary measure as I have no evidence to suggest we've
hit a bug here (I was hoping this might explain gdg's odd behaviour, but
alas), but given that we have a function to flush the ggtt writes it
seems prudent to use it prior to changing the fence register. Due to the
intrinsic nat
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_flip:
Subgroup wf_vb
On Tue, Jan 30, 2018 at 09:29:34AM -0500, Sean Paul wrote:
> The commit below returned earlier than before, but failed to move the
> info message when authenticating without downstream devices. This patch
> restores the message on authentication success.
>
> Changes in v2:
> - s/no downstream devi
On Tue, Jan 30, 2018 at 04:12:14PM +0100, Daniel Vetter wrote:
> On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote:
> > HDCP was a bit too chatty to get along with the rest of the i915 driver.
> >
> > Suggested-by: Daniel Vetter
> > Signed-off-by: Sean Paul
>
> Reviewed-by: Daniel Vette
Quoting Mika Kuoppala (2018-01-30 13:00:50)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2018-01-30 12:18:17)
> >> Chris Wilson writes:
> >>
> >> > Previously, we relied on only running the hangcheck while somebody was
> >> > waiting on the GPU, in order to minimise the amount of time ha
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/r
On 30/01/18 15:01, Lahtinen, Joonas wrote:
On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote:
Thanks all,
I don't really read much opposition to the current patch series. If
anything we could actually want to do more it seems.
It would be good to have the green light and land that.
I'v
Although this is a debugfs routine, so it may seem a little pointless to
optimize, it is heavily used by igt to idle the driver and HW between
every test. As such, speeding it from 40ms to 40us on a plain Broadwell
system is beneficial overall.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: J
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, January 30, 2018 8:53 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v3] drm/i915: Fix Limited Rang
From: Johnson Lin
Some panels support limited range output (16-235) compared
to full range RGB values (0-255). Also userspace can control
the RGB range using "Broadcast RGB" property. Currently the
code to handle full range to limited range is broken. This
patch fixes the same by properly scaling
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_flip:
Subgroup wf_vb
Quoting Imre Deak (2018-01-30 14:29:39)
> There is no requirement for doing the PCODE request polling atomically,
> so do that only for a short time switching to sleeping poll afterwards.
> The specification requires a 150usec timeout for the change notification,
> so let's use that for the atomic
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, December 22, 2017 9:43 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited R
On Tue, Jan 30, 2018 at 08:49:22PM +0530, Uma Shankar wrote:
> From: Johnson Lin
>
> Some panels support limited range output (16-235) compared
> to full range RGB values (0-255). Also userspace can control
> the RGB range using "Broadcast RGB" property. Currently the
> code to handle full range
On Tue, Jan 30, 2018 at 04:05:20PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7.
>
> For level 0 the number of lines is ignored, so always write 0 there
> to prevent overflowing the 5 bits value.
>
> This is required to
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_sysfs_edid_timing:
On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote:
> HDCP was a bit too chatty to get along with the rest of the i915 driver.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Sean Paul
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 9 +
> 1 file change
From: Johnson Lin
Some panels support limited range output (16-235) compared
to full range RGB values (0-255). Also userspace can control
the RGB range using "Broadcast RGB" property. Currently the
code to handle full range to limited range is broken. This
patch fixes the same by properly scaling
On Tue, Jan 16, 2018 at 02:05:30PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915: Add display WA #1175 for
> planes ending close to right screen edge
> URL : https://patchwork.freedesktop.org/series/36526/
> State : failure
The failures look
According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7.
For level 0 the number of lines is ignored, so always write 0 there
to prevent overflowing the 5 bits value.
This is required to make NV12 work.
Signed-off-by: Maarten Lankhorst
Cc: Ville Syrjälä
---
driver
On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote:
>
> Thanks all,
>
> I don't really read much opposition to the current patch series. If
> anything we could actually want to do more it seems.
> It would be good to have the green light and land that.
> I've played quickly with a Chris'
HDCP was a bit too chatty to get along with the rest of the i915 driver.
Suggested-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_hdcp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i
There is no requirement for doing the PCODE request polling atomically,
so do that only for a short time switching to sleeping poll afterwards.
The specification requires a 150usec timeout for the change notification,
so let's use that for the atomic poll. Do the extra 2ms poll - needed as
a workar
The commit below returned earlier than before, but failed to move the
info message when authenticating without downstream devices. This patch
restores the message on authentication success.
Changes in v2:
- s/no downstream devices/no repeater present/ (Ram)
Fixes: 87eb3ec818fa ("drm/i915: II stag
Currently we see sporadic timeouts during CDCLK changing both on BXT and
GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
changing the frequency in a tight loop after blanking the display. The
upper bound for the completion time is 800us based on my tests, so
increase it from
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)
URL : https://patchwork.freedesktop.org/series/36068/
State : failure
== Summary ==
Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/2/mbox
On Tue, Jan 30, 2018 at 09:35:34AM +0100, Daniel Vetter wrote:
> On Mon, Jan 22, 2018 at 12:55:00PM -0500, Sean Paul wrote:
> > The commit below returned earlier than before, but failed to move the
> > info message when authenticating without downstream devices. This patch
> > restores the message
On Tue, Jan 30, 2018 at 03:42:45PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote:
> > Currently we see sporadic timeouts during CDCLK changing both on BXT and
> > GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> > changing the frequ
On Tue, Jan 30, 2018 at 02:54:11PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7, so correctly apply the check there.
The register still has only 5 bits for the line watermark. However the
spec says "Hardware ignores the l
== Series Details ==
Series: drm/i915: Enable debugobjects for request validation (rev3)
URL : https://patchwork.freedesktop.org/series/37240/
State : failure
== Summary ==
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Subgrou
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()
https://patchwork.freedesktop.org/api/1.0/series/373
According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7, so correctly apply the check there.
This is required to make NV12 work.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the CNL patch by Nanley Chery.
v2: Rebase.
Cc: Anuj Phogat
Cc: Nanley Chery
Cc: Rodrigo Vivi
Requested-by: Anuj Phogat
Tested-by: Anuj Phogat
Reviewed-by: Rodrigo Vivi
From: James Ausmus
ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.
v2: No changes
v3:
From: Mahesh Kumar
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra pare
From: Mahesh Kumar
We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar
Reviewed-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 766f4fdd
From: Mahesh Kumar
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by:
From: Kelvin Gardiner
This patch clears a single bit. The bit is 0 by default but expected
not to be set. Explicitly clearing the bit in this patch is intended
to indicate some thinking has occurred, and that we want this bit
cleared and we are not just excepting the default value.
We also stop
From: Mahesh Kumar
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it co
From: Mahesh Kumar
GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already says.
Reviewed-by: Paulo
These patches were part of the other ICL series that arrived on the
list a few days ago, they already received public reviews. They should
be good to go, but let's see what the CI system has to say about them
first.
James Ausmus (1):
drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Kelvin G
On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote:
> Currently we see sporadic timeouts during CDCLK changing both on BXT and
> GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> changing the frequency in a tight loop after blanking the display. The
> upper bound for
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()
https://patchwork.freedesktop.org/api/1.0/series/373
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)
URL : https://patchwork.freedesktop.org/series/36068/
State : warning
== Summary ==
Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/2/mbox
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/r
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