[PATCH] allow CPUID vendor override

KVM will always report the vendor ID of the physical CPU it is running on. Allow to override this if explicitly requested on the command line. It will not suffice to name a CPU type (like -cpu phenom), but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD Signed-off-by: Andre

[PATCH 1/2] use explicit 64bit storage for sysenter values

Since AMD does not support sysenter in 64bit mode, the VMCB fields storing the MSRs are truncated to 32bit upon VMRUN/#VMEXIT. So store the values in a separate 64bit storage to avoid truncation. Signed-off-by: Christoph Egger --- arch/x86/kvm/kvm_svm.h |4 arch/x86/kvm/svm.c | 12

[PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

y sketched by Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-of

Re: [PATCH 2/2] add sysenter/syscall emulation for 32bit compat mode

ode out of the switch and into separate functions. Ok, will do. Thanks for the review! Renewed patch will follow. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord..

[PATCH] move performance counter MSR access interception to generic x86 KVM path

something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 16 arch/x86/kvm/vmx.c | 12 arch/x86/kvm/

[PATCH] add sysenter/syscall emulation for 32bit compat mode

Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. Signed-off-by: Amit Shah Sig

Re: [PATCH] add sysenter/syscall emulation for 32bit compat mode

Amit Shah wrote: Hi Andre, On (Tue) Jun 16 2009 [15:25:13], Andre Przywara wrote: sysenter/sysexit are not supported on AMD's 32bit compat mode, whereas syscall is not supported on Intel's 32bit compat mode. To allow cross vendor migration we emulate the missing instructions by sett

[PATCH 0/6] add sysenter/syscall emulation for 32bit compat mode

Amit Shah, it was completed, debugged, syscall added and made-to-work by Christoph Egger and polished up by Andre Przywara. Please note that sysret does not need to be emulated, because it will be exectued in 64bit mode and returning to 32bit compat mode works on Intel. This has been tested with GE

[PATCH 1/6] allow emulation of syscalls instructions on #UD

Add the opcodes for syscall, sysenter and sysexit to the list of instructions handled by the undefined opcode handler. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 33 ++--- 1 files changed, 26

[PATCH 2/6] add missing EFLAGS bit definitions

Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm/x86_emulate.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/x86_emulate.c index 22c765d..e387c83 100644 --- a/arch/x86

[PATCH 3/6] prepare for emulation of syscall instructions

Add the flags needed for syscall, sysenter and sysexit to the opcode table. Catch (but for now ignore) the opcodes in the emulation switch/case. Signed-off-by: Andre Przywara Signed-off-by: Amit Shah Signed-off-by: Christoph Egger --- arch/x86/kvm/x86_emulate.c | 17 +++-- 1

[PATCH 5/6] add sysenter emulation

Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 4/6] add syscall emulation

Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. Signed-off-by: Christoph Egger Signed-off-by: Andre Przywara

[PATCH 6/6] add sysexit emulation

Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara

Re: [PATCH 4/6] add syscall emulation

Avi Kivity wrote: On 06/17/2009 04:50 PM, Andre Przywara wrote: +static inline void +setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, +struct kvm_segment *cs, struct kvm_segment *ss) +{ +memset(cs, 0, sizeof(struct kvm_segment)); +kvm_x86_ops->get_segment(ctxt->vc

[PATCH 4/6 v2] add syscall emulation

Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. Signed-off-by: Christoph Egger Signed-off-by: Andre Przywara

[PATCH 5/6 v2] add sysenter emulation

Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 6/6 v2] add sysexit emulation

Handle #UD intercept of the sysexit instruction in 64bit mode returning to 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by: Christoph Egger Signed-off-by: Amit Shah Signed-off-by: Andre Przywara

[PATCH] fix renamed MSR_K8_HWCR name

The definition of MSR_K8_HWCR was removed upstream in favor of MSR_K7_HWCR. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index c283201..481010c 100644 --- a/arch/x86/kvm

[PATCH 1/2] allow hypervisor CPUID bit to be overriden

. Signed-off-by: Andre Przywara --- target-i386/helper.c | 25 + 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 8a76abd..529f962 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -44,7 +44,7

[PATCH 2/2] introduce -cpu host target

27;, which will propagate the host's CPUID bits to the guest. Problematic bits can still be turned off by using the existing syntax (-cpu host,-skinit) Signed-off-by: Andre Przywara --- target-i386/helper.c | 65 + 1 files changed, 59 insertions(+

[PATCH 1/2] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH 2/2] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 1/2 v2] allow hypervisor CPUID bit to be overriden

disable it by using: -cpu qemu64,-hypervisor Fix some whitespace damage on the way. Signed-off-by: Andre Przywara --- target-i386/helper.c | 23 +++ 1 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 8a76abd

[PATCH 2/4] ignore reads from AMDs C1E enabled MSR

If the Linux kernel detects an C1E capable AMD processor (K8 RevF and higher), it will access a certain MSR on every attempt to go to halt. Explicitly handle this read and return 0 to let KVM run a Linux guest with the native AMD host CPU propagated to the guest. Signed-off-by: Andre Przywara

[PATCH 3/4] ignore PCI ECS I/O enablement

Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore this write attempt. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 ++ 1 files changed, 2 insertions(

[PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7 @@ static void do_cpuid_ent

[PATCH 1/4] ignore AMDs HWCR register access to set the FFDIS bit

Linux tries to disable the flush filter on all AMD K8 CPUs. Since KVM does not handle the needed MSR, the injected #GP will panic the Linux kernel. Ignore setting of the HWCR.FFDIS bit in this MSR to let Linux boot with an AMD K8 family guest CPU. Signed-off-by: Andre Przywara --- arch/x86/kvm

Re: [PATCH 2/2] introduce -cpu host target

Avi Kivity wrote: On 06/23/2009 12:47 AM, Andre Przywara wrote: Should we ignore unhandled MSRs like QEMU or Xen do? Ignoring unhandled msrs is dangerous. If a write has some effect the guest depends on, and we're not emulating that effect, the guest will fail. Similarly if you

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Avi Kivity wrote: On 06/24/2009 01:44 PM, Andre Przywara wrote: Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e6e61ee..6ad0f93 100644 --- a/arch/x86/kvm/x86.c +++ b

Re: [PATCH 4/4] dont trim the guest's hypervisor CPUID bit in KVM if the guest requests it

Andre Przywara wrote: Avi Kivity wrote: --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1415,7 +1415,7 @@ static void do_cpuid_ent(struct -0 /* Reserved, XSAVE, OSXSAVE */; +0 /* Reserved, XSAVE, OSXSAVE */ | F(HYPERVISOR); I think this should be handled in qemu, since

[PATCH 3/4] ignore PCI ECS I/O enablement

Linux guests will try to enable access to the extended PCI config space via the I/O ports 0xCF8/0xCFC on AMD Fam10h CPU. Since we (currently?) don't use ECS, simply ignore write and read attempts. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |3 +++ 1 files changed, 3 inser

[Qemu-devel] KVMs default CPU type (was: allow sysenter on 32bit guests running on vmx host)

tored when saving/migrating and loaded exactly the same on other hosts, when it's technically possible. You do not want to use -cpu host if you plan to migrate, another safer CPU type should be used then (the aforementioned -cpu migrate). Although preserving the boot CPU's vendor/family/

[PATCH] introduce module parameter for ignoring unknown MSRs accesses

reads will return 0, while MSR writes are simply dropped. In both cases we print a message to dmesg to inform the user about that. You can change the behaviour at any time by saying: # echo 1 > /sys/modules/kvm/parameters/ignore_msrs Signed-off-by: Andre Przywara --- arch/x86/kvm

[PATCH] qemu-kvm: fix KVMs GET_SUPPORTED_CPUID feature usage

the host and helps to use -cpu host. Signed-off-by: Andre Przywara --- qemu-kvm-x86.c | 21 +++-- 1 files changed, 11 insertions(+), 10 deletions(-) Hi, this is a port of patch 4/6 of my "-cpu host" series for QEMU. The bug is similar, although the fix is a dif

[PATCH] add KVM module parameters documentation

Signed-off-by: Andre Przywara --- Documentation/kernel-parameters.txt | 38 +++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index d77fbd8..097ea9f 100644 --- a

[PATCH] fix AMD Fam10h unhandled MSRs

onfig space accesses, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/x86

[PATCH] qemu-kvm: remove CPUID host hacks

KVM provides an in-kernel feature to disable CPUID bits that are not present in the current host. So there is no need here to duplicate this work. Additionally allows 3DNow! on capable processors, since the restriction seems to apply to QEMU/TCG only. Signed-off-by: Andre Przywara --- target

target-i386/kvm.c vs. qemu-kvm-x86.c

e is not triggered. What is the future of these two files? Will one vanish? Will they be merged? Where to put new features in? Thanks and regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a

[PATCH] fix MMIO_CONF_BASE MSR access

Some Windows versions check whether the BIOS has setup MMI/O for config space accesses on AMD Fam10h CPUs, we say "no" by returning 0 on reads and only allow disabling of MMI/O CfgSpace setup by igoring "0" writes. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.

[PATCH] qemu-kvm: preserve the hypervisor bit while KVM trims the CPUID bits

in qemu-kvm-x86.c, too. Signed-off-by: Andre Przywara --- qemu-kvm-x86.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86.c index d6735c1..b02e604 100644 --- a/qemu-kvm-x86.c +++ b/qemu-kvm-x86.c @@ -1211,8 +1211,13 @@ int

[PATCH v2] qemu-kvm: preserve the hypervisor bit while KVM trims the CPUID bits

in qemu-kvm-x86.c, too. Signed-off-by: Andre Przywara --- qemu-kvm-x86.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) The last patch had a typo (and I compile tested the wrong branch), so here is the correct version. Regards, Andre. diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86

[PATCH] qemu-kvm: remove "KVM misreports CPUID" hack

This should be no longer necessary. Effectively reverts 143eb2bd043e82bcf353cf82d33c127f06411d82. Signed-off-by: Andre Przywara --- kvm/libkvm/libkvm-x86.c |9 - qemu-kvm-x86.c |9 - 2 files changed, 0 insertions(+), 18 deletions(-) Hi Avi, I am not sure what

[PATCH] handle AMD microcode MSR

Windows 7 tries to update the CPU's microcode on some processors, so we ignore the MSR write here. The patchlevel register is already handled (returning 0), because the MSR number is the same as Intel's. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |1 + 1 files

[RFC] allow multi-core guests: introduce cores= option to -cpu

mp 16 -cpu host,cores=8 with WindowsXP Pro. Regards, Andre. Signed-off-by: Andre Przywara --- target-i386/cpu.h|1 + target-i386/helper.c | 26 -- 2 files changed, 25 insertions(+), 2 deletion

Re: [RFC] allow multi-core guests: introduce cores= option to -cpu

Brian Jackson wrote: Andre Przywara wrote: currently SMP guests happen to see vCPUs as different sockets. Some guests (Windows comes to mind) have license restrictions and refuse to run on multi-socket machines. So lets introduce a "cores=" parameter to the -cpu option to let the us

Re: [Qemu-devel] [RFC] allow multi-core guests: introduce cores= option to -cpu

Samuel Thibault wrote: Andre Przywara, le Fri 03 Jul 2009 16:41:56 +0200, a écrit : -smp 16 -cpu host,cores=8 That means 8 cores with 2 threads each, thus 16 threads? No, that meant: 16 vCPUs total with 8 cores per physical packages. I don't have any notion for threads in the current

Re: [Qemu-devel] [RFC] allow multi-core guests: introduce cores= option to -cpu

cores=2 to specify a dual core guest. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More maj

Re: kvm guest for 486 sx

ge it), then inject #NM into the guest? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b. Muenchen Gescha

[PATCH v2] add KVM module parameters documentation

Signed-off-by: Andre Przywara --- Documentation/kernel-parameters.txt | 39 +++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index d77fbd8..8ca488d 100644 --- a

Re: This combination of AMDprocessors is not suitable for SMP?

this warning, as it only applies to non-KVM capable processors and has no meaning for virtual SMP anyway. If you like this warning to disappear, you can use "-cpu host" (and probably loose migration capability) or wait for the new safe64 CPU type, which will use family 15 instea

unconditional CPUID propagation?

dress this. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: OpenBSD 5.0 kernel panic in AMD K10 cpu power state

uld end up emulating them, too. I have a hard time to think about a strategy how to emulate this in general. So unless there is a real framework for dealing with P-state "hints" from the guest OS, I'd be reluctant with quick and dirty emulations. Thanks, Andre. -- Andre Przywara

[PATCH] kvm/svm: fix DR interception handling on upcoming AMD CPUs

Somehow the code line advancing the RIP and checking for exceptions got dropped between the post on the ML and the commit. Add it again to let guests boot on upcoming AMD CPUs again. Reported-by: Joerg Roedel Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |1 + 1 files changed, 1

Re: [PATCH] kvm/svm: fix DR interception handling on upcoming AMD CPUs

Roedel, Joerg wrote: On Tue, Feb 08, 2011 at 07:22:29PM -0500, Andre Przywara wrote: Somehow the code line advancing the RIP and checking for exceptions got dropped between the post on the ML and the commit. Add it again to let guests boot on upcoming AMD CPUs again. Reported-by: Joerg Roedel

[PATCH 1/2] kvm/x86: fix XSAVE bit scanning

s and simply skip zero ones to also cover later features. CC: [2.6.38] Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index bfd7763..6e86cec 100644 --- a/arch/x86/kvm/x86.c

[PATCH 2/2] kvm/x86: remove unneeded substitute search for missing CPUID entries

rs of this function can all deal with the no-match situation. So lets remove this code, as it serves no purpose. This fixes a crash of newer Linux kernels as KVM guests on AMD Bulldozer CPUs, where bogus values were returned in response to a CPUID intercept. CC: [2.6.38] Signed-off-by: Andre Prz

Re: [PATCH 2/2] kvm/x86: remove unneeded substitute search for missing CPUID entries

Avi Kivity wrote: On 03/30/2011 03:01 PM, Andre Przywara wrote: If KVM cannot find an exact match for a requested CPUID leaf, the code will try to find the closest match instead of simply confessing it's failure. The heuristic is on one hand wrong nowadays, since it does not take the KVM

[PATCH 2/2] kvm/x86: move and fix substitue search for missing CPUID entries

here bogus values were returned in response to a CPUID intercept. CC: [2.6.38] Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 19 +-- 1 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6e86cec..552b8f8 100644 ---

Re: [PATCH 2/2] kvm/x86: move and fix substitue search for missing CPUID entries

Avi Kivity wrote: On 03/31/2011 03:13 PM, Andre Przywara wrote: If KVM cannot find an exact match for a requested CPUID leaf, the code will try to find the closest match instead of simply confessing it's failure. The implementation was meant to satisfy the CPUID specification, but di

[PATCH 2/2 v3] kvm/x86: move and fix substitue search for missing CPUID entries

here bogus values were returned in response to a CPUID intercept. CC: [2.6.38] Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c | 31 +-- 1 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6e86cec..a38f

Re: Semantics of "-cpu host" (was Re: [Qemu-devel] [PATCH 2/2] Expose tsc deadline timer cpuid to guest)

d on either case, but first we need to figure out what are the expectations/requirements, to know _which_ changes will be needed. On Tue, Apr 24, 2012 at 02:19:25PM -0300, Eduardo Habkost wrote: (CCing Andre Przywara, in case he can help to clarify what's the expected meaning of "-cpu ho

Re: AMD SVM specification

/lkml.org/lkml/2011/6/22/20] Any help will be appreciated. Prateek -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majo

[PATCH] kvm/x86: enlarge number of possible CPUID leaves

Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara --- arch/x86/include/asm/kvm_host.h

Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

Avi Kivity wrote: On 12/01/2010 01:17 PM, Andre Przywara wrote: Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors

[PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/include/asm/svm.h |2

[PATCH 3/5] kvm/svm: enhance mov DR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 55

[PATCH 1/5] kvm/svm: add new SVM feature bit names

the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86

[PATCH 5/5] kvm/svm: copy instruction bytes from VMCB

In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by: Andre Przywara --- arch/x86

[PATCH 4/5] kvm/svm: implement enhanced INVLPG intercept

When the DecodeAssist feature is available, the linear address is provided in the VMCB on INVLPG intercepts. Use it directly to avoid any decoding and emulation. This is only useful for shadow paging, though. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |7 ++- 1 files changed

[PATCH 0/5] kvm/svm: implement new DecodeAssist features

Hi, upcoming AMD CPUs will have a SVM enhancement called DecodeAssist which will provide more information when intercepting certain events. These information allows to skip the instruction fetching and decoding and handle the intercept immediately. This patch set implements all the features which

Re: [PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Avi Kivity wrote: On 12/07/2010 12:59 PM, Andre Przywara wrote: Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed

Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara --- arch/x86/include/asm/kvm_host.h |2 +- 1 files changed, 1 insertions

[PATCH] kvm: cleanup CR8 handling

The handling of CR8 writes in KVM is currently somewhat cumbersome. This patch makes it look like the other CR register handlers and fixes a possible issue in VMX, where the RIP would be incremented despite an injected #GP. Signed-off-by: Andre Przywara --- arch/x86/include/asm/kvm_host.h

[PATCH 5/5] kvm/svm: copy instruction bytes from VMCB

In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by: Andre Przywara --- arch/x86

[PATCH -v2 0/5] kvm/svm: implement new DecodeAssist features

Hi, version 2 of the DecodeAssist patches. Changes over version 1: - goes on top of the CR8 handling fix I sent out earlier this week (required for proper handling of CR8 exceptions) - handles exception cases properly (for mov cr and mov dr) - uses X86_FEATURE_ names instead of SVM_FEATURE names

[PATCH 1/5] kvm/svm: add new SVM feature bit names

the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86

[PATCH 3/5] kvm/svm: enhance mov DR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 61

[PATCH 4/5] kvm/svm: implement enhanced INVLPG intercept

When the DecodeAssist feature is available, the linear address is provided in the VMCB on INVLPG intercepts. Use it directly to avoid any decoding and emulation. This is only useful for shadow paging, though. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |7 ++- 1 files changed

[PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/include/asm/svm.h |2

Re: [PATCH 3/5] kvm/svm: enhance mov DR intercept handler

Avi Kivity wrote: On 12/10/2010 03:51 PM, Andre Przywara wrote: Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided

Re: [PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Marcelo Tosatti wrote: On Fri, Dec 10, 2010 at 02:51:25PM +0100, Andre Przywara wrote: Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the

[PATCH -v3 0/8] kvm/svm: implement new DecodeAssist features

Hi, this is version 3 of the DecodeAssist patches. I added 3 clean up patches which are not SVM specific. Changes between v2 and v3: - now includes the (unchanged) CR8 handling fix - move complete_insn_gp() helper function into x86.c - remove unnecessary comment - fix handling of illegal CR access

[PATCH 6/8] kvm/svm: enhance mov DR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c | 57

[PATCH 4/8] kvm/svm: add new SVM feature bit names

the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86

[PATCH 8/8] kvm/svm: copy instruction bytes from VMCB

In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by: Andre Przywara --- arch/x86

[PATCH 2/8] kvm: move complete_insn_gp() into x86.c

move the complete_insn_gp() helper function out of the VMX part into the generic x86 part to make it usable by SVM. Signed-off-by: Andre Przywara --- arch/x86/include/asm/kvm_host.h |2 ++ arch/x86/kvm/vmx.c | 16 arch/x86/kvm/x86.c |9

[PATCH 3/8] kvm: cleanup emulate_instruction

emulate_instruction had many callers, but only one used all parameters. One parameter was unused, another one is now hidden by a wrapper function (required for a future addition anyway), so most callers use now a shorter parameter list. Signed-off-by: Andre Przywara --- arch/x86/include/asm

[PATCH 1/8] kvm: fix CR8 handling

The handling of CR8 writes in KVM is currently somewhat cumbersome. This patch makes it look like the other CR register handlers and fixes a possible issue in VMX, where the RIP would be incremented despite an injected #GP. Signed-off-by: Andre Przywara --- arch/x86/include/asm/kvm_host.h

[PATCH 7/8] kvm/svm: implement enhanced INVLPG intercept

When the DecodeAssist feature is available, the linear address is provided in the VMCB on INVLPG intercepts. Use it directly to avoid any decoding and emulation. This is only useful for shadow paging, though. Signed-off-by: Andre Przywara --- arch/x86/kvm/svm.c |7 ++- 1 files changed

[PATCH 5/8] kvm/svm: enhance MOV CR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara --- arch/x86/include/asm/svm.h |2

Re: [PATCH] kvm: cleanup CR8 handling

Avi Kivity wrote: On 12/08/2010 01:27 PM, Andre Przywara wrote: The handling of CR8 writes in KVM is currently somewhat cumbersome. This patch makes it look like the other CR register handlers and fixes a possible issue in VMX, where the RIP would be incremented despite an injected #GP

[PATCH] KVM: fix XSAVE bit scanning (now properly)

x27;s array indicies and fills the entry before querying it's value. This fixes AVX support in KVM guests. Signed-off-by: Andre Przywara --- arch/x86/kvm/x86.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 694538

[PATCH] QEMU: Fix KVM XSAVE feature bit enumeration

When iterating through the XSAVE feature enumeration CPUID leaf (0xD) we should not stop at the first zero EAX, but instead keep scanning since there are gaps in the enumeration (ECX=1 for instance). This fixes the proper usage of AVX in KVM guests. Signed-off-by: Andre Przywara --- target-i386

[PATCH] KVM: Fix XSAVE feature bit enumeration

When iterating through the XSAVE feature enumeration CPUID leaf (0xD) we should not stop at the first zero EAX, but instead keep scanning since there are gaps in the enumeration (ECX=1 for instance). This fixes the proper usage of AVX in KVM guests. Signed-off-by: Andre Przywara --- target-i386

Re: [RFC PATCH] Emulate MOVBE

On Wed, 10 Apr 2013 01:46:02 +0200 Borislav Petkov wrote: > Hi guys, > > so I was trying to repro tglx's bug in smpboot.c and for some reason, > the most reliable way to trigger it was to boot an 32-bit atom smp > guest in kvm (don't ask :)). > > The problem, however, was that atom wants MOVBE

Re: [RFC PATCH] Emulate MOVBE

On Wed, 10 Apr 2013 13:08:46 +0300 Gleb Natapov wrote: > On Wed, Apr 10, 2013 at 11:29:42AM +0200, Andre Przywara wrote: > > In a real world VendorSpecific should be replaced with something > > more meaningful. Depends on KVMs intention to emulate instructions, > > actual

[PATCH 07/14] arm/arm64: KVM: make the value of ICC_SRE_EL1 a per-VM variable

registers on a world switch, but actually disallow a guest to change it by only restoring a fixed, once-initialized value. This value depends on the GIC model userland has chosen for a guest. Signed-off-by: Andre Przywara --- arch/arm64/kernel/asm-offsets.c |1 + arch/arm64/kvm/vgic-v3-switch.S

[PATCH 12/14] arm/arm64: KVM: add SGI system register trapping

-by: Andre Przywara --- arch/arm/kvm/coproc.c | 19 +++ arch/arm64/kvm/sys_regs.c | 26 ++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index c58a351..4adadb7 100644 --- a/arch/arm/kvm/coproc.c +++ b

[PATCH 11/14] arm/arm64: KVM: add virtual GICv3 distributor emulation

into a new file (vgic-v3-emul.c). Signed-off-by: Andre Przywara --- arch/arm64/kvm/Makefile|1 + include/kvm/arm_vgic.h | 11 +- include/linux/irqchip/arm-gic-v3.h | 26 ++ include/linux/kvm_host.h |1 + include/uapi/linux/kvm.h |1

  1   2   3   4   5   6   7   >