Hi,
I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
mode). Bisecting the guest shows that the problem shows up at
91ef84428a86b75a52e15c6fe4f56b446ba75f93
irqchip/gic-v3: Reset BPR during initialization
If I remove the write to the ICC_BPR1_EL1 register on guest, the VM
+Robert
On 21/10/16 08:01, Auger Eric wrote:
> Hi,
>
> I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
> mode). Bisecting the guest shows that the problem shows up at
>
> 91ef84428a86b75a52e15c6fe4f56b446ba75f93
> irqchip/gic-v3: Reset BPR during initialization
>
> If I
Hi Marc,
On 21/10/2016 10:45, Marc Zyngier wrote:
> +Robert
>
> On 21/10/16 08:01, Auger Eric wrote:
>> Hi,
>>
>> I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
>> mode). Bisecting the guest shows that the problem shows up at
>>
>> 91ef84428a86b75a52e15c6fe4f56b446ba75f9
GITS_BASER's Entry Size is much smaller than 64-bit, but when it
used as a divider it forces compiler to generate __aeabi_uldivmod if
build in 32-bit mode. So, casting it to int (like it is done in other
places) where used as a divider would give a hint to compiler that
32-bit division can be used.
Hi,
This series introduces GICv3 ITS and vITS to 32-bit world. The first
six patches make it possible to use ITS in a 32-bit guest with vITS on
64-bit host. The last two patches extend vITS to 32-bit host.
I used Andrea's its/v8 branch at [1] for testing with the following
diff on top
diff --git
This patch allows to build and use vGICv3 ITS in 32-bit mode.
Signed-off-by: Vladimir Murzin
---
Documentation/virtual/kvm/api.txt |2 +-
arch/arm/include/uapi/asm/kvm.h |2 ++
arch/arm/kvm/Kconfig|1 +
arch/arm/kvm/Makefile |1 +
arch/arm/kvm/
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin
---
arch/arm64/include/asm/arch_gicv3.h | 16
drivers/irqchip/irq-gic-v3-its.c| 30
Make sure that constants which are supposed to be applied on 64-bit
data is actually unsigned long long, so they won't be truncated when
used in 32-bit mode.
Signed-off-by: Vladimir Murzin
---
drivers/irqchip/irq-gic-v3-its.c | 28 ++--
include/linux/irqchip/arm-gic-v
Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so
GICv3 ITS gets all it needs to be built and run.
Signed-off-by: Vladimir Murzin
---
arch/arm/include/asm/arch_gicv3.h | 59 -
1 file changed, 52 insertions(+), 7 deletions(-)
diff --git a
This patch allows ARM guests to use GICv3 ITS on an arm64 host
Signed-off-by: Vladimir Murzin
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529f..caef684 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -703,6 +703
Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER's
Entry Size is 5-bit wide only), so when used as divider no reference
to __aeabi_uldivmod is generated when build for AArch32.
Use unsigned long long for GITS_BASER_PAGE_SIZE_* since they are
used in conjunction with 64-bit data.
Sig
It'd be better to switch to CMA... but before that done redirect
flush_dcache operation, so 32-bit implementation could be wired
latter.
Signed-off-by: Vladimir Murzin
---
arch/arm64/include/asm/arch_gicv3.h |3 +++
drivers/irqchip/irq-gic-v3-its.c| 17 -
2 files change
On 21/10/16 10:05, Auger Eric wrote:
> Hi Marc,
>
> On 21/10/2016 10:45, Marc Zyngier wrote:
>> +Robert
>>
>> On 21/10/16 08:01, Auger Eric wrote:
>>> Hi,
>>>
>>> I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
>>> mode). Bisecting the guest shows that the problem shows up
Hi Marc,
On 21/10/2016 11:40, Marc Zyngier wrote:
> On 21/10/16 10:05, Auger Eric wrote:
>> Hi Marc,
>>
>> On 21/10/2016 10:45, Marc Zyngier wrote:
>>> +Robert
>>>
>>> On 21/10/16 08:01, Auger Eric wrote:
Hi,
I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
>>
Hi,
On 21/10/16 10:36, Vladimir Murzin wrote:
> Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER's
> Entry Size is 5-bit wide only), so when used as divider no reference
> to __aeabi_uldivmod is generated when build for AArch32.
>
> Use unsigned long long for GITS_BASER_PAGE_SIZE_*
On 21/10/16 09:45, Marc Zyngier wrote:
+Robert
On 21/10/16 08:01, Auger Eric wrote:
Hi,
I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi
mode). Bisecting the guest shows that the problem shows up at
91ef84428a86b75a52e15c6fe4f56b446ba75f93
irqchip/gic-v3: Reset BPR dur
Hi,
On 21/10/16 10:36, Vladimir Murzin wrote:
> This patch allows to build and use vGICv3 ITS in 32-bit mode.
Ah, what a relief to see that config option go. Thanks for that!
I quickly booted an ITS guest on a (64-bit) model and couldn't spot any
regressions.
> Signed-off-by: Vladimir Murzin
On 21/10/16 10:49, Andre Przywara wrote:
> Hi,
>
> On 21/10/16 10:36, Vladimir Murzin wrote:
>> Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER's
>> Entry Size is 5-bit wide only), so when used as divider no reference
>> to __aeabi_uldivmod is generated when build for AArch32.
>>
>>
On 21/10/16 12:02, Andre Przywara wrote:
> Hi,
>
> On 21/10/16 10:36, Vladimir Murzin wrote:
>> This patch allows to build and use vGICv3 ITS in 32-bit mode.
>
> Ah, what a relief to see that config option go. Thanks for that!
>
> I quickly booted an ITS guest on a (64-bit) model and couldn't sp
On Fri, Oct 21, 2016 at 11:46:04AM +0200, Auger Eric wrote:
> Hi Marc,
> On 21/10/2016 11:40, Marc Zyngier wrote:
> > On 21/10/16 10:05, Auger Eric wrote:
> >> Hi Marc,
> >>
> >> On 21/10/2016 10:45, Marc Zyngier wrote:
> >>> +Robert
> >>>
> >>> On 21/10/16 08:01, Auger Eric wrote:
> Hi,
> >>>
On 21 October 2016 at 12:49, Andrew Jones wrote:
> I also read the register before writing it and saw it was 3. I tried
> writing 3 instead of 0 to see what would happen, but the failure
> persisted. I did read back the register after writing it to confirm the
> change took affect.
So what does i
On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote:
> On 21 October 2016 at 12:49, Andrew Jones wrote:
> > I also read the register before writing it and saw it was 3. I tried
> > writing 3 instead of 0 to see what would happen, but the failure
> > persisted. I did read back the registe
Hi Andre,
On Thu, Oct 20, 2016 at 06:29:01PM +0100, Andre Przywara wrote:
> Hi Drew,
>
> On 15/07/16 14:00, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones
> >
> > ---
> > v2: configure irqs as NS GRP1
> > ---
> > lib/arm/asm/arch_gicv3.h | 184 ++
> > lib/arm/as
On 21/10/16 13:07, Andrew Jones wrote:
> On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote:
>> On 21 October 2016 at 12:49, Andrew Jones wrote:
>>> I also read the register before writing it and saw it was 3. I tried
>>> writing 3 instead of 0 to see what would happen, but the failure
On 21 October 2016 at 13:52, Marc Zyngier wrote:
> diff --git a/arch/arm/include/asm/arch_gicv3.h
> b/arch/arm/include/asm/arch_gicv3.h
> index a808829..5c03171 100644
> --- a/arch/arm/include/asm/arch_gicv3.h
> +++ b/arch/arm/include/asm/arch_gicv3.h
> @@ -222,6 +222,11 @@ static inline void gic
On Fri, Oct 21, 2016 at 01:52:43PM +0100, Marc Zyngier wrote:
> On 21/10/16 13:07, Andrew Jones wrote:
> > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote:
> >> On 21 October 2016 at 12:49, Andrew Jones wrote:
> >>> I also read the register before writing it and saw it was 3. I tried
On Fri, 21 Oct 2016 13:58:47 +0100
Peter Maydell wrote:
> On 21 October 2016 at 13:52, Marc Zyngier wrote:
> > diff --git a/arch/arm/include/asm/arch_gicv3.h
> > b/arch/arm/include/asm/arch_gicv3.h
> > index a808829..5c03171 100644
> > --- a/arch/arm/include/asm/arch_gicv3.h
> > +++ b/arch/arm/
On Fri, 21 Oct 2016 15:06:39 +0200
Andrew Jones wrote:
> On Fri, Oct 21, 2016 at 01:52:43PM +0100, Marc Zyngier wrote:
> > On 21/10/16 13:07, Andrew Jones wrote:
> > > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote:
> > >> On 21 October 2016 at 12:49, Andrew Jones wrote:
> >
On 21.10.16 13:52:43, Marc Zyngier wrote:
> On 21/10/16 13:07, Andrew Jones wrote:
> > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote:
> >> On 21 October 2016 at 12:49, Andrew Jones wrote:
> >>> I also read the register before writing it and saw it was 3. I tried
> >>> writing 3 ins
Currently when a RAS error is reported it is not timestamped.
The ACPI 6.1 spec adds the timestamp field to the generic error
data entry v3 structure. The timestamp of when the firmware
generated the error is now being reported.
Signed-off-by: Jonathan (Zhixiong) Zhang
Signed-off-by: Richard Ruig
A RAS (Reliability, Availability, Serviceability) controller
may be a separate processor running in parallel with OS
execution, and may generate error records for consumption by
the OS. If the RAS controller produces multiple error records,
then they may be overwritten before the OS has consumed th
Add support for ARMv8 Common Platform Error Record (CPER).
UEFI 2.6 specification adds support for ARMv8 specific
processor error information to be reported as part of the
CPER records. This provides more detail on for processor error logs.
Signed-off-by: Jonathan (Zhixiong) Zhang
Signed-off-by:
SEA exceptions are often caused by an uncorrected hardware
error, and are handled when data abort and instruction abort
exception classes have specific values for their Fault Status
Code.
When SEA occurs, before killing the process, go through
the handlers registered in the notification list.
Updat
From: "Jonathan (Zhixiong) Zhang"
Even if an error status block's severity is fatal, the kernel does not
honor the severity level and panic.
With the firmware first model, the platform could inform the OS about a
fatal hardware error through the non-NMI GHES notification type. The OS
should pani
ARM APEI extension proposal added SEA (Synchrounous External
Abort) notification type for ARMv8.
Add a new GHES error source handling function for SEA. If an error
source's notification type is SEA, then this function can be registered
into the SEA exception handler. That way GHES will parse and re
UEFI spec allows for non-standard section in Common Platform Error
Record. This is defined in section N.2.3 of UEFI version 2.5.
Currently if the CPER section's type (UUID) does not match with
one of the section types that the kernel knows how to parse, the
section is skipped. Therefore, user is n
When a memory error, CPU error, PCIe error, or other type of hardware error
that's covered by RAS occurs, firmware should populate the shared GHES memory
location with the proper GHES structures to notify the OS of the error.
For example, platforms that implement firmware first handling may impleme
UEFI spec allows for non-standard section in Common Platform Error
Record. This is defined in section N.2.3 of UEFI version 2.5.
Currently if the CPER section's type (UUID) does not match with
any section type that the kernel knows how to parse, trace event
is not generated for such section. And t
Currently there are trace events for the various RAS
errors with the exception of ARM processor type errors.
Add a new trace event for such errors so that the user
will know when they occur. These trace events are
consistent with the ARM processor error section type
defined in UEFI 2.6 spec section
Currently external aborts are unsupported by the guest abort
handling. Add handling for SEAs so that the host kernel reports
SEAs which occur in the guest kernel.
Signed-off-by: Tyler Baicar
---
arch/arm/include/asm/kvm_arm.h | 1 +
arch/arm/include/asm/system_misc.h | 5 +
arch/ar
On Fri, 21 Oct 2016 11:30:12 -0600
Tyler Baicar wrote:
> Currently there are trace events for the various RAS
> errors with the exception of ARM processor type errors.
> Add a new trace event for such errors so that the user
> will know when they occur. These trace events are
> consistent with th
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