Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Mon, Jun 15, 2015 at 01:38:53PM +0200, Boris Brezillon wrote: > Oh right. > I still have trouble understanding the need for the backlog concept > (maybe you can give some insight): the backlog is just another list > where we put all the requests when the queue has exceeded the limit > fixed in c

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Mon, Jun 15, 2015 at 01:31:35PM +0200, Boris Brezillon wrote: > > I haven't found any driver updating the req->info field with the new > IV. Could you point me to one of them. This is an integral part of the API so if any driver isn't doing this then they should be fixed. Ironically the origin

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Boris Brezillon
On Mon, 15 Jun 2015 17:37:54 +0800 Herbert Xu wrote: > On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > > > +static inline int mv_cesa_sg_count(struct scatterlist *sg, int nbytes) > > +{ > > + int nents = 0; > > + > > + while (nbytes > 0) { > > + nents++; > > +

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Boris Brezillon
On Mon, 15 Jun 2015 17:48:27 +0800 Herbert Xu wrote: > On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > > > +static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine *engine) > > +{ > > + struct crypto_async_request *req; > > + struct mv_cesa_ctx *ctx; > > + > > +

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Boris Brezillon
On Mon, 15 Jun 2015 17:54:21 +0800 Herbert Xu wrote: > On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > > > +static int mv_cesa_cbc_aes_op(struct ablkcipher_request *req, > > + struct mv_cesa_op_ctx *tmpl) > > +{ > > + mv_cesa_update_op_cfg(tmpl, CESA

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Boris Brezillon
On Mon, 15 Jun 2015 17:59:44 +0800 Herbert Xu wrote: > On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > +struct ahash_alg mv_ahmac_sha1_alg = { > > + .init = mv_cesa_ahmac_sha1_init, > > + .update = mv_cesa_ahash_update, > > + .final = mv_cesa_ahash_final, > > + .finup

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > +struct ahash_alg mv_ahmac_sha1_alg = { > + .init = mv_cesa_ahmac_sha1_init, > + .update = mv_cesa_ahash_update, > + .final = mv_cesa_ahash_final, > + .finup = mv_cesa_ahash_finup, > + .digest = mv_cesa_ahmac_sha

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > +static int mv_cesa_cbc_aes_op(struct ablkcipher_request *req, > + struct mv_cesa_op_ctx *tmpl) > +{ > + mv_cesa_update_op_cfg(tmpl, CESA_SA_DESC_CFG_CRYPTCM_CBC, > + CESA_SA

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > +static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine *engine) > +{ > + struct crypto_async_request *req; > + struct mv_cesa_ctx *ctx; > + > + spin_lock_bh(&cesa_dev->lock); > + req = crypto_dequeue_reque

Re: [RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-15 Thread Herbert Xu
On Fri, Jun 12, 2015 at 09:15:56AM +0200, Boris Brezillon wrote: > > +static inline int mv_cesa_sg_count(struct scatterlist *sg, int nbytes) > +{ > + int nents = 0; > + > + while (nbytes > 0) { > + nents++; > + nbytes -= sg->length; > + sg = sg_next(sg);

[RESEND PATCH v4 04/14] crypto: add a new driver for Marvell's CESA

2015-06-12 Thread Boris Brezillon
The existing mv_cesa driver supports some features of the CESA IP but is quite limited, and reworking it to support new features (like involving the TDMA engine to offload the CPU) is almost impossible. This driver has been rewritten from scratch to take those new features into account. This commi