Hi Marc,
On 2021/4/15 下午4:11, Marc Zyngier wrote:
Hi Kever,
On Thu, 15 Apr 2021 08:24:33 +0100,
Kever Yang wrote:
Hi Marc, Peter,
RK356x GIC has two issues:
1. GIC only support 32bit address while rk356x supports 8GB DDR SDRAM,
so we use ZONE_DMA32 to fix this issue;
What
Hi Marc, Peter,
RK356x GIC has two issues:
1. GIC only support 32bit address while rk356x supports 8GB DDR SDRAM,
so we use ZONE_DMA32 to fix this issue;
2. GIC version is r1p6-00rel0, RK356x interconnect does not support GIC
and CPU snoop to each other, hence the GIC does not support th
On 2021/3/1 下午2:47, Elaine Zhang wrote:
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang
Patch looks good to me.
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/clk/rockchip/Kconfig |7 +
drivers/clk/rockchip/Makefile |1
On 2021/3/1 下午2:47, Elaine Zhang wrote:
Add the dt-bindings header for the rk3568, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3568.
Signed-off-by: Elaine Zhang
Patch looks good to me.
Reviewed-by: Kever Yang
Thanks,
- Kever
On 2021/3/1 下午2:47, Elaine Zhang wrote:
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang
Patch looks good to me.
Reviewed-by: Kever Yang
Thanks
On 2021/3/1 下午2:47, Elaine Zhang wrote:
Document the device tree bindings of the rockchip Rk3568 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml.
Signed-off-by: Elaine Zhang
Patch looks good to me.
Reviewed-by: Kever Yang <mailto:kever.y...@r
Hi Daniel,
On 2020/10/15 下午11:23, Daniel Vetter wrote:
On Wed, Oct 14, 2020 at 09:48:43AM +0800, Kever Yang wrote:
Hi Maintainers,
Does this patch ready to merge?
Would maybe be good to get some acks from other drivers using this, then
Sandy can push to drm-misc-next.
Thanks for your
if (!of_device_is_available(ep))
+ continue;
+
remote_port = of_graph_get_remote_port(ep);
if (!remote_port) {
of_node_put(ep);
Looks good to me.
Reviewed-by: Kever Yang
Thanks,
- Kever
Hi Miquel and maintainers,
This patch set seems ready for upstream, could you pick and merge
to linux-mtd?
Thanks,
- Kever
On 2020/9/30 上午10:07, Yifeng Zhao wrote:
Rockchp's NFC(Nand Flash Controller) has four versions: V600, V622, V800 and
V900.This series patch can support all four v
Changes in v2: None
arch/arm/boot/dts/rk3036.dtsi | 52 +++
1 file changed, 52 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 093567022386..dda5a1f79aca
, bank);
-
- /* map the gpio irqs here, when the clock is still running */
- for (j = 0 ; j < 32 ; j++)
- irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
trl_drv_unregister);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index a1a08cb9364e..1696ea19488b 100644
--- a/arch/arm/boot
: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3xxx.dtsi | 9 +
1 file changed, 9 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 859a7477909f..97415180d5bb
subpages.
- No support for the builtin randomizer.
- The original bad block mask is not supported. It is recommended to use
the BBT(bad block table).
Signed-off-by: Yifeng Zhao
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v10:
- Fix compile error on master v5.9
title for the dt-bindings.
Changes in v2: None
.../mtd/rockchip,nand-controller.yaml | 162 ++
1 file changed, 162 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
Looks good to me,
Reviewed-by: Kever Yang
Thanks
: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 15 +++
1 file changed, 15 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
b/arch/arm64/boot
in v2: None
arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++
1 file changed, 15 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 2695ea8cda14
)
if (!bank->domain)
return -ENXIO;
+ clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+ clk_disable(bank->clk);
return (virq) ? : -ENXIO;
}
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Looks good to me,
Reviewed-by: Kever Yang
Thanks,
- Kever
diff --git a/MAINTAINERS b/MAINTAINERS
index 190c7fa2ea01..5500df349836 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2382,12 +2382,12 @@ L: linux-arm-ker
(rockchip_register_softrst);
This looks good to me, so
Reviewed-by: Kever Yang
Thanks,
- Kever
(rockchip_clk_register_ddrclk);
This looks good to me, so
Reviewed-by: Kever Yang
Thanks,
- Kever
clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
This looks good to me, so
Reviewed-by: Kever Yang
Thanks,
- Kever
+= clk-rk3036.o
+obj-$(CONFIG_CLK_RK312X)+= clk-rk3128.o
+obj-$(CONFIG_CLK_RK3188)+= clk-rk3188.o
+obj-$(CONFIG_CLK_RK322X)+= clk-rk3228.o
+obj-$(CONFIG_CLK_RK3288)+= clk-rk3288.o
+obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
+obj-$(CONFIG_CLK_RK3328)+= clk-rk3328.o
+obj-$(CONFIG_CLK_RK3368)+= clk-rk3368.o
+obj-$(CONFIG_CLK_RK3399)+= clk-rk3399.o
This looks good to me, so
Reviewed-by: Kever Yang
Thanks,
- Kever
arents,
+ NULL, NULL,
+ &fix->hw, &clk_fixed_factor_ops,
+ &gate->hw, &clk_gate_ops, flags);
+ if (IS_ERR(hw)) {
kfree(fix);
kfree
YMBOL(rockchip_register_restart_notifier);
This looks good to me, so
Reviewed-by: Kever Yang
Thanks,
- Kever
The rk3288 fennec board has been removed, remove the binding document at
the same time.
Signed-off-by: Kever Yang
---
Changes in v2: None
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 -
1 file changed, 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm
Since there is no one using this board, remove it.
Signed-off-by: Kever Yang
---
Changes in v2:
- update document at the same time
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/rk3288-fennec.dts | 347
2 files changed, 348 deletions(-)
delete
On 2019/8/20 下午9:56, Heiko Stuebner wrote:
Hi Kever,
Am Dienstag, 20. August 2019, 12:03:52 CEST schrieb Kever Yang:
Since there is no one using this board, remove it.
so just to elaborate a bit, I guess this board was internal to Rockchip,
never went to the market and therefore is obsolete
Since there is no one using this board, remove it.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288-fennec.dts | 347
1 file changed, 347 deletions(-)
delete mode 100644 arch/arm/boot/dts/rk3288-fennec.dts
diff --git a/arch/arm/boot/dts/rk3288-fennec.dts
b
Hi Heiko,
On 2019/8/16 下午8:24, Heiko Stuebner wrote:
Hi Kever, TL,
[added TL Lim for clarification]
Am Donnerstag, 15. August 2019, 10:12:52 CEST schrieb Kever Yang:
According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is
controlled by USB_20_HOST_DRV, which is the same as
According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is
controlled by USB_20_HOST_DRV, which is the same as VCC_HOST1_5V.
Signed-off-by: Kever Yang
---
Changes in v2:
- remove enable-active-high property
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 11 ++-
1 file
According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is
controlled by USB_20_HOST_DRV, which is the same as VCC_HOST1_5V.
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch
We need to init vop aclk and hclk incase the U-Boot does not do
the initialize.
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Hi Huibing,
Does this patch suppose to be V3?
and there is a typo in subject.
Thanks,
- Kever
On 08/07/2017 09:45 AM, Huibin Hong wrote:
Add spi node and spi pinctrl for rk322x
Signed-off-by: Huibin Hong
---
arch/arm/boot/dts/rk322x.dtsi | 50 +
Hi Frank,
On 05/17/2017 11:40 AM, Frank Wang wrote:
Correct UART2 PINCTRL flag and add another PINCTRL sets for UART2
in case of confict with SDMMC.
Signed-off-by: Frank Wang
---
arch/arm/boot/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/a
Heiko,
On 05/10/2017 05:43 AM, Heiko Stuebner wrote:
Am Mittwoch, 12. April 2017, 15:10:43 CEST schrieb Kever Yang:
Use command below to replace the IO naming in pinctrl:
sed -i -e 's/ 31 RK_FUNC_/ RK_PD7 RK_FUNC_/' arch/arm/boot/dts/rk*
sed -i -e 's/ 0 RK_FUNC_/ RK_PA0 RK_FUN
Hi Heiko,
On 04/12/2017 09:29 PM, Heiko Stuebner wrote:
Hi Kever,
Am Montag, 10. April 2017, 11:50:13 CEST schrieb Kever Yang:
Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/
This patch add basic node for the
Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi.
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 113 +++
1 file changed, 113 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Add power domain for sd, usb, edp.
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 36 +++-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Add qos setting reg for some peripheral like sd, usb, pcie.
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45
1 file changed, 40 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot
:
- USB 3.0 HOST, type-C port
- sdio, sd-card
Not test for other peripheral:
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP
Signed-off-by: Kever Yang
---
Changes in v3:
- remove not upstream defined properties;
- remove fusb302 and gsl3673 node
Changes in v2:
- rebase on
Hi Heiko,
On 04/08/2017 07:01 AM, Heiko Stuebner wrote:
Hi Kever,
Am Mittwoch, 5. April 2017, 17:33:19 CEST schrieb Kever Yang:
Firefly-rk3399 is a bord from T-Firefly, you can find detail about
it here:
http://en.t-firefly.com/en/firenow/Firefly_RK3399/
This patch add basic node for the
Use "firefly,firefly-rk3399" compatible string for firefly-rk3399 board.
Signed-off-by: Kever Yang
---
Changes in v2: None
Documentation/devicetree/bindings/arm/rockchip.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockc
:
- USB 3.0 HOST, type-C port
- sdio, sd-card
Not test for other peripheral:
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP
Signed-off-by: Kever Yang
---
Changes in v2:
- rebase on Heiko's for-next
- using pinctrl binding header definition instead of a number
- other f
Hi Heiko, Andreas,
On 04/01/2017 03:41 AM, Heiko Stuebner wrote:
Hi,
Am Freitag, 31. März 2017, 18:59:49 CEST schrieb Andreas Färber:
Am 31.03.2017 um 14:56 schrieb Heiko Stuebner:
Hi Kever,
Am Freitag, 31. März 2017, 17:59:07 CEST schrieb Kever Yang:
Firefly-rk3399 is a bord from T
:
- USB 3.0 HOST, type-C port
- sdio, sd-card
Not test for other peripheral:
- HDMI
- Ethernet
- OPTICAL
- WiFi/BT
- MIPI CSI/DSI
- IR
- EDP/DP
Signed-off-by: Kever Yang
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 772
Hi David,
On 03/02/2017 03:11 PM, David Wu wrote:
From: "david.wu"
You do not need to add this when you send mail for yourself,
it's need when you send mail for others.
To prevent external signal crosstalk, some pins need to
enable input schmitt, like i2c pins, 32k-input pin and so on.
Si
operate at RBR, HBR and
HBR2 data rates.
Signed-off-by: Chris Zhong
Signed-off-by: Kever Yang
---
Changes in v2:
- select RESET_CONTROLLER
- alphabetic order
- modify some spelling mistakes
- make mode cleaner
- use bool for enable/disable
- check all of the return value
- return a better err
+ * Rockchip usb3 PHY driver
+ *
+ * Copyright (C) 2016 Kever Yang
+ *Chris Zhong
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free
Hi Chris,
On 05/27/2016 02:02 PM, Chris Zhong wrote:
Hi all
This series patch is for rockchip Type-C phy and DisplayPort controller
driver.
The USB Type-C PHY is designed to support the USB3 and DP applications.
The PHY basically has two main components: USB3 and DisplyPort. USB3
operates in S
Doug,
Thanks for your detail debug information, pls add my Reviewed-by for
this patch.
Thanks,
- Kever
On 02/03/2016 06:47 AM, Doug Anderson wrote:
Kever,
On Mon, Feb 1, 2016 at 11:46 PM, Kever Yang wrote:
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
When setting up ISO and
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
When setting up ISO and INT transfers dwc2 needs to specify whether the
transfer is for an even or an odd frame (or microframe if the controller
is running in high speed mode).
The controller appears to use this as a simple way to figure out
Doug,
On 02/02/2016 08:36 AM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 8:36 PM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 7:32 PM, Kever Yang wrote:
Doug,
On 02/01/2016 06:09 AM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 1:36 AM, Kever Yang
wrote:
Doug
Doug,
On 02/01/2016 06:09 AM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 1:36 AM, Kever Yang wrote:
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
In dwc2_hcd_qh_deactivate() we will put some things on the
periodic_sched_ready list. These things won't be taken of
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
In dwc2_hcd_qh_deactivate() we will put some things on the
periodic_sched_ready list. These things won't be taken off the ready
list until the next SOF, which might be a little late. Let's put them
on right away.
Signed-off-by: Douglas And
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
According to the most up to date version of the dwc2 databook, the FRINT
field of the HFIR register should be programmed to:
* 125 us * (PHY clock freq for HS) - 1
* 1000 us * (PHY clock freq for FS/LS) - 1
I got 3 version of dwc_otg databoo
Doug,
Reviewed-by: Kever Yang
Thanks,
- Kever
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
I find that when I plug a full speed (NOT high speed) hub into a dwc2
port and then I plug a bunch of devices into that full speed hub that
dwc2 goes bat guano crazy. Specifically, it just spews
Hi Doug,
On 01/28/2016 03:44 AM, Doug Anderson wrote:
If it's all the same to you, I'll probably change it back to 525 and
then increase the periodic FIFO size by 3 DWORDS in the next patch.
12 bytes may not be much, but might as well make use of them to
improve performance / compatibility?
Pre
e.
Thanks,
- Kever
On 01/28/2016 11:28 AM, Doug Anderson wrote:
Kever,
On Wed, Jan 27, 2016 at 7:10 PM, Kever Yang wrote:
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-packet data
prepare latenc
driver.
For this patch:
Reviewed-by: Kever Yang
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
In preparation for future changes to the scheduler let's add some
tracing that makes it easy for us to see what's happening. By default
this tracing will be off.
B
Hi Doug,
The NULL pointer bug is one of the most frequent issue we met
during hot plug stress test, thanks for this bug fix.
Reviewed-by: Kever Yang
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
When poking around with USB devices with slub_debug enabled, I found
another
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-packet data
prepare latency when the bus/DRAM is busy.
For the actual usage in TX, we have very little change to use the
period TX FIFO with mo
Hi Doug,
I test this patch with USB 2.0 analyzer, and it make the CSPLIT in the
same order with the SSPLIT, so
Reviewed-by: Kever Yang
Tested-by: Kever Yang
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
We're supposed to keep outstanding splits in order. Keep track
Hi Doug,
This is obviously a bug in dwc2 driver which not meet the usb 2.0
spec, and this patch can fix it.
Reviewed-by: Kever Yang
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
The queues the the dwc2 host controller used are truly queues. That
means FIFO or first in
We've got 960 / 972 total_fifo_size on rk3288 (and presumably on
rk3066) and 525 + 128 + 256 = 909 so we're still under on both ports
even when we increment by 5.
Since we have space, Kever Yang suggests bumping by 8. He says this
will meet INCR16 access and next fifo type can start with
Hi Zhang Qing,
On 12/31/2015 10:14 PM, zhangqing wrote:
make rtc-rk8xx.c compatible for all pmic chips.
for pmic chips(rk808\rk807\rk816\rk818) in the future.
The commit message will be better like this:
Rename the file to rtc-rk8xx.c to compatible other Rockchip PMIC chips
like rk807/rk816/rk8
+
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
Reviewed-by: Kever Yang
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.or
udelay(10);
+ mdelay(1); /* ensure the cpus other than cpu0 to startup */
+
writel(virt_to_phys(rockchip_secondary_startup),
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
Reviewed-by: Kever Yang
--
To unsubscribe from th
/WFE state
+* prior to having the power domain disabled.
+*/
+ mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
}
Reviewed-by: Kever Yang
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of
Hi Caesar,
Subject typo WIF/WFI.
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1
Hi Caesar,
On 04/08/2015 06:18 PM, Caesar Wang wrote:
To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.
Signed-off-by: jay.xu
Signed-off-by: zhengxing
Signed-off-by: Caesar Wang
Serien-cc: linux-kernel@vger.kernel.org
Serien-c
Hi Daniel,
On 01/25/2015 05:42 PM, Daniel Lezcano wrote:
The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This dri
Hi Paul,
I think you need this patch to fix the problem:
usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/
Thanks,
- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent
Hi Roy,
Why you send two patches with different commit message but the same
change,
you should use V2 for a new patch.
On 12/03/2014 09:46 PM, LiYunzhi wrote:
From: lyz
You don't need the From for the patches from yourself.
Add a driver for the Rockchip SoC internal USB2.0 PHY.
This d
Hi Roger,
Please use the --in-reply-to option for patches other than 0/4
with the git send-email.
On 11/25/2014 05:07 PM, Roger Chen wrote:
Roger Chen (4):
patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
patch2: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
Hi Chris,
On 11/25/2014 05:37 PM, Chris Zhong wrote:
The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.
I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In this
Hi Roger,
The subject should prefix:
Arm: dts: rockchip: enable ...
On 11/25/2014 05:09 PM, Roger Chen wrote:
enable gmac in rk3288-evb-rk808.dts
Signed-off-by: Roger Chen
---
arch/arm/boot/dts/rk3288-evb-rk808.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git
Hi Roger,
The Subject should use below prefix:
ARM: dts: rockchip: add gmac info for rk3288
On 11/25/2014 05:08 PM, Roger Chen wrote:
add gmac info in rk3288.dtsi for GMAC driver
Signed-off-by: Roger Chen
---
arch/arm/boot/dts/rk3288.dtsi | 59 +
1
Hi Roger,
This patch should be split into two patch, one for clock ID definition,
one for mac related clocks update.
The Subject for clk-rk3288.c should use below prefix:
clk: rockchip: modify clock for mac ...
On 11/25/2014 05:08 PM, Roger Chen wrote:
modify CRU config for GMAC driver
Coul
Hi Jay,
On 11/19/2014 04:09 PM, Jianqun Xu wrote:
Patch is from Sonny Rao
Here should be,
From: Sonny Rao
- Kever
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After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li
Signed-off-by: Kever Yang
---
Changes in v2
Hi Julius,
On 11/18/2014 05:21 AM, Julius Werner wrote:
On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device
This patch is no complete, Sorry for that, I will upload a new version
tomorrow.
- Kever
On 11/17/2014 09:14 PM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.
Signed-off-by: Kever Yang
---
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3
We will need a pll to support all kinds of clock rate requirement
for HDMI(from DCLK_VOP0) which may change the rate at run time.
In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP0 can select npll
as parent.
Signed-off-by: Kever Yang
Kever Yang (2):
clk: rockchip: leave npll for VOP0 only
arm: dts: rockchip: select npll as parent of DCLK_VOP0
arch/arm/boot/dts/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 24
2 files changed, 14 insertions(+), 12 deletions(-)
--
1.9.1
--
To
On 11/14/2014 11:55 PM, Alan Stern wrote:
On Thu, 13 Nov 2014, Julius Werner wrote:
Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all othe
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li
Signed-off-by: Kever Yang
---
drivers/usb
Hi
On 11/14/2014 09:46 AM, Mike Turquette wrote:
Looking through the clock-tree there are a lot more components possibly
> >>using
> >>(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
> >>hevc,
> >>gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
> >>reser
This patch adds document for how to use the opetion property
assigned-clock-force-rates.
We may use this property to force update a clock setting.
Signed-off-by: Kever Yang
---
Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions
meter if the rate is not changed by now.
This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.
Signed-off-by: Kever Yang
---
drivers/clk/clk-conf.c | 33 +
When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.
Kever Yang (2):
clk: add property for force to update clock setting
dt-bindings: clk: add documen
Hi Heiko,
On 11/07/2014 05:06 AM, Heiko Stübner wrote:
Hi Kever,
Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:
we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3
cture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/c
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index
it so that we can use in dts.
Signed-off-by: Kever Yang
---
include/dt-bindings/clock/rk3288-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3288-cru.h
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock
According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.
Signed-off-by: Kever Yang
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk
0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5,
GFLAGS),
The H/PCLK_VIO2_H2P is some kind of bus clock for a ahb2apb bridge
inside the VIO,
it should be on when some of VIO logic is working, but it is not easy to
assign these
two clocks to module driver. I think it is reasonable to ma
Doug,
On 11/13/2014 07:22 AM, Doug Anderson wrote:
Kever,
On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we
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