[PATCH] usb: dwc2: fix the incorrect bitmaps for the ports of multi_tt hub

this patch, I can easily meet a Kernel panic issue if connect a low-speed USB mouse with the max port of FE2.1 multi-tt hub (1a40:0201) on rk3288 platform. Signed-off-by: William Wu --- drivers/usb/dwc2/hcd_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc2

[PATCH v5 2/2] usb: dwc2: fix isoc split in transfer with no data

SPLIT IN transaction - MDATA packet (176 bytes) - CSPLIT IN transaction - DATA0 packet (0 byte) This patch use both the length of DATA0 and qtd->isoc_split_offset to check if the DATA0 is in the second transaction. Signed-off-by: William Wu --- Changes in v5: - None Changes in v4: - None Ch

[PATCH v5 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

Note that according to usb 2.0 spec, the maximum data payload size is 1023 bytes for each fs isoc ep, and the maximum allowable interrupt data payload size is 64 bytes or less for fs interrupt ep. So we set the size of object to be 1024 bytes in the kmem cache. Signed-off-by: William Wu Re

[PATCH v5 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb

[PATCH v4 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

Note that according to usb 2.0 spec, the maximum data payload size is 1023 bytes for each fs isoc ep, and the maximum allowable interrupt data payload size is 64 bytes or less for fs interrupt ep. So we set the size of object to be 1024 bytes in the kmem cache. Signed-off-by: William Wu --- Chan

[PATCH v4 2/2] usb: dwc2: fix isoc split in transfer with no data

SPLIT IN transaction - MDATA packet (176 bytes) - CSPLIT IN transaction - DATA0 packet (0 byte) This patch use both the length of DATA0 and qtd->isoc_split_offset to check if the DATA0 is in the second transaction. Signed-off-by: William Wu --- Changes in v4: - None Changes in v3: -

[PATCH v4 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb

[PATCH v3 2/2] usb: dwc2: fix isoc split in transfer with no data

SPLIT IN transaction - MDATA packet (176 bytes) - CSPLIT IN transaction - DATA0 packet (0 byte) This patch use both the length of DATA0 and qtd->isoc_split_offset to check if the DATA0 is in the second transaction. Signed-off-by: William Wu --- Changes in v3: - Remove "qtd->isoc_split_of

[PATCH v3 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

Note that according to usb 2.0 spec, the maximum data payload size is 1023 bytes for each fs isoc ep, and the maximum allowable interrupt data payload size is 64 bytes or less for fs interrupt ep. So we set the size of object to be 1024 bytes in the kmem cache. Signed-off-by: William Wu --- Changes

[PATCH v3 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb

[PATCH v2 2/2] usb: dwc2: fix isoc split in transfer with no data

SPLIT IN transaction - MDATA packet (176 bytes) - CSPLIT IN transaction - DATA0 packet (0 byte) This patch use both the length of DATA0 and qtd->isoc_split_offset to check if the DATA0 is in the second transaction. Signed-off-by: William Wu --- Changes in v2: - Modify the commit message drive

[PATCH v2 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb

[PATCH v2 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

igned DMA for isoc split in. Signed-off-by: William Wu --- Changes in v2: - None drivers/usb/dwc2/hcd.c | 63 +--- drivers/usb/dwc2/hcd.h | 10 +++ drivers/usb/dwc2/hcd_intr.c | 8 ++ drivers/usb/dwc2/hcd_queue.c | 8 +- 4 files c

[PATCH 1/2] usb: dwc2: alloc dma aligned buffer for isoc split in

igned DMA for isoc split in. Signed-off-by: William Wu --- drivers/usb/dwc2/hcd.c | 63 +--- drivers/usb/dwc2/hcd.h | 10 +++ drivers/usb/dwc2/hcd_intr.c | 8 ++ drivers/usb/dwc2/hcd_queue.c | 8 +- 4 files changed, 85 insertio

[PATCH 2/2] usb: dwc2: fix isoc split in transfer with no data

SPLIT IN transaction - MDATA packet (176 bytes) - CSPLIT IN transaction - DATA0 packet (0 byte) This patch use both the length of DATA0 and qtd->isoc_split_offset to check if the DATA0 is in the second transaction. Signed-off-by: William Wu --- drivers/usb/dwc2/hcd_intr.c | 2 +- 1 file changed,

[PATCH 0/2] usb: dwc2: fix isoc split in transfer issue

This patch fix dma unaligned problem and data lost problem for isoc split in transfer. Test on rk3288 platform, use an usb hs Hub (GL852G-12) and an usb fs audio device (Plantronics headset) to capture and playback. William Wu (2): usb: dwc2: alloc dma aligned buffer for isoc split in usb

[PATCH] usb: gadget: f_fs: get the correct address of comp_desc

fc fc fc fc fc fc fc fc == Disabling lock debugging due to kernel taint android_work: sent uevent USB_STATE=CONFIGURED This patch adds struct usb_endpoint_descriptor * -> u8 * type conversion for ds variable, then we can get the correct address of comp_desc with offset USB_DT_ENDPOINT_SIZE byte

[PATCH 1/3] dt-bindings: phy: phy-rockchip-typec: add usb3 otg reset

This patch adds USB3 OTG reset property for rk3399 Type-C PHY to hold the USB3 controller in reset state. Signed-off-by: William Wu --- Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation

[PATCH 2/3] arm64: dts: rockchip: add USB3 OTG reset for Type-C PHY on rk3399

Add USB3 OTG reset for Type-C PHY. It can be used to hold the USB3 OTG controller in reset state before initializing the Type-C PHY. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64

[PATCH 3/3] phy: rockchip-typec: reset USB3 controller before initializing PHY

igned-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-typec.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index ee85fa0..68a5840 100644 --- a/driver

[PATCH 0/3] Reset USB3 controller before initializing Type-C PHY on rk3399

This series adds USB3 OTG controller reset for rk3399 Type-C PHY, and use the reset to hold the whole USB3 OTG controller in reset state to keep the PIPE power state in P2 before initializing Type-C PHY, it's useful to avoid waiting for PHY PMA and PIPE ready timeout. William Wu (3):

[PATCH] usb: dwc3: core: power on PHYs before initializing core

GUID register after powering on the PHYs. Signed-off-by: William Wu --- drivers/usb/dwc3/core.c | 46 ++ 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index c32d2b9..4f5573f 100644

[PATCH] usb: dwc2: host: fix isoc urb actual length

Let's update the urb actual_length if the isoc frame is valid. Signed-off-by: William Wu --- drivers/usb/dwc2/hcd_intr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c index 28a8210..01b1e13 100644 --- a/drivers/usb/dwc2/hcd_in

[PATCH v3 0/3] Add usb3 ctrl node on RK3328 SoCs and enable usb3 host on RK3328 evb

This series add support for usb3 controller on RK3328 SoCs. This series don't include usb3 phy patches, and I will try to submit usb3 phy patches individually later. Tested on RK3328 evaluation board. William Wu (3): dt-bindings: usb: add DT binding for RK3328 dwc3 controller arm64

[PATCH v3 2/3] arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs

RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu --- Changes in v3: - Move dt-binding changes to a separate

[PATCH v3 3/3] arm64: dts: rockchip: enable usb3 for RK3328 evaluation board

Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller, we enable it and set it act as static xHCI host controller to support USB 3.0 HOST on RK3328 evaluation board. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None arch/arm64/boot/dts/rockchip/r

[PATCH v3 1/3] dt-bindings: usb: add DT binding for RK3328 dwc3 controller

Adds the device tree bindings description for RK3328 and compatible USB DWC3 controller. Signed-off-by: William Wu --- Changes in v3: - Add this for separate usb dt-bindings patch. Changes in v2: - None Documentation/devicetree/bindings/usb/rockchip,dwc3.txt | 4 +++- 1 file changed, 3

[PATCH] arm64: dts: rockchip: disable tx ipgap linecheck for rk3399 dwc3

heck-quirk" to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk33

[PATCH v2 2/2] arm64: dts: rockchip: enable usb3 for RK3328 evaluation board

Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller, we enable it and set it act as static xHCI host controller to support USB 3.0 HOST on RK3328 evaluation board. Signed-off-by: William Wu --- Changes in v2: - None arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 9 +++

[PATCH v2 0/2] Add usb3 ctrl node on RK3328 SoCs and enable usb3 host on RK3328 evb

This series add support for usb3 controller on RK3328 SoCs. This series don't include usb3 phy patches, and I will try to submit usb3 phy patches individually later. Tested on RK3328 evaluation board. William Wu (2): arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs arm64

[PATCH v2 1/2] arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs

RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu --- Changes in v2: - Modify the dwc3 quirk "snps,tx-ipgap

[PATCH 2/2] arm64: dts: rockchip: enable usb3 for RK3328 evaluation board

Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller, we enable it and set it act as static xHCI host controller to support USB 3.0 HOST on RK3328 evaluation board. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 9 + 1 file changed, 9 inser

[PATCH 0/2] Add usb3 ctrl node on RK3328 SoCs and enable usb3 host on RK3328 evb

This series add support for usb3 controller on RK3328 SoCs. This series don't include usb3 phy patches, and I will try to submit usb3 phy patches individually later. Tested on RK3328 evaluation board. William Wu (2): arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs arm64

[PATCH 1/2] arm64: dts: rockchip: add usb3 controller node for RK3328 SoCs

RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu --- .../devicetree/bindings/usb/rockchip,dwc3.txt

[PATCH v2 2/2] arm64: dts: rockchip: enable usb2 for RK3328 evaluation board

Rockchip's RK3328 evaluation board has one usb2 otg controller and one usb2 host controller which consist of EHCI and OHCI. Each usb controller connects with one usb2 phy port through UTMI+ interface. Let's enable them to support usb2 on RK3328 evaluation board. Signed-off-by:

[PATCH v2 1/2] arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs

This patch adds usb2 otg/host controllers and phys nodes for Rockchip RK3328 SoCs. Signed-off-by: William Wu --- Changes in v2: - set usb2 otg dr_mode as "otg" arch/arm64/boot/dts/rockchip/rk3328.dtsi | 76 1 file changed, 76 insertions(+) diff --

[PATCH v2 0/2] Add usb2 nodes on RK3328 SoCs and enable usb2 on RK3328 evb

This series adds support for usb2 on RK3328 SoCs. Tested on RK3328 evaluation board. William Wu (2): arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs arm64: dts: rockchip: enable usb2 for RK3328 evaluation board arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 25 ++ arch/arm64

[PATCH 2/2] arm64: dts: rockchip: enable usb2 for RK3328 evaluation board

Rockchip's RK3328 evaluation board has one usb2 otg controller and one usb2 host controller which consist of EHCI and OHCI. Each usb controller connects with one usb2 phy port through UTMI+ interface. Let's enable them to support usb2 on RK3328 evaluation board. Signed-off-by:

[PATCH 1/2] arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs

This patch adds usb2 otg/host controllers and phys nodes for Rockchip RK3328 SoCs. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 76 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64

[PATCH 0/2] Add usb2 nodes on RK3328 SoCs and enable usb2 on RK3328 evb

This series adds support for usb2 on RK3328 SoCs. Tested on RK3328 evaluation board. William Wu (2): arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs arm64: dts: rockchip: enable usb2 for RK3328 evaluation board arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 25 ++ arch/arm64

[PATCH v2 1/2] ARM: dts: rockchip: add usb nodes on rk322x

This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu --- arch/arm/boot/dts/rk322x.dtsi | 138 +- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts

[PATCH v2 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb

This series adds support for usb on rk322x SoCs. William Wu (2): ARM: dts: rockchip: add usb nodes on rk322x ARM: dts: rockchip: enable usb for rk3229 evb board Tested on rk3229 evb board, and depended on the following patches and config. [1] https://patchwork.kernel.org/patch/9761507/ [2

[PATCH v2 2/2] ARM: dts: rockchip: enable usb for rk3229 evb board

d. Signed-off-by: William Wu --- arch/arm/boot/dts/rk3229-evb.dts | 74 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 275092a..1b55192 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts

[PATCH 2/2] ARM: dts: rockchip: enable usb for rk3229 evb board

d. Signed-off-by: William Wu --- arch/arm/boot/dts/rk3229-evb.dts | 74 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 275092a..1b55192 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts

[PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x

This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu --- arch/arm/boot/dts/rk322x.dtsi | 138 +- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts

[PATCH 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb

This series adds support for usb on rk322x SoCs. William Wu (2): ARM: dts: rockchip: add usb nodes on rk322x ARM: dts: rockchip: enable usb for rk3229 evb board Tested on rk3229 evb board, and depended on the following patches and config. [1] https://patchwork.kernel.org/patch/9732473/ [2

[PATCH] usb: dwc2: resume root hub to handle disconnect of device

: William Wu --- drivers/usb/dwc2/hcd.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 740c7e8..cc84f97 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1975,11 +1975,13 @@ void

[PATCH] usb: gadget: f_fs: avoid out of bounds access on comp_desc

fc fc fc fc fc fc fc fc fc fc ffc0601f6600: fc fc fc fc fc fc fc fc 00 00 00 00 00 00 00 00 == Signed-off-by: William Wu --- drivers/usb/gadget/function/f_fs.c | 10 +- 1 file changed, 5 insertions(+), 5 deleti

[PATCH v3] usb: dwc3: add disable u2mac linestate check quirk

from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Signed-off-by: William Wu --- Changes in v3: - change quirk name - only read and write GUCTL1 if dwc3 version >= 2.50a Changes in v2: - fix coding style Documentation/devicetree/bindings/

[PATCH v2] usb: dwc3: add disable u2mac linestate check quirk

from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Signed-off-by: William Wu --- Changes in v2: - fix coding style Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c| 14

[PATCH] usb: dwc3: add disable u2mac linestate check quirk

from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Signed-off-by: William Wu --- Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c| 14 ++ drivers/usb/dwc3/core.h

[PATCH v2] usb: host: xhci: plat: check hcc_params after add hcd

From: William wu The commit 4ac53087d6d4 ("usb: xhci: plat: Create both HCDs before adding them") move add hcd to the end of probe, this cause hcc_params uninitiated, because xHCI driver sets hcc_params in xhci_gen_setup() called from usb_add_hcd(). This patch checks the Maximum Prim

[PATCH] usb: host: xhci: plat: check hcc_params after add hcd

From: William wu The commit 4ac53087d6d4 ("usb: xhci: plat: Create both HCDs before adding them") move add hcd to the end of probe, this cause hcc_params uninitiated, because xHCI driver sets hcc_params in xhci_gen_setup() called from usb_add_hcd(). This patch checks the Maximum Prim

[RESEND PATCH] usb: hcd: initialize hcd->flags to 0 when rm hcd

From: William wu On some platforms(e.g. rk3399 board), we can call hcd_add/remove consecutively without calling usb_put_hcd/usb_create_hcd in between, so hcd->flags can be stale. If the HC dies due to whatever reason then without this patch we get the below error on next hcd_add. [173.296

[PATCH] usb: hcd: initialize hcd->flags to 0 when rm hcd

From: William wu On some platforms(e.g. rk3399 board), we can call hcd_add/remove consecutively without calling usb_put_hcd/usb_create_hcd in between, so hcd->flags can be stale. If the HC dies due to whatever reason then without this patch we get the below error on next hcd_add. [173.296

[PATCH v4 0/2] phy: rockchip-inno-usb2: correct 480MHz clk_ops callbacks and stable time

This series try to correct the 480MHz output clock of USB2 PHY clk_ops callback and fix the delay time. It aims to make the 480MHz clock gate more sensible and stable. Tested on rk3366/rk3399 EVB board. William Wu (2): phy: rockchip-inno-usb2: correct clk_ops callback phy: rockchip-inno-usb2

[PATCH v4 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

;waiting". Signed-off-by: William Wu Reviewed-by: Douglas Anderson --- Changes in v4: - add Reviewed-by and fix a spelling error Changes in v3: - None Changes in v2: - None drivers/phy/phy-rockchip-inno-usb2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/p

[PATCH v4 1/2] phy: rockchip-inno-usb2: correct clk_ops callback

latency is not sensible. The 480MHz output clock should be handled in prepare callbacks which support gate a clk if the operation may sleep. Signed-off-by: William Wu Reviewed-by: Douglas Anderson --- Changes in v4: - add Reviewed-by Changes in v3: - None Changes in v2: - None drivers/phy/ph

[PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct clk_ops callback") used prepare callbacks instead of enable callbacks to support gate a clk if the operation may sleep. So we can switch from delay to sleep functions. Signed-off-by: William Wu --- Changes in v3: - fix kbuild test

[PATCH v3 1/2] phy: rockchip-inno-usb2: correct clk_ops callback

latency is not sensible. The 480MHz output clock should be handled in prepare callbacks which support gate a clk if the operation may sleep. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None drivers/phy/phy-rockchip-inno-usb2.c | 12 ++-- 1 file changed, 6 i

[PATCH v3 0/2] phy: rockchip-inno-usb2: correct 480MHz clk_ops callbacks and stable time

This series try to correct the 480MHz output clock of USB2 PHY clk_ops callback and fix the delay time. It aims to make the 480MHz clock gate more sensible and stable. Tested on rk3366/rk3399 EVB board. William Wu (2): phy: rockchip-inno-usb2: correct clk_ops callback phy: rockchip-inno-usb2

[PATCH v2 0/2] phy: rockchip-inno-usb2: correct 480MHz clk_ops callbacks and stable time

This series try to correct the 480MHz output clock of USB2 PHY clk_ops callback and fix the delay time. It aims to make the 480MHz clock more sensible and stable. Tested on rk3366/rk3399 EVB board. William Wu (2): phy: rockchip-inno-usb2: correct clk_ops callback phy: rockchip-inno-usb2

[PATCH v2 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct clk_ops callback") used prepare callbacks instead of enable callbacks to support gate a clk if the operation may sleep. So we can switch from delay to sleep functions. Signed-off-by: William Wu --- Changes in v2: - use us

[PATCH v2 1/2] phy: rockchip-inno-usb2: correct clk_ops callback

latency is not sensible. The 480MHz output clock should be handled in prepare callbacks which support gate a clk if the operation may sleep. Signed-off-by: William Wu --- drivers/phy/phy-rockchip-inno-usb2.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/p

[PATCH] phy: rockchip-inno-usb2: correct 480MHz output clock stable time

-off-by: William Wu --- drivers/phy/phy-rockchip-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c index ecfd7d1..8f2d2b6 100644 --- a/drivers/phy/phy-rockchip-inno-usb2.c +++ b/drivers/phy

[PATCH v3 1/2] phy: rockchip-inno-usb2: support otg-port for rk3399

extcon notifier to send USB charger types to power driver. - Support PHY suspend for power management. - Support OTG Host only mode. Signed-off-by: William Wu --- Changes in v3: - split the clock fix into a separate patch Changes in v2: - remove wakelock drivers/phy/phy-rockchip-inno-usb2.c

[PATCH v3 0/2] support USB2 PHY OTG port for rk3399

This series add support for rk3399 USB2 PHY0 and PHY1 OTG port. rk3399 has two USB2 PHYs, and each USB2 PHY is comprised of one Host port and one OTG port. We have supported Host port before, and try to support OTG port now. Test on rk3399-evb board. William Wu (2): phy: rockchip-inno-usb2

[PATCH v3 2/2] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399

Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu --- Changes in v3: - None Changes in v2: - None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 + 1 file changed, 21 insertions

[PATCH v2 1/2] phy: rockchip-inno-usb2: support otg-port for rk3399

gpu module. Theoretically, 1 millisecond is a critical value for 480 output clock stable time, so we try changing the delay time to 1.2 millisecond to avoid this issue. Signed-off-by: William Wu --- Changes in v2: - remove wakelock drivers/phy/phy-rockchip-inno-usb2.c | 593

[PATCH v2 0/2] support USB2 PHY OTG port for rk3399

This series add support for rk3399 USB2 PHY0 and PHY1 OTG port. rk3399 has two USB2 PHYs, and each USB2 PHY is comprised of one Host port and one OTG port. We have supported Host port before, and try to support OTG port now. Test on rk3399-evb board. William Wu (2): phy: rockchip-inno-usb2

[PATCH v2 2/2] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399

Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu --- Changes in v2: - None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm64

[PATCH 2/2] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399

Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399

[PATCH 0/2] support USB2 PHY OTG port for rk3399

This series add support for rk3399 USB2 PHY0 and PHY1 OTG port. rk3399 has two USB2 PHYs, and each USB2 PHY is comprised of one Host port and one OTG port. We have supported Host port before, and try to support OTG port now. Test on rk3399-evb board. William Wu (2): phy: rockchip-inno-usb2

[PATCH 1/2] phy: rockchip-inno-usb2: support otg-port for rk3399

of USB2 PHY was unstable after clock had been enabled by gpu module. Theoretically, 1 millisecond is a critical value for 480 output clock stable time, so we try changing the delay time to 1.2 millisecond to avoid this issue. Signed-off-by: William Wu --- drivers/phy/phy-rockchip-inno-usb2.c

[PATCH v11 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v11

[PATCH v11 0/5] support rockchip dwc3 driver

Peripheral Only configurations. The current driver supports Host only and Peripheral Only, for now, and we can add support for DRD after dwc3 driver adds generic handling of DRD. William Wu (5): usb: dwc3: of-simple: add compatible for rockchip rk3399 usb: dwc3: add dis_u2_freeclk_exists_quirk

[PATCH v11 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu --- Changes in v11: - add compatible in dwc3-of-simple.c, and remove dwc3-rockchip.c (balbi) Changes in v10: - None Changes in v9

[PATCH v11 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v11: - None Changes in v10: - None

[PATCH v11 3/5] usb: dwc3: make usb2 phy utmi interface configurable

PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v11: - None Changes in v10: - None Changes in v9: - None Changes in v8: - configure utmi interface via phy_type property in DT (Heiko, Rob Herring) - add Acked-by

[PATCH v11 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v11: - None Changes in v10: - None

[PATCH v10 5/5] usb: dwc3: add rockchip specific glue layer

it need to reconfigure USB PHY interface of DWC3 core after deassert DWC3 controller reset. The current driver supports Host only and Peripheral Only well, for now, we will add support for OTG after we have it all stabilized. Signed-off-by: William Wu --- Changes in v10: - fix building error

[PATCH v10 4/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v10

[PATCH v10 3/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v10: - None Changes in v9: - None

[PATCH v10 2/5] usb: dwc3: make usb2 phy utmi interface configurable

PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v10: - None Changes in v9: - None Changes in v8: - configure utmi interface via phy_type property in DT (Heiko, Rob Herring) - add Acked-by (Rob Herring) - modify c

[PATCH v10 1/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v10: - None Changes in v9: - None

[PATCH v10 0/5] support rockchip dwc3 driver

than use the generic of glue layer which merely enable some clocks and populate its children. William Wu (5): usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: make usb2 phy utmi interface configurable usb: dwc3: add dis_del_phy_power_chg_quirk usb: dwc3: rockchip: add devicetree bindings

[PATCH v9 5/5] usb: dwc3: add rockchip specific glue layer

it need to reconfigure USB PHY interface of DWC3 core after deassert DWC3 controller reset. The current driver supports Host only and Peripheral Only well, for now, we will add support for OTG after we have it all stabilized. Signed-off-by: William Wu --- drivers/usb/dwc3/Kconfig | 9

[PATCH v9 4/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v9

[PATCH v9 2/5] usb: dwc3: make usb2 phy utmi interface configurable

PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v9: - None Changes in v8: - configure utmi interface via phy_type property in DT (Heiko, Rob Herring) - add Acked-by (Rob Herring) - modify commit message (Rob He

[PATCH v9 3/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v9: - None Changes in v8: - add Acked-by

[PATCH v9 0/5] support rockchip dwc3 driver

use the generic of glue layer which merely enable some clocks and populate its children. William Wu (5): usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: make usb2 phy utmi interface configurable usb: dwc3: add dis_del_phy_power_chg_quirk usb: dwc3: rockchip: add devicetree bindings

[PATCH v9 1/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v9: - None Changes in v8: - add Acked-by

[PATCH v8 0/5] support rockchip dwc3 driver

This series add support for rockchip dwc3 driver, and add additional optional properties for specific platforms (e.g., rockchip rk3399 platform). William Wu (5): usb: dwc3: of-simple: add compatible for rockchip rk3399 usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: make usb2 phy utmi

[PATCH v8 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v8: - add Acked-by (Rob Herring) Changes

[PATCH v8 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v8: - add Acked-by (Rob Herring) Changes

[PATCH v8 3/5] usb: dwc3: make usb2 phy utmi interface configurable

PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v8: - configure utmi interface via phy_type property in DT (Heiko, Rob Herring) - add Acked-by (Rob Herring) - modify commit message (Rob Herring) Changes in v7: - r

[PATCH v8 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu --- Changes in v8: - None Changes in v7: - None Changes in v6: - None Changes in v5: - change compatible from "rockchip,dwc

[PATCH v8 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v8

[PATCH v7 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip USB3.0 core wrapper consisting of USB3.0 IP from Synopsys. It supports DRD mode, and could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: William Wu Acked-by: Rob Herring --- Changes in v7

[PATCH v7 0/5] support rockchip dwc3 driver

This series add support for rockchip dwc3 driver, and add additional optional properties for specific platforms (e.g., rockchip rk3399 platform). William Wu (5): usb: dwc3: of-simple: add compatible for rockchip rk3399 usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: make usb2 phy utmi

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