Re: [PATCH 0/3] Fix USB3.0 DRD PHY calibration issues (DWC3/XHCI) on Exynos542x SoCs

Hi Marek, On Mon, 15 Jul 2019 at 17:49, Marek Szyprowski wrote: > > Hi Anand, > > On 2019-06-28 17:32, Anand Moon wrote: > > Hi Marek, > > > > On Thu, 27 Jun 2019 at 12:47, Marek Szyprowski > > wrote: > >> Dear All, > >> > >> Commit d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for

Re: [PATCH 0/3] Fix USB3.0 DRD PHY calibration issues (DWC3/XHCI) on Exynos542x SoCs

Hi Marek, On Thu, 27 Jun 2019 at 12:47, Marek Szyprowski wrote: > > Dear All, > > Commit d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for > exynos5420/5800") added support for Exynos5 USB3.0 DRD PHY calibration, > what enabled proper Super-Speed enumeration of USB3.0 devices

[PATCH 0/3] Fix USB3.0 DRD PHY calibration issues (DWC3/XHCI) on Exynos542x SoCs

Dear All, Commit d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800") added support for Exynos5 USB3.0 DRD PHY calibration, what enabled proper Super-Speed enumeration of USB3.0 devices connected to various Exynos5 SoCs. After some time it turned out that the mentioned