Il 10/01/24 20:16, Konrad Dybcio ha scritto:
On 1/9/24 12:24, Luca Weiss wrote:
On Tue Jan 9, 2024 at 11:09 AM CET, Konrad Dybcio wrote:
On 1/5/24 15:54, Luca Weiss wrote:
Configure the thermals for the PA_THERM1, MSM_THERM, PA_THERM0,
RFC_CAM_THERM, CAM_FLASH_THERM and QUIET_THERM thermis
:
The devicetree schema core defines firmware-name as a string-array:
remove the override and narrow the number of expected file names to 1.
Besides,
Reviewed-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 4 ++--
.../devicetree/bindings
rious risks which I believe I really don't need to
describe, leaving it to the reader's imagination :-)
Please note that the first fix is URGENT.
P.S.: Of course, this was tested OK on multiple MTK platforms.
AngeloGioacchino Del Regno (2):
remoteproc: mediatek: Make sure IPI buffe
or the SCP at
all, if this is single core).
Fixes: 3efa0ea743b7 ("remoteproc/mediatek: read IPI buffer offset from FW")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/re
only available subnodes having compatible "mediatek,scp-core".
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Il 21/03/24 16:25, Mathieu Poirier ha scritto:
Good day,
On Thu, Mar 21, 2024 at 09:46:13AM +0100, AngeloGioacchino Del Regno wrote:
The IPI buffer location is read from the firmware that we load to the
System Companion Processor, and it's not granted that both the SRAM
(L2TCM) size th
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu, Mar 21, 2024 at 09:46:14AM +0100, AngeloGioacchino Del Regno wrote:
When probing multi-core SCP, this driver is parsing all sub-nodes of
the scp-cluster node, but one of those could be not an actual SCP core
and that would make the entire
Il 28/03/24 15:38, Mathieu Poirier ha scritto:
On Wed, Mar 27, 2024 at 01:49:58PM +0100, AngeloGioacchino Del Regno wrote:
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu, Mar 21, 2024 at 09:46:14AM +0100, AngeloGioacchino Del Regno wrote:
When probing multi-core SCP, this driver is
Il 02/04/24 16:23, Mathieu Poirier ha scritto:
On Tue, 2 Apr 2024 at 03:56, AngeloGioacchino Del Regno
wrote:
Il 28/03/24 15:38, Mathieu Poirier ha scritto:
On Wed, Mar 27, 2024 at 01:49:58PM +0100, AngeloGioacchino Del Regno wrote:
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu
;rockchip,rk3036-qos', 'rockchip,rk3066-qos',
'rockchip,rk3128-qos', 'rockchip,rk3228-qos', 'rockchip,rk3288-qos',
'rockchip,rk3368-qos', 'rockchip,rk3399-qos', 'rockchip,rk356
8-qos', 'rockchip,rk3588-qos', 'rockchip,rv1126-qos',
'starfive,jh7100-sysmain', 'ti,am62-usb-phy-ctrl', 'ti,am654-dss-oldi-io-ctrl',
'ti,am654-serdes-ctrl', 'ti,j784s4-pcie-ctrl']
from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml#
Signed-off-by: Luca Weiss
Reviewed-by: AngeloGioacchino Del Regno
Il 08/04/24 21:32, Luca Weiss ha scritto:
Add compatible for the Qualcomm MSM8974 APCS block.
Signed-off-by: Luca Weiss
Reviewed-by: AngeloGioacchino Del Regno
Il 11/04/24 05:37, olivia.wen ha scritto:
To Support MT8188 SCP core 1 for ISP driver.
The SCP on different chips will require different code sizes
and IPI buffer sizes based on varying requirements.
Signed-off-by: olivia.wen
---
drivers/remoteproc/mtk_common.h| 5 +--
drivers/remotep
:
- mediatek,mt8192-scp
- mediatek,mt8195-scp
- mediatek,mt8195-scp-dual
-
Don't remove the blank line, it's there for readability.
+ - mediatek,mt8188-scp-dual
After addressing that comment,
Reviewed-by: AngeloGioacchino Del Regno
reg:
d
Il 11/04/24 09:34, AngeloGioacchino Del Regno ha scritto:
Il 11/04/24 05:37, olivia.wen ha scritto:
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
---
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 3 ++-
1 file
Il 19/04/24 10:42, Olivia Wen ha scritto:
From: "olivia.wen"
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
Il 19/04/24 10:42, Olivia Wen ha scritto:
From: "olivia.wen"
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
ferent code and IPI share buffer sizes.
Introducing a structure mtk_scp_sizes_data to handle them.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
Il 24/04/24 05:03, Olivia Wen ha scritto:
MT8188 SCP has two RISC-V cores which is similar to MT8195 but without
L1TCM. We've added MT8188-specific functions to configure L1TCM in
multicore setups.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
Il 24/04/24 05:03, Olivia Wen ha scritto:
The SCP on different chips will require different DRAM sizes and IPI
shared buffer sizes based on varying requirements.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
a v4.
With that reordered,
Reviewed-by: AngeloGioacchino Del Regno
---
include/linux/remoteproc/mtk_scp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/remoteproc/mtk_scp.h
b/include/linux/remoteproc/mtk_scp.h
index 7c2b7cc9..344ff41 100644
--- a/include/linux/remot
Il 24/04/24 12:02, AngeloGioacchino Del Regno ha scritto:
Il 24/04/24 05:03, Olivia Wen ha scritto:
Integrate the imgsys core architecture driver for image processing on
the MT8188 platform.
Signed-off-by: Olivia Wen
This should be reordered before introducing the 8188 scp core 1 support
Il 30/04/24 03:15, Olivia Wen ha scritto:
Add an IPI command definition for communication with IMGSYS through
SCP mailbox.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
In scp_ipi_handler(), instead of zeroing out the entire shared
buffer, which may be as large as 600 bytes, overwrite it with the
received data, then zero out only the remaining bytes.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c | 2 +-
1 file changed, 1 insertion
Reviewed-by: AngeloGioacchino Del Regno
Il 05/06/24 21:35, Nícolas F. R. A. Prado ha scritto:
The scp_get() helper has two users: the mtk-vcodec and the mtk-mdp3
drivers. mdp3 considers the mediatek,scp phandle optional, and when it's
missing mdp3 will directly look for the scp node based on compatible.
For that reason printing an err
y, as you wish.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Jason Chen
---
drivers/remoteproc/mtk_scp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index b885a9a041e4..2119fc62c3f2 100644
--- a/dr
ot;)
Signed-off-by: Nícolas F. R. A. Prado
Reviewed-by: AngeloGioacchino Del Regno
Il 03/07/24 05:44, Jason Chen ha scritto:
The current DRAM size is insufficient for the HEVC feature, which
requires more memory for proper functionality. This change ensures the
feature has the necessary resources.
Signed-off-by: Jason Chen
Reviewed-by: AngeloGioacchino Del Regno
Il 03/07/24 13:53, Shun-yi Wang ha scritto:
From: "shun-yi.wang"
SCP supports multiple reserved memory regions, intended for
specific hardwards.
Signed-off-by: shun-yi.wang
---
drivers/remoteproc/mtk_scp.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
di
Il 09/09/24 20:37, Nícolas F. R. A. Prado ha scritto:
Currently the set_config callback in the gpio_chip registered by the
pinctrl_paris driver only supports PIN_CONFIG_INPUT_DEBOUNCE, despite
[...] only supports operations configuring the input debounce parameter
of the EINT controller and den
ough the children of the main SCP node and checking if
if there's more than one "mediatek,scp-core" compatible node.
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp
Il 19/09/23 07:03, Chen-Yu Tsai ha scritto:
In the just landed multi-core SCP work, detection of single/multi core
SCP is done by checking the immediate child node of the SCP complex
device node. In the original work this was done by matching the child
node's name. However the name wasn't previou
Il 20/09/23 17:03, Laura Nao ha scritto:
On 9/19/23 11:23, AngeloGioacchino Del Regno wrote:
In older devicetrees we had the ChromeOS EC in a node called "cros-ec"
instead of the newer "cros-ec-rpmsg", but this driver is now checking
only for the latter, breaking comp
ng in the MDP and the block really needs
recovery, this "trick" won't save anyone and the recovery will anyway be
triggered, as the PP-done will anyway timeout.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
MSM8998 support has been added: document the new compatible.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/net/qcom,ipa.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml
b/Documentation/devicetree
In GSI v1.0 the register GSI_HW_PARAM_2_OFFSET has different layout
so the number of channels and events per EE are, of course, laid out
in 8 bits each (0-7, 8-15 respectively).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 16 +---
drivers/net/ipa
In preparation for adding support for the MSM8998 SoC's IPA,
add the necessary bits for IPA version 3.1 featuring GSI 1.0,
found on at least MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 8
drivers/net/ipa/ipa_endpoint.c
The driver supports SC7180, but the binding was not documented.
Just add it.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/net/qcom,ipa.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/qcom
rm when
the modem is up.
This was tested on the F(x)Tec Pro 1 (MSM8998) smartphone.
AngeloGioacchino Del Regno (7):
net: ipa: Add support for IPA v3.1 with GSI v1.0
net: ipa: endpoint: Don't read unexistant register on IPAv3.1
net: ipa: gsi: Avoid some writes during irq setup for older
interrupts.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 6315336b3ca8..b5460cbb085c 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
On IPAv3.1 there is no such FLAVOR_0 register so it is impossible
to read tx/rx channel masks and we have to rely on the correctness
on the provided configuration.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/ipa_endpoint.c | 9 +
1 file changed, 9 insertions(+)
diff
MSM8998 features IPA v3.1 (GSI v1.0): add the required configuration
data for it.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/Makefile | 3 +-
drivers/net/ipa/ipa_data-msm8998.c | 407 +
drivers/net/ipa/ipa_data.h | 5
Il 11/02/21 21:19, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-13 10:38:13)
The function clk_gfx3d_determine_rate is selecting different PLLs
to manage the GFX3D clock source in a special way: this one needs
to be ping-pong'ed on different PLLs to ensure stab
Il 11/02/21 21:27, Alex Elder ha scritto:
On 2/11/21 11:50 AM, AngeloGioacchino Del Regno wrote:
Hey all!
This time around I thought that it would be nice to get some modem
action going on. We have it, it's working (ish), so just.. why not.
Thank you for the patches!
I would like to r
Il 12/02/21 10:24, Amit Pundir ha scritto:
Hi,
On Thu, 11 Feb 2021 at 00:25, AngeloGioacchino Del Regno
wrote:
Il 10/02/21 09:18, Amit Pundir ha scritto:
From: Sumit Semwal
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also
Il 10/02/21 09:18, Amit Pundir ha scritto:
From: Sumit Semwal
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also required to keep some of the regulators as
always-on.
Signed-off-by: Sumit Semwal
Signed-off-by: Amit Pundir
---
Il 02/02/21 19:45, Rob Clark ha scritto:
On Tue, Feb 2, 2021 at 6:32 AM AngeloGioacchino Del Regno
wrote:
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark
Il 28/01/21 10:13, Wolfram Sang ha scritto:
+ qcom,noise-reject-sda:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Noise rejection level for the SDA line.
+minimum: 0
+maximum: 3
+default: 0
What does this u32 describe? I wonder if we can introduce a generi
Il 29/01/21 10:14, Matti Vaittinen ha scritto:
On Thu, 2021-01-28 at 12:10 +, Mark Brown wrote:
On Thu, Jan 28, 2021 at 09:23:08AM +, Vaittinen, Matti wrote:
On Wed, 2021-01-27 at 16:32 +, Mark Brown wrote:
Note that the events the API currently has are expected to be for
the
actu
Il 31/01/21 20:50, Rob Clark ha scritto:
On Sat, Jan 9, 2021 at 5:51 AM AngeloGioacchino Del Regno
wrote:
The VCO rate was being miscalculated due to a big overlook during
the process of porting this driver from downstream to upstream:
here we are really recalculating the rate of the VCO by
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 2:11 AM AngeloGioacchino Del Regno
wrote:
Il 31/01/21 20:50, Rob Clark ha
() instead.
It didn't deadlock, but looking at it again -- oh my, I agree with you.
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 390af53e04114 ("regulator: qcom-labibb: Implement short-circuit and
over-current IRQs")
Signed-off-by: Matti Vaittinen
---
This fix is done pur
Il 02/02/21 08:36, Matti Vaittinen ha scritto:
If a spurious OCP IRQ occurs the isr schedules delayed work
but does not disable the IRQ. The delayed work assumes IRQ was
disabled in handler and attempts enabling it again causing
unbalanced enable.
You break the logic like this. Though, I also
Il 08/02/21 19:24, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59)
The GPU PLL0 is not a fixed PLL and the rate can be set on it:
this is necessary especially on boards which bootloader is setting
a very low rate on this PLL before booting Linux, which would be
Il 08/02/21 19:21, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
The pixel and byte clocks rate should not be cached, as a VCO shutdown
may clear the frequency setup and this may not be set again due to the
cached rate being present.
This will also be useful
Il 08/02/21 19:18, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:53)
The GPU IOMMU depends on this clock and the hypervisor will crash
the SoC if this clock gets disabled because the secure contexts
that have been set on this IOMMU by the bootloader will become
Il 10/01/21 18:18, Rob Herring ha scritto:
On Sat, 09 Jan 2021 14:29:18 +0100, AngeloGioacchino Del Regno wrote:
Document properties to configure soft start and discharge resistor
for LAB and IBB respectively.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/regulator/qcom-labibb
Il 10/01/21 20:35, Linus Walleij ha scritto:
On Sun, Jan 10, 2021 at 3:32 PM AngeloGioacchino Del Regno
wrote:
So, I've retried some basic usage of the regcache, relevant snippets here:
static bool aw9523_volatile_reg(struct device *dev, unsigned int reg)
{
retur
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 112 ++
1 file changed, 112 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1124 ++
3 files changed, 1142 insertions(+)
create
Il 11/01/21 14:16, Mark Brown ha scritto:
On Sat, Jan 09, 2021 at 02:29:15PM +0100, AngeloGioacchino Del Regno wrote:
+ .linear_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(460, 0, 15, 10),
+ },
+ .n_linear_ranges= 1,
If
Il 11/01/21 14:57, Mark Brown ha scritto:
On Sat, Jan 09, 2021 at 02:29:19PM +0100, AngeloGioacchino Del Regno wrote:
+ /* If the regulator is not enabled, this is a fake event */
+ if (!ops->is_enabled(vreg->rdev))
+ return 0;
Or handling the interrupt raced
Il 11/01/21 20:14, AngeloGioacchino Del Regno ha scritto:
Il 11/01/21 14:57, Mark Brown ha scritto:
On Sat, Jan 09, 2021 at 02:29:19PM +0100, AngeloGioacchino Del Regno
wrote:
+ /* If the regulator is not enabled, this is a fake event */
+ if (!ops->is_enabled(vreg-&g
Il 11/01/21 20:23, AngeloGioacchino Del Regno ha scritto:
Il 11/01/21 20:14, AngeloGioacchino Del Regno ha scritto:
Il 11/01/21 14:57, Mark Brown ha scritto:
On Sat, Jan 09, 2021 at 02:29:19PM +0100, AngeloGioacchino Del Regno
wrote:
+ /* If the regulator is not enabled, this is a fake
Il 08/12/20 19:11, Rob Herring ha scritto:
Hello! Replying very late seem to be obligatory for me nowadays
so for this and for any other late replies: I'm sorry!
On Thu, Nov 26, 2020 at 07:45:59PM +0100, AngeloGioacchino Del Regno wrote:
The OSM programming addition has been done unde
Il 12/01/21 18:29, Mark Brown ha scritto:
On Mon, Jan 11, 2021 at 10:06:18PM +0100, AngeloGioacchino Del Regno wrote:
...which was already a requirement before I touched it.
Now, this leaves two options here:
1. Keep the of_get_irq way, or
2. Move the interrupts, change the documentation
Il 09/01/21 14:37, AngeloGioacchino Del Regno ha scritto:
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always
checking if the relative CTL is started by waiting for an interrupt
to fire: it is fine to do that, but then sometimes we call this
function while the CTL is up and has
Add the MSM8998 to the blacklist since the CPU scaling is handled
out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.
Signed-off-by: AngeloGioacchino Del Regno
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 66052be495fb..3d9f9037f1c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14766,6
.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/spm.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 0c8aa9240c41..843732d12c54 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc
accordingly.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 339790ba585d..f9350
), while
needing SAW initialization for other purposes, like AVS control.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpuidle/Kconfig.arm| 1 +
drivers/cpuidle/cpuidle-qcom-spm.c | 294 ++---
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Mak
Add the SAWv4.1 parameters for MSM8998's Gold and Silver clusters.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/spm.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 843732d12c54..2e6312663293 1
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
1 file changed, 241 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff
In preparation for implementing a new driver that will be handling
CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new
file.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/cpr-common.c | 382
usters on these old ones... and, well, also
in 8998/630/660 along with the Hardened one... and the reason is...
that this piece of HW is also capable of doing the same with the GPU,
even though this is not yet implemented in this set.
I didn't feel like implementing the Multimedia Subsystem (M
ned-off-by: AngeloGioacchino Del Regno
---
.../bindings/power/avs/qcom,cpr.txt | 131 +-
.../bindings/soc/qcom/qcom,cpr.yaml | 167 ++
MAINTAINERS | 2 +-
3 files changed, 169 insertions(+), 131 deletions(-)
create m
Add the SDM630, SDM636 and SDM660 to the blacklist since the CPU
scaling is handled out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq
rs to support CPU scaling on SDM630
and MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 1248 -
1 file changed, 1216 insertions(+), 32 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/q
range of SoCs,
from the mid-range to the high end ones including, but not limited
to, MSM8953/8996/8998, SDM630/636/660/845.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Kconfig | 17 +
drivers/soc/qcom/Makefile |1 +
drivers/soc/qcom/cpr-common.c | 35
From: Manivannan Sadhasivam
Convert Qualcomm cpufreq devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 ---
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino
Il 12/01/21 15:59, Alexey Minnekhanov ha scritto:
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
ones?
But downstream sdm660.dtsi has a property "efficiency" [1] with values
which are larger for cores 100-103 than
probably will also be needed
for future SoCs.
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 24 +--
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm
On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
disable the feature when
preparing for cmd commit: instead of disabling it when initializing
the command mode, this road was chosen as to open future possibility
of enabling and managing the autorefresh feature in the driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../drm/msm/disp/dpu1
ed patches "drm/msm/dpu: Add a function to retrieve the current CTL
status"
and "drm/msm/dpu: Fix timeout issues on command mode panels" as the
second patch was wrong.
- Fixed patch apply issues on latest linux-next and 5.11-rcX
AngeloGioacchino Del
Not all DPU versions that are supported in this driver are supposed
to have a 8-Levels VIG QoS setting.
Move this flag to SDM845 and SC7180 specific masks.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
1 file changed, 3 insertions
event that we miss one
external TE signal: this will still trigger recovery mechanisms in
case the display is really unreachable.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
di
feature mask and the sblk config for
each DSPP.
Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu
driver")
Signed-off-by: AngeloGioacchino Del Regno
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 19 ---
1 file changed, 12 insertions(+), 7
ff-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 665eb1d
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1124 ++
3 files changed, 1142 insertions(+)
create
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 115 ++
1 file changed, 115 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
Il 13/01/21 05:37, Danny Lin ha scritto:
On Tue, Jan 12, 2021 at 8:04 pm, AngeloGioacchino Del Regno
wrote:
Il 12/01/21 15:59, Alexey Minnekhanov ha scritto:
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
Il 13/01/21 03:41, Rob Herring ha scritto:
On Mon, Jan 11, 2021 at 07:29:28PM +0100, AngeloGioacchino Del Regno wrote:
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 112
Il giorno lun 7 dic 2020 alle ore 07:43 Dmitry Torokhov
ha scritto:
>
> Hi AngeloGioacchino,
>
> On Wed, Oct 28, 2020 at 11:13:01PM +0100, khol...@gmail.com wrote:
> > +/**
> > + * nt36xxx_set_page - Set page number for read/write
> > + * @ts: Main driver structure
> > + *
> > + * Return: Always z
Pro1 (MSM8998)
AngeloGioacchino Del Regno (3):
dt-bindings: i2c: qcom,i2c-qup: Convert txt to YAML schema
i2c: qup: Introduce SCL/SDA noise rejection
dt-bindings: i2c: qcom,i2c-qup: Document noise rejection properties
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 ---
.../devicetree
Convert the qcom,i2c-qup binding to YAML schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 -
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 87 +++
2 files changed, 87 insertions(+), 40 deletions(-)
delete mode
rough device properties,
"qcom,noise-reject-sda" and "qcom,noise-reject-scl", which will
be used to set the level of noise rejection sensitivity.
If the properties are not specified, noise rejection will not be
enabled.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/
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