The assignment of rth->dst.output in vrf_rt6_create() and
vrf_rtable_create() used a hard tab before the '='. The neighboring
assignments did not. Make the assignment of rth->dst.output consistent
with the surrounding code.
Signed-off-by: Chris Packham
---
drivers/net/vrf.c
Add pin control information for the NAND flash interface. This interface
is multiplexed with the device bus interface to the function is "dev"
not "nand" as one might expect.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-38x.dtsi | 9 +
1 file changed, 9
Two typos in switchdev.txt
Signed-off-by: Chris Packham
---
Documentation/networking/switchdev.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/networking/switchdev.txt
b/Documentation/networking/switchdev.txt
index 3e7b946dea27..5e40e1f68873 100644
Hi Boris,
On 15/10/17 02:13, Boris Brezillon wrote:
> Hi Kalyan,
>
> On Thu, 28 Sep 2017 13:57:56 +1300
> Kalyan Kinthada wrote:
>
>> When the arbitration between NOR and NAND flash is enabled
>> the field bit[21] in the Data Flash Control Register
>> needs to be set to 1 according to guidlein
Check the return status of platform_driver_register() in
mv64x60_edac_init(). Only output messages and initialise the
edac_op_state if the registration is successful.
Signed-off-by: Chris Packham
---
Changes in v3:
- catch the retval of platform_register_drivers and return early on failure
To allow this driver to be used on non-powerpc platforms it needs to use
io accessors suitable for all platforms.
Signed-off-by: Chris Packham
---
Changes in v2:
- use readl/writel as suggested.
Changes in v3:
- None
drivers/edac/mv64x60_edac.c | 84
econd set of changes
for this driver but this first set is just a series of cleanups.
Chris Packham (3):
EDAC: mv64x60: check driver registration success
EDAC: mv64x60: Fix pdata->name
EDAC: mv64x60: replace in_le32/out_le32 with readl/writel
drivers/edac/mv64x60_eda
Change this from mpc85xx_pci_err to mv64x60_pci_err. The former is
likely a hangover from when this driver was created.
Signed-off-by: Chris Packham
---
Changes in v3:
- None
drivers/edac/mv64x60_edac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac
Hi Miquel,
On 09/10/17 19:19, Miquel RAYNAL wrote:
> Hello Kalyan,
>
> On Mon, 9 Oct 2017 02:31:30 +
> Kalyan Kinthada wrote:
>
>> On 05/10/17 20:41, Miquel RAYNAL wrote:
>>> Hello Kalyan,
>>>
>>> On Thu, 28 Sep 2017 13:57:56 +1300
>>> Kalyan Kinthada wrote:
>>>
When the arbitratio
On 02/08/18 23:05, Will Deacon wrote:
> On Thu, Aug 02, 2018 at 09:45:26AM +1200, Chris Packham wrote:
>> GCC warns
>>
>>arm_pmu_platform.c:234:5: error: 'err' may be used uninitialized in this
>> function [-Werror=maybe-uninitialized]
>>
>> Th
On 20/06/18 19:47, Boris Brezillon wrote:
> Hi Chris,
>
> On Wed, 20 Jun 2018 17:05:41 +1200
> Chris Packham wrote:
>
>> From the controllers point of view this is the same as no or
>> software only ECC.
>>
>> Reviewed-by: Boris Brezillon
>
> I
On 20/06/18 19:54, Boris Brezillon wrote:
> On Wed, 20 Jun 2018 17:05:43 +1200
> Chris Packham wrote:
>
>> Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
>> revision number field of the ONFI parameter page. Rather than rejecting
>> these outright
On 20/06/18 20:02, Boris Brezillon wrote:
> On Wed, 20 Jun 2018 17:05:44 +1200
> Chris Packham wrote:
>
>> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
>> per 512 bytes. Add support for this combination.
>>
>> Signed-off-by: Chris Packham
.
Signed-off-by: Chris Packham
---
I'm not convinced that just changing chip->ecc.mode is sensible. An
alternative I considered was only proceeding if the ecc.mode is set to
ON_DIE.
Changes in v4:
- New
drivers/mtd/nand/raw/nand_micron.c | 17 +++--
1 file changed, 15 in
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
drivers/mtd/nand/raw/marvell_nand.c | 1 +
1 file changed
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
This is now
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add doc comment and review from
Add defines for the ONFI version bits and use them in
nand_flash_detect_onfi().
Signed-off-by: Chris Packham
---
Changes in v4:
- New
drivers/mtd/nand/raw/nand_base.c | 10 +-
include/linux/mtd/rawnand.h | 11 +++
2 files changed, 16 insertions(+), 5 deletions(-)
diff
RFC
- dropped "mtd: rawnand: micron: add ONFI_FEATURE_ON_DIE_ECC to supported
features" which Boris has already picked up
- dropped "mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC"
since I can't test it.
Series changes in v4:
- based on top of http://
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, expand
comment for the ECC status
Add defines for the ONFI version bits and use them in
nand_flash_detect_onfi().
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v4:
- New
Changes in v5:
- Add review from Boris
drivers/mtd/nand/raw/nand_base.c | 10 +-
include/linux/mtd
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
---
Notes:
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, expand
co
p://patchwork.ozlabs.org/patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawnand: add defines for ONFI version bits
mtd: rawnand
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add doc
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
This is
.
Signed-off-by: Chris Packham
---
Notes:
Changes in v4:
- New
Changes in v5:
- fail if on-die ECC is mandatory and the current ecc.mode is not
NAND_ECC_ON_DIE.
drivers/mtd/nand/raw/nand_micron.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Notes:
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- N
Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
per 512 bytes. Add support for this combination.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Handle reporting of corrected errors that don't require a rewrite, e
p://patchwork.ozlabs.org/patch/932006/
Series changes in v5:
- address review comments from Boris on patches 5 and 6
Series changes in v6:
- Update commit message on 6/6
Chris Packham (6):
mtd: rawnand: marvell: Handle on-die ECC
mtd: rawnand: add manufacturer fixup for ONFI parameter page
mtd: rawna
>From the controllers point of view this is the same as no or
software only ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add review from Boris
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- None
drivers/mtd/nand/
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
This is now
This is called after the ONFI parameter page checksum is verified
and allows us to override the contents of the parameter page.
Suggested-by: Boris Brezillon
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v2:
- New
Changes in v3:
- Add doc comment and review from
Some Micron NAND chips have on-die ECC forceably enabled. Detect these
based on chip ID as there seems to be no other way of distinguishing
these chips from those that have optional support for on-die ECC.
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Add defines for the ONFI version bits and use them in
nand_flash_detect_onfi().
Signed-off-by: Chris Packham
Reviewed-by: Boris Brezillon
---
Changes in v4:
- New
Changes in v5:
- Add review from Boris
Changes in v6:
- None
drivers/mtd/nand/raw/nand_base.c | 10 +-
include/linux/mtd
_arch() and override whatever
arm_dt_init_cpu_maps() had configured. Now we move the initial
assignment of default smp_ops to a dt_fixup and let
arm_dt_init_cpu_maps() override that if the device tree defines an
enable-method.
Signed-off-by: Chris Packham
---
Pervious versions
v1:
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
Update the nand flash binding to the new style.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
b/arch/arm/boot/dts/armada-xp-db
This board is a plugin card for some of Marvell's switch development
kits. It's similar to the non-amc board except that it has no SATA
support.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/armada-385-db-88f6820-amc.dt
g4 which can be used if you disable the internal CPU on
those platforms.
Chris Packham (4):
ARM: dts: mvebu: 98dx3236: Rename nand controller node
ARM: dts: mvebu: db-dxbc2: use new style nand binding
ARM: dts: mvebu: db-xc3-24g4: use new style nand binding
ARM: dts: mvebu: Add device tree
Update the 98dx3236 SoC and dependent boards to use
"nand-controller" instead of "nand".
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +-
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg
this code would not be running.
Initialise err to 0 to avoid the warning.
Signed-off-by: Chris Packham
---
This has been reported before in https://lkml.org/lkml/2018/3/5/508 I'm not
sure if it was dismmissed as "meh, gcc is wrong" or if it was just wainting for
someone with some rou
On 11/05/17 15:45, Chris Packham wrote:
> Systems using 4-wire fans usually require high frequency (22.5kHz)
> output on the pwm. Add 22500 as a valid option in the pwmfreq_table. In
> high frequency mode the low-order bit are ignored so they can safely be
> set to 0.
>
> Si
To allow this driver to be used on non-powerpc platforms it needs to use
io accessors suitable for all platforms.
Signed-off-by: Chris Packham
---
drivers/edac/mv64x60_edac.c | 84 ++---
1 file changed, 42 insertions(+), 42 deletions(-)
diff --git a
Signed-off-by: Chris Packham
---
drivers/edac/mv64x60_edac.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac/mv64x60_edac.c
index 14b7e7b71eaa..454e1e26ee7c 100644
--- a/drivers/edac/mv64x60_edac.c
+++ b/drivers/edac/mv64x60_edac.c
@@ -853,8 +853,6
Change this from mpc85xx_pci_err to mv64x60_pci_err. The former is
likely a hangover from when this driver was created.
Signed-off-by: Chris Packham
---
drivers/edac/mv64x60_edac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac
On 15/05/17 02:54, Guenter Roeck wrote:
> On 05/10/2017 08:45 PM, Chris Packham wrote:
>> By default adt7475 will stop the fans (pwm duty cycle 0%) when the
>> temperature drops past Tmin - hysteresis. Some systems want to keep the
>> fans moving even when the temperature d
On 15/05/17 03:40, Guenter Roeck wrote:
> On 05/10/2017 08:45 PM, Chris Packham wrote:
>> When enabled temperature smoothing allows ramping the fan speed over a
>> configurable period of time instead of jumping to the new speed
>> instantaneously.
>>
>
When enabled temperature smoothing allows ramping the fan speed over a
configurable period of time instead of jumping to the new speed
instantaneously.
Signed-off-by: Chris Packham
---
Changes in v2:
- use a single tempN_smoothing attribute
Changes in v3:
- change enh_acou to enh_acoustics
minimum configure pwm duty cycle.
Signed-off-by: Chris Packham
---
Changes in v2:
- use pwmN_stall_dis as the attribute name. I think this describes the purpose
pretty well. I went with a new attribute instead of overloading
pwmN_auto_point1_pwm so this doesn't affect existing users.
Changes
Systems using 4-wire fans usually require high frequency (22.5kHz)
output on the pwm. Add 22500 as a valid option in the pwmfreq_table. In
high frequency mode the low-order bit are ignored so they can safely be
set to 0.
Signed-off-by: Chris Packham
---
Changes in v3:
- New
Changes in v4:
- Fix
Hi Gregory,
On 10/01/18 21:24, Gregory CLEMENT wrote:
> Hi Chris,
>
> On mar., janv. 09 2018, Chris Packham
> wrote:
>
> Could you have add a (even small) message in the commit log?
>
> Also could you improve the title by specify that it applies on
> armada-x
On 10/01/18 21:31, Gregory CLEMENT wrote:
> Hi Chris,
>
> On mar., janv. 09 2018, Chris Packham
> wrote:
>
>> The Armada-38x uses an SDRAM controller that is compatible with the
>> Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
>>
ce
is the width of the DDR interface.
[1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2
Changes in v2:
- update commit message
- add labels to dts
Chris Packham (3):
ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
ARM: dts: armada-xp: add label to sdr
The Armada-38x uses an SDRAM controller that is compatible with the
Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
is 32/16). The SDRAM controller registers are the same between the two
SoCs.
Signed-off-by: Chris Packham
---
Changes in v2:
- Add label to sdram-controller
Add the label "sdramc" to the sdram-controller nodes for the Armada-XP
and 98dx3236 SoCs.
Signed-off-by: Chris Packham
---
Changes in v2:
- New
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +-
arch/arm/boot/dts/armada-xp.dtsi | 2 +-
2 files changed, 2 insertions(+), 2
Enable L2 cache parity and ECC on the db-xc3-24g4xg board so that cache
operations are protected and errors can be flagged to the EDAC
subsystem.
Signed-off-by: Chris Packham
---
Changes in v2:
- Update commit message
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +
1 file changed, 5
On 11/01/18 22:14, Gregory CLEMENT wrote:
> Hi Chris,
>
> On jeu., janv. 11 2018, Chris Packham
> wrote:
>
>> I've split this off from my earlier series[1] this is just the dts changes
>> that
>> will enable support for the EDAC series when it land
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions(+)
diff --git a/drivers/edac/deb
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
---
MAINTAINERS | 6 +
drivers
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
2 files changed, 1 insertion(+), 1 d
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
[cp: use shorter names for some #defines]
Signed-off-by: Chris Packham
---
arch/arm/include
Hi Miquel, Ezequiel,
On 23/12/17 05:56, Ezequiel Garcia wrote:
> On 22 December 2017 at 12:53, Miquel RAYNAL
> wrote:
>> Hello Chris,
>>
>> On Fri, 22 Dec 2017 12:19:04 +1300
>> Chris Packham wrote:
>>
>>> From: Kalyan Kinthada
>>>
>>
On 08/01/18 11:35, Chris Packham wrote:
> Hi Miquel, Ezequiel,
>
> On 23/12/17 05:56, Ezequiel Garcia wrote:
>> On 22 December 2017 at 12:53, Miquel RAYNAL
>> wrote:
>>> Hello Chris,
>>>
>>> On Fri, 22 Dec 2017 12:19:04 +1300
>>
interface.
[1] - https://marc.info/?l=linux-edac&m=151030475715706&w=2
Chris Packham (3):
ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board
ARM: dts: mvebu: add sdram controller node to Armada-38x
EDAC: armada_xp: Add support for more SoCs
arch/arm/boot/dts/armada-3
The Armada-38x uses an SDRAM controller that is compatible with the
Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
is 32/16). The SDRAM controller registers are the same between the two
SoCs.
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-38x.dtsi | 5
Signed-off-by: Chris Packham
---
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 06fce35d7491..00ca489fc788 100644
--- a/arch/arm/boot/dts
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
Hi Christophe,
On 14/01/18 06:17, Christophe JAILLET wrote:
> Le 13/01/2018 à 15:22, Borislav Petkov a écrit :
>> + Chris Packham who's been fixing some stuff in here too.
>>
>> On Sat, Jan 13, 2018 at 08:28:21AM +0100, Christophe JAILLET wrote:
>>> Reorder
On 07/12/17 23:42, Wolfram Sang wrote:
> On Sun, Oct 29, 2017 at 06:29:18PM +0100, Wolfram Sang wrote:
>> On Wed, Jul 05, 2017 at 10:13:54PM +1200, Chris Packham wrote:
>>> This series addresses some of the points identified by Andy. The series is
>>> based on top of i2c
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
f_match_ptr() (review comments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
ARM: l2x0: support parity-enable/disable on aurora
dt-bindings: ARM: document marvell,ecc-enable binding
ARM: l2x0: add marvell,ecc-enable property for aurora
EDAC: armada_xp: Add support for more SoCs
Jan L
Add documentation for the marvell,ecc-enable properties which can be
used to enable ECC on the Marvell aurora cache.
Signed-off-by: Chris Packham
Reviewed-by: Rob Herring
---
Notes:
Changes in v7:
- remove marvell,ecc-disable
Changes in v6:
- new (split binding doc from
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
From: Jan Luebbe
The macro name is too generic, so add a AURORA_ prefix.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/include/asm/hardware/cache-aurora-l2.h | 2 +-
arch/arm/mm/cache-l2x0.c| 4 ++--
2 files changed
printf (review comment by Chris)
- L2 cache: Split error injection from the check function (review comment by
Chris)
- DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by
Chris)
- Use of_match_ptr() (review comments by Chris)
- Minor checkpatch cleanups
Chris Packham (4):
From: Jan Luebbe
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).
Signed-off-by: Jan Luebbe
[cp use SPDX license]
Signed-off-by: Chris Packham
The aurora cache on the Marvell Armada-XP SoC supports the same tag
parity features as the other l2x0 cache implementations.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_PARITY_EN]
Signed-off-by: Jan Luebbe
---
arch/arm/mm/cache-l2x0.c | 7 +++
1
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham
---
drivers/edac/
Add documentation for the marvell,ecc-enable and marvell,ecc-disable
properties which can be used to enable/disable ECC on the Marvell aurora
cache.
Signed-off-by: Chris Packham
---
Notes:
Changes in v6:
- new (split binding doc from implementation).
Documentation/devicetree/bindings
From: Jan Luebbe
We already have wrappers for x8 and x16, so add the missing x32 one.
Signed-off-by: Jan Luebbe
Reviewed-by: Borislav Petkov
Signed-off-by: Chris Packham
---
drivers/edac/debugfs.c | 11 +++
drivers/edac/edac_module.h | 5 +
2 files changed, 16 insertions
From: Jan Luebbe
These defines will be used by subsequent patches to add support for the
parity check and error correction functionality in the Aurora L2 cache
controller.
Signed-off-by: Jan Luebbe
Signed-off-by: Chris Packham
---
.../include/asm/hardware/cache-aurora-l2.h| 48
From: Jan Luebbe
This include file will be used by the AURORA EDAC code.
Signed-off-by: Jan Luebbe
Reviewed-by: Gregory CLEMENT
Signed-off-by: Chris Packham
---
arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h | 0
arch/arm/mm/cache-l2x0.c| 2 +-
The aurora cache on the Marvell Armada-XP SoC supports ECC protection
for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
which can be used to enable this.
Signed-off-by: Chris Packham
[j...@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
Signed-o
On 10/11/18 4:58 AM, Arnd Bergmann wrote:
> On Fri, Nov 9, 2018 at 12:48 PM Russell King - ARM Linux
> wrote:
>>
>> On Fri, Nov 09, 2018 at 12:40:06PM +0100, Arnd Bergmann wrote:
>>> On Fri, Nov 9, 2018 at 8:04 AM Chris Packham
>>> wrote:
>>>>
&
Hi Boris,
On 07/07/18 09:37, Boris Brezillon wrote:
> On Fri, 6 Jul 2018 21:27:20 +0200
> Boris Brezillon wrote:
>
>> On Mon, 25 Jun 2018 10:44:42 +1200
>> Chris Packham wrote:
>>
>>> Hi,
>>>
>>> I'm looking at adding support for the M
The MT29F1G08ABAFAWP-ITE:F chip has 2048 byte pages and requires a
minimum ECC strength of 8-bits. Allow for this combination of
requirements using the marvell_nand controller.
Signed-off-by: Chris Packham
---
I've tried to follow the recommended AN-379 from Marvell. They do seem
to
0 00 00 00 00 00 00 00 00 00
00f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 85 a6 ....
Chris Packham (2):
mtd: rawnand: handle ONFI revision number field being 0
mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC
drivers/mtd/nand/raw/marvell_
Some Micron NAND chips (MT29F1G08ABAFAWP-ITE:F) report 00 00 for the
revision number field of the ONFI parameter page. Rather than rejecting
these outright assume ONFI version 1.0 if the revision number is 00 00.
Signed-off-by: Chris Packham
---
At the moment I haven't qualified this che
On 19/06/18 01:15, Miquel Raynal wrote:
> Hi Chris,
>
> On Mon, 18 Jun 2018 16:52:53 +1200, Chris Packham
> wrote:
>
>> Hi,
>>
>> I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip
>> to one of our boards which uses the Marvell
On 19/06/18 12:35, Chris Packham wrote:
> On 19/06/18 01:15, Miquel Raynal wrote:
>> Hi Chris,
>>
>> On Mon, 18 Jun 2018 16:52:53 +1200, Chris Packham
>> wrote:
>>
>>> Hi,
>>>
>>> I'm looking at adding support for the Micron MT
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