driver still has some problems to support the LCDs, the
real LCD device nodes are not added to the device tree files.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts | 49 ++
arch/arm
于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai 写到:
>Hi,
>
>On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote:
>> When claiming SRAM, if the base is set to an error, it means that the
>> SRAM controller has been probed, but failed to remap the controller
>> memor
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.
Add binding for this.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de
于 2017年5月26日 GMT+08:00 下午4:59:18, Andre Przywara 写到:
>Hi,
>
>On 26/05/17 04:54, Chen-Yu Tsai wrote:
>> On Fri, May 26, 2017 at 6:30 AM, André Przywara
> wrote:
>>> On 25/05/17 20:26, Jagan Teki wrote:
From: Jagan Teki
Orangepi Win/WinPlus is an open-source single-board computer
>
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Commit message change.
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3
file for Allwinner R40
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (8):
arm: sunxi: add support for R40 SoC
pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
pinctrl: sunxi: add A20 support to A10 driver
pinctrl: sunxi: drop dedicated A20 driver
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Use V1.0 documents.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Enable A10 driver for A20 and disable A20 driver in this commit, in
order to prevent A10
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v3:
- Added Rob's ACK.
Document
control buttons
This patch adds a dts file that enables debug UART and MMC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Pinmux changes.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 157
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v3:
- Rebased on current linux-next.
- Added Rob'
retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Pinmux changes.
arch/arm/boot/dts/sun8i-r40.dtsi | 408
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Only remove the A20 driver(A10 driver for A20 is enabled in
the previous commit now).
drivers/pinctrl/sunxi/Kconfig
于 2017年5月30日 GMT+08:00 上午3:30:26, Jagan Teki 写到:
>From: Jagan Teki
>
>from BPI(BIPAI KEJI LIMITED) products the Bananapi board
>is named as 'Bananapi M1' and this is the starting
>bananapi board from M1 series.
>
>So rename dts and suffix 'M1' on model for the same,
>so-that next sequence on ba
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts
在 2017-11-02 15:11，Stephen Boyd 写道：
On 10/09, Icenowy Zheng wrote:
于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard
写到:
>On Fri, Oct 06, 2017 at 06:33:31AM +0000, Icenowy Zheng wrote:
>> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration
>register,
>>
在 2017-10-27 23:06，Icenowy Zheng 写道：
This patchset adds support for the SimpleFB on Allwinner SoCs with
"Display Engine 2.0".
PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
PATCH 4 adds the pipeline strings for DE2 SimpleFB.
PATCH 5 to 7 adds necessary device tree nodes (D
在 2017-11-02 17:02，Maxime Ripard 写道：
Hi,
On Wed, Nov 01, 2017 at 05:38:14PM +0800, Icenowy Zheng wrote:
Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
factor and GPIO holes similar to Raspberry Pi Zero.
It features:
- Allwinner H2+ SoC
- Single-chip (16-bit) 512MiB DDR3
在 2017-11-02 23:50，Maxime Ripard 写道：
On Thu, Nov 02, 2017 at 05:07:30PM +0800, Icenowy Zheng wrote:
> > +&mmc0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc0_pins_a>;
> > + vmmc-supply = <®_vcc3v3>;
> > +
Orange Pi R1 is a board design based on Orange Pi Zero, with XR819 Wi-Fi
chip replaced by RTL8189ETV Wi-Fi module and the USB Type-A jack
replaced by an onboard USB RTL8152B USB-Ethernet adapter.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng
---
Changes in v2
sions.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
adds USB host ports support.
Icenowy Zheng (5):
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
ARM: sun8i: v40: enable
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arc
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
Ch
CH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB.
Icenowy Zheng (10):
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
dt-bindings: simplefb-sunxi: add pipelin
hange the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
1 file changed
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47
1 file changed, 47
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2db5d4e00ea7..468d1abaf0ee 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-d
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Acked-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Adds Rob's ACK.
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4
1
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch
ff-by: Icenowy Zheng
---
Changes in v2:
- Adds description of the situation when the SRAM is not claimed.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
b/Documentation/devicetree/bin
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
1 file changed, 31 insertions
As the U-Boot bootloader now is also capable of initialize the HDMI on
A64 boards, add a simplefb device tree node for accessing the HDMI
framebuffer initialized by the bootloader.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped LCD SimpleFB as it's already added. LCD SimpleFB
在 2017-09-26二的 09:22 +0200，Corentin Labbe写道：
> The unit address and register address does not match.
> This patch fix the register address with the good one.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Corentin Labbe
This patch should be backported.
Older LTS also needs patches, but the patch
e-run dw_hdmi_setup when setting mode, in order to prevent such
situation.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
于 2018年7月25日 GMT+08:00 下午8:19:47, Maxime Ripard 写到:
>On Tue, Jul 24, 2018 at 10:42:32PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月24日 GMT+08:00 下午10:41:51, Maxime Ripard
> 写到:
>> >On Tue, Jul 24, 2018 at 10:37:51AM +0800, Chen-Yu Tsai wrote:
>&
于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3
于 2018年7月12日 GMT+08:00 下午2:46:01, Maxime Ripard 写到:
>On Wed, Jul 11, 2018 at 11:15:50PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月11日 GMT+08:00 下午11:05:32, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Wed, Jul 11, 2018 at 09:22:32PM +0800,
It seems that doing some operation will make the value pre-read on H3
SID controller wrong again, so all operation should be performed by
register.
Change the SID reading to use register only.
Signed-off-by: Icenowy Zheng
---
drivers/nvmem/sunxi_sid.c | 71
在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道：
> On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote:
> > This is the RFC initial patchset for the "new" Allwinner SUNIV ARM9 SoC.
> >
> > The same die is packaged differently, come with different co-pa
于 2018年1月25日 GMT+08:00 下午11:35:20, Maxime Ripard
写到:
>Hi,
>
>On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote:
>> 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道：
>> > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote:
>> > > This
于 2017年5月11日 GMT+08:00 下午10:01:54, Linus Walleij 写到:
>On Thu, May 4, 2017 at 1:57 AM, Andre Przywara
>wrote:
>
>> When a pinctrl driver gets interrupted during its probe process
>> (returning -EPROBE_DEFER), the devres system cleans up all allocated
>> resources. During this process it calls
>p
[1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html
Icenowy Zheng (13):
dt-bindings: add binding for the Allwinner DE2 CCU
clk: sunxi-ng: add support for DE2 CCU
dt-bindings: add bindings for DE2 on V3s SoC
drm/sun4i: return only planes for layers created
drm/sun4i: abstrac
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v7:
- Added V3s
pointer in sun4i_crtc struct.
Doing this uncouples the CRTC code from the type of layer (the
sun4i_layers_init function name is still hardcoded and will be changed
in the next patch), so that we can finally gain support for the
mixer in DE2, which has different layers.
Signed-off-by: Icenowy Zheng
Reviewe
nner, so I choose to call them both "engine" here.
Abstract the engine type to a new struct with an ops struct, which contains
functions that should be called outside the engine-specified code (in
TCON, CRTC or TV Encoder code).
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsa
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/s
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
Changes in v7:
- Fixed some parent clocks that are left open if the probe failed.
-
Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.
Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.
Signed-off-by: Icenowy Zheng
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files chang
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v7:
- Reduced some text.
Changes in v4:
- Removed the refact
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v7:
- Dropped the trailing "@0" in rgb666 pinmux node name.
-
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.
Add device nodes for this display pipeline.
Signed-off-by: Icenowy Zheng
---
Changes in v7:
- Change DE2 clock compatible to V3s one.
- Mentio
As sun4i-backend is now a dedicated module, add an Kconfig option for
it to make it optional, since some build may only use other engines.
Signed-off-by: Icenowy Zheng
---
Changes in v7:
- Adjusted the position of BACKEND makefile item. (It's now after
common codes shared between sun4i-ba
missing -- more investigations
are needed to gain enough information for them.
Signed-off-by: Icenowy Zheng
---
Changes in v7:
- Small fixed advised by Maxime Ripard.
- Added fixup on CRTC destination coordinate.
Changes in v6:
- Rebased on wens's multi-pipeline patchset.
Changes in v5:
于 2017年5月15日 GMT+08:00 下午5:20:01, Maxime Ripard
写到:
>On Mon, May 15, 2017 at 12:30:37AM +0800, Icenowy Zheng wrote:
>> As we are going to add support for the Allwinner DE2 engine in
>sun4i-drm
>> driver, we will finally have two types of display engines -- the DE1
>> b
As DE2 support for more SoCs are introducing, there's many reports that
the DE2 is not functional due to DE2 CCU code not included in kernel.
Defaultly enable DE2 CCU for sun8i/sun50i to reduce this kind of
problems.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 2 ++
1
在 2018年1月11日星期四 CST 下午5:36:39，Linus Walleij 写道：
> On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng wrote:
> > This patchset adds initial support for the Allwinner H6 SoC.
>
> Can I apply the pin control patches without the clock patches?
I think it's OK.
Note: on H6 now the p
于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到:
>Hi,
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>>
>> Add support for this kind of pin controllers.
&g
在 2018年1月11日星期四 CST 下午6:41:00，Maxime Ripard 写道：
> On Thu, Jan 11, 2018 at 10:23:52AM +, Andre Przywara wrote:
> > Hi,
> >
> > On 11/01/18 10:14, Chen-Yu Tsai wrote:
> > > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
wrote:
> > >> Hi,
> > &
于 2018年1月11日 GMT+08:00 下午7:48:40, Andre Przywara 写到:
>Hi,
>
>another take to avoid this patch at all, I just remembered this from an
>IRC discussion before:
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs
于 2018年1月19日 GMT+08:00 下午2:25:09, Chen-Yu Tsai 写到:
>Hi Kishon,
>
>On Mon, Jan 15, 2018 at 11:06 PM, Hermann Lauer
> wrote:
>> On Wed, Jan 03, 2018 at 04:49:44PM +0800, Icenowy Zheng wrote:
>>> Allwinner R40 features a USB PHY like the one in A64, but with 3
>PH
在 2018年1月20日星期六 CST 上午5:14:09，Rob Herring 写道：
> On Thu, Jan 11, 2018 at 11:03:43AM +0800, Yong Deng wrote:
> > Add binding documentation for Allwinner V3s CSI.
> >
> > Signed-off-by: Yong Deng
> > ---
> >
> > .../devicetree/bindings/media/sun6i-csi.txt| 59
> > ++ 1
GIC nor arch_timer, like the sun4i/5i Cortex-A8
SoCs. So adapt the IRQ and timer driver used by sun4i/5i to support
suniv. This is PATCH 3~5.
Then it's the common way to support a new SoC -- pinctrl, CCU and
initial DT.
Icenowy Zheng (9):
ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARM
CONFIG_ARCH_SUNXI_V7
option.
Signed-off-by: Icenowy Zheng
---
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm/configs/sunxi_defconfig| 2 +-
arch/arm/mach-sunxi/Kconfig | 14 --
arch/arm/mach-sunxi/Makefile| 2 +-
4 files changed, 15 insertions(+), 5
The new F-series SoCs (suniv) from Allwinner use an stripped version of
the interrupt controller in A10/A13.
Add support for it in irq-sun4i driver.
Signed-off-by: Icenowy Zheng
---
drivers/irqchip/irq-sun4i.c | 43 ++-
1 file changed, 38 insertions
Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die used
for many new F-series products, including F1C100A, F1C100s, F1C200s,
F1C500, F1C600).
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig| 13 +
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach
The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S
CPU, thus it has no architecture timer.
Register sun4i_timer as sched_clock on it.
Signed-off-by: Icenowy Zheng
---
drivers/clocksource/sun4i_timer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
The suniv SoC (the chip in some new F-series products of Allwinner) has
a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.
Add support for the CCU.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile
Lichee Pi Nano is a F1C100s board by Lichee Pi.
Add initial device tree for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 27 +++
1 file changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi
As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As there's nothing special for it, add a dummy DTSI file
for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boo
The suniv (new F-series) chip has a timer with less functionality than
the A10 timer, e.g. it has only 3 channels.
Add a new compatible for it. As we didn't use the extra channels on A10
either now, the code needn't to be changed.
Signed-off-by: Icenowy Zheng
---
drivers/c
The suniv chip (several new F-series SoCs) of Allwinner has a pin
controller like other SoCs from Allwinner.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile| 1 +
drivers/pinctrl/sunxi/pinctrl-suniv.c
于 2018年1月20日 GMT+08:00 上午11:06:40, Julian Calaby 写到:
>Hi Icenowy,
>
>On Sat, Jan 20, 2018 at 10:17 AM, Icenowy Zheng
>wrote:
>> Add option for Allwinner ARMv5 SoCs and a SoC suniv (which is a die
>used
>> for many new F-series products, including F1C100A, F1C100s,
于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard
写到:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > > This commit add
于 2018年1月4日 GMT+08:00 上午5:32:26, "Jernej Škrabec" 写到:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions needed
>to
>> > implement A8
: Icenowy Zheng
---
The NS1066 chip from the same vendor seems to also suffer from this
problem (its USB ID is 2537:1066) according to the report of Armbian
community. However I don't have such device (I have a USB HDD enclosure
with USB ID 2537:1066, but it doesn't report UAS function
one is A80).
This patchset adds the most basical support for it, including the main pin
controller, the main CCU and the basical device tree.
Icenowy Zheng (7):
pinctrl: sunxi: add support for pin controllers without bus gate
pinctrl: sunxi: support pin controllers with holes among IRQ banks
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1
hardware IRQ bank map, so
the new situation in H6 main pin controller can be processed. The old
special situation which uses a constant offset (on A33 and V3s, both
with a offset of 1) can be also processed with the new code.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
iver
format.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 +-
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 679 ++
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---
drivers/clk/sun
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig |5 +
drivers/clk/sunxi-ng
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng
---
arch/arm64
and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Z
于 2018年1月7日 GMT+08:00 上午6:12:57, Hans de Goede 写到:
>Hi,
>
>On 05-01-18 17:56, Icenowy Zheng wrote:
>> The UAS mode of Norelsys NS1068(X) is reported to fail to work on
>> several platforms with the following error message:
>>
>> xhci-hcd xhci-hcd.0.auto: ERROR
在 2018年1月25日星期四 CST 下午11:35:20，Maxime Ripard 写道：
> Hi,
>
> On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote:
> > 在 2018年1月22日星期一 CST 下午8:14:35，Maxime Ripard 写道：
> >
> > > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote:
> > > >
t;>> This commit reworks the code and allows the sampling start/end code
>and
>>> the position of value readout register to be altered. Later the
>start/end
>>> functions will be used to configure the ths and start/stop the
>>> sampling.
>>>
>>&g
于 2018年1月28日 GMT+08:00 下午9:46:18, Philipp Rossak 写到:
>
>
>On 28.01.2018 10:02, Jonathan Cameron wrote:
>> On Fri, 26 Jan 2018 16:19:32 +0100
>> Philipp Rossak wrote:
>>
>>> This patch reworks the driver to support nvmem calibration cells.
>>> The driver checks if the nvmem calibration is suppo
于 2018年1月30日 GMT+08:00 上午2:05:26, Rob Herring 写到:
>On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote:
>> This commit adds all necessary compatibles and descriptions needed to
>> implement A83T HDMI pipeline.
>>
>> Mixer is already properly described, so only compatible is added.
>>
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