On 03/12/15 11:52, Brian Norris wrote:
> Hi,
>
> On Thu, Dec 03, 2015 at 11:38:14AM +0530, Roger Quadros wrote:
>> On 03/12/15 10:39, Brian Norris wrote:
>>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>>>> We do a couple of things in this
Peter,
On 03/12/15 13:49, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:11PM +0300, Roger Quadros wrote:
>> Hi,
>>
>> This series centralizes OTG/Dual-role functionality in the kernel.
>> As of now I've got Dual-role functionality working pretty reliably
Brian,
On 03/12/15 10:39, Brian Norris wrote:
> Hi,
>
> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>> Hi,
>>
>> We do a couple of things in this series which result in
>> cleaner device tree implementation, faster perfomance and
>> multi
Brian,
On 03/12/15 09:59, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Oct 06, 2015 at 01:35:48PM +0300, Roger Quadros wrote:
>> Move NAND specific device tree parsing to NAND driver.
>>
>> The NAND controller node must have a compatible id, register space
>>
Brian,
On 02/12/15 08:56, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Dec 01, 2015 at 04:41:16PM +0200, Roger Quadros wrote:
>> On 30/11/15 21:54, Brian Norris wrote:
>>> On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote:
>>>> On 26/10/15 23:23, B
Hi Brian,
On 30/11/15 21:54, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote:
>> On 26/10/15 23:23, Brian Norris wrote:
>>> I'm not too familiar with OMAP platforms, and I might have missed out on
>>> prior
Daniel,
On 24/11/15 15:36, Daniel. wrote:
> Hi Michael
>
> About this:
> "Two bugs are fixed by this patch. First, OMAP hardware only supports
> target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
> should not wait for these clocks to enable. So, split the appropriate
>
Hi,
On 03/09/15 10:39, Roger Quadros wrote:
> On 28/07/15 14:34, Roger Quadros wrote:
>> Paul,
>>
>> On 16/07/15 16:56, Roger Quadros wrote:
>>> On 16/07/15 04:25, Paul Walmsley wrote:
>>>> Hi
>>>>
>>>> On Tue, 23 Jun 2015, Roge
Brian,
On 27/10/15 11:37, Roger Quadros wrote:
> Hi Brian,
>
> On 26/10/15 23:23, Brian Norris wrote:
>> Hi Roger,
>>
>> I'm not too familiar with OMAP platforms, and I might have missed out on
>> prior discussions/context, so please forgive if I'm ask
Hi,
On 25/08/15 17:50, Ulf Hansson wrote:
> On 3 August 2015 at 14:26, Kishon Vijay Abraham I wrote:
>> From: Roger Quadros
>>
>> For platforms that doesn't have explicit regulator control in MMC,
>> populate voltage-ranges in MMC device tree node and us
ep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ
>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver.
>> This causes performance increase when using prefetch-irq mode.
>> 30%
Boris,
On 27/10/15 10:12, Boris Brezillon wrote:
> Hi Roger,
>
> On Tue, 27 Oct 2015 10:03:02 +0200
> Roger Quadros wrote:
>
>> On 26/10/15 22:49, Brian Norris wrote:
>>>
>>> Others have been looking at using GPIOs for the ready/busy pin too. At a
>>
On 26/10/15 22:49, Brian Norris wrote:
> + others
>
> A few comments below.
>
> On Fri, Sep 18, 2015 at 05:53:40PM +0300, Roger Quadros wrote:
>> The GPMC WAIT pin status are now available over gpiolib.
>> Update the omap_dev_ready() function to use gpio instead of
On 21/10/15 18:20, Tony Lindgren wrote:
> * Roger Quadros [151021 01:31]:
>> On 19/10/15 10:08, Roger Quadros wrote:
>>> On 17/10/15 00:25, Tony Lindgren wrote:
>>>> * Roger Quadros [151006 04:13]:
>>>>>
>>>>> Fine. The updated s
On 19/10/15 10:08, Roger Quadros wrote:
> On 17/10/15 00:25, Tony Lindgren wrote:
>> * Roger Quadros [151006 04:13]:
>>>
>>> Fine. The updated series is now at
>>>
>>> g...@github.com:rogerq/linux.git
>>> * [new branch] for-v4.4/gpmc-v
On 19/10/15 19:01, Tony Lindgren wrote:
> * Roger Quadros [151014 03:48]:
>> Let's keep the SSI ports disabled in the omap3.dtsi to avoid
>> getting the following noise on the console for boards that don't
>> use the SSI ports.
>>
>> "omap_ssi_p
On 17/10/15 00:25, Tony Lindgren wrote:
> * Roger Quadros [151006 04:13]:
>>
>> Fine. The updated series is now at
>>
>> g...@github.com:rogerq/linux.git
>> * [new branch] for-v4.4/gpmc-v4
>
> Looks like it produces some build errors, this
> am37x gp evm
>
> This patchset depends on Roger Quadros recent v4 GPMC/NAND patchset
> https://github.com/rogerq/linux.git
> branch: for-v4.4/gpmc-v4
>
> Franklin S Cooper Jr (5):
> mtd: nand: omap2: Support parsing dma channel information from DT
> mtd: nand: omap2:
On 15/10/15 19:27, Franklin S Cooper Jr wrote:
> GPMC address information is provided by device tree. No longer need
> to include this information within hwmod.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
--
cheers,
-roger
--
To unsubscribe from this list: s
On 15/10/15 19:27, Franklin S Cooper Jr wrote:
> ELM address information is provided by device tree. No longer need
> to include this information within hwmod.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
--
cheers,
-roger
--
To unsubscribe from this list: s
On 14/10/15 23:03, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 01:13 PM, Tony Lindgren wrote:
>> * Franklin S Cooper Jr. [151014 09:27]:
>>>
>>> On 10/14/2015 11:18 AM, Tony Lindgren wrote:
>>>> * Franklin S Cooper Jr. [151014 07:37]:
>
On 14/10/15 16:34, Franklin S Cooper Jr. wrote:
>
>
> On 09/18/2015 09:53 AM, Roger Quadros wrote:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>&g
On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 06:52 AM, Roger Quadros wrote:
>> Franklin,
>>
>> On 14/10/15 14:36, Roger Quadros wrote:
>>> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>>>> Switch from dma_request_channel to
On 14/10/15 14:37, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Oct 14, 2015 at 02:27:27PM +0300, Roger Quadros wrote:
>> On 14/10/15 14:19, Sebastian Reichel wrote:
>>> On Wed, Oct 14, 2015 at 01:44:16PM +0300, Roger Quadros wrote:
>>>> Let's keep the SSI
Franklin,
On 14/10/15 14:36, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> Switch from dma_request_channel to allow passing dma channel
>> information from DT rather than hardcoding a value.
>>
>> Signed-off-by: Franklin S Cooper Jr
&
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add additional details to the gpmc and nand documentation to clarify
> what is needed to enable nand dma prefetch.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 7
> ++-
>
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add dma channel information to the gpmc. Although not enabled by
> default this will allow prefetch-dma to be used.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> arch/arm/boot/dts/am33xx.dtsi | 2 ++
> arch/arm/boot/dts/am4372.dtsi | 2 ++
> arc
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> The prefetch engine sends a dma request once a FIFO threshold has
> been met. No other requests are received until the previous request
> is handled.
>
> Starting an edma transfer (dma_async_issue_pending) results in any
> previous event for the dma
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Switch from dma_request_channel to allow passing dma channel
> information from DT rather than hardcoding a value.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
> ---
> drivers/mtd/nand/omap2.c | 4 +++-
&g
On 14/10/15 14:19, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Oct 14, 2015 at 01:44:16PM +0300, Roger Quadros wrote:
>> Let's keep the SSI ports disabled in the omap3.dtsi to avoid
>> getting the following noise on the console for boards that don't
>> us
Vignesh,
On 14/10/15 12:12, Vignesh R wrote:
>
>
> On 10/14/2015 02:16 PM, Roger Quadros wrote:
>
>>
>> On 14/10/15 08:52, Vignesh R wrote:
>>> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
>>> state via pinctrl and IO d
here.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/omap3-n900.dts | 1 +
arch/arm/boot/dts/omap3.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 5f5e0f3..bdb72fb 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
8c8/0x1f0c)
[ 30.320983] [] (load_module) from []
(SyS_init_module+0xdc/0x150)
[ 30.329223] [] (SyS_init_module) from []
(ret_fast_syscall+0x0/0x1c)
Signed-off-by: Roger Quadros
---
drivers/hsi/controllers/omap_ssi_port.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
Hi,
This series fixes warnings and console noise for boards that don't use
ssi ports. Tested on beagleboard-c4.
cheers,
-roger
Roger Quadros (2):
hsi: omap_ssi_port: Prevent warning if cawake_gpio is not defined.
ARM: dts: omap3: keep ssi ports by default
arch/arm/boot/dts/omap3-n90
: Roger Quadros
---
v4: Applied Tony's patch to fix broken ethernet on torpedo.
updated v4 series available at
g...@github.com:rogerq/linux.git
* [branch] for-v4.4/gpmc-v4
arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 3 ++-
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+Dave
On 14/10/15 08:52, Vignesh R wrote:
> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
> state via pinctrl and IO daisy chain using generic wakeirq framework.
> With commit 3fffd1283927 ("i2c: allow specifying separate wakeup
> interrupt in device tree") i2c core allows
Tony,
On 13/10/15 18:18, Tony Lindgren wrote:
> * Roger Quadros [151012 23:33]:
>> On 13/10/15 03:43, Tony Lindgren wrote:
>>> * Roger Quadros [150918 08:00]:
>>>> Add compatible id, GPMC register resource and interrupt
>>>> resource to NAND contr
On 13/10/15 16:44, Franklin S Cooper Jr wrote:
> ELM address information is provided by device tree. No longer need
> to include this information within hwmod.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
Franklin,
Can you please do the same for gpmc_addr a
Ben,
On 13/10/15 11:23, Ben Dooks wrote:
> On 12/10/15 20:19, Tony Lindgren wrote:
>> * Ben Dooks [151012 11:22]:
>>> On 12/10/15 18:45, Tony Lindgren wrote:
* Ben Dooks [151012 10:38]:
> The AM3715 OHCI controller will not function without the EHCI
> unit's 120m fclk being enabled.
On 13/10/15 03:43, Tony Lindgren wrote:
> * Roger Quadros [150918 08:00]:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller an
On 07/10/15 16:40, Tony Lindgren wrote:
> * Roger Quadros [151007 04:12]:
>> On 07/10/15 14:02, Uwe Kleine-König wrote:
>>> Hello Tony,
>>>
>>> On Wed, Oct 07, 2015 at 03:41:19AM -0700, Tony Lindgren wrote:
>>>> * Uwe Kleine-König [151007 00:57]
On 07/10/15 14:02, Uwe Kleine-König wrote:
> Hello Tony,
>
> On Wed, Oct 07, 2015 at 03:41:19AM -0700, Tony Lindgren wrote:
>> * Uwe Kleine-König [151007 00:57]:
>>> On Wed, Oct 07, 2015 at 10:45:50AM +0300, Roger Quadros wrote:
>>>>
>>>> Ho
On 06/10/15 23:07, Uwe Kleine-König wrote:
> Most register values for the chip select setup depend on the frequency
> of the fck clock.
> So add a hint that the values setup by the bootloader might differ from
> the right setup for Linux if the bootloader uses a different frequency.
>
> Signed-off
On 06/10/15 23:07, Uwe Kleine-König wrote:
> When gpmc_cs_show_timings is called in gpmc_cs_set_timings()
> gpmc_cs_program_settings() was already run which modifies the CONFIG1
> register. So to be more useful do the "before" dump earlier.
>
> Signed-off-by: Uwe Klein
45b1013 ("memory: omap-gpmc: Add Kconfig option for debug")
> Reported-by: Uwe Kleine-König
> Signed-off-by: Tony Lindgren
Acked-by: Roger Quadros
> ---
> drivers/memory/Kconfig | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> --- a/drivers/me
On 06/10/15 14:01, Tony Lindgren wrote:
> * Roger Quadros [151006 03:32]:
>> On 06/10/15 13:05, Roger Quadros wrote:
>>> On 06/10/15 13:00, Tony Lindgren wrote:
>>>> * Roger Quadros [151006 02:59]:
>>>>> On 06/10/15 11:33, Tony Lindgren wrote:
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
v4: Warn if using older incompatible DT i.e. compatible property not present
in nand node.
arch/arm/mach
On 06/10/15 13:05, Roger Quadros wrote:
> On 06/10/15 13:00, Tony Lindgren wrote:
>> * Roger Quadros [151006 02:59]:
>>> On 06/10/15 11:33, Tony Lindgren wrote:
>>>> Does build and boot and use NAND work throughtout the series?
>>>> Otherwise we'll
On 06/10/15 13:00, Tony Lindgren wrote:
> * Roger Quadros [151006 02:59]:
>> On 06/10/15 11:33, Tony Lindgren wrote:
>>> Does build and boot and use NAND work throughtout the series?
>>> Otherwise we'll have hard time bisecting anything..
>>
>&g
On 06/10/15 11:33, Tony Lindgren wrote:
> * Roger Quadros [150930 04:04]:
>> Tony,
>>
>> On 18/09/15 17:53, Roger Quadros wrote:
>>> Hi,
>>>
>>> We do a couple of things in this series which result in
>>> cleaner device tree implementation
Tony,
On 18/09/15 17:53, Roger Quadros wrote:
> Hi,
>
> We do a couple of things in this series which result in
> cleaner device tree implementation, faster perfomance and
> multi-platform support. As an added bonus we get new GPI/Interrupt pins
> for use in the system.
>
&
Brian/David,
On 18/09/15 17:53, Roger Quadros wrote:
> Hi,
>
> We do a couple of things in this series which result in
> cleaner device tree implementation, faster perfomance and
> multi-platform support. As an added bonus we get new GPI/Interrupt pins
> for use in the system.
Hi Felipe,
I see the following warning when g_zero is loaded
and USB cable is plugged to host on dra7-evm's USB1 port.
It happens only once and no longer appears on re-loading gadget
or plugging/unplugging cable.
root@rockdesk:~# modprobe g_zero
[ 28.414895] zero gadget: Gadget Zero, version:
Paul,
On 16/07/15 16:56, Roger Quadros wrote:
> On 16/07/15 04:25, Paul Walmsley wrote:
>> Hi
>>
>> On Tue, 23 Jun 2015, Roger Quadros wrote:
>>
>>> For some hwmods (e.g. DCAN on DRA7) we need the possibility to
>>> disable HW_AUTO for the clock
for OMAP5. So now the flag appears twice in the expression.
>
> make coccicheck complains with the following message:
>
> omap_hwmod_54xx_data.c:1846:37-58: duplicated argument to & or |
>
> Signed-off-by: Javier Martinez Canillas
Acked-by: Roger Quadros
>
> -
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 ---
include/linux/platform_data/gpmc-omap.h | 137
2 files changed, 137
,
-roger
Changelog:
v3:
-Fixed and tested NAND using legacy boot on omap3-beagle.
-Support rising and falling edge interrupts on WAITpins.
-Update DT node of all gpmc users.
Roger Quadros (27):
ARM: OMAP2+: gpmc: Add platform data
ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --gi
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index a80c53e
gpmc_nand_regs. This API will be called by the OMAP NAND driver
to access the necessary bits in GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 21
include/linux/omap-gpmc.h | 49 --
2 files changed, 68
write speed is 6537 KiB/s
[ 36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s
Test results on dra7-evm using mtd_speedtest.ko
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 65 +++-
1 file changed, 31 insertions(+), 34
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 f
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree
The WAIT pins support either rising or falling edge interrupts
so add irqchip support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 132 +
1 file changed, 132 insertions(+)
diff --git a/drivers/memory/omap
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 130
: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 5 -
arch/arm/boot/dts/dra7.dtsi | 4
arch/arm/boot/dts/dra72-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a6c82e5..8a31161
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux
d was unchanged at 9941 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am437x-gp-evm.dts | 3 +--
arch/arm/boot/dts/am43x-epos-evm.dts | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arc
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra72
: Roger Quadros
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 3 +++
arch/arm/boot/dts/am335x-evm.dts | 3 +++
arch/arm/boot/dts/am335x-igep0033.dtsi | 3 +++
arch/arm/boot/dts/am33xx.dtsi | 4
4 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi
: Roger Quadros
---
arch/arm/boot/dts/am4372.dtsi| 4
arch/arm/boot/dts/am437x-gp-evm.dts | 5 -
arch/arm/boot/dts/am43x-epos-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index
Make gpmc node gpio+interrupt capable.
Add compatible id, interrupt and wait pin to NAND node.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dm8168-evm.dts | 7 ---
arch/arm/boot/dts/dm816x.dtsi| 4
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot
d was unchanged at 5100 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 4 +---
arch/arm/boot/dts/am335x-evm.dts | 4 +---
arch/arm/boot/dts/am335x-igep0033.dtsi | 4 +---
3 files changed, 3 insertions(+), 9 deletions(-)
: Roger Quadros
---
arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +--
arch/arm/boot/dts/omap3-beagle.dts | 2 ++
arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 -
arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 +++
arch/arm/boot/dts/omap3-evm-37xx.dts | 7
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 163
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
On 06/09/15 05:20, Peter Chen wrote:
> On Wed, Sep 02, 2015 at 09:43:38AM -0500, Felipe Balbi wrote:
>> Hi,
>>
>>> +
>>> +static irqreturn_t dwc3_otg_irq(int irq, void *_dwc)
>>> +{
>>> + struct dwc3 *dwc = _dwc;
>>> + irqreturn_t ret = IRQ_NONE;
>>> + u32 reg;
>>> +
>>> + spin_lock(&dwc->l
Tony,
On 03/09/15 10:36, Roger Quadros wrote:
> Chanwoo,
>
> On 06/08/15 02:36, Chanwoo Choi wrote:
>> On 08/05/2015 07:37 PM, Tony Lindgren wrote:
>>> * Roger Quadros [150727 06:13]:
>>>> The VBUS line of USB2 is connected to VBUS detect logic on
>>
On 10/09/15 08:35, Peter Chen wrote:
> On Wed, Sep 09, 2015 at 01:21:50PM +0300, Roger Quadros wrote:
>> On 09/09/15 11:45, Peter Chen wrote:
>>> On Wed, Sep 09, 2015 at 12:33:20PM +0300, Roger Quadros wrote:
>>>> On 09/09/15 11:13, Peter Chen wrote:
>>>>
On 10/09/15 12:28, Li Jun wrote:
> On Wed, Sep 09, 2015 at 01:01:14PM +0300, Roger Quadros wrote:
> ... ...
>
>>>>>> +return -EINVAL;
>>>>>
>>>>> Return non-zero, then if err, do we need call usb_otg_add_hcd() after
>>
(adding back folks in cc)
On 08/09/15 20:35, Alan Stern wrote:
> On Tue, 8 Sep 2015, Roger Quadros wrote:
>
>>>> What if there is another architecture like so?
>>>>
>>&
On 09/09/15 11:45, Peter Chen wrote:
> On Wed, Sep 09, 2015 at 12:33:20PM +0300, Roger Quadros wrote:
>> On 09/09/15 11:13, Peter Chen wrote:
>>> On Wed, Sep 09, 2015 at 12:08:10PM +0300, Roger Quadros wrote:
>>>> On 09/09/15 05:21, Peter Chen wrote:
>>>>
On 09/09/15 09:20, Li Jun wrote:
> On Mon, Sep 07, 2015 at 01:53:19PM +0300, Roger Quadros wrote:
>> On 07/09/15 10:40, Li Jun wrote:
>>> On Mon, Aug 24, 2015 at 04:21:18PM +0300, Roger Quadros wrote:
>>>> The OTG core instantiates the OTG Finite State Machine
>&
On 09/09/15 05:23, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:21PM +0300, Roger Quadros wrote:
>> The existing usb_add/remove_hcd() functionality
>> remains unchanged for non-OTG devices. For OTG
>> devices they only register the HCD with the OTG core.
>>
>>
On 09/09/15 11:13, Peter Chen wrote:
> On Wed, Sep 09, 2015 at 12:08:10PM +0300, Roger Quadros wrote:
>> On 09/09/15 05:21, Peter Chen wrote:
>>> On Tue, Sep 08, 2015 at 03:25:25PM +0300, Roger Quadros wrote:
>>>>
>>>>
>>>> On 08/09/15 11:31,
On 09/09/15 05:21, Peter Chen wrote:
> On Tue, Sep 08, 2015 at 03:25:25PM +0300, Roger Quadros wrote:
>>
>>
>> On 08/09/15 11:31, Peter Chen wrote:
>>> On Mon, Sep 07, 2015 at 01:23:01PM +0300, Roger Quadros wrote:
>>>> On 07/09/15 04:23, Peter Chen wrote
Alan,
On 08/09/15 17:34, Alan Stern wrote:
> On Tue, 8 Sep 2015, Roger Quadros wrote:
>
>> On 08/09/15 11:31, Peter Chen wrote:
>>> On Mon, Sep 07, 2015 at 01:23:01PM +0300, Roger Quadros wrote:
>>>> On 07/09/15 04:23, Peter Chen wrote:
>>>>>
On 08/09/15 11:31, Peter Chen wrote:
> On Mon, Sep 07, 2015 at 01:23:01PM +0300, Roger Quadros wrote:
>> On 07/09/15 04:23, Peter Chen wrote:
>>> On Mon, Aug 24, 2015 at 04:21:18PM +0300, Roger Quadros wrote:
>>>> + * This is used by the USB Host stack to register t
On 08/09/15 09:54, Peter Chen wrote:
> On Mon, Sep 07, 2015 at 12:57:21PM +0300, Roger Quadros wrote:
>> On 07/09/15 04:24, Peter Chen wrote:
>>> On Mon, Aug 24, 2015 at 04:21:15PM +0300, Roger Quadros wrote:
>>>> This is to prevent missing symbol build error if OTG
On 06/09/15 10:06, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:11PM +0300, Roger Quadros wrote:
>> Hi,
>>
>> This series centralizes OTG/Dual-role functionality in the kernel.
>> As of now I've got Dual-role functionality working pretty reliably on
>>
On 07/09/15 10:40, Li Jun wrote:
> On Mon, Aug 24, 2015 at 04:21:18PM +0300, Roger Quadros wrote:
>> The OTG core instantiates the OTG Finite State Machine
>> per OTG controller and manages starting/stopping the
>> host and gadget controllers based on the bus state.
>>
On 07/09/15 04:23, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:18PM +0300, Roger Quadros wrote:
>> + * This is used by the USB Host stack to register the Host controller
>> + * to the OTG core. Host controller must not be started by the
>> + * caller as it is left upto
On 07/09/15 04:24, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:15PM +0300, Roger Quadros wrote:
>> This is to prevent missing symbol build error if OTG is
>> enabled (built-in) and HCD core (CONFIG_USB) is module.
>>
>> Signed-off-by: Roger Quadr
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