Hi Sylwester,
On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim wrote:
> On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>
>> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
>>> On Fri, Nov 21, 2014 at 07:05:43PM +0530, Vivek Gautam wrote:
>>>> The seri
Hi Alim,
On Sat, Nov 22, 2014 at 7:07 PM, Alim Akhtar wrote:
> Hi Vivek,
>
> On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam
> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl suppor
Adding fixed voltage regulators for Vbus and Vbus-boost required
by USB 3.0 DRD controller on Exynos7-espresso board.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot
Adding USB 3.0 DRD controller device node, with its clock
and phy information to enable using the same on Exynos7.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts
BUS1 pinctrl provides gpios for usb and power regulator
available on exynos7-espresso board. So add relevant device
node for pinctrl-bus1.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 26 +++
arch/arm64
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.
Signed-off-by: Vivek Gautam
---
drivers/clk/samsung/clk-exynos7.c | 64 +++
include/dt-bindings/clock/exynos7-clk.h |9 -
2 files changed, 72 insertions(+), 1 deletion(-)
diff
This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: Vivek Gautam
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy
Some Exynos boards have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 32
: Anton Tikhomirov
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|6 ++
drivers/phy/phy-exynos5-usbdrd.c | 104
2 files changed, 92 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy
DWC3 controller on Exynos7 SoC has separate control for
AXI UpScaler which connects DWC3 DRD controller to AXI bus.
Get the gate clock for the same to control it across power
cycles.
Suggested-by: Anton Tikhomirov
Signed-off-by: Vivek Gautam
---
Documentation/devicetree/bindings/usb/exynos
DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.
Suggested-by: Anton Tikhomirov
Signed-off-by: Vivek
There's no need to keep one local variable for clock, and
then assign the same to 'clk' member of dwc3_exynos.
Just cleaning it up.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/d
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Vivek Gautam
Cc: Linus Walleij
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 12
1 file changed, 12
is series only so as to avoid having 'n' number of dependencies.
The USB driver patches in this series were part of [1] sent earlier.
[1] [PATCH v2 0/4] usb: dwc3/phy-exynos5-usbdrd: Extend support to Exynos7
https://lkml.org/lkml/2014/10/7/191
Vivek Gautam (11):
pinctrl: exynos: Add
AHB clock. So add support for the same.
>>
>> As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
>> by the driver. Adding only sclk is not enough.
>>
>> >
>> > Signed-off-by: Vivek Gautam
>> > ---
>> > drivers/usb/dwc3/dwc3-exy
> Exynos7 doesn't have "Gating all clocks for USBDRD30" bit. The clocks
> should be controlled separately.
true, on Exynos7 we have separate gates for the available clocks going to
USB-DRD block. So we will have to add these basic required number of
clocks.
--
Best Regards
boards instead. Thanks for pointing it out.
>
>> Boost 5V supply which goes as input for VBUS regulator.
>> So adding a control for the same in driver, to enable
>> vbus supply on the port.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>> drivers/phy/phy-ex
On Tue, Oct 7, 2014 at 7:41 PM, Felipe Balbi wrote:
> On Tue, Oct 07, 2014 at 03:49:33PM +0530, Vivek Gautam wrote:
>> Exynos7 also has a separate special gate clock going to the IP
>> apart from the usual AHB clock. So add support for the same.
>>
>> Signed-off-by:
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers/phy/phy-exynos5-usbdrd.c
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 30
This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: Vivek Gautam
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy
7
from v1 of this series, since its not required now.
Vivek Gautam (4):
dwc3: exynos: Add support for SCLK present on Exynos7
phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support
phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
phy: exynos7-usbdrd: Update dependency for AR
On Tue, Sep 2, 2014 at 8:07 PM, Felipe Balbi wrote:
> On Mon, Sep 01, 2014 at 01:30:21PM +0530, Vivek Gautam wrote:
>> On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi wrote:
>> > 2014-08-28 10:02 GMT+02:00 Vivek Gautam:
>> >
>> >> This USB 3.0 PH
On Fri, Aug 29, 2014 at 12:58 AM, Felipe Balbi wrote:
> On Thu, Aug 28, 2014 at 01:31:59PM +0530, Vivek Gautam wrote:
>> The Exynos-DWC3 USB 3.0 DRD controller is also present on
>> Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
>> for this driver.
>>
>
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland wrote:
> On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
>> Exynos7 also has a separate special gate clock going to the IP
>> apart from the usual AHB clock. So add support for the same.
>>
>>
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi wrote:
> 2014-08-28 10:02 GMT+02:00 Vivek Gautam:
>
>> This USB 3.0 PHY controller is also present on Exynos7
>> platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
>
>> +++ b/drivers/phy/Kconfig
&g
Hi Felipe,
On Fri, Aug 29, 2014 at 12:46 AM, Felipe Balbi wrote:
> hi,
>
> On Thu, Aug 28, 2014 at 01:31:58PM +0530, Vivek Gautam wrote:
>> @@ -457,11 +458,19 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
>> clk_prepare_enable(phy_drd->ref_clk);
&g
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/Kconfig b
Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
clock, as well as 60MHz utmi phy clock.
So get the same and control in the phy-exynos5-usbdrd driver.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt|4
drivers/phy/phy-exynos5-usbdrd.c
Some Exynos SoCs have a separate regulator controlling a
Boost 5V supply which goes as input for VBUS regulator.
So adding a control for the same in driver, to enable
vbus supply on the port.
Signed-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usbdrd.c | 27 +--
1
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this driver.
Signed-off-by: Vivek Gautam
---
drivers/phy/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index
.html
The series is based on usb-next branch.
Vivek Gautam (5):
usb: dwc3: exynos: Add support for SCLK present on Exynos7
phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support
phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply
usb: dwc3: Adding Kconfig dependency for Exynos7
phy
Putting together the code related to getting the 'IORESOURCE_MEM'
and assigning the same to dwc->xhci_resources, for increasing
the readability.
Signed-off-by: Vivek Gautam
---
Changes from v1:
- Fixed issue with 'res->start' as pointed out by Paul Zimmerman
by d
Hi,
On Wed, Jun 4, 2014 at 12:41 AM, Paul Zimmerman
wrote:
>> From: linux-usb-ow...@vger.kernel.org
>> [mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of Vivek Gautam
>> Sent: Tuesday, June 03, 2014 3:40 AM
>>
>> Putting together the code related to getti
Putting together the code related to getting the 'IORESOURCE_MEM'
and assigning the same to dwc->xhci_resources, for increasing
the readability.
Signed-off-by: Vivek Gautam
---
Based on 'next' branch of Felipe's usb tree.
Also cleanly applies to 'usb-next'
Hi Jingoo,
On Thu, Apr 24, 2014 at 6:56 AM, Jingoo Han wrote:
> On Thursday, April 24, 2014 9:33 AM, Jingoo Han wrote:
>> On Thursday, April 24, 2014 9:18 AM, Anton Tikhomirov wrote:
>> > On Monday, April 21, 2014 9:17 PM, Vivek Gautam wrote:
>> > >
>> >
Hi,
On Thu, Apr 24, 2014 at 6:08 AM, Anton Tikhomirov
wrote:
> Hi,
>
>> Hi,
>>
>> > -Original Message-
>> > From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
>> > ow...@vger.kernel.org] On Behalf Of Vivek Gautam
>> > Sen
Hi,
On Wed, Apr 23, 2014 at 4:27 PM, Anton Tikhomirov
wrote:
> Hi,
>
>> Hi Anton,
>>
>>
>> On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
>> wrote:
>> > Hello,
>> >
>> >> -Original Message-
>> >> From: V
Hi Anton,
On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
wrote:
> Hello,
>
>> -Original Message-----
>> From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
>> Vivek Gautam
>> Sent: Monday, April 21, 2014 9:17 PM
>> To: linu
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam
Cc: Jingoo Han
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ehci-exynos.c | 47
1 file ch
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam
Cc: Anton Tikhomirov
---
Based on 'usb-next' branch of Greg's USB tree.
Also cleanly applies on 'next' branch of Balbi's USB tree.
dr
that,
they request VDD regulators in their drivers, and enable
them so as to make them working.
Signed-off-by: Vivek Gautam
Cc: Jingoo Han
---
Based on 'usb-next' branch of Greg's usb tree.
drivers/usb/host/ohci-exynos.c | 47
1 file ch
Hi,
On Wed, Apr 16, 2014 at 7:42 PM, Heikki Krogerus
wrote:
> Hi,
>
> On Tue, Apr 15, 2014 at 06:24:11PM +0530, Vivek Gautam wrote:
>> I had seen your patches in the mailing list, but i don't see any
>> updated version of these patches.
>> Are you planning to wo
Hi Heikki,
On Tue, Dec 10, 2013 at 7:25 PM, Heikki Krogerus
wrote:
Giving life to this thread after long time.
> Hi,
>
> On Tue, Dec 10, 2013 at 04:25:25PM +0530, Vivek Gautam wrote:
>> @@ -170,6 +189,15 @@ static int xhci_plat_probe(struct platfo
usb_phy_set_suspend(dwc->usb2_phy, 0);
>> usb_phy_set_suspend(dwc->usb3_phy, 0);
>>
>> + if (dwc->usb2_generic_phy)
>> + phy_power_on(dwc->usb2_generic_phy);
>> + if (dwc->usb3_generic_phy)
>> + phy_power_on(dwc->usb
Hi Kishon,
On Wed, Dec 11, 2013 at 1:47 PM, Kishon Vijay Abraham I wrote:
> On Wednesday 11 December 2013 12:08 PM, Vivek Gautam wrote:
>> Hi,
>>
>>
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> wrote:
>>> Hi,
>>
>> Thanks for re
Hi,
On Wed, Dec 11, 2013 at 1:39 PM, Heikki Krogerus
wrote:
> Hi,
>
> On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> > I think "setup" instead of "tune" is much more clear and re
Hi,
On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
wrote:
> Hi,
Thanks for reviewing this.
>
> On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
>> Some PHY controllers may need to tune PHY post-initialization,
>> so that the PHY consumers can call phy-
generic PHY framework
http://lwn.net/Articles/575586/
Vivek Gautam (4):
phy: Add provision for tuning phy.
xhci: Add quirk for DWC3-Exynos controller
xhci: Tune PHY for the DWC3-Exynos host controller
phy-exynos-usb3: Fine tune LOS levels for exynos5420
drivers/phy/phy-core.c
-off-by: Vivek Gautam
---
drivers/phy/phy-exynos5-usb3.c | 107
1 files changed, 107 insertions(+), 0 deletions(-)
diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c
index 2bafc9d..669f998 100644
--- a/drivers/phy/phy-exynos5-usb3
controller has been reset.
Adding a xHCI quirk for this purpose.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/xhci-plat.c | 19 +++
drivers/usb/host/xhci.h |1 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb
Some PHY controllers may need to tune PHY post-initialization,
so that the PHY consumers can call phy-tuning at appropriate
point of time.
Signed-off-by: vivek Gautam
---
drivers/phy/phy-core.c | 20
include/linux/phy/phy.h |7 +++
2 files changed, 27 insertions
ndary HCD of XHCI.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/host.c |7 ++
drivers/usb/host/xhci-plat.c | 43 -
include/linux/usb/hcd.h |1 +
3 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/hos
On Tue, Nov 5, 2013 at 11:41 PM, Vivek Gautam wrote:
> Dear Kishon, Roger
>
>
> On Wed, Oct 16, 2013 at 6:40 PM, Kishon Vijay Abraham I wrote:
>> Hi roger,
>>
>> On Wednesday 16 October 2013 06:33 PM, Roger Quadros wrote:
>>> Hi Kishon,
>
>
t;
>> In the Exynos case, there is only 1 phy and it is the USB3 phy. This code
>> will wrongly treat it as usb2_phy.
Thank you Roger for your concern regarding Exynos case.
It's true that, Exynos5 series of SoCs have got only one IP block for
DWC3'c PHY.
This block is actually
)
sequence.
We should get rid of this delay, since things will still work
fine without this.
Signed-off-by: Vivek Gautam
---
Hi Felipe,
I remember this change for phy_init including msleep(100) was
suggested by me, after testing the patch-series for PM support
to dwc3.
Sorry for that !!
driver
Hi,
On Thu, Sep 12, 2013 at 6:41 PM, Roger Quadros wrote:
> On 09/12/2013 02:26 PM, Vivek Gautam wrote:
>> Hi,
>>
>>
>> On Thu, Sep 12, 2013 at 4:34 PM, Roger Quadros wrote:
>>> Hi,
>>>
>>> On 09/12/2013 01:47 PM, Vivek Gautam wrote:
>
Hi,
On Thu, Sep 12, 2013 at 4:34 PM, Roger Quadros wrote:
> Hi,
>
> On 09/12/2013 01:47 PM, Vivek Gautam wrote:
>> On Thu, Sep 12, 2013 at 4:06 PM, Roger Quadros wrote:
>>> Hi Kishon,
>>>
>>> On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
>&
On Thu, Sep 12, 2013 at 4:06 PM, Roger Quadros wrote:
> Hi Kishon,
>
> On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
>> There can be systems which does not have a external usb_phy, so get
>> usb_phy only if usb-phy property is added in the case of dt boot or if
>> platform_data indicates t
On Thu, Sep 12, 2013 at 3:40 PM, Kishon Vijay Abraham I wrote:
> On Thursday 12 September 2013 02:57 PM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Mon, Sep 2, 2013 at 9:13 PM, Kishon Vijay Abraham I wrote:
>>> Adapted dwc3 core to use the Gene
Hi Kishon,
On Mon, Sep 2, 2013 at 9:13 PM, Kishon Vijay Abraham I wrote:
> Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
> power_on and power_off the following APIs are used phy_init(), phy_exit(),
> phy_power_on() and phy_power_off().
>
> However using the old USB phy l
71a5e61 usb: chipidea: fix and improve dependencies if usb host or gadget
support is built as module
Let us limit the DWC3 mode to depend on corresponding usb-subsystem
and USB_DWC3.
Signed-off-by: Vivek Gautam
Cc: Felipe Balbi
Cc: Fengguang Wu
---
drivers/usb/dwc3/Kconfig |6 +++---
1 fi
On Tue, Apr 23, 2013 at 11:42 PM, Alan Stern wrote:
> On Tue, 23 Apr 2013, Vivek Gautam wrote:
>
>> Hi,
>>
>>
>> On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern
>> wrote:
>> > On Tue, 23 Apr 2013, Vivek Gautam wrote:
>> >
>> >> >
Hi,
On Tue, Apr 23, 2013 at 10:23 PM, Alan Stern wrote:
> On Tue, 23 Apr 2013, Vivek Gautam wrote:
>
>> >> Alright, so here's my understanding:
>> >>
>> >> I suggested letting e.g. DWC3 enable the PHY's runtime_pm; Alan said
>> >>
Hi,
On Thu, Apr 4, 2013 at 8:16 PM, Alan Stern wrote:
Apologies for delay in replying.
> On Thu, 4 Apr 2013, Felipe Balbi wrote:
>
>> > >> Some subsystems handle this issue by calling pm_runtime_get_sync()
>> > >> before probing a driver and pm_runtime_put_sync() after unbinding the
>> > >> dr
Hi,
On Thu, Apr 4, 2013 at 12:48 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 02:14:02PM -0400, Alan Stern wrote:
>> > > Lets suppose DWC3 enables runtime_pm on USB 2 type phy,
>> > > it will try to go into suspend state and thereby call runtime_suspend(),
>> > > if any.
>> > > And
On Thu, Apr 4, 2013 at 12:40 PM, Felipe Balbi wrote:
> On Thu, Apr 04, 2013 at 10:34:57AM +0530, Vivek Gautam wrote:
>> Hi Sarah,
>>
>>
>> On Wed, Apr 3, 2013 at 10:57 PM, Sarah Sharp
>> wrote:
>> > Question: Do you still need this patch for 3.10?
&g
es for 3.10, sorry.
>
> Sarah Sharp
>
> On Mon, Apr 01, 2013 at 07:23:59PM +0530, Vivek Gautam wrote:
>> This patch-series enables runtime power management on xhci-plat,
>> dwc3-core, dwc3-exynos as well as on Samsung's USB 2.0 type and
>> USB 3.0 type PHYs.
&g
On Wed, Apr 3, 2013 at 7:48 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 07:40:44PM +0530, Vivek Gautam wrote:
>> >> > >> >> +static inline void usb_phy_autopm_enable(struct usb_phy *x)
>> >> > >> >> +{
>> >>
Hi,
On Wed, Apr 3, 2013 at 7:26 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 04:54:14PM +0300, Felipe Balbi wrote:
>> > >> >> +static inline void usb_phy_autopm_enable(struct usb_phy *x)
>> > >> >> +{
>> > >> >> + if (!x || !x->dev) {
>> > >> >> + dev_err(x->dev,
Hi Felipe,
On Wed, Apr 3, 2013 at 1:45 PM, Felipe Balbi wrote:
> Hi,
>
> On Wed, Apr 03, 2013 at 11:48:39AM +0530, Vivek Gautam wrote:
>> >> Adding APIs to handle runtime power management on PHY
>> >> devices. PHY consumers may need to wake-up/suspend
Hi Kishon,
On Wed, Apr 3, 2013 at 10:38 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
>
> On Monday 01 April 2013 07:24 PM, Vivek Gautam wrote:
>>
>> Adding APIs to handle runtime power management on PHY
>> devices. PHY consumers may need to wake-up/suspend
Hi Felipe,
On Tue, Apr 2, 2013 at 1:59 PM, Felipe Balbi wrote:
> On Mon, Apr 01, 2013 at 07:24:01PM +0530, Vivek Gautam wrote:
>> The current code in the dwc3 probe effectively disables runtime pm
>> from ever working because it calls a get() that was never put() until
&g
Hi Balbi,
On Tue, Apr 2, 2013 at 2:02 PM, Felipe Balbi wrote:
> Hi,
>
> On Mon, Apr 01, 2013 at 07:24:03PM +0530, Vivek Gautam wrote:
>> +#else
>> +#define dwc3_runtime_suspend NULL
>> +#define dwc3_runtime_resume NULL
>
> this #else b
Hi,
On Tue, Apr 2, 2013 at 5:40 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Apr 02, 2013 at 04:04:01PM +0530, Vivek Gautam wrote:
>> > On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
>> >> Adding APIs to handle runtime power management on PHY
>>
Hi,
On Tue, Apr 2, 2013 at 1:53 PM, Felipe Balbi wrote:
> On Mon, Apr 01, 2013 at 07:24:00PM +0530, Vivek Gautam wrote:
>> Adding APIs to handle runtime power management on PHY
>> devices. PHY consumers may need to wake-up/suspend PHYs
>> when they work across autosuspend
The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal. Change the runtime pm code to match the standard
formula and allow runtime pm to function.
Signed-off-by: Vivek Gautam
CC: Doug Anderson
Allow dwc3 to enable auto power management only after its PHYs
are initialized so that any further PHY handling by dwc3's
runtime power management callbacks is fine.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/core.c | 18 +-
1 files changed, 9 insertions(+), 9 dele
Right now it doesn't handle full runtime suspend/resume
functionality. However it allows to handle PHYs' sleep
and wakeup across runtime suspend/resume.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/core.c | 43 +++
1 files changed, 43
Adding APIs to handle runtime power management on PHY
devices. PHY consumers may need to wake-up/suspend PHYs
when they work across autosuspend.
Signed-off-by: Vivek Gautam
---
include/linux/usb/phy.h | 141 +++
1 files changed, 141 insertions(+), 0
Enabling runtime power management on dwc3-exynos
letting dwc3 controller to be autosuspended on exynos
platform when not in use.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/dwc3-exynos.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc3
Enable autosuspending of Samsung usb3.0 PHY
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb3.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb3.c
b/drivers/usb/phy/phy-samsung-usb3.c
index 54f6418..a713585 100644
The PHY controller can choose between ref_pad_clk (XusbXTI-external PLL),
or EXTREFCLK (XXTI-internal clock crystal) to generate the required clock.
Adding the provision for ref_pad_clk here.
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb3.c | 46
Enable autosuspending of Samsung usb2.0 PHY
Signed-off-by: Vivek Gautam
---
drivers/usb/phy/phy-samsung-usb2.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-samsung-usb2.c
b/drivers/usb/phy/phy-samsung-usb2.c
index 45ffe03..d378fe9 100644
By enabling runtime pm in this driver allows users of
xhci-plat to enter into runtime pm. This is not full
runtime pm support (AKA xhci-plat doesn't actually power
anything off when in runtime suspend mode) but,
just basic enablement.
Signed-off-by: Vivek Gautam
CC: Doug Anderson
---
dr
d of in any glue layer.
- Splitting the patch:
[PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb
into required number to bifurcate functionality.
Vivek Gautam (11):
usb: phy: Add APIs for runtime power management
USB: dwc3: Adjust runtime pm to allow autosuspend
Hi,
On Thu, Mar 14, 2013 at 4:23 PM, Felipe Balbi wrote:
> Hi,
>
> On Thu, Mar 14, 2013 at 04:14:58PM +0530, Vivek Gautam wrote:
>> Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
>> calls as required by common clock framework.
>>
>> S
Used of_platform_populate() to create dwc3 core platform_device
from device tree data. Additionally some cleanup is also done.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
Changes from v1:
- Added method to unregister dwc3 core from dwc3_exynos_remove()
using
On Thu, Mar 14, 2013 at 4:21 PM, Felipe Balbi wrote:
> Hi,
>
> On Thu, Mar 14, 2013 at 04:14:57PM +0530, Vivek Gautam wrote:
>> @@ -170,7 +155,6 @@ static int dwc3_exynos_remove(struct platform_device
>> *pdev)
>> {
>> struct dwc3_exynos *e
patches in fact ;-), on top of 3.9rc2 tag).
Also based on: "usb: dwc3: set dma_mask for dwc3_omap device" by Kishon
in which DMA mask for dwc3-core is being set from its parent.
Vivek Gautam (2):
usb: dwc3: exynos: Use of_platform API to create dwc3 core pdev
usb: dwc3: exynos: use clk_
Convert clk_enable/clk_disable to clk_prepare_enable/clk_disable_unprepare
calls as required by common clock framework.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
drivers/usb/dwc3/dwc3-exynos.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a
Used of_platform_populate() to create dwc3 core platform_device
from device tree data. Additionally some cleanup is also done.
Signed-off-by: Vivek Gautam
CC: Felipe Balbi
CC: Kukjin Kim
---
drivers/usb/dwc3/dwc3-exynos.c | 46 +---
1 files changed, 15
On Wed, Mar 13, 2013 at 2:44 PM, Felipe Balbi wrote:
> On Wed, Mar 13, 2013 at 02:42:22PM +0530, Vivek Gautam wrote:
>> Hi Balbi,
>>
>>
>> On Sat, Mar 2, 2013 at 6:55 PM, Vivek Gautam
>> wrote:
>> > Now that machines may select the mode of worki
Hi Balbi,
On Sat, Mar 2, 2013 at 6:55 PM, Vivek Gautam wrote:
> Now that machines may select the mode of working of DWC3 (HOST only,
> GADGET only or DUAL_ROLE), lets set DWC3 mode based on that
> rather than fixing it to whatever DWC3 hardware says.
> This way we can skip initial
Hi,
On Sat, Mar 2, 2013 at 9:23 PM, Alan Stern wrote:
> On Sat, 2 Mar 2013, Vivek Gautam wrote:
>
>> By enabling runtime pm in this driver allows users of
>> xhci-plat to enter into runtime pm. This is not full
>> runtime pm support (AKA xhci-plat doesn't actually
The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal. Change the runtime pm code to match the standard
formula and allow runtime pm to function.
Signed-off-by: Vivek Gautam
CC: Doug Anderson
-off-by: Vivek Gautam
---
Changes from RFC patch "usb: dwc3: Set GCTL.PrtCapDir based on selected mode"
- Setting the mode in dwc3 context structure based on
selected mode in machine, rather than programming PrtCapDir
drivers/usb/dwc3/core.c |7 ++-
1 files changed, 6
Right now it doesn't handle full runtime suspend/resume
functionality. However it allows to handle PHYs' sleep
and wakeup across runtime suspend/resume.
Signed-off-by: Vivek Gautam
---
drivers/usb/dwc3/core.c | 27 +++
1 files changed, 27 insertions(+), 0
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