After checking all the available manuals, I have enough information to
conclude that the 'shift_rd0' flag is only relevant for the Ether cores
supporting so called "intelligent checksum" (and hence having CSMR) which
is indicated by the 'hw_crc' flag. Since all the relevant SoCs now have
bot
The 'struct sh_eth_cpu_data' field indicating the "intelligent checksum"
support was misnamed 'hw_crc' -- rename it to 'hw_checksum'.
Signed-off-by: Sergei Shtylyov
---
drivers/net/ethernet/renesas/sh_eth.c | 12 ++--
drivers/net/ethernet/renesas/sh_eth.h |2 +-
2 files changed, 7
Hello.
Here's a set of 2 patches against DaveM's 'net.git' repo, as they are based
on a couple patches merged there recently; however, the patches are destined
for 'net-next.git' (once 'net.git' gets merged there next time). I'm cleaning
up the "intelligent checksum" related code (however, the
From: Sergei Shtylyov
Date: Thu, 5 Jan 2017 12:33:21 +0300
>Oops, typo in the subject, "shecksumming". David, should I resend?
I accidently pushed this out without fixing the typo, sorry about
that but that's going to be how it is I'm afraid :-)
From: Sergei Shtylyov
Date: Thu, 05 Jan 2017 00:29:32 +0300
> The R8A7740 GEther controller supports the packet checksum offloading
> but the 'hw_crc' (bad name, I'll fix it) flag isn't set in the R8A7740
> data, thus CSMR isn't cleared...
>
> Fixes: 73a0d907301e ("net: sh_eth: add support R8A7
From: Sergei Shtylyov
Date: Wed, 04 Jan 2017 22:18:24 +0300
> As the SH77{34|63} manuals are freely available, I've checked the EESIPR
> values written against the manuals, and they appeared to set the reserved
> bits 11-15 (which should be 0 on write). Fix those EESIPR values.
>
> Fixes: 380af
Hello!
On 01/05/2017 01:43 PM, Simon Horman wrote:
From: Kazuya Mizuguchi
"swiotlb buffer is full" errors occur after repeated initialisation of a
device - f.e. suspend/resume or ip link set up/down. This is because memory
mapped using dma_map_single() in ravb_ring_format() and ravb_start_xmi
It is possible that device is capable of 64-bit DMA addresses, and
device driver tries to set wide DMA mask, but bridge or bus used to
connect device to the system can't handle wide addresses.
With swiotlb, memory above 4G still can be used by drivers for streaming
DMA, but *dev->mask and dev->dma
Hi Jose,
On Friday 06 Jan 2017 10:07:03 Jose Abreu wrote:
> Hi Laurent,
>
> Sorry for the delayed answer but I am quite busy at the moment.
No worries, your help is really appreciated.
> On 06-01-2017 01:48, Laurent Pinchart wrote:
>
> [snip]
>
> The TX_READY signal is documented in the
Hello Jithin,
On Friday 06 Jan 2017 07:15:27 Jithin T Raj wrote:
> hello Laurent and all,
>
> Can anybody give me an insight to VSPD .Recently I am going through
> the term VSPD..Is it associated with Display Unit ? ..It will be a help if
> someone share some links about VSPD..I am a beginner in
It is possible that device is capable of 64-bit DMA addresses, and
device driver tries to set wide DMA mask, but bridge or bus used to
connect device to the system can't handle wide addresses.
With swiotlb, memory above 4G still can be used by drivers for streaming
DMA, but *dev->mask and dev->dma
>>> Just a guess, but if the inbound translation windows in the host
>>> bridge are wider than 32-bit, the reason for setting up a single
>>> 32-bit window is probably because that is what the parent bus supports.
I've re-checked rcar-pcie hardware documentation.
It indeed mentions that AXI bus i
Hi Geert,
Thank you for the patch.
On Friday 02 Dec 2016 13:35:10 Geert Uytterhoeven wrote:
> If a UART has dedicated RTS/CTS pins, there are some issues:
>
> 1. When changing hardware control flow, the new AUTORTS state is not
>immediately reflected in the hardware, but only when RTS is rai
Hi Geert,
Thank you for the patch.
On Friday 02 Dec 2016 13:35:11 Geert Uytterhoeven wrote:
> When the .set_termios() callback resets the UART, it first waits until
> all characters in the transmit FIFO have been transmitted, to prevent a
> port configuration change from impacting these character
SCI instances found in SH SoCs have different spacing between registers
depending on the SoC. The platform data contains a regshift field that
tells the driver by how many bits to shift the register offset to
compute its address. We can compute the regshift value automatically
based on the memory r
When a suspend/resume action is taken, the pipeline is reset and never
reconfigured.
To correct this, we establish a new flag pipe->configured and utilise
this to establish when we write a full configuration set to the current
display list.
Signed-off-by: Kieran Bingham
---
drivers/media/platfo
With multiple inputs through the BRU it is feasible for the streams to
race each other at stream-on.
Multiple VIDIOC_STREAMON calls racing each other could have process
N-1 skipping over the pipeline setup section and then start the pipeline
early, if videobuf2 has already enqueued buffers to the
Move the static vsp1_video_setup_pipeline() function in preparation for
the callee updates so that the vsp1_video_pipeline_run() call can
configure pipelines following suspend resume actions.
This commit is just a code move for clarity performing no functional
change.
Signed-off-by: Kieran Bingha
The pipe->dl is used only inside vsp1_du_atomic_flush(), and can be
obtained and stored locally to simplify the code.
Signed-off-by: Kieran Bingham
---
drivers/media/platform/vsp1/vsp1_drm.c | 20 ++--
drivers/media/platform/vsp1/vsp1_pipe.h | 2 --
2 files changed, 10 insertio
This small patchset helps rework the VSP1 driver to repair an issue on
suspend/resume operations whereby the pipeline does not get reconfigured after
it has been re-initialised following a resume operation.
Along side this, there was an intrinsic race in the vsp1_video_start_streaming()
function w
Even though most of its registers are 8-bit wide, the IRDA has two
16-bit registers that make it a 16-bit peripheral and not a 8-bit
peripheral with addresses shifted by one. Fix the registers offset in
the driver and the platform data regshift value.
Signed-off-by: Laurent Pinchart
---
arch/sh/
From: Niklas Söderlund
The adv7612 is used on Gen2 boards (Lager, Koelsch and Gose) for HDMI
input. Enable support for this chip in shmobile_defconfig.
Signed-off-by: Niklas Söderlund
Signed-off-by: Simon Horman
---
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
di
From: Laurent Pinchart
Signed-off-by: Laurent Pinchart
[geert: Add pinctrl]
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/rene
Enable recently added r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs.
Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
arch/arm/configs/shmobile_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/shmobile_defconfig
b/arch/arm/configs/shmobile_defconfig
ind
From: Laurent Pinchart
Add the 7 PWM channels to the r8a7795 device tree, in the disabled
state.
Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 63
1 file changed, 63
Use recently added R-Car Gen 3 fallback binding for msiof nodes in
DT for r8a7796 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7796 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman
Revi
From: Chris Paterson
Adds CAN controller nodes for r8a7796.
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Acked-by: Marc Kleine-Budde
Acked-by: Rob Herring
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC DT updates for v4.11.
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linu
From: Chris Paterson
Adds CAN FD controller node for r8a7796.
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Acked-by: Marc Kleine-Budde
Acked-by: Rob Herring
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesa
Use recently added R-Car Gen 3 fallback binding for i2c nodes in
DT for r8a7796 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7796 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman
Review
Use recently added en 3 fallback compat string for PCIE
in r8a7795 DT.
Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/a
From: Laurent Pinchart
Signed-off-by: Laurent Pinchart
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 43
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/a
From: Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b/Documentation/devicetree/bindi
A fallback binding for the Renesas R-Car Gen3 for USB2.0 PHY driver was
added by commit cde7bc367f09 ("phy: rcar-gen3-usb2: add fallback binding").
This patch makes use of this binding in the DT for the r8a7795 SoC.
Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
arch/arm64/boot
From: Niklas Söderlund
To be able to use VIN with larger frame sizes CMA memory are needed for
DMA. If this is not enabled trying to capture large frames can result in
errors such as:
rcar-vin e6ef.video: dma_alloc_coherent of size 8388608 failed
A CMA area of 64MB are needed for v4l2-compl
Enable recently added r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs.
Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
ind
From: Kuninori Morimoto
This patch adds CTU (= Channel Transfer Unit) support which is needed
to sound mixing.
Signed-off-by: Kuninori Morimoto
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 1 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 ++
Use recently added R-Car Gen 3 fallback binding for i2c nodes in
DT for r8a7795 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7795 and the
fallback binding for R-Car Gen 3.
Signed-off-by: Simon Horman
Review
From: Geert Uytterhoeven
Add the device nodes for all MSIOF SPI controllers.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 54
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ren
From: Kuninori Morimoto
This patch adds MIX (= Mixer) support.
Signed-off-by: Kuninori Morimoto
Signed-off-by: Simon Horman
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 1 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 7 +++
2 files changed, 8 insertions(+)
diff --gi
From: Takeshi Kihara
This patch updates memory region:
- After changes, the new map of the Salvator-X board on R8A7796 SoC
Bank0: 2GiB RAM : 0x4800 -> 0x000bfff
Bank1: 2GiB RAM : 0x0006 -> 0x0067fff
- Before changes, the old map looked like this:
Bank0: 2
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC defconfig updates for v4.11.
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
https://git.kernel.org/pub/s
From: Chris Paterson
Adds external CAN clock node for r8a7796. This clock can be used as
fCAN clock of CAN and CAN FD controller.
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Acked-by: Marc Kleine-Budde
Signed-off-by:
Hi Laurent,
I've been reworking this series to split things out and adapt for the
comments you've provided, but I have the following queries outstanding:
On 15/12/16 11:50, Kieran Bingham wrote:
> Hi Laurent,
>
> On 14/12/16 16:30, Laurent Pinchart wrote:
>> Hi Kieran,
>>
>> Thank you for the pa
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM64 based SoC DT updates for v4.11.
This is based on v4.10-rc2 as v4.10-rc1 does not compile using
the defconfig.
The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:
Linux 4.10-rc2 (2017-01-01 14:31:53 -0800
From: Geert Uytterhoeven
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7745.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts
Use recently added R-Car Gen 1 fallback binding for i2c nodes in
DT for r8a7778 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7778 and the
fallback binding for R-Car Gen 1.
Signed-off-by: Simon Horman
Review
Use the SoC-specific compat string for mmcif in DT for the r8a73a4 SoC.
This is in keeping with the use of compat strings for mmcif for other
Renesas ARM based SoCs.
Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a73a4.dtsi | 4 ++--
1 file changed, 2 insertion
From: Geert Uytterhoeven
To preserve both alphabetical (label) and numerical ordering (unit
address).
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7745.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/d
Use the SoC-specific compat string for mmcif in DT for the r8a7778 SoC.
This is in keeping with the use of compat strings for mmcif for other
Renesas ARM based SoCs.
Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7778.dtsi | 2 +-
1 file changed, 1 insertion(+
A fallback binding for the Renesas R-Car Gen2 PHY driver was
added by commit cb8ba08d ("phy: rcar-gen2: add fallback binding").
This patch makes use of this binding in the DT for the r8a7790 SoC.
Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7790.dtsi
Use the SoC-specific compat string for mmcif in DT for the sh73a0 SoC.
This is in keeping with the use of compat strings for mmcif for other
Renesas ARM based SoCs.
Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
arch/arm/boot/dts/sh73a0.dtsi | 2 +-
1 file changed, 1 insertion(+),
A fallback binding for the Renesas R-Car Gen2 PHY driver was
added by commit cb8ba08d ("phy: rcar-gen2: add fallback binding").
This patch makes use of this binding in the DT for the r8a7791 SoC.
Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7791.dtsi
From: Geert Uytterhoeven
To preserve both alphabetical (label) and numerical ordering (unit
address).
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7743.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/d
From: Geert Uytterhoeven
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7743.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts
Use recently added R-Car Gen 2 fallback binding for iic nodes in
DT for r8a7794 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7794 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 1 fallback binding for i2c nodes in
DT for r8a7779 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7779 and the
fallback binding for R-Car Gen 1.
Signed-off-by: Simon Horman
Review
A fallback binding for the Renesas R-Car Gen2 PHY driver was
added by commit cb8ba08d ("phy: rcar-gen2: add fallback binding").
This patch makes use of this binding in the DT for the r8a7794 SoC.
Signed-off-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi
From: Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven
Tested-by: Hiep Cao Minh
Signed-off-by: Simon Horman
---
arch/arm/mach-shmobile/platsmp-apmu.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c
b/arch/arm/mach-
Use recently added R-Car Gen 2 fallback binding for msiof nodes in
DT for r8a7792 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7792 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Revi
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7793 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7793 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC updates for v4.11.
The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/k
From: Geert Uytterhoeven
Enable i2c6, and add a device node for the da9063 PMIC, with subnodes
for rtc and wdt. Regulator support is not yet included.
This allows the system to be restarted when the watchdog timer times
out, or when a system restart is requested.
Signed-off-by: Geert Uytterhoe
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7791 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7791 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7792 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7792 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for iic nodes in
DT for r8a7791 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7791 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for msiof nodes in
DT for r8a7791 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7791 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Revi
Use recently added R-Car Gen 2 fallback binding for msiof nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Revi
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for iic nodes in
DT for r8a7793 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7793 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7794 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7794 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
Use recently added R-Car Gen 2 fallback binding for iic nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman
Review
From: Geert Uytterhoeven
Now debug resource reset is handled properly, allow booting secondary
CPU cores when hardware debug mode is enabled (MD21=1) on SoCs using the
"renesas,apmu" enable method.
Signed-off-by: Geert Uytterhoeven
Tested-by: Hiep Cao Minh
Signed-off-by: Simon Horman
---
arc
From: Geert Uytterhoeven
In debug mode (MD21=1), reset requests derived from power-shutoff to the
AP-system CPU cores must be enabled before the AP-system CPU cores
resume from power-shutoff for the first time. Else resume may fail,
causing the system to hang during boot.
As setting these bits i
From: Geert Uytterhoeven
Now debug resource reset is handled properly, allow booting secondary
CPU cores when hardware debug mode is enabled (MD21=1, SW8-4=OFF on
koelsch) on legacy r8a7791.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/mach-shmobile/smp-r8a7791.c
From: Geert Uytterhoeven
After
1. commit 9f5ce39ddb8f68b3 ("ARM: shmobile: rcar-gen2: Obtain extal
frequency from DT"),
2. commit 80951f04c3f92533 ("ARM: shmobile: rcar-gen2: Stop passing
mode pins state to clock driver"),
3. and handling of debug resource reset,
there are no more
On Wednesday, January 4, 2017 6:29:39 PM CET Nikita Yushchenko wrote:
> > Just a guess, but if the inbound translation windows in the host
> > bridge are wider than 32-bit, the reason for setting up a single
> > 32-bit window is probably because that is what the parent bus supports.
>
> Well anyw
Hi Geert,
On Friday 06 Jan 2017 11:59:58 Geert Uytterhoeven wrote:
> On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart wrote:
> > The field isn't set by any platform but is only used internally in the
> > driver to hold data parsed from DT. Move it to the sci_port structure.
>
> This does mean le
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The field isn't set by any platform but is only used internally in the
> driver to hold data parsed from DT. Move it to the sci_port structure.
This does mean legacy platform data can no longer set it
(no platform data did).
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> SCI instances found in SH SoCs have different spacing between registers
> depending on the SoC. The platform data contains a regshift field that
> tells the driver by how many bits to shift the register offset to
> compute its
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> Most of the patches in this series have been sitting in my development tree
> for three years now. While rebasing all my development branches I decided it
> was time to send them out in case they're considered useful. I've the
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The sh-sci driver implements manual break debouncing for a few SH
> platforms by reading the value of the RX pin port register. This feature
> is optional and the driver considers all negative or zero values of the
> platform data port_reg
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> Only SH platforms still use platform data for the sh-sci, and none of
> them declare DMA channels connected to the SCI. Remove the corresponding
> platform data fields and simplify the driver accordingly.
>
> Signed-off-by: Laurent Pinchar
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The fifo size, overrun register and mask, sampling rate mask and error
> mask all depend on the port type only and don't need to be computed at
> runtime. Add them to the sci_port_parameters structure.
>
> Signed-off-by: Laure
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> Turn the regmap two-dimensional array to an array of port parameters and
> store a pointer to the port parameters in the sci_port structure. This
> will allow handling additional port type dependent parameters.
>
> Signed-off-by: Laurent P
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The driver modifies platform data for internal purpose only. Fix that
> and make the platform data structure const.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The bit is only set by platforms that also set the CKE1 but, in which
> case its value is ignored by the device. Don't set it, this simplifies
> platform data and only leaves the CKE1 bit to be handled.
>
> Signed-off-by: Laurent Pinchart
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The compiler zeros uninitialized fields, don't zero them manually.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux be
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> According to the datasheets, the sh7760 SIM and sh7723 SCIFA instances
> don't implement the REIE bit. Don't set it in platform data.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
> ---
> arch/sh/ker
Hi Geert,
On Friday 06 Jan 2017 11:18:32 Geert Uytterhoeven wrote:
> On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart wrote:
> > Even though most of its registers are 8-bit wide, the IRDA has two
> > 16-bit registers that make it a 16-bit peripheral and not a 8-bit
> > peripheral with addresses s
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> Even though most of its registers are 8-bit wide, the IRDA has two
> 16-bit registers that make it a 16-bit peripheral and not a 8-bit
> peripheral with addresses shifted by one. Fix the memory resource size
> and the platform
Hi Laurent,
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The regshift value is computed automatically by the driver, there's no
> need to set it in platform data. Specify the associated memory resource
> lengths to ensure proper computation of the value.
>
> Signed-off-by: Laurent P
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The driver considers all negative or zero values of the port_reg field
> as invalid. The four platforms that set the field to a register address
> all use an address higher than 0x7fff, which is thus considered by
> the driver as inval
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The flag is set by the driver internally, don't set it in platform data.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Li
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The SCIF ports on sh7264 and sh7269 don't support the TOIE bit according
> to the datasheets.
>
> Signed-off-by: Laurent Pinchart
Looks OK for sh7269
I don't have a sh7264 datasheet, so let's trust you on that ;-)
Reviewed-by: Geert Uyt
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The Transmit Enable and Receive Enable bits are set in the scscr field
> of all instances of the sh-sci platform data. Set them in the driver
> directly to prepare for their removal from platform data.
>
> Signed-off-by: Laurent Pinchart
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The UPF_BOOT_AUTOCONF platform data flag is set by all platforms,
> hardcode it.
>
> The UPF_IOREMAP flag is set by a single SH platform and thus needs to be
> kept. However, for ARM platforms, we can base the decision on whether an
> OF n
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The scscr platform data field is used by the driver in three locations.
> One of them masks out all bits except SCSCR_REIE. The two other are the
> set_termios handler and the console write handler.
>
> The set_termios handler calls sci_st
On Wed, Jan 4, 2017 at 12:06 AM, Laurent Pinchart
wrote:
> The bits are set by the driver internally, don't set them in platform
> data.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots
Hi Laurent,
Sorry for the delayed answer but I am quite busy at the moment.
On 06-01-2017 01:48, Laurent Pinchart wrote:
[snip]
The TX_READY signal is documented in the i.MX6 datasheet as being a PHY
output signal, but there seems to be no HDMI TX register from which its
state
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