On Wed, Mar 08, 2017 at 11:28:19AM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
>
> This series gets rid of the last usage of the Allwinner specific pinconf
> bindings, and drops inclusion of dt-bindings/pinctrl/sun4i-a10.h across
> the tree.
>
> Patch 1 gets rid of the last occurrence of Allwinner sp
>> + if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
>> + val = 1;
>> + else
>> + val = 0;
Isn't this better written as
val = (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC);
-- Stefan
--
You received this message because you are subsc
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> It seems like what's called a backporch in the datasheet is actually the
> backporch plus the sync period. Fix that in our driver.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 ++---
> 1 file changed, 2 ins
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> Even though that mux is undocumented, it seems like it needs to be set to 1
> when using composite, and 0 when using HDMI.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++-
> 1 file changed, 6 insertion
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> One of the possible output of the display pipeline, on the SoCs that have
> it, is the HDMI controller.
>
> Add a binding for it.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
TODO: A31 will also need a DDC clock.
--
You receiv
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> The Allwinner Timings Controller has two, mutually exclusive, channels.
> When the binding has been introduced, it was assumed that there would be
> only a single user per channel in the system.
>
> While this is likely for the channel 0 which
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> While all functions have debug logs, the channel enable and disable are not
> logged. Make sure this is the case.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
--
You received this message because you are subscribed to the Googl
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> The A10s Olinuxino has an HDMI connector. Make sure we can use it.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe f
Hi,
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> The A10s has an HDMI controller connected to the second TCON channel. Add
> it to our DT.
>
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/sun5i-a10s.dtsi | 34 -
> arch/arm/boot/dts/sun5i.dtsi
All dts files for the sunxi platform have been switched to the generic
pinconf bindings. As a result, the sunxi specific pinctrl macros are
no longer used.
Remove the #include entry with the following command:
sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \
arch/arm/boot/dts/s
The old sunxi specific pinctrl bindings are deprecated, in favor of
the new generic pinconf bindings. Also, we are moving towards handling
GPIO pinmux settings that don't require extra bias or drive strength
settings to use the GPIO bindings only.
This patch removes the last instance of the sunxi
Hi Maxime,
This series gets rid of the last usage of the Allwinner specific pinconf
bindings, and drops inclusion of dt-bindings/pinctrl/sun4i-a10.h across
the tree.
Patch 1 gets rid of the last occurrence of Allwinner specific pinconf
properties, which is actually a GPIO pinmux.
Patch 2 drops t
08.03.2017, 01:07, "Maxime Ripard" :
> Hi,
>
> On Tue, Mar 07, 2017 at 01:17:44AM +0800, Icenowy Zheng wrote:
>> Allwinner H5 is a 64-bit SoC with a design like the 32-bit
>> H3, and it's pin-to-pin compatible with H3.
>>
>> This patchset adds support for it, along with the first available
>>
08.03.2017, 01:07, "Maxime Ripard" :
> Hi,
>
> On Tue, Mar 07, 2017 at 01:17:44AM +0800, Icenowy Zheng wrote:
>> Allwinner H5 is a 64-bit SoC with a design like the 32-bit
>> H3, and it's pin-to-pin compatible with H3.
>>
>> This patchset adds support for it, along with the first available
>>
On Mon, Mar 06, 2017 at 10:49:05PM +0100, Rask Ingemann Lambertsen wrote:
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
> > new file mode 100644
> > index ..30639729920d
> > --- /dev/null
> > +++
Hi,
On Tue, Mar 07, 2017 at 01:17:44AM +0800, Icenowy Zheng wrote:
> Allwinner H5 is a 64-bit SoC with a design like the 32-bit
> H3, and it's pin-to-pin compatible with H3.
>
> This patchset adds support for it, along with the first available
> board -- Orange Pi PC2.
>
> Several H5 boards by S
Okay, shame on me,
On Sun, Feb 26, 2017 at 03:23:48PM +0100, Michael Weiser wrote:
> With 4.10 the sensor isn't found any more and /sys/class/hwmon is
> completely empty:
Turns out with CONFIG_MFD_SUN4I_GPADC enabled sun4i-ts isn't found any
more. If I leave sun4i-gpadc out of the kernel, all is
On 03/07, Maxime Ripard wrote:
> So far, divider_round_rate only considers the parent clock returned by
> clk_hw_get_parent.
>
> This works fine on clocks that have a single parents, this doesn't work on
> muxes, since we will only consider the first parent, while other parents
> may totally be ab
> Here is an attempt at getting the HDMI controller running.
> This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s,
> A20, A31).
Thank you thank you thank you.
Stefan "I need it on the A20, so we're not quite
there yet, but it's great to see progres
Hi Maxime,
On Tue, Mar 7, 2017 at 7:56 PM, Maxime Ripard
wrote:
> The video PLLs are used directly by the HDMI controller. Export them so
> that we can use them in our DT node.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/ccu-sun5i.h | 6 --
> include/dt-bindings/clock
Hi,
On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
This is true for both channels, though we handle them differently.
>
> Signed-off-by: Maxime Ripard
> ---
>
The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu_div.c | 7 ---
driv
The A10s Olinuxino has an HDMI connector. Make sure we can use it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 12
1 file changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot
Hi,
Here is an attempt at getting the HDMI controller running.
This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s,
A20, A31).
This driver only supports for now the A10s because it was an easy target,
being very close to the A13 that is already supported by our DRM driver.
It appears that the total vertical resolution needs to be doubled when
we're not in interlaced. Make sure that is the case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon
So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.
This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.
Clocks
The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
controller.
That HDMI controller is able to do audio and CEC, but those have been left
out for now.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile | 5 +-
drivers/gpu/drm/sun4i/sun4i_hdmi.h
One of the possible output of the display pipeline, on the SoCs that have
it, is the HDMI controller.
Add a binding for it.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 21 +++-
1 file changed, 21 insertions(+), 0 deletions(-)
diff --git
divider_round_rate already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu_div.c | 25 ++---
1 file changed, 2 insertions(+), 23 deletions(-)
The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu-sun5i.h | 6 --
include/dt-bindings/clock/sun5i-ccu.h | 3 +++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --
The mode set function need some changes based on which encoder is being
used. Make sure we can differentiate between our encoders by passing the
encoder structure asking for the mode set.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon
The A10s has an HDMI controller connected to the second TCON channel. Add
it to our DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 34 -
arch/arm/boot/dts/sun5i.dtsi | 1 +-
2 files changed, 35 insertions(+), 0 deletions(-)
diff --
It seems like what's called a backporch in the datasheet is actually the
backporch plus the sync period. Fix that in our driver.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4
On Sun, Mar 05, 2017 at 09:36:57PM +0800, Icenowy Zheng wrote:
> Allwinner V3s features a audio codec with dedicated digital and analog parts,
> like the ones on A23/H3, but much simpler (lack of MIC2, LINE IN and MBIAS).
>
> Add support for it.
>
> In order to make the codec usable, DMA support
The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.
However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that migh
While all functions have debug logs, the channel enable and disable are not
logged. Make sure this is the case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/driver
The Allwinner Timings Controller has two, mutually exclusive, channels.
When the binding has been introduced, it was assumed that there would be
only a single user per channel in the system.
While this is likely for the channel 0 which only connects to LCD displays,
it turns out that the channel 1
Even though that mux is undocumented, it seems like it needs to be set to 1
when using composite, and 0 when using HDMI.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.
2017年3月3日 17:55于 Andre Przywara 写道:
>
> Hi,
>
> On 03/03/17 09:22, Maxime Ripard wrote:
> > On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote:
> >>
> >> 2017年3月1日 23:51于 Maxime Ripard 写道:
> >>>
> >>> Hi Andre,
> >>>
> >>> On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara
2017年3月7日 10:47于 Chen-Yu Tsai 写道:
>
> On Tue, Mar 7, 2017 at 8:24 AM, Icenowy Zheng wrote:
> >
> >
> > 07.03.2017, 07:48, "Ondřej Jirman" :
> >> Hi Icenowy,
> >>
> >> when I was trying to add OTG support I found an issue with powercycling.
> >> When I have USB cable connecting PC and the O
I'm glad to hear that.
I hope that you will find out what the cause is.
However, before ioctl reset, sometimes i had some strange glitches in h264
decoded picture when work simultaneous with h264enc.
Some small blocks in the picture was wrong (usually upper left part of
picture) color or someth
41 matches
Mail list logo