Hi Priit,
On 26 June 2017 at 15:53, Priit Laes wrote:
> On Mon, Jun 26, 2017 at 08:05:16AM +1000, Jonathan Liu wrote:
>> Hi Priit,
>>
>> This is showing from clock rate of 171428572 in the output of "cat
>> /sys/kernel/debug/clk/clk_summary" for pll-periph-sata.
>> The clock rate should be 10
On Mon, Jun 26, 2017 at 08:05:16AM +1000, Jonathan Liu wrote:
> Hi Priit,
>
> This is showing from clock rate of 171428572 in the output of "cat
> /sys/kernel/debug/clk/clk_summary" for pll-periph-sata.
> The clock rate should be 1 (100 MHz) when read from the hardware.
This is what I see
Hi Priit,
This is showing from clock rate of 171428572 in the output of "cat
/sys/kernel/debug/clk/clk_summary" for pll-periph-sata.
The clock rate should be 1 (100 MHz) when read from the hardware.
On 26 June 2017 at 06:45, Priit Laes wrote:
> SATA clock on sun4i/sun7i is of type (paren
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/ccu_div.c | 12 ++--
drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_d