[PATCH] headers: untangle kmemleak.h from mm.h

From: Randy Dunlap Currently #includes for no obvious reason. It looks like it's only a convenience, so remove kmemleak.h from slab.h and add to any users of kmemleak_* that don't already #include it. Also remove from source files that do not use it. This is tested on

Re: [PATCH] headers: untangle kmemleak.h from mm.h

* Randy Dunlap wrote: > From: Randy Dunlap > > Currently #includes for no obvious > reason. It looks like it's only a convenience, so remove kmemleak.h > from slab.h and add to any users of kmemleak_* > that don't already #include it. > Also

Re: [PATCH v1] PCI: Make PCI_SCAN_ALL_PCIE_DEVS work for Root as well as Downstream Ports

Hi Bjorn, Sorry for my late answer. The X1000 boots and works since yesterday. I think the following patch solved the issue: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c591c2e36ccc9a08f265841d2fd68e35327ab3c4 Cheers, Christian Sent from my iPhone > On 10.

Re: [PATCH v4 4/5] powerpc/mm/slice: Allow up to 64 low slices

Christophe Leroy writes: > While the implementation of the "slices" address space allows > a significant amount of high slices, it limits the number of > low slices to 16 due to the use of a single u64 low_slices_psize > element in struct mm_context_t > > On the 8xx, the

Re: [PATCH 1/1] powerpc/pseries: Enable RAS hotplug events late

On Mon, Feb 12, 2018 at 11:19 AM, Sam Bobroff wrote: > Currently if the kernel receives a memory hot-unplug event early > enough, it may get stuck in an infinite loop in > dissolve_free_huge_pages(). This appears as a stall just after: > > pseries-hotplug-mem: Attempting

Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32

Christophe Leroy writes: > In preparation for the following patch which will fix an issue on > the 8xx by re-using the 'slices', this patch enhances the > 'slices' implementation to support 32 bits CPUs. > > On PPC32, the address space is limited to 4Gbytes, hence only

Re: [PATCH 2/4] powerpc/vas: Fix cleanup when VAS is not configured

Sukadev Bhattiprolu writes: > When VAS is not configured in the system, make sure to remove > the VAS debugfs directory and unregister the platform driver. > > Signed-off-by: Sukadev Bhattiprolu ... > diff --git

Re: [PATCH kernel v3] powerpc/pci: Fix broken INTx configuration via OF

Bjorn Helgaas writes: > On Fri, Feb 09, 2018 at 12:07:41PM -0600, Bjorn Helgaas wrote: >> On Fri, Feb 09, 2018 at 05:23:58PM +1100, Alexey Kardashevskiy wrote: >> > Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper") >> > replaced of_irq_parse_pci() +

[PATCH 1/1] powerpc/pseries: Enable RAS hotplug events late

Currently if the kernel receives a memory hot-unplug event early enough, it may get stuck in an infinite loop in dissolve_free_huge_pages(). This appears as a stall just after: pseries-hotplug-mem: Attempting to hot-remove XX LMB(s) at It appears to be caused by "minimum_order" being

Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32

On Sun, 11 Feb 2018 21:04:42 +0530 "Aneesh Kumar K.V" wrote: > On 02/11/2018 07:29 PM, Nicholas Piggin wrote: > > On Sat, 10 Feb 2018 13:54:27 +0100 (CET) > > Christophe Leroy wrote: > > > >> In preparation for the following patch

Re: [PATCH V2 3/4] powerpc/mm/hash64: Store the slot information at the right offset.

On Sun, Feb 11, 2018 at 08:30:08PM +0530, Aneesh Kumar K.V wrote: > The hugetlb pte entries are at the PMD and PUD level. Use the right offset > for them to get the second half of the table. > > Signed-off-by: Aneesh Kumar K.V > --- >

Re: [PATCH V2 2/4] powerpc/mm/hash64: Allocate larger PMD table if hugetlb config is enabled.

On Sun, Feb 11, 2018 at 08:30:07PM +0530, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +- > arch/powerpc/include/asm/book3s/64/hash.h | 3 ++- > 2 files changed, 3 insertions(+), 2

Re: [PATCH V2 1/4] powerpc/mm: Fix crashes with PUD level hugetlb config

On Sun, Feb 11, 2018 at 08:30:06PM +0530, Aneesh Kumar K.V wrote: > To support memory keys, we moved the hash pte slot information to the second > half of the page table. This was ok with PTE entries at level 4 and level 3. > We already allocate larger page table pages at those level to accomodate

Re: [PATCH 2/3] cxl: Introduce module parameter 'enable_psltrace'

Thanks for reviewing the patch Christophe, christophe lombard writes: >> +bool cxl_enable_psltrace = true; >> +module_param_named(enable_psltrace, cxl_enable_psltrace, bool, 0600); >> +MODULE_PARM_DESC(enable_psltrace, "Set PSL traces on probe. default: on"); >> + >

Re: [PATCH 1/3] cxl: Introduce various enums/defines for PSL9 trace arrays

Thanks for reviewing the patch Christophe, christophe lombard writes: >> +for (traceid = 0; traceid < CXL_PSL9_TRACEID_MAX; ++traceid) { >> +trace_state = CXL_PSL9_TRACE_STATE(trace_cfg, traceid); >> +dev_dbg(>dev, "Traceid-%d

KVM compile error

Just for info: KVM doesn’t compile currently. Error messages: CC arch/powerpc/kvm/powerpc.o arch/powerpc/kvm/powerpc.c: In function 'kvm_arch_vcpu_ioctl_run': arch/powerpc/kvm/powerpc.c:1611:1: error: label 'out' defined but not used [-Werror=unused-label] out: ^ cc1: all warnings being

Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32

On 02/11/2018 07:29 PM, Nicholas Piggin wrote: On Sat, 10 Feb 2018 13:54:27 +0100 (CET) Christophe Leroy wrote: In preparation for the following patch which will fix an issue on the 8xx by re-using the 'slices', this patch enhances the 'slices' implementation to

[PATCH V2 4/4] powerpc/mm/hash64: memset the pagetable pages on allocation.

Now that we are using second half of the table to store slot details and we don't clear them in the huge_pte_get_and_clear, we need to make sure we zero out the range on allocation. Simplify this by calling the object initialization after kmem_cache_alloc and update the constructor do nothing.

[PATCH V2 3/4] powerpc/mm/hash64: Store the slot information at the right offset.

The hugetlb pte entries are at the PMD and PUD level. Use the right offset for them to get the second half of the table. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 3 ++- arch/powerpc/include/asm/book3s/64/hash-64k.h |

[PATCH V2 2/4] powerpc/mm/hash64: Allocate larger PMD table if hugetlb config is enabled.

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +- arch/powerpc/include/asm/book3s/64/hash.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h

[PATCH V2 1/4] powerpc/mm: Fix crashes with PUD level hugetlb config

To support memory keys, we moved the hash pte slot information to the second half of the page table. This was ok with PTE entries at level 4 and level 3. We already allocate larger page table pages at those level to accomodate extra details. For level 4 we already have the extra space which was

Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32

On Sat, 10 Feb 2018 13:54:27 +0100 (CET) Christophe Leroy wrote: > In preparation for the following patch which will fix an issue on > the 8xx by re-using the 'slices', this patch enhances the > 'slices' implementation to support 32 bits CPUs. > > On PPC32, the address