he hardware (Ken)
> - Update comments in the code accordingly (Ian)
> - Put the code in a utility function (Ian)
>
> Fixes:
> dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=907
On Wednesday, June 10, 2015 05:57:05 PM Neil Roberts wrote:
> Kenneth Graunke writes:
>
> > _mesa_meta_fb_tex_blit_begin(ctx, &blit);
> > + ctx->Extensions.ARB_texture_stencil8 = true;
>
> Maybe you could put assert(ctx->Extensions.ARB_texture_stencil8==
On Thursday, June 11, 2015 09:03:37 AM Iago Toral Quiroga wrote:
> The same fix Marius implemented for gen6 (commit a9b04d8a) and
> gen7 (commit 24ecf37a).
> ---
> src/mesa/drivers/dri/i965/gen8_sf_state.c | 22 --
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> Ken, I
tions)
> + if (options->NirOptions) {
> prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage)
> stage);
> + ralloc_free(shader->ir);
> + shader->ir = NULL;
> + }
>
> _mesa_reference_program(ctx, &prog, NUL
r function
> we use to compute the line width.
Fixes Piglit's line-aa-width and line-flat-clip-color on Broadwell.
Reviewed-by: Kenneth Graunke
Thanks, Iago!
> ---
> src/mesa/drivers/dri/i965/brw_util.h | 31
> +++
> src/mesa/dr
(-2.16%)
helped:64
HURT: 0
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_algebraic.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index eace791..3
On Tuesday, June 16, 2015 10:08:38 PM Meng, David wrote:
> Hi:
> I am new to this email list. I would like to get a help from you.
>
> I found a patch with number of 47790 which supports Intel Broadwell(BDW)
> system gen8 GPU. The author is Topi Pohjolainen. The description is in
> below.
> I
advertised:
python>> hex((1 << 8) - 1)
'0xff'
python>> hex((1 << 16) - 1)
'0x'
python>> hex((1 << 32) - 1)
'0xffff'
python>> hex(0x >> (32 - 8))
'0xff'
pyth
On Tuesday, June 16, 2015 11:34:17 PM Meng, David wrote:
> Hi Ken:
>
> Thank you very much for your quick response.
>
> I have been developing a GPU driver for VMware ESXi kernel. ESXi kernel is a
> virtualized hypervisor and our GPU driver provides graphics support for that
> kernel. We used
On Wednesday, June 17, 2015 12:05:05 AM Meng, David wrote:
> Hi Ken:
> Thank you for the help and clarification.
>
> The back trace we got from the dump file is in blow. The brw_blorp_exec()
> is called in the thread 1.
>
> We do not have other major patches in the Mesa but some small patche
This was originally only used by the vertex shader, but it's now used by
the geometry shader as well, and will also eventually be used for
tessellation control and evaluation shaders.
I suspect it will be easier to find in a file named after the concept.
Signed-off-by: Kenneth Graunke
---
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vue_map.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vue_map.c
b/src/mesa/drivers/dri/i965/brw_vue_map.c
index ff92bd2..7687578 100644
--- a/src/mesa/drivers
ed this in review.
> /me hides
>
> Reviewed-by: Ben Widawsky
Scratch one mystery! Thanks Matt.
Reviewed-by: Kenneth Graunke
>
> > ---
> > src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
ld puts that table index in
[6:1] and bit 0 is something else.
So shifting left by 1 seems like a good plan. Perhaps write it as
#define SKL_MOCS_WB (0b000101 << 1)
#define SKL_MOCS_WT (0b001001 << 1)
so the index value is written like it is in the documentation, and the
shift 1 indicates
On Friday, June 19, 2015 01:14:07 PM Timothy Arceri wrote:
> Just link directly to the piglit repo the old link has outdated information.
>
> Add note about updating patchwork when sending patch revisions.
> ---
> docs/devinfo.html | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
On Wednesday, June 17, 2015 01:01:11 AM Marek Olšák wrote:
> From: Fabian Bieler
>
> Tessellation dependencies added by Marek.
> ---
> src/mesa/main/get.c | 1 +
> src/mesa/main/get_hash_params.py | 28 ++
> src/mesa/main/shaderapi.c| 84
> +
On Wednesday, June 17, 2015 01:01:15 AM Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/mesa/main/api_validate.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
> index 401120a..9a5ac69 100644
> --- a
On Wednesday, June 17, 2015 01:01:16 AM Marek Olšák wrote:
> From: Fabian Bieler
>
> ---
> src/glsl/ast.h | 54 +++-
> src/glsl/ast_to_hir.cpp | 133
> +++-
> src/glsl/ast_type.cpp | 112
On Wednesday, June 17, 2015 01:01:18 AM Marek Olšák wrote:
> From: Fabian Bieler
>
> ---
> src/glsl/ast.h| 1 +
> src/glsl/ast_to_hir.cpp | 45
> src/glsl/ast_type.cpp | 3 +-
> src/glsl/builtin_variables.cp
On Wednesday, June 17, 2015 01:00:59 AM Marek Olšák wrote:
> From: Fabian Bieler
>
> Marek: remove unused members, cleanup
> ---
> src/mesa/main/mtypes.h | 105
> +
> 1 file changed, 105 insertions(+)
>
> diff --git a/src/mesa/main/mtypes.h b/src
I made some comments, but assuming those are taken care of,
patches 1-22 are:
Reviewed-by: Kenneth Graunke
I plan on reviewing the rest, but probably not tonight.
Thanks for picking this up!
signature.asc
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e_rvalue((ir_rvalue **)&ir->lhs);
> + this->fix_lhs(ir);
> +
> + return rvalue_visit(ir);
> +}
> +
> +
> +/**
> + * Set up base_ir properly and call visit_leave() on a newly created
> + * ir_assignment node. This is used in cases where we have to insert an
+ varying_matches(bool disable_varying_packing,
> + gl_shader_stage producer_type,
> + gl_shader_stage consumer_type);
Could we perhaps call these producer_stage and consumer-stage?
Either way,
Reviewed-by: Kenneth Graunke
signature.as
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 4770838..12253e4 100644
--- a/src/mesa
Matt, Jason, and I haven't found this useful in a long time.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_nir.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_
src0_1_w.stride = 2;
> +}
> src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
>
> ibld.MUL(low, src0_0_w, inst->src[1]);
>
Whoops. Yeah, this makes sense.
Reviewed-by: Kenneth Graunke
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___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Wednesday, June 17, 2015 01:01:24 AM Marek Olšák wrote:
> From: Marek Olšák
>
> There is no way to lower them, because the array sizes are unknown
> at compile time.
>
> Based on a patch from: Fabian Bieler
I'm a bit confused by the justification given for this patch.
TCS/TES per-vertex in
On Monday, June 22, 2015 05:24:11 PM Ben Widawsky wrote:
> On Thu, Jun 18, 2015 at 03:41:50PM -0700, Kenneth Graunke wrote:
> > On Wednesday, June 17, 2015 03:50:13 PM Ben Widawsky wrote:
> > > On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0
> &
On Monday, June 22, 2015 06:07:25 PM Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 10 +-
> src/mesa/drivers/dri/i965/intel_debug.c | 13 ++---
> src/mesa/drivers/dri/i965/intel_debug.h | 4 ++--
> src/mesa/drivers/dri/i965/intel_screen.c | 2 ++
> 4
On Monday, June 22, 2015 06:07:29 PM Jason Ekstrand wrote:
> This creates the options at screen cration time and then we just copy them
> into the context at context creation time. We also move is_scalar to the
> brw_compiler structure.
>
> We also end up manually setting some values that the cor
/vec4: Turn some _mesa_problem calls into asserts
> i965/vec4_vs: Add an explicit use_legacy_snorm_formula flag
> i965: Remove the brw_context from the visitors
>
> Kenneth Graunke (1):
> mesa: Add a va_args variant of _mesa_gl_debug().
I requested a few small changes. With tho
Suggested by Jason Ekstrand.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_peephole_select.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/nir_opt_peephole_select.c
b/src/glsl/nir/nir_opt_peephole_select.c
index ef7c977
This is always 0 - only brw_workaround_depthstencil_alignment ever sets
it, and that doesn't run on Gen6+. My initial Broadwell depth state
commit had this mistake.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen8_depth_state.c |7 ++-
1 file changed, 2 inser
d looked like a typo. It doesn't really buy us
anything, so just write the obvious code in normal C.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_fbo.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/
. However, we talked about this with
> Ken and this doesn't really tell much as piglit doesn't really
> re-use shader sources during one execution.
>
> Signed-off-by: Topi Pohjolainen
> CC: Kenneth Graunke
> CC: Tapani P\344lli
> ---
> src/mesa/drivers/dri/i
This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19.
No Piglit changes on Sandybridge.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 +-
1 file changed, 5 insertions(+), 1 del
When binding a layered texture, the layer is already 0. There's no need
to special case this.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_st
}
> - _mesa_DepthRange(save->DepthNear, save->DepthFar);
> + _mesa_set_depth_range(ctx, 0, save->DepthNear, save->DepthFar);
> }
>
> if (state & MESA_META_CLAMP_FRAGMENT_COLOR &&
>
Good catch - this code predates GL_ARB_viewport_array,
On Thursday, June 25, 2015 02:29:13 PM Tapani Pälli wrote:
> Huh I see this went in already, I've noticed a problem and thought to
> share it.
>
> Currently program resource list (used by gl api shader queries) is
> generated in linker, before backend LinkShader call. What this means is
> that
According to the "URB SIMD8 Write > Write Data Payload" documentation,
"The write data payload can be between 1 and 8 message phases long."
Apparently, the simulator considers it an error if you issue an URB
SIMD8 message with only a header and no actual data to write.
Hence, it is also unnecessary for geometry
shaders.
This patch moves the call up to run_vs(). This is equivalent for VS,
but removes the need to pass clip distances into emit_urb_writes().
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp |4 +++-
src/mesa/dr
Adding new shader stages to a switch statement is less confusing than an
if-else-if ladder where all but the first case are fragment shader
specific (but don't claim to be).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 59 +-
1
On Friday, June 26, 2015 04:17:39 PM Jason Ekstrand wrote:
> On Fri, Jun 26, 2015 at 3:56 PM, Kenneth Graunke
> wrote:
> > Legacy user clipping (using gl_Position or gl_ClipVertex) is handled by
> > turning those into the modern gl_ClipDistance equivalents.
> >
> &g
On Friday, June 26, 2015 04:15:46 PM Jordan Justen wrote:
> On 2015-06-26 15:18:52, Kenneth Graunke wrote:
> > According to the "URB SIMD8 Write > Write Data Payload" documentation,
> > "The write data payload can be between 1 and 8 message phases long."
>
On Saturday, June 27, 2015 05:00:22 PM Jordan Justen wrote:
> On 2015-06-26 16:03:21, Kenneth Graunke wrote:
> > Adding new shader stages to a switch statement is less confusing than an
> > if-else-if ladder where all but the first case are fragment shader
> > specific (
On Monday, June 29, 2015 01:13:30 AM Ilia Mirkin wrote:
> ProgramResourceList might not yet have been initialized. In that case,
> parent the var to the program.
>
> Fixes: c2ff3485b3d (glsl: clone inputs and outputs during linking)
> Signed-off-by: Ilia Mirkin
> Cc: mesa-sta...@lists.freedesktop
On Friday, June 26, 2015 10:06:18 AM Eduardo Lima Mitev wrote:
> The NIR->vec4 pass will be activated if ALL the following conditions are met:
>
> * INTEL_USE_NIR environment variable is defined and is positive (1 or true)
> * The stage is vertex shader
> * The HW generation is either SandyBridge
; ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 19 ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 9 +++--
> 2 files changed, 15 insertions(+), 13 deletions(-)
Reviewed-by: Kenneth Graunke
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This is more consistent with how we do it in the FS backend, and reduces
a tiny bit of duplication. It'll also allow for a bit more tidying.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_gs.c | 5 +
src/mesa/drivers/dri/i965/brw_vec4.cpp | 7 +--
src/mesa/dr
At this point, the brw_vs_compile structure only contains the key and
gl_vertex_program pointer. We may as well pass and store them directly;
it's simpler and more convenient (key-> instead of vs_compile->key...).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/b
This patch makes us only issue the performance warning about register
spilling if we actually spilled registers. We also use scratch space
for indirect addressing and the like.
This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for
the vec4 backend.
Signed-off-by: Kenneth Graunke
Jason plumbed this through a while back in the FS backend, but
apparently we were just passing NULL in the vec4 backend.
This patch passes brw in as intended.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_vec4.h
After tearing it out another level or two, and just passing the key and
vp directly, we can finally remove this struct. It also eliminates a
pointless memcpy() of the key.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 37 +-
src
Nothing outside of vec4_visitor uses it, so we may as well keep it
internal.
Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend.
(The empty class will be going away soon.)
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 ++--
src
his saves a CMP/IF/ENDIF in every shader that uses EndPrimitive() or
multiple streams. The only downside is that a shader which emits no
vertices at all will execute an additional URB write---but such shaders
are pointless and not worth optimizing.
Signed-off-by: Kenneth Graunke
---
src/mes
The last patch left the code indented too far.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 142 +++---
1 file changed, 70 insertions(+), 72 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
b/src/mesa/drivers
gt;Color.AlphaEnabled)
> + if (nr_draw_buffers == 0)
>nr_draw_buffers = 1;
>
> size = sizeof(*blend) * nr_draw_buffers;
>
Great catch!
Reviewed-by: Kenneth Graunke
And pushed:
9d408a4..fe2b748 master -> master
I think we ought to change gen8_blend_state.c as well
Matrix vertex attributes have their columns padded out to vec4s, which
I was failing to account for. Scalar NIR expects them to be packed,
however.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 15 +++
1 file
Matrix vertex attributes have their columns padded out to vec4s, which
I was failing to account for. Scalar NIR expects them to be packed,
however.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 15 +++
1 file
On Friday, July 03, 2015 10:50:52 AM Pohjolainen, Topi wrote:
> On Wed, Jul 01, 2015 at 03:03:31PM -0700, Kenneth Graunke wrote:
> > Jason plumbed this through a while back in the FS backend, but
> > apparently we were just passing NULL in the vec4 backend.
> >
> >
On Friday, July 03, 2015 11:11:45 AM Pohjolainen, Topi wrote:
> On Wed, Jul 01, 2015 at 03:03:32PM -0700, Kenneth Graunke wrote:
> > This patch makes us only issue the performance warning about register
> > spilling if we actually spilled registers. We also use scratch space
&
d_ps_extra(struct brw_context *brw,
> if (prog_data->uses_omask)
>dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
>
> + if (brw->gen >= 9 && prog_data->pulls_bary)
> + dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
> +
> if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx))
&g
ld.
Cc: i...@freedesktop.org
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/mesa/program/program_parse_extra.c | 50 +-
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/src/mesa/program/program_parse_extra.c
b/src/me
On Monday, July 06, 2015 02:45:59 AM Francisco Jerez wrote:
> Matt Turner writes:
> > On Fri, Jul 3, 2015 at 3:46 AM, Francisco Jerez
> > wrote:
[snip]
> Yeah. I did in fact try to implement uaddCarry last Friday without
> using the accumulator by doing something like:
>
> | CMP.o tmp, src0, -
On Monday, July 06, 2015 04:24:12 PM Emil Velikov wrote:
> Hello gents,
>
> On 2 July 2015 at 08:45, Kenneth Graunke wrote:
> > On Wednesday, July 01, 2015 10:16:28 AM Mike Stroyan wrote:
> >> When there are no color buffer render targets, gen6 and gen7 still
> &
On Monday, July 06, 2015 11:33:07 AM Chris Wilson wrote:
> With the exception of gen8, the sole user of the workaround bo are for
> emitting pipe controls. Move it out of the purview of the batchbuffer
> and into the pipecontrol.
>
> Signed-off-by: Chris Wilson
Reviewed-by:
On Monday, July 06, 2015 11:33:08 AM Chris Wilson wrote:
> Since the workaround bo is used strictly as a write-only buffer, we need
> only allocate one per screen and use the same one from all contexts.
>
> (The caveat here is during extension initialisation, where we write into
> and read back re
On Monday, July 06, 2015 11:33:10 AM Chris Wilson wrote:
> Rather than allocating a fresh page every time we clear a buffer, keep
> that page around between invocations by tracking the last used offset
> and only allocating a fresh page when we wrap.
>
> Signed-off-by: Chris Wilson
> ---
> src/m
mipmap_tree.c | 28
> ++-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
> 2 files changed, 17 insertions(+), 14 deletions(-)
Huh, I thought I fixed this ages ago. Guess not. Thanks!
Reviewed-by: Kenneth Graunke
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On Monday, July 06, 2015 11:33:12 AM Chris Wilson wrote:
> No external users, so no need to export the symbol outside of our
> compilation unit.
>
> Signed-off-by: Chris Wilson
Good call.
Reviewed-by: Kenneth Graunke
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ff-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 72aad96..b67d9ca 100644
--- a/src/mesa/drivers/dri
ome old kernels trigger a hw bug resulting in the
> TIMESTAMP register being shifted and the low 32bits always zero. Detect
> this by repeating the read a few times and check the register is
> incrementing every 80ns as expected and not stuck on zero (as would be
> the
In the kernel, this is called __must_check; all our attribute macros in
Mesa appear to be uppercase, so I went with that.
Signed-off-by: Kenneth Graunke
Cc: ch...@chris-wilson.co.uk
Cc: matts...@gmail.com
---
configure.ac | 1 +
src/util/macros.h | 6 ++
2 files changed, 7 insertions
dest(p, insn, brw_imm_w(0));
>
Hah! I always thought there were just some bugs in this area, but I'm
surprised to see that they were so small. Great work tracking them
down!
We were doing a bunch of other bogus stuff back in the day, but some of
that got fixed during the Gen4-7 and Gen8+ code
ched is equally buggy.
> * Add full-ppgtt softpinning support (no more relocations, at least for
> the first 256TiB), at the moment there is a limited proof-of-principle
> demonstration
> * polish and move to libdrm; though at the cost of sealing the structs?
>
> Signed-off-by:
On Monday, July 06, 2015 11:33:15 AM Chris Wilson wrote:
> Since the purpose of transform feedback tends to be for the client to
> act upon the results to change the geometry in the scene, it is likely
> that the client will soon be waiting upon the results. Flush the batch
> early so that we don't
y: Chris Wilson
> Cc: Kenneth Graunke
> ---
> src/mesa/swrast_setup/ss_context.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/swrast_setup/ss_context.c
> b/src/mesa/swrast_setup/ss_context.c
> index 74b1da3..028eccb 100644
>
On Monday, July 06, 2015 12:18:18 PM Matt Turner wrote:
> On Mon, Jul 6, 2015 at 9:55 AM, Kenneth Graunke wrote:
> > It looks like this was forgotten in commit 3c9dc2d31b80fc73bffa1f40a
> > (i965: Make a brw_stage_prog_data for storing the SURF_INDEX
> > information.) In o
On Monday, July 06, 2015 09:27:12 PM Chris Wilson wrote:
> On Mon, Jul 06, 2015 at 11:18:00AM -0700, Kenneth Graunke wrote:
> > In the kernel, this is called __must_check; all our attribute macros in
> > Mesa appear to be uppercase, so I went with that.
> >
> > Sig
On Tuesday, June 23, 2015 01:23:05 PM Anuj Phogat wrote:
> In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
> using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
> libdrm need not know about the tiling format because these buffers
> don't have hardware support
On Wednesday, June 10, 2015 03:30:47 PM Anuj Phogat wrote:
> Buffers with Yf/Ys tiling end up using meta upload / download
> paths or the blitter for cases where they used tiled_memcpy paths
> in case of Y tiling. This has exposed some bugs in meta path. To
> avoid any piglit regressions on SKL thi
On Tuesday, July 07, 2015 04:46:22 PM Chris Wilson wrote:
> On Tue, Jul 07, 2015 at 10:12:20AM +0100, Chris Wilson wrote:
> > On Mon, Jul 06, 2015 at 09:05:18PM -0700, Kristian Høgsberg wrote:
> > > On Mon, Jul 6, 2015 at 12:36 PM, Kenneth Graunke
> > > wrote:
> >
On Tuesday, July 07, 2015 09:02:16 PM Chris Wilson wrote:
> On Tue, Jul 07, 2015 at 10:31:07AM -0700, Kenneth Graunke wrote:
> > On Tuesday, July 07, 2015 04:46:22 PM Chris Wilson wrote:
> > > On Tue, Jul 07, 2015 at 10:12:20AM +0100, Chris Wilson wrote:
> > > > On M
Hi Chris,
I made a genuine effort to review this patch, hoping to better understand
the various changes and what you were trying to accomplish. I spent many
hours reading and trying to enumerate changes - or potential changes I
needed to look hard at to convince myself whether they were correct.
Presumably Connor renamed the parameter, inverting the sense.
Update the comment accordingly.
Cc: Connor Abbott
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 4cb7d2f
On Wednesday, July 08, 2015 03:17:35 PM Chris Wilson wrote:
> On Wed, Jul 08, 2015 at 09:51:07AM +0100, Chris Wilson wrote:
> > On Tue, Jul 07, 2015 at 10:03:09PM -0700, Kenneth Graunke wrote:
> > > * Gen4-5 structure changes.
>
> Did you mean brw_structs.h?
>
> dif
_test_LDADD = -lm
>
>
Yeah...haven't thought through a plan yet. This certainly seems
reasonable. Reverting it all and pushing it back in later isn't crazy
either, but with this patch I'm not sure it's hurting anything...
Revie
On Tuesday, June 30, 2015 10:04:47 AM Iago Toral wrote:
> Hi Jason,
>
> On Mon, 2015-06-29 at 16:22 -0700, Jason Ekstrand wrote:
> > On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev
> > wrote:
> > > From: Iago Toral Quiroga
> > >
> > > This is based on similar code existing in vec4_visitor.
lush before the CC_STATE, and the required
workaround flush afterwards
v3: Only perform workaround for render ring
Add text to the BATCH_RESERVE comments
v4: Rebase; update citation to mention PRM and Wa name; combine two blocks.
Signed-off-by: Ben Widawsky
Reviewed-by: Kenneth Graunke
---
src/mesa/d
On Thursday, July 09, 2015 11:00:40 AM Ben Widawsky wrote:
> While implementing the workaround in the previous patch I noticed things were
> starting to get a bit messy. Since gen8 works differently enough from gen7, I
> thought splitting it out with be good.
IMHO this is still a bit messy. What
intel_get_yf_ys_bo_size' from incompatible pointer type
>
> intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but
> argument is of type 'long unsigned int *'
>
> Reported-by: Kenneth Graunke
> Signed-off-by: Anuj Phogat
> ---
> src/m
On Monday, July 13, 2015 11:21:05 AM Iago Toral wrote:
> On Sat, 2015-07-11 at 10:13 +1000, Timothy Arceri wrote:
> > @@ -648,27 +653,28 @@ glsl_type::get_array_instance(const glsl_type *base,
> > unsigned array_size)
> > mtx_lock(&glsl_type::mutex);
> >
> > if (array_types == NULL) {
>
On Tuesday, July 14, 2015 04:26:50 PM Timothy Arceri wrote:
> On Mon, 2015-07-13 at 22:19 -0700, Kenneth Graunke wrote:
> > On Monday, July 13, 2015 11:21:05 AM Iago Toral wrote:
> > > On Sat, 2015-07-11 at 10:13 +1000, Timothy Arceri wrote:
> > > > @
lue. As a result, calls to it can be CSEed. Note that using memory
> + * pointed to by the arguments is not allowed for const functions.
> + */
> +#ifdef HAVE_FUNC_ATTRIBUTE_CONST
> +#define ATTRIBUTE_CONST __attribute__((__const__))
> +#else
> +#define ATTRIBUTE_CONST
> +#endif
> +
&
From: Chris Wilson
The kernel actually waits forever when supplied a timeout value < 0,
rather than returning immediately. See i915_gem_wait_ioctl() in
i915_gem.c's call to __i915_wait_request().
(split by Ken from a large patch authored by Chris Wilson)
Reviewed-by: Kenneth Graunke
From: Connor Abbott
This will split the block containing the instruction and put the CF node
in between.
v2: (by Kenneth Graunke)
- Simplify split_block_after_instr()'s implementation by using
split_block_end() rather than duplicating code.
- Fix a bug in nir_cf_node_insert_after_
From: Connor Abbott
Reviewed-by: Kenneth Graunke
---
src/glsl/nir/nir.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index e9a506c..0db1fc3 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -443,6 +443,18 @@ nir_instr_prev
From: Connor Abbott
Reviewed-by: Kenneth Graunke
---
src/glsl/nir/nir.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 0db1fc3..62cdbd4 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1233,6 +1233,8 @@ nir_block_last_instr
d-off-by: Abdiel Janulgue
This patch is:
Reviewed-by: Kenneth Graunke
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oad->function->name, "main") == 0);
> @@ -1151,10 +1143,8 @@ fs_reg_for_nir_reg(fs_visitor *v, nir_register
> *nir_reg,
> unsigned base_offset, nir_src *indirect)
> {
> fs_reg reg;
> - if (nir_reg->is_global)
> - reg = v-&g
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