On Sat, Jan 14, 2012 at 9:03 AM, Zhi Yong Wu wrote:
> On Sat, Jan 14, 2012 at 5:49 AM, Ryan Harper wrote:
>> We can test out the virtio-blk drive serial number by generating and then
>> reading it back via the file in sysfs.
>>
>> Signed-off-by: Ryan Harper
>> ---
>> tests/virtio-blk-drive-seri
On Sat, Jan 14, 2012 at 5:49 AM, Ryan Harper wrote:
> We can test out the virtio-blk drive serial number by generating and then
> reading it back via the file in sysfs.
>
> Signed-off-by: Ryan Harper
> ---
> tests/virtio-blk-drive-serial.sh | 40
> ++
> 1 f
On Fri, Jan 13, 2012 at 12:11:30PM +0100, Vasilis Liaskovitis wrote:
>
> Signed-off-by: Vasilis Liaskovitis
The SeaBIOS change is okay with me, but the qemu/kvm change needs to
be accepted first.
[...]
> Method (CPEJ, 2, NotSerialized) {
> // _EJ0 method - eject callback
>
Can this patch please be merged? It fixes an important regression
with ioeventfd.
Thanks,
Cam
On Thu, Nov 24, 2011 at 3:05 AM, wrote:
> From: Hongyong Zang
>
> When a guest boots with ioeventfd, an error (by gdb) occurs:
> Program received signal SIGSEGV, Segmentation fault.
> 0x006
Hello,
Can this patch be merged, please?
Thanks,
Cam
On Mon, Dec 5, 2011 at 12:48 PM, Michael S. Tsirkin wrote:
> ivshmem used msix but didn't call it on either reset or
> config write paths. This used to partically work since
> guests don't use all of msi-x configuration fields,
> and reset is
Am 08.12.2011 01:41, schrieb Andreas Färber:
> Am 10.11.2011 19:40, schrieb Pavel Borzenkov:
>> When SDL support is disabled, there is no way to build QEMU without
>> Cocoa support on MacOS X. This patch adds '--disable-cocoa' switch and
>> allows to build QEMU without both SDL and Cocoa frontends.
Just like prep_pci.c, these were not associated with any MAINTAINERS
section, including PCI.
Signed-off-by: Andreas Färber
Cc: Alexander Graf
---
MAINTAINERS |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a4a428a..d56d8fb 100644
--- a/M
Signed-off-by: Andreas Färber
Cc: Alexander Graf
---
MAINTAINERS |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 764c92d..a4a428a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -93,6 +93,7 @@ F: target-mips/
PowerPC
M: Alexander Gra
Hello Alex,
As discussed recently, here's two patches to update the ppc entries in
MAINTAINERS. They're based on ppc-next.
Intent is to have get_maintainers.pl pick up you and qemu-ppc for ppc files.
Regards,
Andreas
Cc: Alexander Graf
Andreas Färber (2):
MAINTAINERS: Add qemu-ppc to all pp
On 11 January 2012 15:26, Mark Langsdorf wrote:
> This adds very basic support for XG-mac ethernet core from Synopsis and
> others.
> +typedef struct rxtx_stats {
> + uint64_t rx_bytes;
> + uint64_t tx_bytes;
> +
> + uint64_t rx;
> + uint64_t rx_bcast;
> + uint64_t rx_mcast;
> +} r
On 01/13/2012 03:05 PM, Ryan Harper wrote:
> Create a cleanup function and call it from all exits so we don't leave
> temp files and directories around since we change the name on each invocation.
>
> Also, no need to delete the files in the tmpdir, so just remove the tmpdir
> if it exists.
>
>
On 01/13/2012 04:05 PM, Ryan Harper wrote:
Signed-off-by: Ryan Harper
You should replace them with 8 spaces and then you wouldn't need the next patch.
Regards,
Anthony Liguori
Signed-off-by: Ryan Harper
---
qemu-test | 62 ++--
1 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/qemu-test b/qemu-test
index 71c1ba1..445ca6d 100755
--- a/qemu-test
+++ b/qemu-test
@@ -29,9 +29,9 @@ if ! which qmp >/dev
Ran qemu-test for the first time and found a few places to clean up the output.
Did tab removal in qemu-test and then updated the indentation to be consistent.
Signed-off-by: Ryan Harper
On Thu, 2012-01-12 at 15:56 -0500, Konrad Rzeszutek Wilk wrote:
> On Tue, Jan 10, 2012 at 11:35:54AM -0700, Alex Williamson wrote:
> > On Tue, 2012-01-10 at 11:26 -0500, Konrad Rzeszutek Wilk wrote:
> > > On Wed, Dec 21, 2011 at 02:42:02PM -0700, Alex Williamson wrote:
> > > > This series includes
Create a cleanup function and call it from all exits so we don't leave
temp files and directories around since we change the name on each invocation.
Also, no need to delete the files in the tmpdir, so just remove the tmpdir
if it exists.
Signed-off-by: Ryan Harper
---
qemu-test | 11 +++
On 2012-01-13 22:18, Anthony Liguori wrote:
> On 01/13/2012 11:35 AM, Jan Kiszka wrote:
>> The KVM in-kernel APIC model will reuse parts of the user space model
>> while providing the same frontend view to guest and most management
>> interfaces.
>>
>> Factor out an APIC base class to encapsulate t
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Am 13.01.2012 21:09, schrieb Jan Kiszka:
> This actually also converts it to a proper ISADevice - a value of
> its own.
Could this by any chance help with eliminating the global
isa_mem_base? Don't see that in this patch.
Andreas
$ grep -r isa_mem_
On Fri, Jan 13, 2012 at 05:50:37PM +, Peter Maydell wrote:
> A small target-arm pullreq, but I want to get the SCR change
> committed because the Calxeda patchset depends on it, and then
> the Samsung patchset is going to need to be updated to sit on
> top of that, as are some Cortex-A15 relate
Inner blocks of if/for/while are all indented.
Signed-off-by: Ryan Harper
---
qemu-test | 56
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/qemu-test b/qemu-test
index 445ca6d..9750a3f 100755
--- a/qemu-test
+++ b/qemu
In some cases, when qemu is just starting up the logfile hasn't yet
been created and will throw an error message into the output:
ls: cannot access .tmp-3070/logfile-3070.log: No such file or directory
if we check to see if the file is readable first then we know the file
is present and we can ex
Am 13.01.2012 22:31, schrieb Andreas Färber:
Am 13.01.2012 22:13, schrieb Stefan Weil:
Am 22.12.2011 11:20, schrieb Stefan Weil:
System emulation executables with SDL are typically windows
executables. Sometimes console executables are more useful,
so create both variants if linker option -mwin
We can test out the virtio-blk drive serial number by generating and then
reading it back via the file in sysfs.
Signed-off-by: Ryan Harper
---
tests/virtio-blk-drive-serial.sh | 40 ++
1 files changed, 40 insertions(+), 0 deletions(-)
create mode 100755 te
On 01/13/2012 12:15 PM, Luiz Capitulino wrote:
> The guest-suspend command supports three modes:
>
> o hibernate (suspend to disk)
> o sleep (suspend to ram)
> o hybrid(save RAM contents to disk, but suspend instead of
> powering off)
>
> To reap terminated children, a ne
Am 13.01.2012 22:13, schrieb Stefan Weil:
> Am 22.12.2011 11:20, schrieb Stefan Weil:
>> System emulation executables with SDL are typically windows
>> executables. Sometimes console executables are more useful,
>> so create both variants if linker option -mwindows was detected.
>>
>> v2:
>> This v
On 2012-01-08 22:09, Blue Swirl wrote:
> Improve VGA selection logic, push check for device availabilty to vl.c.
> Create the devices at board level unconditionally.
>
> Remove now unused pci_try_create*() functions.
>
> Make PCI VGA devices optional.
>
> Signed-off-by: Blue Swirl
> ---
> hw/a
On real Versatile Express hardware, the boot ROM puts the secondary
CPU bootcode/holding pen in SRAM. We can therefore rely on Linux not
trashing this memory until secondary CPUs have booted up, and can
put our QEMU-specific pen code in the same place. This allows us to
drop the odd "hack" RAM page
This actually also converts it to a proper ISADevice - a value of its own.
On 2012-01-08 22:11, Blue Swirl wrote:
> Signed-off-by: Blue Swirl
> ---
> Makefile.target | 13 +++---
> default-configs/alpha-softmmu.mak|2 +
> default-configs/arm-softmmu.mak |
From: Evgeny Voevodin
The secondary CPU bootloader in arm_boot.c holds secondary CPUs in a
pen until the primary CPU releases them. Make boards specify the
address to be polled to determine whether to leave the pen (it was
previously hardcoded to 0x1030, which is a Versatile Express/
Realview
The arm_boot secondary boot loader code needs the address of
the GIC CPU interface. Obtaining this from the base address
of the private peripheral region was possible for A9 and 11MPcore,
but the A15 puts the GIC CPU interface in a different place.
So make boards pass in the GIC CPU interface addre
On 01/13/2012 11:35 AM, Jan Kiszka wrote:
Analogously to the APIC, we will reuse some parts of the user space
i8259 model for KVM. In this case it is a common device state, a common
vmstate, the property list, a reset core and some init bits.
This also introduces a common helper to instantiate a
On 01/13/2012 11:35 AM, Jan Kiszka wrote:
The KVM in-kernel APIC model will reuse parts of the user space model
while providing the same frontend view to guest and most management
interfaces.
Factor out an APIC base class to encapsulate those parts that will be
shared by user space and KVM model
Add a model of the Cortex-A15 memory mapped private peripheral
space. This is fairly simple because the only memory mapped
bit of the A15 is the GIC.
Note that we don't currently model a VGIC and therefore don't
map the VGIC related bits of the GIC.
Signed-off-by: Peter Maydell
---
Makefile.tar
Am 05.01.2012 14:18, schrieb Stefan Weil:
9634d9031c140b24c7ca0d8872632207f6ce7275 disabled unused code.
This patch removes what was left.
If do_pty is 2, the function returns immediately, so any later checks
for do_pty == 2 will always fail and can be removed together with
the code which is nev
Am 22.12.2011 11:20, schrieb Stefan Weil:
System emulation executables with SDL are typically windows
executables. Sometimes console executables are more useful,
so create both variants if linker option -mwindows was detected.
v2:
This version uses QEMU_PROGW / QEMU_PROG instead of QEMU_PROG / Q
On 13 January 2012 20:52, Peter Maydell wrote:
> This patchset adds support for (a rather limited version of) the
> Cortex-A15 CPU and the Versatile Express A15 daughterboard.
> The resulting model is capable of booting a Linux kernel which has
> been configured for Cortex-A15 with the Versatile E
Add the vexpress-a15 machine, and the A-Series memory map it uses.
Signed-off-by: Peter Maydell
---
hw/vexpress.c | 141 +
1 files changed, 141 insertions(+), 0 deletions(-)
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 4b9454f..9d16fb
Instantiate the CLCD on the vexpress motherboard as well as one on
the daughterboard -- the A15 daughterboard does not have a CLCD
and so relies on the motherboard one.
At the moment QEMU doesn't provide infrastructure for selecting
which display device gets to actually show graphics -- the first
Instantiate the L2 cache controller on the ARM devboards which have one,
since we have a dummy model of it now. Note that the only non-MP board
with an L2x0 is the PB1176, which we don't model.
Signed-off-by: Peter Maydell
---
hw/realview.c |2 ++
hw/vexpress.c |1 +
2 files changed, 3 i
Factor out daughterboard specifics into a data structure and
daughterboard initialization function, in preparation for adding
vexpress-a15 support.
Signed-off-by: Peter Maydell
---
hw/vexpress.c | 118 -
1 files changed, 83 insertions(+),
Pull the addresses used for mapping motherboard peripherals into
memory out into a table. This will allow us to simply provide a
second table to implement the "Cortex-A Series" memory map used by
the A15 variant of Versatile Express, as well as the current
"Legacy" map used by A9.
Signed-off-by: P
On 01/09/2012 05:24 AM, Luiz Capitulino wrote:
Signed-off-by: Luiz Capitulino
---
blockdev.c | 47 ++-
blockdev.h |2 --
hmp-commands.hx |3 +--
hmp.c| 14 ++
hmp.h|1 +
qapi-schema
From: Mark Langsdorf
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,
and create a configurable property for each defaulting to 96 and 64
(respectively) so that device modelers can set the value appropriately
for their SoC. Other ARM processors also set their maximum numb
This patchset adds support for (a rather limited version of) the
Cortex-A15 CPU and the Versatile Express A15 daughterboard.
The resulting model is capable of booting a Linux kernel which has
been configured for Cortex-A15 with the Versatile Express "extended
memory map" and without support for LPA
Add a definition of a Cortex-A15 CPU. Note that for the moment we do
not implement any of:
* Large Physical Address Extensions (LPAE)
* Virtualization Extensions
* Generic Timer
* TrustZone (this is also true of our existing Cortex-A9 model, etc)
This CPU model is sufficient to boot a Linux ke
Add a dummy implementation of the cp15 registers for the generic
timer (found in the Cortex-A15), just sufficient for Linux to
decide that it can't use it. This requires at least CNTP_CTL and
CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14.
Signed-off-by: Peter Maydell
---
target-arm/cp
Clarify that enum type names and function type names should follow
the CamelCase style used for structured type names.
Signed-off-by: Peter Maydell
---
During a conversation on IRC with Anthony, I realised that the coding
standard isn't entirely clear about what convention should be followed
for
Prepare Intel 82378 emulation for use by PReP platforms.
Signed-off-by: Hervé Poussineau
Create ISA bus in this device (suggested by Markus).
Rebase onto Memory API, mark memory ops as Little Endian.
Add VMState. Provide access to i8259 IRQs via qdev GPIOs.
Signed-off-by: Andreas Färber
Cc: Ma
Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge.
Signed-off-by: Hervé Poussineau
Confine to CONFIG_I82374. Add VMState.
Signed-off-by: Andreas Färber
Reviewed-by: Alexander Graf
---
Makefile.objs |1 +
default-configs/ppc-softmmu.mak |1 +
hw/i8
Drop pci_prep_init() in favor of extended device state. Inspired by
patches from Hervé and Alex.
Assign the 4 IRQs from the board after device instantiation. This moves
the knowledge out of prep_pci and allows for future machines with
different IRQ wiring (IBM 40P). Suggested by Alex.
Signed-off-
Hello,
Here's an improved initial qdev'ification series for PReP, as prerequisite
for Anthony's second QOM series.
On Jan's suggestion, the i8259 IRQs are exposed through qdev GPIO-in IRQs on
the i82378 PCI->ISA bridge
Regards,
Andreas
Changes since v3:
* i82378: Add i8259 IRQs as state and pro
Am 13.01.2012 20:04, schrieb Jan Kiszka:
> On 2012-01-13 19:49, Peter Maydell wrote:
>> On 13 January 2012 17:35, Jan Kiszka wrote:
>>> Subject: kvm: Arm in-kernel irqchip support
>>
>> I have to say I found this Subject rather confusing :-)
>
> Deeply sorry, but I guess that verb predates the ar
Move initialization of vendor ID, etc. to PCIDeviceInfo.
Introduce VMState.
Signed-off-by: Andreas Färber
Reviewed-by: Alexander Graf
Cc: Hervé Poussineau
Cc: Michael S. Tsirkin
Cc: Anthony Liguori
---
hw/prep_pci.c | 55 ++-
1 files chan
This fixes a bug when using -m isa-serial where qemu-ga will
hang on a read()'s when communicating to the host via isa-serial.
Original fix by Michael Roth.
Signed-off-by: Luiz Capitulino
---
qemu-ga.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/qemu-ga.c b/qemu-ga
The guest-suspend command supports three modes:
o hibernate (suspend to disk)
o sleep (suspend to ram)
o hybrid(save RAM contents to disk, but suspend instead of
powering off)
Before trying to suspend, the command queries the guest in order
to know whether a given mode is
I've tried to address all review comments in this new version. The
two most important changes is that I've added the 'sleep' and 'hybrid'
modes back and now the guest is queried for suspend support (the way
I'm doing this is also worth reviewing).
This series depends on this patch from Michael:
On 01/13/2012 06:05 PM, Paolo Bonzini wrote:
> I think it's not entirely correct because the cast in QTAILQ_PREV and
> QTAILQ_FOREACH_REVERSE does not look like valid ANSI C. No matter how
> hard I look I admit I cannot figure out how it works, but anyway I
> suspect it can be changed to ANSI C
Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up
individually by the machine. Effectively, no-op speaker I/O is replaced
by pcspk; PIT and i82374 DMA are introduced.
Signed-off-by: Hervé Poussineau
Remove related dead, alternative code.
Wire up PCI host bridge IRQs via GPIO-in I
The prep PowerPC CPU is Big Endian. An explicit byte swap therefore
effectively becomes Little Endian.
Remove explicit byte swaps and mark as Little Endian.
Signed-off-by: Andreas Färber
Reviewed-by: Alexander Graf
Cc: Michael S. Tsirkin
---
hw/prep_pci.c |6 +-
1 files changed, 1 ins
Signed-off-by: Andreas Färber
Acked-by: Alexander Graf
---
MAINTAINERS |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index de2a916..148f0d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -307,6 +307,7 @@ PReP
M: Andreas Färber
S: Odd Fixes
Convert to new-style read/write callbacks.
Signed-off-by: Andreas Färber
Reviewed-by: Alexander Graf
Cc: Michael S. Tsirkin
Cc: Avi Kivity
Cc: Benoît Canet
---
hw/prep_pci.c | 61 +---
1 files changed, 23 insertions(+), 38 deletions(-)
d
On 2012-01-13 19:49, Peter Maydell wrote:
> On 13 January 2012 17:35, Jan Kiszka wrote:
>> Subject: kvm: Arm in-kernel irqchip support
>
> I have to say I found this Subject rather confusing :-)
Deeply sorry, but I guess that verb predates the architecture by a few
years. ;)
Jan
--
Siemens AG
Changes in v6:
- back to the roots: model irqchip variants as separate qdev devices
with a common base class
- i8259: Completely privatize PicState
- ioapic: Drop post-load irr initialization
I hope this meets all expectations now and can soon be merged.
Jan
CC: Lai Jiangshan
Jan Kiszka (18)
On real hardware, NMI button events are injected via the LINT1 line of
the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC
LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that
should not receive them. Change the APIC emulation code to reflect this.
Based on qemu
On 13 January 2012 17:35, Jan Kiszka wrote:
> Subject: kvm: Arm in-kernel irqchip support
I have to say I found this Subject rather confusing :-)
-- PMM
More KVM-specific devices will come, so let's start with moving the
kvmclock into a dedicated folder.
Signed-off-by: Jan Kiszka
---
Makefile.target|4 ++--
configure |1 +
hw/{kvmclock.c => kvm/clock.c} |4 ++--
hw/{kvmclock.h => kvm/clock.h} |
Rename msix_supported to msi_supported and control MSI and MSI-X
activation this way. That was likely to original intention for this
flag, but MSI support came after MSI-X.
Signed-off-by: Jan Kiszka
---
hw/msi.c |8
hw/msi.h |2 ++
hw/msix.c |9 -
hw/msix.h |2
Sure, usually a tb chain is setup after a subsequent tb is
found/constructed in the loop in cpu_exec when a tb returns.
Taken/non-taken branch chaining is implemented by indicating the
branch direction by the two least significant digits of the the
previously returned tb. This is usually 0/1. When
The in-kernel i8259 and IOAPIC backends for KVM will need this, so
encapsulate the shared bits.
Signed-off-by: Jan Kiszka
---
hw/apic.c| 11 ---
hw/apic.h|1 +
trace-events |2 +-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/apic.c b/hw/apic.c
inde
This will run all tests through gtester. The main targets are:
$ make check
Which will run each unit test and:
$ make check-report.html
Which will generate a nice HTML report of the test status.
Signed-off-by: Anthony Liguori
---
scripts/gtester-cat | 32
test
Signed-off-by: Anthony Liguori
---
tests/Makefile |2 +-
tests/rtc-test.c | 281 ++
2 files changed, 282 insertions(+), 1 deletions(-)
create mode 100644 tests/rtc-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 9db8553..a6b99
The idea behind qtest is pretty simple. Instead of executing a CPU via TCG or
KVM, rely on an external process to send events to the device model that the CPU
would normally generate.
qtest presents itself as an accelerator. In addition, a new option is added to
establish a qtest server (-qtest)
This also includes a qtest wrapper script to make it easier to launch qtest
tests directly.
Signed-off-by: Anthony Liguori
---
scripts/qtest|5 +
tests/Makefile |2 +
tests/libqtest.c | 334 ++
tests/libqtest.h | 63 ++
This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and
extends the IRQ routing setup by the 0->2 redirection when needed.
The kvm-ioapic model has a property that allows to define its GSI base
for injecting interrupts into the kernel model. This will allow to
disentangle PIC and IOAPIC
This involves replacing the local APIC with the qtest interrupt controller.
It should be pretty straight forward to do the same for other machine types.
Signed-off-by: Anthony Liguori
---
hw/pc_piix.c |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/pc_piix.c
Signed-off-by: Anthony Liguori
---
hw/mc146818rtc.c | 33 --
hw/mc146818rtc.h |3 +-
hw/mc146818rtc_regs.h | 62 +
3 files changed, 63 insertions(+), 35 deletions(-)
create mode 100644 hw/mc146818rtc_regs.h
Introduce the alternative 'kvm-i8259' device model that exploits KVM
in-kernel acceleration.
The PIIX3 initialization code is furthermore extended by KVM specific
IRQ route setup. GSI injection differs in KVM mode from the user space
model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC
Introduce a memory region type that can reserve I/O space. Such regions
are useful for modeling I/O that is only handled outside of QEMU, i.e.
in the context of an accelerator like KVM.
Any access to such a region from QEMU is a bug, but could theoretically
be triggered by guest code (DMA to reser
This introduces the alternative APIC device which makes use of KVM's
in-kernel device model. External NMI injection via LINT1 is emulated by
checking the current state of the in-kernel APIC, only injecting a NMI
into the VCPU if LINT1 is unmasked and configured to DM_NMI.
MSI is not yet supported,
To enable migration between accelerated and non-accelerated APIC models,
we will need to handle the timer saving and restoring specially and can
no longer rely on the automatics of VMSTATE_TIMER. Specifically,
accelerated model will not start any QEMUTimer.
This patch therefore factors out the gen
All LVTs are masked on reset, so the timer becomes ineffective. Letting
it tick nevertheless is harmless, but will at least create a spurious
trace event.
Signed-off-by: Jan Kiszka
---
hw/apic.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/apic.c b/hw/apic.c
index
The KVM in-kernel APIC model will reuse parts of the user space model
while providing the same frontend view to guest and most management
interfaces.
Factor out an APIC base class to encapsulate those parts that will be
shared by user space and KVM model. This class offers callback hooks for
init,
Make the basic in-kernel irqchip support selectable via
-machine ...,kernel_irqchip=on. Leave it off by default until it can
fully replace user space models.
Signed-off-by: Jan Kiszka
---
qemu-config.c |4
qemu-options.hx |5 -
2 files changed, 8 insertions(+), 1 deletions(-)
Fix errors in the decode of M profile CPS:
* the decode of the I (affects PRIMASK) and F (affects FAULTMASK)
bits was reversed
* the FAULTMASK system register number is 19, not 17
This fixes an issue reported as LP:913925.
Signed-off-by: Peter Maydell
---
target-arm/translate.c |8
A small target-arm pullreq, but I want to get the SCR change
committed because the Calxeda patchset depends on it, and then
the Samsung patchset is going to need to be updated to sit on
top of that, as are some Cortex-A15 related changes I've been
working on.
The M profile patch only went on the l
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Signed-off-by: Peter Maydell
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.h
This simplifies the code later when the i8259 moves to the i82378
PCI->ISA bridge and happens to fix a SysBus m48t59 io_base issue
introduced by commit 0fb56ffc5edd66f12ccfc0d71af5f9c79c0a2612 (m48t59:
drop obsolete address base arithmetic). Suggested by Hervé and Jan.
Signed-off-by: Andreas Färbe
Split up the IOAPIC analogously to APIC and i8259. KVM will share the
IOAPICCommonState, the vmstate, reset logic and certain init parts with
the user space model.
Signed-off-by: Jan Kiszka
---
Makefile.target |2 +-
hw/ioapic.c | 140 --
KVM is forced to disable the IRQ0 override when we run with in-kernel
irqchip but without IRQ routing support of the kernel. Set the fwcfg
value correspondingly. This aligns us with qemu-kvm.
Signed-off-by: Jan Kiszka
---
hw/pc.c|3 ++-
kvm-all.c |5 +
kvm-stub.c |5 +
k
Add the basic infrastructure to active in-kernel irqchip support, inject
interrupts into these models, and maintain IRQ routes.
Routing is optional and depends on the host arch supporting
KVM_CAP_IRQ_ROUTING. When it's not available on x86, we looe the HPET as
we can't route GSI0 to IOAPIC pin 2.
Analogously to the APIC, we will reuse some parts of the user space
i8259 model for KVM. In this case it is a common device state, a common
vmstate, the property list, a reset core and some init bits.
This also introduces a common helper to instantiate a single i8259 chip
from the cascade-creating
Use DeviceState instead of PicState in the public i8259 API. This is
cleaner and allows to reorganize the PIC data structures for KVM reuse.
Signed-off-by: Jan Kiszka
---
hw/i8259.c | 15 ++-
hw/pc.h|7 +++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a
As all devices undergo a reset prior to vmloa, and the reset value of
irr is 0, we do not need to do this clearing for older vmstates
explicitly. Dropping this redundant code will also make KVM integration
a bit simpler.
Signed-off-by: Jan Kiszka
---
hw/ioapic.c | 12
1 files chan
QSLIST can be used for a free list, do it.
Signed-off-by: Paolo Bonzini
---
coroutine-ucontext.c | 10 +-
qemu-coroutine-int.h |2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/coroutine-ucontext.c b/coroutine-ucontext.c
index 3d01075..5f43083 100644
--- a/corou
On 01/13/2012 05:44 PM, Peter Maydell wrote:
The main advantage of circular lists (the fact that the head node
> has the same memory layout as any other node) is completely negated
> by the implementation in qemu-queue.h. Not surprisingly, nobody
> uses QCIRCLEQ. While this might change if R
On 01/13/2012 10:44 AM, Paolo Bonzini wrote:
All files under GPLv2 will get GPLv2+ changes starting tomorrow.
event_notifier.c and exec-obsolete.h were only ever touched by Red Hat
employees and can be relicensed now.
Signed-off-by: Paolo Bonzini
Applied. Thanks.
Regards,
Anthony Liguori
The main advantage of circular lists (the fact that the head node
has the same memory layout as any other node) is completely negated
by the implementation in qemu-queue.h. Not surprisingly, nobody
uses QCIRCLEQ. While this might change if RCU is ever adopted by
QEMU, the QLIST is also RCU-friend
Am 13.01.2012 12:19, schrieb Hannes Reinecke:
> This patch adds an emulation for the LSI Megaraid SAS 8708EM2 HBA.
> I've tested it to work with Linux, Windows Vista, and Windows7.
>
> Changes since v8:
> - Remove 'disable' keyword from trace definitions
> - Convert hand-crafted debugging statemen
On 01/13/2012 07:45 AM, Anthony Liguori wrote:
Commit 8eb0283 broken device_del by having too overzealous reference counting
checks. Move the reference count checks to qdev_free(), make sure to remove
the parent link on free, and decrement the reference count on property removal.
Reported-by: M
On 01/13/2012 10:07 AM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
Applied. Thanks.
Regards,
Anthony Liguori
---
v5->v6: Just yet another rebase.
hw/arm_timer.c|1 +
hw/etraxfs_timer.c|1 +
hw/grlib_apbuart.c|1 +
hw/grlib_gptimer.c|
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