This implements APEI GHES Table by passing the error CPER info
to the guest via a fw_cfg_blob. After a CPER info is recorded, an
SEA(Synchronous External Abort)/SEI(SError Interrupt) exception
will be injected into the guest OS.
Below is the table layout, the max number of error soure is 11,
which
Add CONFIG_ACPI_APEI configuration in the Makefile and
enable it in the arm-softmmu.mak
Signed-off-by: Dongjiu Geng
---
thanks a lot Laszlo's review and comments:
change since v3:
(1) change name to "CONFIG_ACPI_APEI" from CONFIG_ACPI_APEI_GENERATION
---
default-configs/arm-softmmu.mak | 1 +
(1) Add related APEI/HEST table structures and macros, these
definition refer to ACPI 6.1 and UEFI 2.6 spec.
(2) Add generic error status block and CPER memory section
definition, user space only handle memory section errors.
Signed-off-by: Dongjiu Geng
---
thanks Laszlo and Michael's re
In the armv8 platform, the mainly hardware error source are ARMv8
SEA/SEI/GSIV. For the ARMv8 SEA/SEI, the KVM or host kernel will signal SIGBUS
or use other interface to notify user space, such as Qemu. After Qemu gets
the notification, it will record the CPER and inject the SEA/SEI to KVM. this
s
Se non visualizzi correttamente questa email clicca:http://email.mailtoshop.com/c/eJxVjsFuwyAQRL_G3IJ2lwDhwCGy3ZvVSv2AiASILRmTOqRW_75EyiXSHGbe4Wm8jZeoJJssAWrQiKBIEHBCPABvqe-x7bUUoNsOTLOH5Ka55PuYb_ySExstRaOcQO_kOXqBDrxH7WN0MkBFhiVLe6ONBDbbsZRbI44NfdRs28bfdRUCQEOSoOuHup6vnlDo3asO7edw-lqnFDr3d_rOsczTE
Hi Jean,
> -Original Message-
> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
> Sent: Friday, July 07, 2017 8:50 PM
> To: Bharat Bhushan ; Auger Eric
> ; eric.auger@gmail.com;
> peter.mayd...@linaro.org; alex.william...@redhat.com; m...@redhat.com;
> qemu-...@nongn
At the moment VFIO PCI device initialization works as follows:
vfio_realize
vfio_get_group
vfio_connect_container
register memory listeners (1)
update QEMU groups lists
vfio_kvm_device_add_group
Then (example f
Copying qemu-trivial.
Marc-André Lureau writes:
> user_creatable_add_opts() returns a reference (the other reference is
> for the root parent/child link).
>
> Leak introduced in commit a1af255f065cc.
>
> Signed-off-by: Marc-André Lureau
> ---
> tests/check-qom-proplist.c | 2 ++
> 1 file chang
Public bug reported:
HyperThreading/SMT is supported by AMD Ryzen CPUs but results in this
message when setting the topology to threads=2:
qemu-system-x86_64: AMD CPU doesn't support hyperthreading. Please
configure -smp options properly.
Checking in a Windows 10 guest reveals that SMT is not en
At the moment, spapr_drc_release() has an ugly switch on the DRC type to
call the right, device-specific release function. This cleans it up by
doing that via a proper QOM method.
It's still arguably an abstraction violation for the DRC code to call into
the specific device code, but one mess at
From: Laurent Vivier
since commit 5c4537bd ("spapr: Fix 2.7<->2.8 migration of PCI host bridge"),
some migration fields are forged from the new ones in spapr_pci_pre_save().
It works well, except when the number of MSI devices is 0,
because in this case the function exits immediately.
This fix
From: Greg Kurz
We have more of these since the addition of KVMPPC_H_LOGICAL_MEMOP in 2012.
Signed-off-by: Greg Kurz
Reviewed-by: Thomas Huth
Signed-off-by: David Gibson
---
include/hw/ppc/spapr.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/hw/ppc/spapr.h
From: Cédric Le Goater
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility
(the former POWER8 interrupt model) or in XIVE exploitation mode (the
newer POWER9 interrupt model).
Bit 7 of Byte 23 of vector 5 is used
From: Greg Kurz
When running KVM on POWER, we allow the user to pass "-cpu POWERx" instead
of "-cpu host". This is achieved by patching the ppc_cpu_aliases[] array
so that "POWERx" points to the CPU class with the same PVR as the host CPU.
This causes CPUs to be instantiated from this CPU class i
From: Greg Kurz
QEMU shouldn't abort if spapr_add_lmbs()->spapr_drc_attach() fails.
Let's propagate the error instead, like it is done everywhere else
where spapr_drc_attach() is called.
Signed-off-by: Greg Kurz
Reviewed-by: Daniel Barboza
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 26
We print a warning if the spapr IOMMU isn't configured to support a page
size matching the host page size backing RAM. When that's the case we need
more complex logic to translate VFIO mappings, which is slower.
But, it's not so slow that it would be at all noticeable against the
general slowness
From: Cédric Le Goater
When XIVE is supported, the device tree should be populated
accordingly and the XIVE memory regions mapped to activate MMIOs.
Depending on the design we choose, we could also allocate different
ICS and ICP objects, or switch between objects. This needs to be
discussed.
Si
spapr_drc_attach() has a 'coldplug' parameter which sets the DRC into
configured state initially, instead of the usual ISOLATED/UNUSABLE state.
It turns out this is unnecessary: although coldplugged devices do need to
be in CONFIGURED state once the guest starts, that will already be
accomplished b
From: Aaron Larson
Properly set the book E exception syndrome register when a floating
point exception occurs.
Currently on a book E processor, the POWERPC_EXCP_FP exception handler
fails to set "env->spr[SPR_BOOKE_ESR] = ESR_FP;" as required by the
book E specification.
Signed-off-by: Aaron La
AIUI, ->unplug_request in the HotplugHandler is used for "soft"
unplug, where acknowledgement from the guest is required before
completing the unplug, whereas ->unplug is used for "hard" unplug
where qemu unilaterally removes the device, and the guest just has to
cope with its sudden absence. For
From: Greg Kurz
$ git grep spapr_ppc_reset
hw/ppc/spapr.c: * as part of spapr_ppc_reset().
$ git grep ppc_spapr_reset
hw/ppc/spapr.c:static void ppc_spapr_reset(void)
hw/ppc/spapr.c:mc->reset = ppc_spapr_reset;
hw/ppc/spapr_hcall.c:/* If ppc_spapr_reset() did not set up a HPT
but on
The DR-indicator is essentially a "virtual LED" attached to a hotpluggable
device, which the guest can set to various states for the attention of
the operator or management layers.
It's mostly guest managed, except that we once-off set it to
ACTIVE/INACTIVE in the attach/detach path. While that m
From: Suraj Jitindar Singh
The mmu-radix64.c file implements functions to enable the radix mmu
emulation in tcg mode. There is a function ppc_radix64_walk_tree() which
performs the radix tree walk and also implicitly checks the pte
protection.
Move the protection checking of the pte from the ppc
From: Suraj Jitindar Singh
In target/ppc/mmu-hash64.c there already exists the function
ppc_hash64_get_phys_page_debug() to get the physical (real) address for
a given effective address in hash mode.
Implement the function ppc_radix64_get_phys_page_debug() to allow a real
address to be obtained
The following changes since commit 6b06e3e49eb8c91cc286c16d6bf3181ac296f33d:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-10-v2' into
staging (2017-07-10 16:12:47 +0100)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.10-20170711
From: Greg Kurz
Since commit ff9006ddbfd1 ("spapr: move spapr_core_[foo]plug() callbacks
close to machine code in spapr.c"), this function doesn't need to be extern
anymore.
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 4 ++--
include/hw/ppc/spapr.h | 2 --
DRC objects have a regular device reset method. However, it only gets
called in the usual way for PCI DRCs. Because of where CPU and LMB DRCs
are in the QOM tree, their device reset method isn't automatically called.
So, the machine manually registers reset handlers to call device_reset().
This
Parallel device don't register be->chr_can_read function, but remote
disconnect event is handled in chr_read.So connected parallel device
can not detect remote disconnect event. The chardevs with chr_can_read=NULL
has the same problem.
Signed-off-by: Peng Hao
Reviewed-by: Wang Yechao
---
charde
On Wed, Jun 28, 2017 at 08:00:40PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Cause the vhost-user client to be woken up whenever:
> a) We place a page in postcopy mode
Just to make sure I understand it correctly - UFFDIO_COPY will only
wake up the waiters
This finishes QOM'fication of IOMMUMemoryRegion by introducing
a IOMMUMemoryRegionClass. This also provides a fastpath analog for
IOMMU_MEMORY_REGION_GET_CLASS().
This makes IOMMUMemoryRegion an abstract class.
Signed-off-by: Alexey Kardashevskiy
---
Changes:
v9:
* moved IOMMU MR typenames next
This defines new QOM object - IOMMUMemoryRegion - with MemoryRegion
as a parent.
This moves IOMMU-related fields from MR to IOMMU MR. However to avoid
dymanic QOM casting in fast path (address_space_translate, etc),
this adds an @is_iommu boolean flag to MR and provides new helper to
do simple cas
Here is a couple of patches to QOM'fy IOMMU memory regions.
I have made them in order to proceed with in-kernel TCE stuff acceleration
enablement which sort of depends on sPAPR IOMMU MR being QOM'ed.
This is based on sha1
3f0602927b Peter Maydell "Merge remote-tracking branch
'remotes/pmaydell/
On Wed, Jun 28, 2017 at 08:00:34PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Stash the RAMBlock and offset for later use looking up
> addresses.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> hw/virtio/trace-events | 1 +
> hw/virtio/vhost-user.c | 11
Hmmm it seems I squashed "add debian/powerpc" (only docker + Makefile)
altogether with this one (shippable entry)
On Tue, Jul 11, 2017 at 12:09 AM, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Alex Bennée
> ---
> .shippable.yml
Hi Richard,
On Mon, Jul 10, 2017 at 11:38 PM, Richard Henderson wrote:
> On 07/10/2017 03:55 PM, Philippe Mathieu-Daudé wrote:
>>
>> This include was forgotten when splitting cacheinfo.c out of
>> tcg/ppc/tcg-target.inc.c (see commit b255b2c8).
>>
>> While compiling on powerpc:
>>
>>CC
Signed-off-by: Philippe Mathieu-Daudé
---
.shippable.yml | 5 +
1 file changed, 5 insertions(+)
diff --git a/.shippable.yml b/.shippable.yml
index 4c8a85941f..1f05d934e4 100644
--- a/.shippable.yml
+++ b/.shippable.yml
@@ -1,6 +1,11 @@
language: c
git:
submodules: false
+branches:
+ o
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian8.docker | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 tests/docker/dockerfiles/debian8.docker
diff --git a/tests/docker/dockerfiles/debian8.docker
b/tests/docker/dockerfiles/de
Signed-off-by: Philippe Mathieu-Daudé
---
.shippable.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.shippable.yml b/.shippable.yml
index 189d193da5..7a89341cea 100644
--- a/.shippable.yml
+++ b/.shippable.yml
@@ -5,6 +5,8 @@ env:
global:
- LC_ALL=C
matrix:
+- IMAGE=debi
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian-amd64-cross.docker | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker
b/tests/docker/dockerfiles/debian-amd64-cross.docker
index 8fb9f90814..48a5e77db7 100644
--- a/te
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian-arm64-cross.docker | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker
b/tests/docker/dockerfiles/debian-arm64-cross.docker
index 6ed12a3f6e..877d863475 100644
--- a/te
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian-amd64-cross.docker | 8
1 file changed, 8 insertions(+)
diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker
b/tests/docker/dockerfiles/debian-amd64-cross.docker
index 88b1b3f4e3..8fb9f90814 100644
---
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
.shippable.yml | 2 ++
tests/docker/Makefile.include | 3 ++
.../docker/dockerfiles/debian-powerpc-cross.docker | 40 ++
3 files changed, 45 insertion
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/Makefile.include | 1 +
tests/docker/dockerfiles/debian-s390x-cross.docker | 20 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/Makefile.include | 6 +++---
tests/docker/dockerfiles/debian-arm64-cross.docker | 4 ++--
tests/docker/dockerfiles/debian-armhf-cross.docker | 4 ++--
tests/docker/dockerfiles/debian-mipsel-cros
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/Makefile.include | 1 +
.../docker/dockerfiles/debian-ppc64el-cross.docker | 24 ++
2 files changed, 25 insertions(+)
create mode 100644 tests/docker/dockerfiles/debian-ppc64el-cross.docker
diff --g
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/Makefile.include | 1 +
tests/docker/dockerfiles/debian-amd64-cross.docker | 18 ++
2 files changed, 19 insertions(+)
create mode 100644 tests/docker/dockerfiles/debian-amd64-cross.docker
diff --git a/t
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian-amd64-cross.docker | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker
b/tests/docker/dockerfiles/debian-amd64-cross.docker
index 9d10a886df..88b1b3f4e3 100644
--
Signed-off-by: Philippe Mathieu-Daudé
---
.shippable.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.shippable.yml b/.shippable.yml
index 5e0caa65c5..abcaf6f4d4 100644
--- a/.shippable.yml
+++ b/.shippable.yml
@@ -5,6 +5,8 @@ env:
global:
- LC_ALL=C
matrix:
+- IMAGE=debi
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
tests/docker/dockerfiles/debian-apt-fake.sh | 46 +
1 file changed, 46 insertions(+)
create mode 100755 tests/docker/dockerfiles/debian-apt-fake.sh
diff --git a/tests/docker/dockerfiles/debian-apt-fa
This patchset add 3 more architectures to the cross-build farm.
Altough amd64 'cross' target sounds weird, I find it useful to cover
more codebase having libraries installed in image I don't need on my
workstation.
There is still some issue trying to cross-build mips64el-softmmu, it
seems the cro
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/Makefile.include | 1 +
tests/docker/dockerfiles/debian-armel-cross.docker | 24 ++
2 files changed, 25 insertions(+)
create mode 100644 tests/docker/dockerfiles/debian-armel-cross.docker
diff --git
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian9.docker | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/docker/dockerfiles/debian9.docker
b/tests/docker/dockerfiles/debian9.docker
index c74f71283c..51c13939ff 100644
--- a/tests/docker/docker
Signed-off-by: Philippe Mathieu-Daudé
---
.shippable.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.shippable.yml b/.shippable.yml
index abcaf6f4d4..189d193da5 100644
--- a/.shippable.yml
+++ b/.shippable.yml
@@ -16,6 +16,8 @@ env:
# mips64el-softmmu disabled due to libfdt proble
Signed-off-by: Philippe Mathieu-Daudé
---
tests/docker/dockerfiles/debian-arm64-cross.docker | 3 ---
tests/docker/dockerfiles/debian-armhf-cross.docker | 3 ---
tests/docker/dockerfiles/debian-mipsel-cross.docker | 3 ---
tests/docker/dockerfiles/debian-s390x-cross.docker | 3 ---
4 files cha
linking on Linux debian/stretch/arm[64] with libxen-4.8:
exec.o: In function `reclaim_ramblock':
qemu/exec.c:2071: undefined reference to `xen_invalidate_map_cache_entry'
exec.o: In function `qemu_map_ram_ptr':
qemu/exec.c:2177: undefined reference to `xen_map_cache'
qemu/exec.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xen/xen_pt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index 375efa68f6..21c32b0991 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -58,7 +58,7 @@
#include "hw/pci/pci.h"
#includ
linking on Linux debian/stretch/arm64 with libxen-4.8:
hw/xen/xen_pt.o: In function `xen_pt_pci_read_config':
qemu/hw/xen/xen_pt.c:206: undefined reference to `xen_shutdown_fatal_error'
hw/xen/xen_pt.o: In function `xen_igd_passthrough_isa_bridge_create':
qemu/hw/xen/xen_pt.c:698:
Hi,
Those errors were triggered installing libxen v4.8 on debian Stretch
ARM (32b and 64b).
It seems QEMU only support Xen on x86 host.
patch 1 disable PCI Passthrough if not on x86,
patch 2 disable xen_map_cache() on ARM, I don't think it is the correct
way to do it, then
patch 3 add few commen
On 07/10/2017 03:55 PM, Philippe Mathieu-Daudé wrote:
This include was forgotten when splitting cacheinfo.c out of
tcg/ppc/tcg-target.inc.c (see commit b255b2c8).
While compiling on powerpc:
CC util/cacheinfo.o
qemu/util/cacheinfo.c: In function 'arch_cache_info':
qemu/uti
On 07/10/2017 03:15 AM, Kashyap Chamarthy wrote:
> This is part of the on-going effort to convert QEMU upstream
> documentation syntax to reStructuredText (rST).
>
> The conversion to rST was done using:
>
> $ pandoc -f markdown -t rst bitmaps.md -o bitmaps.rst
>
> Then, make a couple of sma
Hi Eric,
On 2017/7/10 21:54, Eric Blake wrote:
> On 07/10/2017 04:25 AM, Dongjiu Geng wrote:
>> (1) Add related APEI/HEST table structures and macros, these
>> definition refer to ACPI 6.1 and UEFI 2.6 spec.
>
> Your mail is missing In-Reply-To: and References: headers, which makes
> it appe
This include was forgotten when splitting cacheinfo.c out of
tcg/ppc/tcg-target.inc.c (see commit b255b2c8).
While compiling on powerpc:
CC util/cacheinfo.o
qemu/util/cacheinfo.c: In function 'arch_cache_info':
qemu/util/cacheinfo.c:137:33: error: 'AT_ICACHEBSIZE' undeclared (f
Dear,Laszlo
On 2017/7/10 22:04, Laszlo Ersek wrote:
> Yes, the git-send-email options to use are:
>
> --thread --no-chain-reply-to
>
> Best to set them permanently in one's qemu clone,
>
> $ git config --bool sendemail.thread true
> $ git config --bool sendemail.chainreplyto false
>
>
On 07/10/2017 01:24 PM, Xie Changlong wrote:
在 7/9/2017 5:57 PM, Wang Dong 写道:
Hi,
I am new to QEMU. But I got some problem so that I want to figure it
out.
So I try to debug qemu to see what happened.
And I found trace framework. I think this will help me understand the
point.
So I c
This reverts commit 0bcba41fe379e4c6834adcf1456d9099db31a5b2.
The bug addressed by that commit is now fixed in a better way by the
commit "qdev: fix the order compat and global properties are applied".
Signed-off-by: Eduardo Habkost
---
hw/core/machine.c | 26 +++---
1 file
Test case to detect the bug fixed by commit
"qdev: fix the order compat and global properties are applied".
Signed-off-by: Eduardo Habkost
---
tests/test-qdev-global-props.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/tests/test-qdev-global-props.c b/te
From: Greg Kurz
The current code recursively applies global properties from child up to
parent types. This can cause properties passed with the -global option to
be silently overridden by internal compat properties.
This is exactly what happens with virtio-*-pci drivers since commit:
"9a4c0e220
Before 2.8 was released, we found a bug in the way global
properties are applied by device code. Greg Kurz sent a fix[1],
but we decide to include a more conservative workaround[2]
because the 2.8 release was very close.
The plan was to include Greg's patch in 2.9, but we forgot to do
that. I'm
On Sun, Jul 09, 2017 at 10:11:21 -1000, Richard Henderson wrote:
> On 07/08/2017 09:50 PM, Emilio G. Cota wrote:
> >To avoid wasting a byte. I don't have any use in mind for this byte,
> >but I think it's good to leave this byte explicitly free for future use.
> >See this discussion for how the u16
On 07/10/2017 01:17 PM, Ricardo Ribalda Delgado wrote:
0x0040008179bf <+31>: 8f ea 78 10 d0 08 04 00 00 bextr $0x408,%eax,%edx
...
It seems that, bextr is not supported by the emulator/cpu, althoug I
have launched the emualtor with -cpu Haswell, that should support bmi1
(https://en.wik
> On 07/09/2017 11:12 PM, Jiang Biao wrote:
> > Reserve a register for the guest_base using ppc code for reference.
> > By doing so, we do not have to recompute it for every memory load.
> >
> > Signed-off-by: Jiang Biao
> > Signed-off-by: Richard Henderson
> > ---
> > tcg/mips/tcg-target.inc.c
On 07/10/2017 05:17 AM, Vladimir Sementsov-Ogievskiy wrote:
Can we document this somehow?
In this terminology, what happens with frozen bitmap (which in fact is
like "active" for the user) on successful backup finish? It turns into a
difference between current-state and what-was-backed-up?
On 07/03/2017 11:10 AM, Eric Blake wrote:
Thanks to recent cleanups, most callers were scaling a return value
of sectors into bytes (the exception, in qcow2-bitmap, will be
converted to byte-based iteration later). Update the interface to
do the scaling internally instead.
Signed-off-by: Eric
Hi
I have the following assembly snipset (from get_common_indeces in
glibc compiled with gcc 6.3 -march=bdver4)
0x0040008179b3 <+19>: 89 15 8b c3 20 00 mov
%edx,0x20c38b(%rip)# 0x4000a23d44 <_rtld_local_ro+132>
0x0040008179b9 <+25>: 89 1d 7d c3 20 00 mov
%ebx,0x20c37d(%rip
On 07/03/2017 11:10 AM, Eric Blake wrote:
All callers to bdrv_dirty_iter_new() passed 0 for their initial
starting point, drop that parameter.
Most callers to bdrv_set_dirty_iter() were scaling a byte offset to
a sector number; the exception qcow2-bitmap will be converted later
to use byte rat
On 07/03/2017 11:10 AM, Eric Blake wrote:
We are gradually converting to byte-based interfaces, as they are
easier to reason about than sector-based. Change the qcow2 bitmap
helper function sectors_covered_by_bitmap_cluster(), renaming it
in the process.
Signed-off-by: Eric Blake
It reall
This new call is trying to update a requested map cache entry
according to the changes in the physmap. The call is searching
for the entry, unmaps it and maps again at the same place using
a new guest address. If the mapping is dummy this call will
make it real.
This function makes use of a new xe
If we have a system with xenforeignmemory_map2() implemented
we don't need to save/restore physmap on suspend/restore
anymore. In case we resume a VM without physmap - try to
recreate the physmap during memory region restore phase and
remap map cache entries accordingly. The old code is left
for co
Non-functional change.
Signed-off-by: Igor Druzhinin
Reviewed-by: Stefano Stabellini
Reviewed-by: Paul Durrant
---
hw/i386/xen/xen-hvm.c | 57 ---
1 file changed, 31 insertions(+), 26 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen
Saving/restoring the physmap to/from xenstore was introduced to
QEMU majorly in order to cover up the VRAM region restore issue.
The sequence of restore operations implies that we should know
the effective guest VRAM address *before* we have the VRAM region
restored (which happens later). Unfortuna
Dummys are simple anonymous mappings that are placed instead
of regular foreign mappings in certain situations when we need
to postpone the actual mapping but still have to give a
memory region to QEMU to play with.
This is planned to be used for restore on Xen.
Signed-off-by: Igor Druzhinin
Rev
I don’t believe so, I haven’t been able to find it in the bug database.
~Theodore
> On Jul 10, 2017, at 2:48 PM, Paolo Bonzini wrote:
>
> On 10/07/2017 22:57, Theodore Dubois wrote:
>> - Clang doesn't support size suffixes on the loop instructions.
>
> Has this bug been reported?
>
> Paolo
>
On Mon, Jul 10, 2017 at 17:33:07 -0400, Paolo Bonzini wrote:
>
> > I agree that it would be nice to have the same mechanism for all.
> >
> > The main hurdle I see is how to allow for concurrent code generation while
> > minimizing flushes of the single, fixed-size[*] code_gen_buffer.
> > In user-
On 10 July 2017 at 20:58, Richard Henderson wrote:
> As an aside, I presume we don't have support for armv7ve? I was expecting
> there to be an eret insn in the aa32 translator and had to dig up previous
> manuals to see when that insn was introduced.
We don't yet fully support 32-bit EL2, no. W
On 10/07/2017 22:57, Theodore Dubois wrote:
> - Clang doesn't support size suffixes on the loop instructions.
Has this bug been reported?
Paolo
On 07/03/2017 11:10 AM, Eric Blake wrote:
Right now, the dirty-bitmap code exposes the fact that we use
a scale of sector granularity in the underlying hbitmap to anything
that wants to serialize a dirty bitmap. It's nicer to uniformly
expose bytes as our dirty-bitmap interface, matching the p
> I agree that it would be nice to have the same mechanism for all.
>
> The main hurdle I see is how to allow for concurrent code generation while
> minimizing flushes of the single, fixed-size[*] code_gen_buffer.
> In user-mode this is tricky because there is no way to bound the number
> of thre
First of all, OK, you don't want QNum(42.0) to equal QNum(42) at all (at
least not right now and in the foreseeable future).
You're the maintainer, so you decide, so I'll go along with it. :-)
Now, let's follow up with my therefore rather useless commentary:
(Feel free to disregard, because hones
On 07/10/2017 05:19 PM, Eric Blake wrote:
On 07/10/2017 04:09 PM, John Snow wrote:
On 07/03/2017 11:10 AM, Eric Blake wrote:
We are still using an internal hbitmap that tracks a size in sectors,
with the granularity scaled down accordingly, because it lets us
use a shortcut for our iterator
On 07/10/2017 04:09 PM, John Snow wrote:
>
>
> On 07/03/2017 11:10 AM, Eric Blake wrote:
>> We are still using an internal hbitmap that tracks a size in sectors,
>> with the granularity scaled down accordingly, because it lets us
>> use a shortcut for our iterators which are currently sector-base
On Mon, Jul 10, 2017 at 14:05:01 +0200, Paolo Bonzini wrote:
> On 09/07/2017 09:50, Emilio G. Cota wrote:
> > User-mode is kept out of this: contention due to concurrent translation
> > is more commonly found in full-system mode.
>
> Out of curiosity, is it harder or you just didn't try? It would
On 07/03/2017 11:10 AM, Eric Blake wrote:
We are still using an internal hbitmap that tracks a size in sectors,
with the granularity scaled down accordingly, because it lets us
use a shortcut for our iterators which are currently sector-based.
But there's no reason we can't track the dirty bitm
On 07/10/2017 11:30 AM, Vladimir Sementsov-Ogievskiy wrote:
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: John Snow
> Reviewed-by: Eric Blake
> Reviewed-by: Juan Quintela
> ---
> migration/migration.c | 9 +
> migration/migration.h | 1 +
> qapi-schema.json | 4 +++-
On Mon, 2017-07-10 at 14:49 +0200, Cédric Le Goater wrote:
> On 07/10/2017 12:26 PM, David Gibson wrote:
> > On Wed, Jul 05, 2017 at 07:13:16PM +0200, Cédric Le Goater wrote:
> > > Prepare ground for the new exception model XIVE of POWER9.
> >
> > I'm a bit confused by this. The excp_model is abo
Clang's assembler is slightly incompatible with GCC's assembler, which
caused the program to not compile on Clang for these reasons:
- The "q" constraint was specified for an argument to the set
instruction, which didn't work because Clang chose the esi register,
which has no 8-bit form
The rotation is to the left, but extract shifts to the right.
The computation of the extract parameters needs adjusting.
For the entry condition, simplify
64 - rot + len <= 64
-rot + len <= 0
len <= rot
Reviewed-by: Aurelien Jarno
Reported-by: David Hildenbrand
Suggeste
Drop TRT from the set of insns handled internally by EXECUTE.
It's more important to adjust the existing helper to handle
both TRT and TRTR.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 1 +
target/s390x/mem_helper.c | 20 +---
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 1 +
target/s390x/mem_helper.c | 41 +
target/s390x/translate.c | 13 +
target/s390x/insn-data.def | 2 ++
4 files changed, 57 insertions(+)
dif
Changes since v2:
* Another error in CONVERT UNICODE
Changes since v1:
* Errors corrected in CONVERT UNICODE
* Address writeback corrected in SRST/SRSTU
* IDTES feature added.
* RISBG handling fixed.
r~
David Hildenbrand (1):
target/s390x: Allow to enable "idtes" feature for TCG
R
Since we require all registers saved on input, read R0 from ENV instead
of passing it manually. Recognize the specification exception when R0
contains incorrect data. Keep high bits of result registers unmodified
when in 31 or 24-bit mode.
Reviewed-by: Aurelien Jarno
Signed-off-by: Richard Hend
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