capabalities of different host platform IOMMUs.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/sysemu/host_iommu_device.h | 44 ++
backends/host_iommu_device.c | 29
2 files changed, 73 insertions(+)
diff --git
On 4/29/24 08:50, Zhenzhong Duan wrote:
HostIOMMUDeviceIOMMUFDVFIO represents a host IOMMU device under VFIO
iommufd backend. It will be created during VFIO device attaching and
passed to vIOMMU.
It includes a link to VFIODevice so that we can do VFIO device
specific operations, i.e.,
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 12
hw/vfio/container.c | 6 +-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index b9da6c08ef
On 4/19/24 08:00, Jamin Lin wrote:
Hi Cedric,
Hello Jamin,
On 4/16/24 11:18, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
Side
Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
On 4/19/24 15:41, Cédric Le Goater wrote:
On 4/16/24 11:18, Jamin Lin wrote:
DMA length is from 1 byte to 32MB for AST2600 and AST10x0
and DMA length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte
data for AST2600 and AST
Hello Vinayak,
On 3/28/24 10:30, Cédric Le Goater wrote:
On 3/27/24 21:52, Alex Williamson wrote:
On Wed, 27 Mar 2024 16:11:37 -0400
"Michael S. Tsirkin" wrote:
On Wed, Mar 27, 2024 at 11:39:15AM -0600, Alex Williamson wrote:
On Fri, 22 Mar 2024 12:12:10 +0530
Vinayak Kale wrote
On 4/26/24 19:34, Aditya Gupta wrote:
Hello Cédric,
<...snip...>
- * Multi processor support for POWER8, POWER8NVL and POWER9.
+ * Multi processor support for POWER8, POWER8NVL, POWER9, POWER10 and Power11.
POWER10 -> Power10. Don't ask me why.
Sure, got it !
* XSCOM, serial
On 4/26/24 19:05, Aditya Gupta wrote:
Hello Cédric,
Thanks for your reviews.
On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote:
Hello Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Add base support for "--cpu power11" in QEMU.
Power11 core is same as Power10, h
On 4/26/24 19:12, Aditya Gupta wrote:
Hello Cédric,
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -15,9 +15,9 @@ Supported devices
=
*
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J
.
Cc: Cédric Le Goater
Cc: Joel Stanley
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
pc-bios/skiboot.lid | Bin 2527328 -> 2527328 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
We avoid sending such big blobs on the mailing list.
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Reviewed-by: Cédric Le Goater
Thanks,
C.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan
release, 9.2, 10.0
Thanks,
C.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: David Gibson
Cc: Frédéric Barrat
Cc: Harsh Prateek Bora
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 2
Hello Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
Add base support for "--cpu power11" in QEMU.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Power11 uses the same ISA it seems. What's the value then ?
Cc: Cédric Le Goater
Cc: Daniel Henrique B
On 4/26/24 13:00, Aditya Gupta wrote:
Introduce 'PnvChipClass::chip_type' to easily get which Power chip is
it.
This helps generalise similar codes such as *_dt_populate, and removes
duplication of code between Power11 and Power10 changes in following
patches.
Cc: Cédric Le Goater
Cc: Frédéric
On 4/25/24 14:55, Eric Farman wrote:
On Thu, 2024-04-25 at 12:56 +0200, Markus Armbruster wrote:
Cédric Le Goater writes:
Since vfio_ccw_register_irq_notifier() takes an 'Error **'
argument,
best practices suggest to return a bool. See the qapi/error.h Rules
section.
Signed-off-by: Cédric
On 4/25/24 10:46, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
Hello Zhenzhong,
On 4/18/24 10:42, Duan, Zhenzhong wrote:
Hi Cédric
Signed-off-by: Cédric Le Goater
---
hw/vfio/ccw.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c
index
90e4a534371684c08e112364e1537eb8979f73f4..6764388bc47a970329fce2233626ccb8178e0165
100644
--- a/hw/vfio/ccw.c
+++ b/hw/vfio/ccw.c
Signed-off-by: Cédric Le Goater
---
hw/vfio/ap.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index
7c4caa5938636937680fec87e999249ac84a4498..03f8ffaa5e2bf13cf8daa2f44aa4cf17809abd94
100644
--- a/hw/vfio/ap.c
+++ b/hw/vfio/ap.c
Since vfio_ap_register_irq_notifier() takes and 'Error **' argument,
best practices suggest to return a bool. See the qapi/error.h Rules
section.
Signed-off-by: Cédric Le Goater
---
hw/vfio/ap.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/vfio/ap.c b
Since vfio_ccw_register_irq_notifier() takes an 'Error **' argument,
best practices suggest to return a bool. See the qapi/error.h Rules
section.
Signed-off-by: Cédric Le Goater
---
hw/vfio/ccw.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw
Also change the return value of vfio_ccw_register_irq_notifier() to be
a bool since it takes and 'Error **' argument. See the qapi/error.h
Rules section.
Signed-off-by: Cédric Le Goater
---
hw/vfio/ccw.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff
Also change the return value of vfio_ap_register_irq_notifier() to be
a bool since it takes and 'Error **' argument. See the qapi/error.h
Rules section.
Signed-off-by: Cédric Le Goater
---
hw/vfio/ap.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/hw
This helper routine uses the machine definition, sockets, cores and
threads, to loop on all CPUs of the machine. Replace CPU_FOREACH()
with it.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 48
1 file changed, 36 insertions(+), 12 deletions
On 4/9/24 19:56, Chalapathi V wrote:
In this commit
Creates SPI controller on p10 chip.
Create the keystore seeprom of type "seeprom-25csm04"
Connect the cs of seeprom to PIB_SPIC[2] cs irq.
The QOM tree of spi controller and seeprom are.
/machine (powernv10-machine)
/chip[0]
Hello Chalapathi
On 4/9/24 19:56, Chalapathi V wrote:
This commit implements a Serial EEPROM utilizing the Serial Peripheral
Interface (SPI) compatible bus.
Currently implemented SEEPROM is Microchip's 25CSM04 which provides 4 Mbits
of Serial EEPROM utilizing the Serial Peripheral Interface
On 4/16/24 19:02, Chalapathi V wrote:
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
On 4/16/24 11:18, Jamin Lin wrote:
DMA length is from 1 byte to 32MB for AST2600 and AST10x0
and DMA length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte
data for AST2600 and AST10x0 and 4 bytes data for AST2500.
To support all ASPEED
On 4/16/24 11:18, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
Hello Zhenzhong,
On 4/18/24 10:42, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
Hello Zhenzhong
On 4/17/24 11:24, Duan, Zhenzhong wrote
-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ssi/aspeed_smc.c | 222 +++-
1 file changed, 220 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index a67cac3d0f
Hello Jamin,
On 4/16/24 11:18, Jamin Lin wrote:
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
address, new features and update trace-event
to
On 4/17/24 16:20, Philippe Mathieu-Daudé wrote:
On 17/4/24 08:24, Cédric Le Goater wrote:
Hello,
On 4/16/24 20:47, Philippe Mathieu-Daudé wrote:
We are going to modify these lines, fix their style
in order to avoid checkpatch.pl warnings:
WARNING: line over 80 characters
Signed-off
Hello Zhenzhong
On 4/17/24 11:24, Duan, Zhenzhong wrote:
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
On 4/17/24 06:21, Duan, Zhenzhong wrote:
-Original Message
On 4/17/24 13:02, Nicholas Piggin wrote:
One of the functions of the ADU is indirect memory access engines that
send and receive data via ADU registers.
This implements the ADU LPC memory access functionality sufficiently
for IBM proprietary firmware to access the UART and print characters
to
Hello Nick,
On 4/17/24 13:02, Nicholas Piggin wrote:
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO
and PIB. However it also includes control and status registers and other
functions that are exposed as PIB (xscom)
On 4/17/24 06:21, Duan, Zhenzhong wrote:
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
Hello,
On 4/16/24 09:09, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message
Hello,
On 4/16/24 20:47, Philippe Mathieu-Daudé wrote:
We are going to modify these lines, fix their style
in order to avoid checkpatch.pl warnings:
WARNING: line over 80 characters
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i2c/i2c.h| 11 ++-
is downloaded from the ASPEED Forked OpenBMC GitHub release
repository :
https://github.com/AspeedTech-BMC/openbmc/releases/
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/avocado/machine_aspeed.py | 62
On 4/16/24 11:19, Jamin Lin wrote:
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions
On 4/16/24 11:18, Jamin Lin wrote:
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c197
-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 190 +-
include/hw/misc/aspeed_sdmc.h | 5 +-
2 files changed, 193 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c
D_2700_SLI TYPE_ASPEED_SLI "-ast2700"
+#define TYPE_ASPEED_2700_SLIIO TYPE_ASPEED_SLI "io" "-ast2700"
+OBJECT_DECLARE_TYPE(AspeedSLIState, AspeedSLIClass, ASPEED_SLI)
+
+#define ASPEED_SLI_NR_REGS (0x500 >> 2)
+
+struct AspeedSLIState {
+SysBusDevice parent;
+MemoryRegion iomem;
+
+uint32_t regs[ASPEED_SLI_NR_REGS];
+};
+
+struct AspeedSLIClass {
+SysBusDeviceClass parent_class;
+};
May be use OBJECT_DECLARE_SIMPLE_TYPE() to avoid the empty class.
Anyhow,
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 4/16/24 11:18, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 11
On 4/16/24 11:18, Jamin Lin wrote:
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff
Hello,
On 4/16/24 09:09, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
compatibility check with host IOMMU cap/ecap
On 4/8/24 10:44, Zhenzhong Duan wrote:
From: Yi Liu
If check fails
Hello,
On 4/16/24 05:41, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v2 02/10] vfio: Introduce HIODLegacyVFIO device
On 4/8/24 10:12, Zhenzhong Duan wrote:
HIODLegacyVFIO represents a host IOMMU device under VFIO legacy
container
Hello,
Please rephrase the subject to something like:
"ppc/pnv: Extend SPI model ..."
Using a verb is preferable.
On 4/9/24 19:56, Chalapathi V wrote:
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to
On 4/8/24 10:44, Zhenzhong Duan wrote:
From: Yi Liu
If check fails, the host side device(either vfio or vdpa device) should not
be passed to guest.
Implementation details for different backends will be in following patches.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI
On 4/9/24 19:56, Chalapathi V wrote:
-- Empty commit to align the patch numbers between PATCH v1 and PATCH v2.
SPI responder model is removed as pnv spi controller and seeprom is
implemented using QEMU SSI framework.
Please drop this empty patch. Patch numbers do not need to be aligned
between
On 4/12/24 17:25, Alex Williamson wrote:
On Wed, 10 Apr 2024 18:06:03 +0200
Philippe Mathieu-Daudé wrote:
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,
resulting in painful developper experience. Use g_strdup_printf()
instead.
Isn't this code only compiled for Linux
On 4/8/24 10:12, Zhenzhong Duan wrote:
With HostIOMMUDevice passed, vIOMMU can check compatibility with host
IOMMU, call into IOMMUFD specific methods, etc.
Originally-by: Yi Liu
Signed-off-by: Nicolin Chen
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
LGTM, waiting v3.
Thanks,
On 4/8/24 10:12, Zhenzhong Duan wrote:
From: Yi Liu
This adds pci_device_set/unset_iommu_device() to set/unset
HostIOMMUDevice for a given PCI device. Caller of set
should fail if set operation fails.
Extract out pci_device_get_iommu_bus_devfn() to facilitate
I would separate this change in
On 4/8/24 10:12, Zhenzhong Duan wrote:
Create host IOMMU device instance and initialize it based on backend.
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 1 +
hw/vfio/container.c | 5 +
hw/vfio/iommufd.c | 8
3 files changed, 14
On 4/8/24 10:12, Zhenzhong Duan wrote:
It calls iommufd_backend_get_device_info() to get host IOMMU
related information.
Define a common structure HIOD_IOMMUFD_INFO to describe the info
returned from kernel. Currently only vtd, but easy to add arm smmu
when kernel supports.
I think you can
On 4/8/24 10:12, Zhenzhong Duan wrote:
Introduce a helper function iommufd_backend_get_device_info() to get
host IOMMU related information through iommufd uAPI.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
include/sysemu/iommufd.h | 4
On 4/8/24 10:12, Zhenzhong Duan wrote:
Utilize iova_ranges to calculate host IOMMU address width and
package it in HIOD_LEGACY_INFO for vIOMMU usage.
HIOD_LEGACY_INFO will be used by both VFIO and VDPA so declare
it in host_iommu_device.h.
Signed-off-by: Zhenzhong Duan
---
hiod_iommufd_init() to initialize HIODIOMMUFD
device.
Suggested-by: Cédric Le Goater
Originally-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
include/sysemu/iommufd.h | 22 +++
backends/iommufd.c | 47 ++--
2
On 4/8/24 10:12, Zhenzhong Duan wrote:
HIODLegacyVFIO represents a host IOMMU device under VFIO legacy
container backend.
It includes a link to VFIODevice.
Suggested-by: Eric Auger
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 11
for VFIO, and VDPA in the future.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
LGTM,
---
MAINTAINERS| 2 ++
include/sysemu/host_iommu_device.h | 19 +++
backends/host_iommu_device.c | 19 +++
backends/Kconfig
series))
Daniel Henrique Barboza (reviewer:sPAPR (pseries))
David Gibson (reviewer:sPAPR (pseries))
Harsh Prateek Bora (reviewer:sPAPR (pseries))
"Cédric Le Goater" (odd fixer:PowerNV Non-Virt...)
"Frédéric Barrat" (reviewer:PowerNV Non-Virt...)
qemu-...@nongnu.org (open list:s
On 3/29/24 13:50, Philippe Mathieu-Daudé wrote:
Hi Cédric, Thomas,
On 29/3/24 10:27, Cédric Le Goater wrote:
The test mangles the GPIO address and the pin number in the
qtest_add_data_func data parameter. Doing so, it assumes that the host
pointer size is always 64-bit, which breaks on 32-bit
Hello Aditya,
On 4/2/24 08:39, Aditya Gupta wrote:
Hello Cédric,
Thanks for reviewing this.
On Mon, Apr 01, 2024 at 10:25:31AM +0200, Cédric Le Goater wrote:
Hello Aditya,
Please run ./scripts/get_maintainer.pl when sending a series. qemu-ppc should be
in Cc:
Tried it now, For some reason
Hello Aditya,
Please run ./scripts/get_maintainer.pl when sending a series. qemu-ppc should be
in Cc:
Briefly looking at this, please separate the changes using one patch per model,
that is : first CPU (target), LPC, OCC, PSI, SBE, PnvCore, SpaprCore. Last the
PnvChip and the machines,
Hello Zhenzhong,
On 3/28/24 04:06, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Subject: Re: [PATCH v1 01/11] Introduce a common abstract struct
HostIOMMUDevice
Hello Zhenzhong,
On 3/19/24 12:58, Duan, Zhenzhong wrote:
Hi Cédric,
-Original
Change the board revision number and RAM size to 1Gb on 32-bit hosts.
On these systems, RAM has a 2047 MB limit and this breaks the tests.
Fixes: 7785e8ea2204 ("hw/arm: Introduce Raspberry PI 4 machine")
Signed-off-by: Cédric Le Goater
---
hw/arm/raspi4b.c | 4
1 file changed, 4
This allows to report more precise errors in the migration handler
dirty_bitmap_save_setup().
Suggested-by Vladimir Sementsov-Ogievskiy
Signed-off-by: Cédric Le Goater
---
To apply on top of :
https://lore.kernel.org/qemu-devel/20240320064911.545001-1-...@redhat.com/
migration/block
Hello Vladimir,
On 3/29/24 10:32, Vladimir Sementsov-Ogievskiy wrote:
On 20.03.24 09:49, Cédric Le Goater wrote:
diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c
index
2708abf3d762de774ed294d3fdb8e56690d2974c..542a8c297b329abc30d1b3a205d29340fa59a961
100644
tails.
Cc: Arnaud Minier
Cc: Inès Varhol
Signed-off-by: Cédric Le Goater
---
tests/qtest/stm32l4x5_gpio-test.c | 59 ++-
1 file changed, 35 insertions(+), 24 deletions(-)
diff --git a/tests/qtest/stm32l4x5_gpio-test.c
b/tests/qtest/stm32l4x5_gpio-te
On 3/28/24 16:50, Avihai Horon wrote:
On 28/03/2024 17:21, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_s
Hello Avihai,
On 3/28/24 15:02, Avihai Horon wrote:
After commit 9425ef3f990a ("migration: Use migrate_has_error() in
close_return_path_on_source()"), close_return_path_on_source() assumes
that migration error is set if an error occurs during migration.
This may not be true if migration errors
() error paths.
Fixes: 908927db28ea ("migration: Update error description whenever migration
fails")
Signed-off-by: Avihai Horon
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
migration/migration.c | 8
1 file changed, 8 insertions(+)
diff --git a/migration/mig
On 3/27/24 21:52, Alex Williamson wrote:
On Wed, 27 Mar 2024 16:11:37 -0400
"Michael S. Tsirkin" wrote:
On Wed, Mar 27, 2024 at 11:39:15AM -0600, Alex Williamson wrote:
On Fri, 22 Mar 2024 12:12:10 +0530
Vinayak Kale wrote:
In case of migration, during restore operation, qemu checks
t_xsrc may be ?
Thanks,
C.
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
On
Hello Zhenzhong,
On 3/19/24 12:58, Duan, Zhenzhong wrote:
Hi Cédric,
-Original Message-
From: Cédric Le Goater
Sent: Tuesday, March 19, 2024 4:17 PM
To: Duan, Zhenzhong ; qemu-
de...@nongnu.org
Cc: alex.william...@redhat.com; eric.au...@redhat.com;
pet...@redhat.com; jasow
On 3/26/24 10:55, Philippe Mathieu-Daudé wrote:
On 25/3/24 14:48, Cédric Le Goater wrote:
The PCA9552 and PCA9554 devices are both I2C GPIO controllers and the
PCA9552 also can drive LEDs. Do all the necessary adjustments to move
the models under hw/gpio.
Cc: Glenn Miles
Signed-off-by: Cédric
On 3/21/24 11:04, Saif Abrar wrote:
SW cannot write the read-only(RO) bits of a register
and write-only(WO) bits of a register return 0 when read.
Added ro_mask[] for each register that defines which
bits in that register are RO.
When writing to a register, the RO-bits are not updated.
When
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-host/pnv_phb4.c | 190 ++--
include/hw/pci-host/pnv_phb4_regs.h | 12 +-
tests/qtest/pnv-phb4-test.c | 9 ++
3 files changed, 170 insertions(+), 41 deletions(-)
diff --git a/hw/pci-host
The PCA9552 and PCA9554 devices are both I2C GPIO controllers and the
PCA9552 also can drive LEDs. Do all the necessary adjustments to move
the models under hw/gpio.
Cc: Glenn Miles
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 4 ++--
include/hw/{misc => g
On 3/21/24 11:04, Saif Abrar wrote:
Get the current link-status from PCIE macro.
Extract link-speed and link-width from the link-status
and set in the DLP training control (PCIE_DLP_TCR) register.
Signed-off-by: Saif Abrar
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-host
On 3/21/24 11:04, Saif Abrar wrote:
IODA PCT table (#3) is implemented
without any functionality, being a debug table.
Signed-off-by: Saif Abrar
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-host/pnv_phb4.c | 6 ++
include/hw/pci-host/pnv_phb4.h | 2
On 3/21/24 11:04, Saif Abrar wrote:
PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
You should resend this patch independently of the PowerNV PHB changes.
Thanks,
C.
Signed-off-by: Saif Abrar
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Looks ok.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2
Cc: +Fred +Daniel
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to be invoked on QEMU reset.
Also add CFG and PBL core-blocks reset logic using
appropriate bits of PHB_PCIE_CRESET register.
Tested by reading the reset value of a register.
Signed-off-by: Saif Abrar
---
Hello Saif,
On 3/21/24 11:04, Saif Abrar wrote:
New qtest TB added for PHB4.
TB reads PHB Version register and asserts that
bits[24:31] have value 0xA5.
Signed-off-by: Saif Abrar
---
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 74 +
On 3/20/24 16:00, Peter Maydell wrote:
On Wed, 20 Mar 2024 at 14:10, Mark Burton wrote:
I’d broaden this to all ’signals’ (IRQ, Reset etc) - and I guess
similar statements apply, with the “bridge” between the function
and the GPIO mechanism moved closer or further from the originator(s)
of the
On 3/21/24 18:15, Philippe Mathieu-Daudé wrote:
On 21/3/24 17:01, Cédric Le Goater wrote:
Coverity detected an "Integer handling" issue with the pin value :
In expression "state >> pin", right shifting "state" by more than 7
bits always yields zero.
On 3/21/24 17:08, Miles Glenn wrote:
On Thu, 2024-03-21 at 17:01 +0100, Cédric Le Goater wrote:
Coverity detected an "Integer handling" issue with the pin value :
In expression "state >> pin", right shifting "state" by more than 7
bits always
happen because the properties "pin8" and
above are not created. Nevertheless, fix the range to avoid this warning.
Fixes: CID 1534917
Fixes: de0c7d543bca ("misc: Add a pca9554 GPIO device model")
Cc: Glenn Miles
Signed-off-by: Cédric Le Goater
---
hw/misc/pca9554.c | 4 ++--
1 file change
On 3/20/24 15:42, Peter Xu wrote:
On Wed, Mar 20, 2024 at 07:49:05AM +0100, Cédric Le Goater wrote:
Modify all .log_global_start() handlers to take an Error** parameter
and return a bool. Adapt memory_global_dirty_log_start() to interrupt
on the first error the loop on handlers. In such case
On 3/20/24 09:02, Markus Armbruster wrote:
Cédric Le Goater writes:
This will be useful to report errors at a higher level, mostly in VFIO
today.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
Signed-off-by: Cédric Le Goater
---
[...]
diff --git a/migration/savevm.c b
Cc: Paolo Bonzini
Cc: David Hildenbrand
Cc: Hyman Huang
Signed-off-by: Cédric Le Goater
---
Changes in v5:
- Removed Yong Huang's R-b
- Made use of ram_bitmaps_destroy() in ram_init_bitmaps() to cleanup
allocated bitmaps
include/exec/memory.h | 5 -
hw/i386/xen/xen-hvm.c | 2 +-
Cc: Halil Pasic
Cc: Thomas Huth
Cc: Eric Blake
Cc: Vladimir Sementsov-Ogievskiy
Cc: John Snow
Cc: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
Reviewed-by: Thomas Huth
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Cédric Le Goater
---
include
the cleanup to preserve the error
reported by .save_setup() handlers.
Since the previous behavior was to ignore errors at this step of
migration, this change should be examined closely to check that
cleanups are still correctly done.
Signed-off-by: Cédric Le Goater
---
Changes in v5
() to take an Error** argument
- Various refinements on error handling
Cédric Le Goater (14):
s390/stattrib: Add Error** argument to set_migrationmode() handler
vfio: Always report an error in vfio_save_setup()
migration: Always report an error in block_save_setup()
migration: Always repor
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