Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrange
---
migration/channel.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/migration/channel.c b/migration/channel.c
index edceebdb7b..70ec7ea3b7 100644
---
From: Vladimir Sementsov-Ogievskiy
Now postcopy-able states are recognized by not NULL
save_live_complete_postcopy handler. But when we have several different
postcopy-able states, it is not convenient. Ram postcopy may be
disabled, while some other postcopy enabled, in
From: Peter Xu
Count how many bits set in the bitmap.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
We need that on later patches.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
Reviewed-by: Daniel P. Berrange
---
migration/migration.c | 14 --
1 file
From: Alexey Perevalov
This modification is necessary for userfault fd features which are
required to be requested from userspace.
UFFD_FEATURE_THREAD_ID is a one of such "on demand" feature, which will
be introduced in the next patch.
QEMU have to use separate
TPMDriverOps inside TPMBackend is not required, as it is supposed to be a class
member. The only possible reason for keeping in TPMBackend was, to get the
backend type in tpm.c where dedicated backend api, tpm_backend_get_type() is
present.
Signed-off-by: Amarnath Valluri
Initialize and free TPMBackend data members in it's own instance_init() and
instance_finalize methods.
Took the opportunity to remove unneeded destroy() method from TpmDriverOps
interface as TPMBackend is a Qemu Object, we can use object_unref() inplace of
tpm_backend_destroy() to free the
On Fri, 09/22 13:03, Kevin Wolf wrote:
> Am 22.09.2017 um 04:30 hat Fam Zheng geschrieben:
> > On Thu, 09/21 18:39, Manos Pitsidianakis wrote:
> > > On Thu, Sep 21, 2017 at 09:29:43PM +0800, Fam Zheng wrote:
> > > > On Thu, 09/21 16:17, Manos Pitsidianakis wrote:
> > > It might imply to someone
On Fri, 09/22 11:17, Daniel P. Berrange wrote:
> Sorry yes, my bad - its the iothread behind the monitor. I still think that
> is a detail worth keeping private in case we want to refactor how the
> monitor threading works later.
I agree. I convinced Peter to reuse IOThread just because we can,
On 21 September 2017 at 13:25, Stefan Hajnoczi wrote:
> On Wed, Sep 20, 2017 at 09:38:21PM -0400, John Snow wrote:
>> Apparently GCC gets bent over comparing enum values against zero.
>> Replace the conditional with something less readable.
>>
>> Tested-by: Mark Cave-Ayland
On Fri, 09/22 16:56, Peter Xu wrote:
> When gcontext is used with iothread, the context will be destroyed
> during iothread_stop(). That's not good since sometimes we would like
> to keep the resources until iothread is destroyed, but we may want to
> stop the thread before that point.
Would be
From: Marc-André Lureau
Modify fw_cfg_read_blob() to use DMA if the device supports it.
Return errors, because the operation may fail.
This is a proof-of-concept patch with some FIXME. It uses yield() to
wait for the memory to be cleared. Help on how to improve this
On Thu, 21 Sep 2017 18:11:06 +0200
Halil Pasic wrote:
> So, there is nothing to be addressed about about this series so far.
> Does this mean good for inclusion once prerequisites are met -- unless
> somebody finds something?
It is in my pipeline, and I currently don't
On Fri, Sep 22, 2017 at 12:56:40PM +0200, Cédric Le Goater wrote:
> On 09/22/2017 08:00 AM, Nikunj A Dadhania wrote:
> > David Gibson writes:
> >
> >
> > As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the
> > default value of 1 in vl.c.
* Peter Xu (pet...@redhat.com) wrote:
> After we updated the dirty bitmaps of ramblocks, we also need to update
> the critical fields in RAMState to make sure it is ready for a resume.
>
> Signed-off-by: Peter Xu
> ---
> migration/ram.c| 37
On Fri, Sep 22, 2017 at 01:37:39PM +0200, Cédric Le Goater wrote:
> >> well, it would be good to be able to define chips with different
> >> numbers of cpus. That is something will we want to do for sure.
> >
> > You mean multiple chips in a single system with non-uniform numbers of
> > cores?
On 15/09/17 20:09, Ian Jackson wrote:
> Signed-off-by: Ian Jackson
> ---
> configure | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/configure b/configure
> index fd7e3a5..c59a0c0 100755
> --- a/configure
> +++ b/configure
> @@ -2072,14
Indicates how many pages we are going to send in each batch to a multifd
thread.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
--
Be consistent with defaults and documentation
Use new
git://github.com/juanquintela/qemu.git tags/migration/20170922-1
for you to fetch changes up to 54ae0886b12c4934e84381af777d4df6147cc2ec:
migration: split ufd_version_check onto receive/request features part
(2017-09-22 14:11:29 +0
As this is defined on glib 2.32, add compatibility macros for older glibs.
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrange
Reviewed-by: Peter Xu
---
include/glib-compat.h | 2 ++
migration/exec.c | 2 +-
Indicates the number of channels that we will create. By default we
create 2 channels.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
--
Catch inconsistent defaults (eric).
Improve comment
On 09/22/2017 12:58 PM, David Gibson wrote:
> On Wed, Sep 20, 2017 at 02:54:31PM +0200, Cédric Le Goater wrote:
>> On 09/19/2017 04:57 AM, David Gibson wrote:
>>> On Mon, Sep 11, 2017 at 07:12:21PM +0200, Cédric Le Goater wrote:
Each interrupt source is associated with a two bit state machine
From: Vladimir Sementsov-Ogievskiy
Split common postcopy staff from ram postcopy staff.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Juan Quintela
buffer reallocation is very unlikely to be backend specific. Hence move inside
the tis.
Signed-off-by: Amarnath Valluri
Reviewed-by: Stefan Berger
Reviewed-by: Marc-André Lureau
---
backends/tpm.c
This allows backend implementations left optional interface methods.
For mandatory methods assertion checks added.
Took the opportunity to remove unused tpm_backend_get_desc() method
Signed-off-by: Amarnath Valluri
Reviewed-by: Marc-André Lureau
TPM configuration options are backend implementation details and shall not be
part of base TPMBackend object, and these shall not be accessed directly outside
of the class, hence added a new interface method, get_tpm_options() to
TPMDriverOps., which shall be implemented by the derived classes to
On 09/22/2017 01:00 PM, David Gibson wrote:
> On Tue, Sep 19, 2017 at 03:15:44PM +0200, Cédric Le Goater wrote:
>> On 09/19/2017 04:27 AM, David Gibson wrote:
>>> On Mon, Sep 11, 2017 at 07:12:15PM +0200, Cédric Le Goater wrote:
Start with a couple of attributes for the XIVE sPAPR controller
On 09/22/2017 02:13 PM, Pierre Morel wrote:
> On 22/09/2017 10:38, Christian Borntraeger wrote:
>> Instead of unconditionally enabling the KVM AIS capability
>> in the kvm arch init function, do this in the flic realize function
>> when we know if migration is available. This requires to
On 22/09/2017 14:59, Fam Zheng wrote:
> On Fri, 09/22 11:17, Daniel P. Berrange wrote:
>> Sorry yes, my bad - its the iothread behind the monitor. I still think that
>> is a detail worth keeping private in case we want to refactor how the
>> monitor threading works later.
> I agree. I convinced
* Peter Xu (pet...@redhat.com) wrote:
> This patch implements the first part of core RAM resume logic for
> postcopy. ram_resume_prepare() is provided for the work.
>
> When the migration is interrupted by network failure, the dirty bitmap
> on the source side will be meaningless, because even
On 9/18/2017 6:20 PM, Manos Pitsidianakis wrote:
On Thu, Sep 14, 2017 at 06:40:05AM -0400, Pradeep Jagadeesh wrote:
This patch factors out the duplicate throttle code that was still
present in block and fsdev devices.
Signed-off-by: Pradeep Jagadeesh
Reviewed-by:
On 22 September 2017 at 08:46, Fam Zheng wrote:
> The following changes since commit 0a8066f0c068f1e318a1aacd7864fc00e455a37b:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20170921' into staging (2017-09-21
> 17:42:27 +0100)
>
> are available in
* Peter Xu (pet...@redhat.com) wrote:
> Finish the last step to do the final handshake for the recovery.
>
> First source sends one MIG_CMD_RESUME to dst, telling that source is
> ready to resume.
>
> Then, dest replies with MIG_RP_MSG_RESUME_ACK to source, telling that
> dest is ready to resume
This patch creates a throttle initialization function to maximize the
code reusability. The same code is also used by fsdev.
Signed-off-by: Pradeep Jagadeesh
Reviewed-by: Alberto Garcia
Reviewed-by: Greg Kurz
Acked-by: Dr. David
These patches provide the qmp interface, to query the io throttle
status of the all fsdev devices that are present in a vm.
also, it provides an interface to set the io throttle parameters of a
fsdev to a required value. Some of the patches also remove the
duplicate code that was present in block
This patch factors out code to use the ThrottleLimits
structure.
Signed-off-by: Pradeep Jagadeesh
---
qapi/block-core.json | 75 +++-
1 file changed, 3 insertions(+), 72 deletions(-)
diff --git a/qapi/block-core.json
Trying to start a domain with a qdisk backend on an old dom0 kernel
(non-pvops xen kernel) will fail as xengnttab_set_max_grants() will
succeed only if called directly after opening the gnttab device.
These two patches address the issue by:
- moving the test for availability of
Trying to call xengnttab_set_max_grants() with the same file handle
might fail on some kernels, as this operation is allowed only once.
This is a problem for the qdisk backend as blk_connect() can be
called multiple times for a domain, e.g. in case grub-xen is being
used to boot it.
So instead
Creation of the threads, nothing inside yet.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
--
Use pointers instead of long array names
Move to use semaphores instead of conditions as paolo suggestion
Put all the state inside one
From: Vladimir Sementsov-Ogievskiy
Fill postcopy-able pending only if ram postcopy is enabled.
It is necessary because of there will be other postcopy-able states and
when ram postcopy is disabled, it should not spoil common postcopy
related pending.
Signed-off-by:
On 09/22/2017 12:58 PM, David Gibson wrote:
> On Tue, Sep 19, 2017 at 09:28:45PM +0200, Cédric Le Goater wrote:
>> On 09/19/2017 09:36 AM, David Gibson wrote:
>>> On Mon, Sep 11, 2017 at 07:12:23PM +0200, Cédric Le Goater wrote:
The XIVE interrupt presenter exposes a set of Thread Interrupt
From: Alexey Perevalov
Reviewed-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Alexey Perevalov
Signed-off-by: Juan Quintela
---
migration/postcopy-ram.c |
Signed-off-by: Amarnath Valluri
Reviewed-by: Stefan Berger
Reviewed-by: Marc-André Lureau
---
hw/tpm/tpm_passthrough.c | 64
hw/tpm/tpm_util.c| 25
On Fri, Sep 22, 2017 at 10:37:44AM +0200, Lukáš Doktor wrote:
> Dne 21.9.2017 v 18:22 Eduardo Habkost napsal(a):
> > Not all scripts using qemu.py configure the Python logging
> > module, and end up generating a "No handlers could be found for
> > logger" message instead of actual log messages.
>
On Fri, 09/22 13:42, Paolo Bonzini wrote:
> Drop ccache on Fedora, because it fails on RHEL 7.4, it is not used
> by any other distro and it is not particularly useful on throwaway
> containers.
I wonder what exactly failed with ccache? Patchew relies on it to speed up
compiling every series on
On Fri, 09/22 08:10, Programmingkid wrote:
> Could a Darwin test be added? Both x86 and PowerPC versions would be great.
It's nice to cover macOS in our test, but to be honest I don't know how to do
it. If there isn't any copyright problem, and if there are instructions
available in wiki.qemu.org
On 09/07/2017 10:05 AM, Michal Privoznik wrote:
> diff to v4:
> - in 3/3 compare passed action string case insensitively to the qapi enum
>
> Michal Privoznik (3):
> qapi: Rename WatchdogExpirationAction enum
> watchdog.h: Drop local redefinition of actions enum
> watchdog: Allow setting
On Fri, 09/22 14:55, Kevin Wolf wrote:
> qemu-io provides a 'reopen' command that allows switching from writable
> to read-only access. We need to make sure that we don't try to keep
> write permissions to a BlockBackend that becomes read-only, otherwise
> things are going to fail.
>
> This
From: Marc-André Lureau
Add an optional kernel module (or command line) parameter
using the following syntax:
[qemu_fw_cfg.]ioport=@[::[:]]
or
[qemu_fw_cfg.]mmio=@[::[:]]
and initializes the register address using given or default offset.
From: Marc-André Lureau
Since qemu 2.9, DMA write operations are allowed. However, usage of this
interface from kernel or user-space is strongly discouraged by the
maintainers. This patch is meant for experimentations for now.
Signed-off-by: Marc-André Lureau
On 09/21/2017 04:59 AM, Thomas Huth wrote:
> $ time ppc64-softmmu/qemu-system-ppc64 -nographic -vga none -prom-env
> 'use-nvramrc?=true' -prom-env 'nvramrc=power-off'
> [...]
> real 0m13.953s
> user 0m13.904s
> sys 0m0.046s
>
> That's impressive! Richard, may I ask what's the current state of
Hi Marc-André,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.14-rc1 next-20170922]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/marcandre-lureau-redhat-com/fw_cfg
On 09/22/2017 10:38 AM, Christian Borntraeger wrote:
> Conny, this seem to work on KVM (needs more testing and review).
> Can you check what happens with TCG?
>
> Patch 1 is the known base patch,
> Patch 2 fixes the ais detection to be based on the flic interfaces
> Patch 3 disables ais for all
On Wed, 20 Sep 2017 17:30:13 +0200
David Hildenbrand wrote:
> Some leftover from "target/s390x: tcg improvments + MSA functions".
>
> Implement all basic MSA (cpacf/crypto) instructions <= z13. Only provide
> the query subfunction (to query available subfunctions), no actual
>
Basic test that "make install" works; this requires msgfmt so add
gettext to the packages.
Drop ccache on Fedora, because it fails on RHEL 7.4, it is not used
by any other distro and it is not particularly useful on throwaway
containers.
Signed-off-by: Paolo Bonzini
---
This patch factors out the duplicate throttle code that was still
present in block and fsdev devices.
Signed-off-by: Pradeep Jagadeesh
Reviewed-by: Alberto Garcia
Reviewed-by: Greg Kurz
Reviewed-by: Eric Blake
On 22/09/2017 10:38, Christian Borntraeger wrote:
Instead of unconditionally enabling the KVM AIS capability
in the kvm arch init function, do this in the flic realize function
when we know if migration is available. This requires to initialize
flic before the CPUs.
I am not sure to agree.
Alex, Peter,
JTLYK I just finished to test this one too (which was merged in the
meaning time).
On 09/21/2017 12:07 PM, Fam Zheng wrote:
The image is prepared following instructions as in:
https://wiki.qemu.org/Hosts/BSD
Signed-off-by: Fam Zheng
---
tests/vm/openbsd |
On 09/22/2017 12:33 PM, David Gibson wrote:
> On Thu, Sep 21, 2017 at 04:18:33PM +0200, Cédric Le Goater wrote:
>> On 09/21/2017 03:25 AM, David Gibson wrote:
>>> On Wed, Sep 20, 2017 at 02:33:37PM +0200, Cédric Le Goater wrote:
On 09/19/2017 10:46 AM, David Gibson wrote:
> On Tue, Sep
This change introduces a new TPM backend driver that can communicate with
swtpm(software TPM emulator) using unix domain socket interface. QEMU talks to
TPM emulator using socket based chardev backend device.
Swtpm uses two Unix sockets for communications, one for plain TPM commands and
On 22.09.2017 12:50, Daniel P. Berrange wrote:
On Fri, Sep 22, 2017 at 12:39:24PM +0300, Pavel Butsykin wrote:
Now after shrinking the qcow2 image, at the end of the image file, there might
be a tail that probably will never be used. Although it will not bring any
tangible benefit, we can cut
On 21/09/2017 20:08, Halil Pasic wrote:
The architecture mandates the addresses to be accessed on the first
indirection level (that is, the data addresses without IDA, and the
(M)IDAW addresses with (M)IDA) to be checked against an CCW format
dependent limit maximum address. If a violation is
qemu-io provides a 'reopen' command that allows switching from writable
to read-only access. We need to make sure that we don't try to keep
write permissions to a BlockBackend that becomes read-only, otherwise
things are going to fail.
This requires a bdrv_drain() call because otherwise in-flight
This patch contains modification of userfaultfd.h,
necessary for series
"calculate blocktime for postcopy live migration"
it was decided to send it separatelly with another
modifications.
Build was tested with docker, but it's not fully tested
at runtime.
Based on
On Fri, 09/22 16:56, Peter Xu wrote:
> So that internal iothread users can explicitly stop one iothread without
> destroying it.
>
> Since at it, fix iothread_stop() to allow re-entrance. Before this
I don't think there is any re-entrace here. Maybe you mean
s/re-entrance/calling multiple
On 09/21/2017 04:30 PM, David Hildenbrand wrote:
> +struct sigp_save_area {
> +uint64_tfprs[16]; /* 0x */
> +uint64_tgrs[16];/* 0x0080 */
> +PSW psw;/* 0x0100 */
> +uint8_t
On Fri, Sep 22, 2017 at 08:44:05PM +0800, Fam Zheng wrote:
> On Fri, 09/22 08:10, Programmingkid wrote:
> > Could a Darwin test be added? Both x86 and PowerPC versions would be great.
>
> It's nice to cover macOS in our test, but to be honest I don't know how to do
> it. If there isn't any
Hello
This is known issue, it was mentioned at first time about 9 years ago.
https://lkml.org/lkml/2008/2/5/401
https://bugzilla.redhat.com/show_bug.cgi?id=986761
But it seems not fixed. I tested on my setup.
My Host machine Debian Stretch (kernel 4.9-30), Guest vanilla kernel
4.4-76.
David Gibson writes:
>> >>
>> >> As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the
>> >> default value of 1 in vl.c. In powernv, we were setting nr-cores like
>> >> this:
>> >>
>> >> object_property_set_int(chip, smp_cores, "nr-cores",
On 09/22/2017 08:00 AM, Nikunj A Dadhania wrote:
> David Gibson writes:
>
>
> As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the
> default value of 1 in vl.c. In powernv, we were setting nr-cores like
> this:
>
>
On 09/21/2017 12:07 PM, Fam Zheng wrote:
The image is prepared following instructions as in:
https://wiki.qemu.org/Hosts/BSD
Signed-off-by: Fam Zheng
$ QEMU=`pwd`/x86_64-softmmu/qemu-system-x86_64 make vm-build-freebsd V=1
[...]
CC tests/test-io-channel-socket.o
CC
Hi Thomas,
On 09/22/2017 12:06 AM, Thomas Huth wrote:
If QEMU has been compiled with the flags --enable-tcg-interpreter and
--enable-debug, the guest is running incredibly slow. The pxe boot test
There already is a qtest_get_arch(), it might be convenient to have a
qtest_get_accel() at some
Instead of using "1.0" as the system version of SMBIOS, we should use
mc->name for mach-virt machine type. This matches with x86 code and
prevents the smbios_table.machine_type test of Avocado from failing.
Signed-off-by: Wei Huang
---
hw/arm/virt.c | 3 ++-
1 file changed, 2
On 22/09/2017 14:40, Christian Borntraeger wrote:
On 09/22/2017 02:13 PM, Pierre Morel wrote:
On 22/09/2017 10:38, Christian Borntraeger wrote:
Instead of unconditionally enabling the KVM AIS capability
in the kvm arch init function, do this in the flic realize function
when we know if
Signed-off-by: Carlo Marcelo Arenas Belón
---
linux-user/mips64/sockbits.h | 1 +
linux-user/socket.h | 4 ++--
linux-user/sparc64/sockbits.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
create mode 100644 linux-user/mips64/sockbits.h
create mode 100644
fixes SOL_SOCKET and SO_LINGER at least
Signed-off-by: Carlo Marcelo Arenas Belón
---
linux-user/socket.h | 46 ++--
linux-user/sparc/sockbits.h | 104
2 files changed, 107 insertions(+), 43 deletions(-)
On 09/22/2017 04:02 PM, Pierre Morel wrote:
> On 22/09/2017 14:40, Christian Borntraeger wrote:
>>
>>
>> On 09/22/2017 02:13 PM, Pierre Morel wrote:
>>> On 22/09/2017 10:38, Christian Borntraeger wrote:
Instead of unconditionally enabling the KVM AIS capability
in the kvm arch init
On 30.06.2017 20:37, Richard Henderson wrote:
> Cc: qemu-...@nongnu.org
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate.c | 23 ---
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/translate.c
On Fri, Sep 22, 2017 at 11:28:08AM +0100, Daniel P. Berrange wrote:
> On Fri, Sep 22, 2017 at 12:26:16PM +0200, Paolo Bonzini wrote:
> > On 22/09/2017 12:20, Daniel P. Berrange wrote:
> > > On Fri, Sep 22, 2017 at 12:18:44PM +0200, Paolo Bonzini wrote:
> > >> On 22/09/2017 12:16, Stefan Hajnoczi
Now that we can handle the CONTROL.SPSEL bit not necessarily being
in sync with the current stack pointer, we can restore the correct
security state on exception return. This happens before we start
to read registers off the stack frame, but after we have taken
possible usage faults for bad
In cpu_mmu_index() we try to do this:
if (env->v7m.secure) {
mmu_idx += ARMMMUIdx_MSUser;
}
but it will give the wrong answer, because ARMMMUIdx_MSUser
includes the 0x40 ARM_MMU_IDX_M field, and so does the
mmu_idx we're adding to, and we'll end up with 0x8n rather
than
On exception return for v8M, the SPSEL bit in the EXC_RETURN magic
value should be restored to the SPSEL bit in the CONTROL register
banked specified by the EXC_RETURN.ES bit.
Add write_v7m_control_spsel_for_secstate() which behaves like
write_v7m_control_spsel() but allows the caller to specify
Implement the register interface for the SAU: SAU_CTRL,
SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the
actual behaviour is implemented here; registers just
read back as written.
When the CPU definition for Cortex-M33 is eventually
added, its initfn will set cpu->sau_sregion, in the same
On 22 September 2017 at 16:11, Abhijit Ray Chaudhury
wrote:
> Hi Peter,
>
> Thanks for your prompt response. I have gone through target
> description xml format for gdb
> (https://sourceware.org/gdb//onlinedocs/gdb/ARM-Features.html#ARM-Features)
> . I could not
Implement the SG instruction, which we emulate 'by hand' in the
exception handling code path.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 129 ++--
1 file changed, 124 insertions(+), 5 deletions(-)
diff --git
Proper support of persistent reservation for multipath devices requires
communication with the multipath daemon, so that the reservation is
registered and applied when a path comes up. The device mapper
utilities provide a library to do so; this patch makes qemu-pr-helper.c
detect multipath
env->psa is a 64bit value, while we copy 4 bytes into the save area,
resulting always in 0 getting stored.
Let's try to reduce such errors by using a proper structure. While at
it, use correct cpu->be conversion (and get_psw_mask()), as we will be
reusing this code for TCG soon.
Signed-off-by:
On 09/22/2017 09:03 AM, David Hildenbrand wrote:
> env->psa is a 64bit value, while we copy 4 bytes into the save area,
> resulting always in 0 getting stored.
>
> Let's try to reduce such errors by using a proper structure. While at
> it, use correct cpu->be conversion (and get_psw_mask()), as
Hi,
Can qEmu expose cp15 register set over gdb interface ? Any idea what
changes are required to qemu to support this ?
I can see cp14 registerset is exposed via neon (vfp) xml file but not cp15.
Thanks in advance,
-Abhijit
Cleber and I are volunteering to review and queue patches for the
Python scripts and modules in scripts/.
I'm setting "M: Odd fixes" because not all scripts are actively
maintained.
Signed-off-by: Eduardo Habkost
Message-Id: <20170915230744.22942-1-ehabk...@redhat.com>
The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into
staging (2017-09-21 14:40:32 +0100)
are available in the git repository at:
git://github.com/ehabkost/qemu.git tags/python-next-pull-request
Not all scripts using qemu.py configure the Python logging
module, and end up generating a "No handlers could be found for
logger" message instead of actual log messages.
To avoid requiring every script using qemu.py to configure
logging manually, call basicConfig() when creating a QEMUMachine
Without initialization to zero dirty_bitmap field may be not zero
for a bitmap which should not be stored and
qcow2_store_persistent_dirty_bitmaps will erroneously call
store_bitmap for it which leads to SYGSEGV on bdrv_dirty_bitmap_name.
Signed-off-by: Vladimir Sementsov-Ogievskiy
On Fri, Sep 22, 2017 at 03:35:05PM +0100, Stefan Hajnoczi wrote:
> On Fri, Sep 22, 2017 at 11:28:08AM +0100, Daniel P. Berrange wrote:
> > On Fri, Sep 22, 2017 at 12:26:16PM +0200, Paolo Bonzini wrote:
> > > On 22/09/2017 12:20, Daniel P. Berrange wrote:
> > > > On Fri, Sep 22, 2017 at 12:18:44PM
Reset for devices does not include an automatic clear of the
device state (unlike CPU state, where most of the state
structure is cleared to zero). Add some missing initialization
of NVIC state that meant that the device was left in the wrong
state if the guest did a warm reset.
(In particular,
In the v8M architecture, return from an exception to a PC which
has bit 0 set is not UNPREDICTABLE; it is defined that bit 0
is discarded [R_HRJH]. Restrict our complaint about this to v7M.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 20 +---
Another week, another set of v8M patches.
This lot adds:
* v8M and security extension changes in exception entry and exit
* the Security Attribution Unit
* SG and BLXNS instructions
* secure function return
* and a couple of fixes for bugs in already-in-master changes
Most of this is just
Currently our M profile exception return code switches to the
target stack pointer relatively early in the process, before
it tries to pop the exception frame off the stack. This is
awkward for v8M for two reasons:
* in v8M the process vs main stack pointer is not selected
purely by the value
For the SG instruction and secure function return we are going
to want to do memory accesses using the MMU index of the CPU
in secure state, even though the CPU is currently in non-secure
state. Write arm_v7m_mmu_idx_for_secstate() to do this job,
and use it in cpu_mmu_index().
Signed-off-by:
Attempting to do an exception return with an exception frame that
is not 8-aligned is UNPREDICTABLE in v8M; warn about this.
(It is not UNPREDICTABLE in v7M, and our implementation can
handle the merely-4-aligned case fine, so we don't need to
do anything except warn.)
Signed-off-by: Peter
201 - 300 of 408 matches
Mail list logo