[PATCH 1/5] target/i386: allow versioned CPUs to specify new cache_info

to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger --- target/i386/cpu.c | 36 +--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/t

[PATCH 5/5] target/i386: Add missing feature bits in EPYC-Milan model

/TechDocs/40332_4.05.pdf Signed-off-by: Babu Moger --- target/i386/cpu.c | 70 + 1 file changed, 70 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e9175da92f..54549a5127 100644 --- a/target/i386/cpu.c +++ b/target/i386

[PATCH 2/5] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger --- target/i386/cpu.c | 118 + 1 file changed, 118 insertions(+) diff --git a/t

[PATCH 4/5] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Signed-off-by: Babu Moger --- target/i386/cpu.c | 24 target/i386/cpu.h |8 2 files changed, 32 insertions(+) diff

[PATCH 3/5] target/i386: Add a couple of feature bits in 8000_0008_EBX

tive-store-forwarding.pdf Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Signed-off-by: Babu Moger --- target/i386/cpu.c |4 ++-- target/i386/cpu.h |4 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[PATCH 0/5] Update AMD EPYC CPU Models

This series adds following changes. a. Allow versioned CPUs to specify new cache_info pointers. b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the cache_info.complex_indexing. c. Introduce EPYC-Milan-v2 by adding few missing feature bits. --- Babu Moger (3): target/i386: Add a

[PATCH v3] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: Rebased to the latest tree. Updated the pc_compat_9_0 for the new flag. v2: https://lore.kernel.org/kvm/20240102231738.46553-1-babu.mo...@amd.com/ Rebased to t

[PATCH v4 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs

Rename few data structures related to X86 topology. X86CPUTopoIDs will have individual arch ids. Next patch introduces X86CPUTopoInfo which will have all topology information(like cores, threads etc..). Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c

[PATCH v4 03/16] hw/i386: Consolidate topology functions

Now that we have all the parameters in X86CPUTopoInfo, we can just pass the structure to calculate the offsets and width. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- include/hw/i386/topology.h | 64 ++-- target/i386/cpu.c | 23

[PATCH v4 00/16] APIC ID fixes for AMD EPYC CPU model

Mildly tested different combinations to make things are working as expected. 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is supported only on AMD EPYC models. I may need some guidance on that. v1: https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.m

[PATCH v4 04/16] hw/i386: Introduce init_topo_info to initialize X86CPUTopoInfo

Initialize all the parameters in one function init_topo_info. Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into x86.h. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c |4 +--- hw/i386/x86.c | 14 +++--- include/hw

[PATCH v4 05/16] machine: Add SMP Sockets in CpuTopology

Store the smp sockets in CpuTopology. The socket information required to build the apic id in EPYC mode. Right now socket information is not passed to down when decoding the apic id. Add the socket information here. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/core/machine.c

[PATCH v4 06/16] hw/i386: Update structures for nodes_per_pkg

Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg. This is required to build EPYC mode topology. Signed-off-by: Babu Moger --- hw/i386/pc.c |1 + hw/i386/x86.c |2 ++ include/hw/i386/topology.h |2 ++ include/hw/i386/x86.h

[PATCH v4 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids

For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids. No functional change. Signed-off-by: Babu Moger --- hw/i386/pc.c |2 +- include/hw/i386/topology.h |6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c

[PATCH v4 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info

This is an effort to re-arrange few data structure for better readability. Add X86CPUTopoInfo which will have all the topology informations required to build the cpu topology. There is no functional changes. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- hw/i386/pc.c

[PATCH v4 08/16] hw/386: Add EPYC mode topology decoding functions

available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 93 include/hw/i386/x86.h

[PATCH v4 09/16] target/i386: Cleanup and use the EPYC mode topology functions

Use the new functions from topology.h and delete the unused code. Given the sockets, nodes, cores and threads, the new functions generate apic id for EPYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger --- target/i386/cpu.c | 162

[PATCH v4 10/16] hw/i386: Introduce apicid functions inside X86MachineState

Introduce model specific apicid functions inside X86MachineState. These functions will be loaded from X86CPUDefinition. Signed-off-by: Babu Moger --- include/hw/i386/x86.h |9 + 1 file changed, 9 insertions(+) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index

[PATCH v4 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition

Load the model specific handlers if available or else default handlers will be loaded. Add the model specific handlers if apicid decoding differs from the standard sequential numbering. Signed-off-by: Babu Moger --- target/i386/cpu.c | 38 ++ target/i386

[PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState

Check and Load the apicid handlers from X86CPUDefinition if available. Update the calling convention for the apicid handlers. Signed-off-by: Babu Moger --- hw/i386/pc.c |6 +++--- hw/i386/x86.c | 27 +++ 2 files changed, 26 insertions(+), 7 deletions(-) diff

[PATCH v4 13/16] target/i386: Add EPYC model specific handlers

mplex ID • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]} Signed-off-by: Babu Moger --- target/i386/cpu.c |4 1 file changed, 4 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 389b68d765..082865d72b 100644 --- a/target/i386

[PATCH v4 15/16] i386: Fix pkg_id offset for EPYC cpu models

If the system is numa configured the pkg_offset needs to be adjusted for EPYC cpu models. Fix it calling the model specific handler. Signed-off-by: Babu Moger --- hw/i386/pc.c |1 + hw/i386/x86.c |4 target/i386/cpu.c |4 ++-- target/i386/cpu.h |1 + 4 files

[PATCH v4 14/16] hw/i386: Move arch_id decode inside x86_cpus_init

this time smp parameter is already completed and numa node information is available. Signed-off-by: Babu Moger --- hw/i386/x86.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b825861b85..472dc3eb77 100644 --- a/hw/i386

[PATCH v4 16/16] tests: Update the Unit tests

Since the topology routines have changed, update the unit tests to use the new APIs. Signed-off-by: Babu Moger --- tests/test-x86-cpuid.c | 115 1 file changed, 68 insertions(+), 47 deletions(-) diff --git a/tests/test-x86-cpuid.c b/tests/test

Re: [Qemu-devel] [RFC 2 PATCH 01/16] numa: Split the numa functionality

cpu_index->value); > props.node_id = nodenr; > props.has_node_id = true; > machine_set_cpu_numa_node(ms, &props, &err); > } > } Yes. I this works fine. Also makes the code simple. Only requirement was to know the number of numa nodes in

Re: [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info

uild the cpu topology. There is no >> functional changes. >> >> Signed-off-by: Babu Moger >> --- >> hw/i386/pc.c | 40 +++- >> include/hw/i386/topology.h | 40 ++-- >>

Re: [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info

uild the cpu topology. There is no >> functional changes. >> >> Signed-off-by: Babu Moger >> --- > [...] >> +typedef struct X86CPUTopoInfo { >> +unsigned numa_nodes; >> +unsigned nr_sockets; >> +unsigned nr_dies; >> +unsign

Re: [Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation

On 10/10/19 9:32 PM, Eduardo Habkost wrote: > On Fri, Sep 06, 2019 at 07:12:11PM +, Moger, Babu wrote: >> Some parameters are unnecessarily passed for offset/width >> calculation. Remove those parameters from function prototypes. >> No functional change. >> &

Re: [Qemu-devel] [RFC 2 PATCH 07/16] hw/386: Add new epyc mode topology decoding functions

se these functions to build the topology. >> >> The topology details are available in Processor Programming Reference (PPR) >> for AMD Family 17h Model 01h, Revision B1 Processors. >> It is available at https://www.amd.com/en/support/tech-docs >> >> Signed-off-by:

Re: [Qemu-devel] [RFC 2 PATCH 16/16] hw/core: Fix up the machine_set_cpu_numa_node for epyc

implified apic id decoding in v3 version. We don't need these changes anymore. > >> >> The function machine_set_cpu_numa_node will fail to find a match to assign >> the node. Added new function machine_set_cpu_numa_node_epyc to set the >> node_id >> directly in epy

[PATCH v3 10/18] hw/386: Add EPYC mode topology decoding functions

available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 93 1 file changed, 93

[PATCH v3 17/18] i386: Fix pkg_id offset for epyc mode

Signed-off-by: Babu Moger --- target/i386/cpu.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e87487bae3..0eaedeb848 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4456,7 +4456,7 @@ void cpu_x86_cpuid

[PATCH v3 11/18] i386: Cleanup and use the EPYC mode topology functions

Use the new functions from topology.h and delete the unused code. Given the sockets, nodes, cores and threads, the new functions generate apic id for EPYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger --- target/i386/cpu.c | 162

[PATCH v3 14/18] hw/i386: Introduce topo_ids_from_apicid handler PCMachineState

Add function pointer topo_ids_from_apicid in PCMachineState. Initialize with correct handler based on mode selected. x86_apicid_from_cpu_idx will be the default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 13 +++-- include/hw/i386/pc.h |2 ++ 2 files changed, 9

[PATCH v3 16/18] hw/i386: Introduce EPYC mode function handlers

Introduce following handlers for new epyc mode. x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index. x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id. x86_apicid_from_topo_ids_epyc: Generate apicid from topo ids. Signed-off-by: Babu Moger --- hw/i386/pc.c

[PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass

Add a new function init_apicid_fn in MachineClass to initialize the mode specific handlers to decode the apic ids. Signed-off-by: Babu Moger --- include/hw/boards.h |1 + vl.c|3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h

[PATCH v3 18/18] tests: Update the Unit tests

Since the topology routines have changed, update the unit tests to use the new APIs. Signed-off-by: Babu Moger --- tests/test-x86-cpuid.c | 115 1 file changed, 68 insertions(+), 47 deletions(-) diff --git a/tests/test-x86-cpuid.c b/tests/test

[PATCH v3 15/18] hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState

Add function pointer apic_id_from_topo_ids in PCMachineState. Initialize with correct handler based on the mode selected. Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids for consistency. x86_apicid_from_topo_ids will be the default handler. Signed-off-by: Babu Moger

[PATCH v3 04/18] hw/i386: Introduce initialize_topo_info to initialize X86CPUTopoInfo

Initialize all the parameters in one function initialize_topo_info. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8c23b1e8c9

[PATCH v3 09/18] i386: Add CPUX86Family type in CPUX86State

Add CPUX86Family type in CPUX86State. This will be used to differentiate generic x86 and x86 EPYC based cpu models. Signed-off-by: Babu Moger --- hw/i386/pc.c |4 target/i386/cpu.c |1 + target/i386/cpu.h |7 +++ 3 files changed, 12 insertions(+) diff --git a/hw/i386

[PATCH v3 13/18] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState

Add function pointers in PCMachineState to handle apic id specific functionalities. This will be used to initialize with correct handlers based on the cpu model selected. x86_apicid_from_cpu_idx will be default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c |5 - include

[PATCH v3 12/18] numa: Split the numa initialization

nodes are configured. So, save the cpu indexes and move the cpu initialization inside the numa_complete_configuration. Cpu initialization is done in new function numa_node_complete_configuration. Signed-off-by: Babu Moger --- hw/core/numa.c| 62

[PATCH v3 06/18] hw/core: Add core complex id in X86CPU topology

Introduce last level cache id(llc_id) in x86CPU topology. This information is required to build the topology in EPIC mode. Signed-off-by: Babu Moger --- hw/core/machine-hmp-cmds.c |3 +++ hw/core/machine.c | 13 + hw/i386/pc.c | 10 ++ include

[PATCH v3 08/18] hw/i386: Update structures for nodes_per_pkg

Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg. This is required to build EPYC mode topology. Signed-off-by: Babu Moger --- hw/i386/pc.c |4 include/hw/i386/topology.h |1 + target/i386/cpu.c |1 + target/i386/cpu.h

[PATCH v3 03/18] hw/i386: Consolidate topology functions

Now that we have all the parameters in X86CPUTopoInfo, we can just pass the structure to calculate the offsets and width. Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 64 ++-- target/i386/cpu.c | 23 2 files

[PATCH v3 02/18] hw/i386: Introduce X86CPUTopoInfo to contain topology info

This is an effort to re-arrange few data structure for better readability. Add X86CPUTopoInfo which will have all the topology informations required to build the cpu topology. There is no functional changes. Signed-off-by: Babu Moger --- hw/i386/pc.c | 40

[PATCH v3 05/18] machine: Add SMP Sockets in CpuTopology

Store the smp sockets in CpuTopology. The socket information required to build the apic id in EPYC mode. Right now socket information is not passed to down when decoding the apic id. Add the socket information here. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/core/machine.c

[PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

d different combinations to make things are working as expected. 5. TODO : Setting the epyc feature bit needs to be worked out. This feature is supported only on AMD EPYC models. I may need some guidance on that. v1: https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@a

[PATCH v3 01/18] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs

Rename few data structures related to X86 topology. X86CPUTopoIDs will have individual arch ids. Next patch introduces X86CPUTopoInfo which will have all topology information(like cores, threads etc..). Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c

Re: [PATCH v3 01/18] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs

On 2/3/20 9:08 AM, Igor Mammedov wrote: > On Tue, 03 Dec 2019 18:37:01 -0600 > Babu Moger wrote: > >> Rename few data structures related to X86 topology. X86CPUTopoIDs will >> have individual arch ids. Next patch introduces X86CPUTopoInfo which will >> have al

Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

On 2/3/20 8:59 AM, Igor Mammedov wrote: > On Tue, 03 Dec 2019 18:36:54 -0600 > Babu Moger wrote: > >> This series fixes APIC ID encoding problems on AMD EPYC CPUs. >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3

Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass

On 2/3/20 9:17 AM, Igor Mammedov wrote: > On Wed, 29 Jan 2020 10:17:11 -0600 > Babu Moger wrote: > >> On 1/29/20 3:14 AM, Igor Mammedov wrote: >>> On Tue, 28 Jan 2020 13:45:31 -0600 >>> Babu Moger wrote: >>> >>>> On 1/28/20 10:29 AM,

Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

On 2/4/20 2:02 AM, Igor Mammedov wrote: > On Mon, 3 Feb 2020 13:31:29 -0600 > Babu Moger wrote: > >> On 2/3/20 8:59 AM, Igor Mammedov wrote: >>> On Tue, 03 Dec 2019 18:36:54 -0600 >>> Babu Moger wrote: >>> >>>> This series fixes

Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

On 2/5/20 3:38 AM, Igor Mammedov wrote: > On Tue, 4 Feb 2020 13:08:58 -0600 > Babu Moger wrote: > >> On 2/4/20 2:02 AM, Igor Mammedov wrote: >>> On Mon, 3 Feb 2020 13:31:29 -0600 >>> Babu Moger wrote: >>> >>>> On 2/3/20 8:59 AM, Igo

Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

On 2/5/20 10:56 AM, Igor Mammedov wrote: > On Wed, 5 Feb 2020 10:10:06 -0600 > Babu Moger wrote: > >> On 2/5/20 3:38 AM, Igor Mammedov wrote: >>> On Tue, 4 Feb 2020 13:08:58 -0600 >>> Babu Moger wrote: >>> >>>> On 2/4/20 2:02 AM, Ig

Re: [PATCH] i386: pass CLZERO to guests with EPYC CPU model on AMD ZEN platform

On 2/5/20 11:53 PM, Ani Sinha wrote: > > >> On Feb 6, 2020, at 11:16 AM, Ani Sinha wrote: >> >> >> >>> On Feb 6, 2020, at 5:30 AM, Moger, Babu wrote: >>> >>> Ani, I am already working on it. >> >> Wow, I see a whole new AMD-Rome CPU model with it’s own cache info data : >> >> https://nam11.

Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models

On 2/6/20 7:08 AM, Igor Mammedov wrote: > On Wed, 5 Feb 2020 13:07:31 -0600 > Babu Moger wrote: > >> On 2/5/20 10:56 AM, Igor Mammedov wrote: >>> On Wed, 5 Feb 2020 10:10:06 -0600 >>> Babu Moger wrote: >>> >>>> On 2/5/20 3:38 AM, Ig

Re: [PATCH] i386: pass CLZERO to guests with EPYC CPU model on AMD ZEN platform

On 2/6/20 9:52 AM, Eduardo Habkost wrote: > On Thu, Feb 06, 2020 at 12:00:04AM +, Moger, Babu wrote: >> [AMD Official Use Only - Internal Distribution Only] > > Considering that this was posted to qemu-devel, I'm assuming this > notice was added by accident. Yes. I noticed that after sendi

[PATCH v3 1/7] target/i386: allow versioned CPUs to specify new cache_info

to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 36 +--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --

[PATCH v3 3/7] target/i386: Add a couple of feature bits in 8000_0008_EBX

s on. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://w

[PATCH v3 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. Signed-off-by: Babu Moger --- target/i3

[PATCH v3 2/7] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 118 ++ 1 file changed, 118 insertion

[PATCH v3 5/7] target/i386: Add missing feature bits in EPYC-Milan model

Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store

[PATCH v3 6/7] target/i386: Add VNMI and automatic IBRS feature bits

chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Santosh Shukla Signed-off-by: Kim Phillips Signed-off-by: Babu Moger Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/file

[PATCH v3 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf --- target/i386/cpu.c | 24 target/i386/cpu.h | 8 2 files changed

[PATCH v3 0/7] Add EPYC-Genoa model and update previous EPYC Models

ARS_BASE to NULL_SEL_CLR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com

[PATCH v4 2/7] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 118 ++ 1 file changed, 118 insertion

[PATCH v4 1/7] target/i386: allow versioned CPUs to specify new cache_info

Definition", to allow new cache_info pointers to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 35 ---

[PATCH v4 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. Signed-off-by: Babu Moger --- target/i3

[PATCH v4 0/7] Add EPYC-Genoa model and update previous EPYC Models

LR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com/ v3: https://lore.kernel.

[PATCH v4 6/7] target/i386: Add VNMI and automatic IBRS feature bits

chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Santosh Shukla Signed-off-by: Kim Phillips Signed-off-by: Babu Moger Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/file

[PATCH v4 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf --- target/i386/cpu.c | 24 target/i386/cpu.h | 8 2 files changed

[PATCH v4 5/7] target/i386: Add missing feature bits in EPYC-Milan model

G c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/securit

[PATCH v4 3/7] target/i386: Add a couple of feature bits in 8000_0008_EBX

s on. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://w

Re: [RFC PATCH 1/1] i386: Remove features from Epyc-Milan cpu

6:08 AM Daniel P. Berrangé >>> wrote: >>>> CC'ing Babu Moger who aded the Milan CPU model. >>>> >>>> On Sat, Jan 29, 2022 at 07:23:37AM -0300, Leonardo Bras wrote: >>>>> While trying to bring a VM with EPYC-Milan cpu on a host with >>&g

[PATCH v2 2/4] i386/cpu: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH v2 4/4] i386/cpu: Add support for EPYC-Turin model

avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair of Mask Register avx-vnni : AVX VNNI Instruction Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Fixed minor typo. Added Zhao's Reviewed-by. --- target/i386/cpu.c

[PATCH v2 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

3.41. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Minor typo. Added Reviewed-by from Zhao. --- target/i386/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v2 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models

interrupts. McaOverflowRecov: MCA overflow recovery support. Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Just added reviewed by from Zhao. --- target/i386/cpu.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v2 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

of 6d00c6f98256 ("Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging") v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ -- 2.34.1 Babu Moger (3): i386/cpu: Add RAS feature bits on EPYC CPU models i386/cpu: Enabl

[PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH 4/4] i386/cpu: Add support for EPYC-Turin model

avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair of Mask Register avx-vnni : AVX VNNI Instruction Signed-off-by: Babu Moger --- target/i386/cpu.c | 131 ++ 1 file changed, 131 insertions(+) diff --git a/target

[PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models

interrupts. McaOverflowRecov: MCA overflow recovery support. Signed-off-by: Babu Moger --- target/i386/cpu.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 165b982c8c..86a90b1405 100644 --- a/target/i386/cpu.c +++ b

[PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

3.41. Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- target/i386/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f1837cdc9..64e6dc62e2 100644 --- a/target/i386/cpu.c +++ b/target/i386/

[PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

This series adds the support for following features in qemu. 1. RAS feature bits (SUCCOR, McaOverflowRecov) 2. perfmon-v2 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits 4. Add support for EPYC-Turin Babu Moger (3): i386/cpu: Add RAS feature bits on EPYC CPU models i386/cpu: Enable

[PATCH v2] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Rebased to the latest tree. Updated the pc_compat_8_2 for the new flag. Added the comment for new property legacy_multi_node. Added Rev

[PATCH] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- hw/i386/pc.c | 4 +++- target/i386/cpu.c | 18 ++ target/i386/cpu.h | 1 + 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1

Re: [Qemu-devel] [PATCH] AMD Processor Topology Information

Hi Stanislav, I am working on to support hyperthreading feature on kvm/qemu guests for AMD EPYC family of processors. I saw your patch series https://patchwork.ozlabs.org/patch/834022/. I am planning to refresh these patches with few changes. Let me know if it is fine with you. Thanks Babu

[Qemu-devel] [PATCH 0/5] Enable TOPOEXT to support hyperthreading on AMD CPU

feature on AMD EPYC CPU. Babu Moger (3): target/i386: Fix instruction cache associativity for AMD target/i386: Enable TOPOEXT feature on AMD EPYC CPU target/i386: Remove generic SMT thread check Stanislav Lanci (2): target/i386: Populate AMD Processor Cache Information target/i386: Add

[Qemu-devel] [PATCH 1/5] target/i386: Fix instruction cache associativity for AMD

Per Processor Programming Reference, CPUID_Fn8005_EDX should report L1 instruction cache associativity as 4(way) instead of 2(way). Signed-off-by: Babu Moger --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[Qemu-devel] [PATCH 3/5] target/i386: Add support for CPUID_8000_001E for AMD

From: Stanislav Lanci Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT feature is supported. This is required to support hyperthreading feature on AMD CPUS. These are supported via CPUID_8000_001E extended functions. Signed-off-by: Stanislav Lanci Signed-off-by: Babu Moger

[Qemu-devel] [PATCH 2/5] target/i386: Populate AMD Processor Cache Information

From: Stanislav Lanci Adds information about cache size and topology from cpuid 0x801D leaf for different cache types on AMD processors. Signed-off-by: Stanislav Lanci Signed-off-by: Babu Moger --- target/i386/cpu.c | 76 +++ target

[Qemu-devel] [PATCH 4/5] target/i386: Enable TOPOEXT feature on AMD EPYC CPU

Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. These are supported via CPUID_8000_001E extended functions. Signed-off-by: Babu Moger --- target/i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b

[Qemu-devel] [PATCH 5/5] target/i386: Remove generic SMT thread check

Remove generic non-intel check while validating hyperthreading support. Certain AMD CPUs can support hyperthreading now. CPU family with TOPOEXT feature can support hyperthreading now. Signed-off-by: Babu Moger --- target/i386/cpu.c | 13 - 1 file changed, 8 insertions(+), 5

[Qemu-devel] [Bug 1703506] Re: SMT not supported by QEMU on AMD Ryzen CPU

Posted few patches to support this feature on AMD EPYC processors. Feel free to test and review. 1. Kernel kvm patch https://patchwork.kernel.org/patch/10190107/ 2. qemu patches https://patchwork.kernel.org/project/qemu-devel/list/?submitter=178527 Thanks -- You received this bug notificat

[Qemu-devel] [Bug 1703506] Re: SMT not supported by QEMU on AMD Ryzen CPU

just to be clear.. The kernel kvm patch is rebased on linux-next. If you are on older kernel then try this kernel patch. https://patchwork.kernel.org/patch/10031775/ plus qemu patch. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. ht

[Qemu-devel] [PATCH v9 2/7] i386: Add new property to control cache info

ious cache structures to legacy_*. If there is any change in the cache information, then it needs to be initialized in builtin_x86_defs. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- include/hw/i386/pc.h | 5 +++ target/i386/cpu.c| 97 target/

[Qemu-devel] [PATCH v9 1/7] pc: add 2.13 machine types

Add pc-q35-2.13 and pc-i440fx-2.13 machine types Signed-off-by: Babu Moger --- hw/i386/pc_piix.c| 15 --- hw/i386/pc_q35.c | 13 +++-- include/hw/i386/pc.h | 3 +++ 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c

[Qemu-devel] [PATCH v9 5/7] i386: Add support for CPUID_8000_001E for AMD

Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT feature is supported. This is required to support hyperthreading feature on AMD CPUs. This is supported via CPUID_8000_001E extended functions. Signed-off-by: Babu Moger Tested-by: Geoffrey McRae --- include/hw/i386/topology.h

[Qemu-devel] [PATCH v9 0/7] i386: Enable TOPOEXT to support hyperthreading on AMD CPU

2 more patches. Patch 1. Fixes cache associativity. Patch 4. Adds TOPOEXT feature on AMD EPYC CPU. Babu Moger (6): pc: add 2.13 machine types i386: Add new property to control cache info i386: Populate AMD Processor Cache Information for cpuid 0x801D i386: Add support for CPUID_8000_0

  1   2   3   4   >