Re: vr(4) baby jumbos

2013-02-09 Thread Mike Belopuhov
On 9 February 2013 16:27, Stuart Henderson wrote: > So I think the vr(4) diff has had a reasonable amount of testing; > any objections or ideally OKs to commit it? > OK > I have also tested sis(4) on a PC Engines WRAP now; despite the > DP83815 datasheet indicating that "Accept Long Packets" > (

Re: vr(4) baby jumbos

2013-02-09 Thread Stuart Henderson
So I think the vr(4) diff has had a reasonable amount of testing; any objections or ideally OKs to commit it? I have also tested sis(4) on a PC Engines WRAP now; despite the DP83815 datasheet indicating that "Accept Long Packets" (SIS_RXCFG_RX_JABBER) should permit frames up to 2046 it seems somet

Re: vr(4) baby jumbos

2013-02-07 Thread Stuart Henderson
On 2013/02/07 20:18, Christopher Zimmermann wrote: > On Thu, 7 Feb 2013 17:41:12 + > Stuart Henderson wrote: > > > This is extremely useful as it permits carrying stacked vlans > > on Alix/net5501, and also permits carrying 1500 MTU packets within > > pppoe(4) using the RFC4638 support. > >

Re: vr(4) baby jumbos

2013-02-07 Thread Bob Beck
Appears not to break my alix... On Thu, Feb 7, 2013 at 10:41 AM, Stuart Henderson wrote: > At least the following vr(4) devices can be configured to permit > larger MTUs. > > vr0 at pci0 dev 18 function 0 "VIA RhineII-2" rev 0x51: irq 11, address > 00:40:63:c0:5d:27 > vr1 at pci2 dev 0 function

Re: vr(4) baby jumbos

2013-02-07 Thread Christopher Zimmermann
On Thu, 7 Feb 2013 17:41:12 + Stuart Henderson wrote: > This is extremely useful as it permits carrying stacked vlans > on Alix/net5501, and also permits carrying 1500 MTU packets within > pppoe(4) using the RFC4638 support. So with 5.3 I can drop the max-mss 1452 on my alix router? Great!!!

Re: vr(4) baby jumbos

2013-02-07 Thread Mike Belopuhov
On Thu, Feb 07, 2013 at 17:41 +, Stuart Henderson wrote: > At least the following vr(4) devices can be configured to permit > larger MTUs. > > vr0 at pci0 dev 18 function 0 "VIA RhineII-2" rev 0x51: irq 11, address > 00:40:63:c0:5d:27 > vr1 at pci2 dev 0 function 0 "VIA VT6105M RhineIII" rev