[llvm] [flang] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote: Ping? https://github.com/llvm/llvm-project/pull/68882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
dtcxzyw wrote:
Looks like it is the string length of `__riscv_`.
https://github.com/llvm/llvm-project/pull/77487
___
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[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)
@@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s dtcxzyw wrote: Can we split `rv32a-invalid.s` into two files? I think it is better than duplicating tests for new extensions. https://github.com/llvm/llvm-project/pull/77424 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Revert "InstCombine: Fold is.fpclass(x, fcInf) to fabs+fcmp" (PR #76338)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] static operators should evaluate object argument (PR #68485)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/68485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lld] [clang] [llvm] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > Can you please fix or revert > https://lab.llvm.org/buildbot/#/builders/74/builds/24592 ? Should be fixed by https://github.com/llvm/llvm-project/commit/7e405eb722e40c79b7726201d0f76b5dab34ba0f. https://lab.llvm.org/buildbot/#/builders/74/builds/24613 https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lld] [llvm] [clang] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > > Yeah, we should skip this inference for functions with the sanitize_memory > > attribute. > > I will post a patch later. Candidate patch: https://github.com/llvm/llvm-project/pull/76691 https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [lld] [clang] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > Yeah, we should skip this inference for functions with the sanitize_memory > attribute. I will post a patch later. https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > Can you please fix or revert > https://lab.llvm.org/buildbot/#/builders/74/builds/24592 ? Thank you for reporting this! I will check the error log. https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw edited https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
llvm/test/Transforms/FunctionAttrs/noundef.ll | 145 ++
1 file changed, 145 insertions(+)
create mode 100644 llvm/test/Transforms/FunctionAttrs/noundef.ll
diff --git a/llvm/test/Transforms/FunctionAttrs/noundef.ll
b/llvm/test/Transforms/FunctionAttrs/noundef.ll
new file mode 100644
index 00..9eca495e111e8f
--- /dev/null
+++ b/llvm/test/Transforms/FunctionAttrs/noundef.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt < %s -passes='function-attrs' -S | FileCheck %s
+
+define i32 @test_ret_constant() {
+; CHECK-LABEL: define i32 @test_ret_constant(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:ret i32 0
+;
+ ret i32 0
+}
+
+define i32 @test_ret_poison() {
+; CHECK-LABEL: define i32 @test_ret_poison(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 poison
+;
+ ret i32 poison
+}
+
+define i32 @test_ret_undef() {
+; CHECK-LABEL: define i32 @test_ret_undef(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 undef
+;
+ ret i32 undef
+}
+
+define i32 @test_ret_param(i32 %x) {
+; CHECK-LABEL: define i32 @test_ret_param(
+; CHECK-SAME: i32 returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_param(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_param(
+; CHECK-SAME: i32 noundef returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_create_poison_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_create_poison_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add nsw i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_freezed(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_freezed(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:[[Z:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT:ret i32 [[Z]]
+;
+ %y = add nsw i32 %x, 1
+ %z = freeze i32 %y
+ ret i32 %z
+}
+
+define i32 @test_ret_control_flow(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_ret_control_flow_may_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_may_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+; TODO: use context-sensitive analysis
+define i32 @test_ret_control_flow_never_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_never_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 2147483647
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 2147483647
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_noundef_prop() {
+; CHECK-LABEL: define i32 @test_noundef_prop(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:[[RET:%.*]] = call i32 @test_ret_constant()
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %ret = call i32 @test_ret_constant()
+ ret i32 %ret
+}
>From c5e8738d4bfbf1e97e3f455fded90b791f223d74 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
[lld] [clang] [llvm] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > Failed Tests (3): LLVM :: CodeGen/BPF/loop-exit-cond.ll LLVM :: CodeGen/NVPTX/nvvm-reflect-opaque.ll LLVM :: CodeGen/NVPTX/nvvm-reflect.ll https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
dtcxzyw wrote: > There are lld test failures. Done. https://github.com/llvm/llvm-project/pull/76553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
llvm/test/Transforms/FunctionAttrs/noundef.ll | 145 ++
1 file changed, 145 insertions(+)
create mode 100644 llvm/test/Transforms/FunctionAttrs/noundef.ll
diff --git a/llvm/test/Transforms/FunctionAttrs/noundef.ll
b/llvm/test/Transforms/FunctionAttrs/noundef.ll
new file mode 100644
index 00..9eca495e111e8f
--- /dev/null
+++ b/llvm/test/Transforms/FunctionAttrs/noundef.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt < %s -passes='function-attrs' -S | FileCheck %s
+
+define i32 @test_ret_constant() {
+; CHECK-LABEL: define i32 @test_ret_constant(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:ret i32 0
+;
+ ret i32 0
+}
+
+define i32 @test_ret_poison() {
+; CHECK-LABEL: define i32 @test_ret_poison(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 poison
+;
+ ret i32 poison
+}
+
+define i32 @test_ret_undef() {
+; CHECK-LABEL: define i32 @test_ret_undef(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 undef
+;
+ ret i32 undef
+}
+
+define i32 @test_ret_param(i32 %x) {
+; CHECK-LABEL: define i32 @test_ret_param(
+; CHECK-SAME: i32 returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_param(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_param(
+; CHECK-SAME: i32 noundef returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_create_poison_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_create_poison_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add nsw i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_freezed(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_freezed(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:[[Z:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT:ret i32 [[Z]]
+;
+ %y = add nsw i32 %x, 1
+ %z = freeze i32 %y
+ ret i32 %z
+}
+
+define i32 @test_ret_control_flow(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_ret_control_flow_may_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_may_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+; TODO: use context-sensitive analysis
+define i32 @test_ret_control_flow_never_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_never_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 2147483647
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 2147483647
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_noundef_prop() {
+; CHECK-LABEL: define i32 @test_noundef_prop(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:[[RET:%.*]] = call i32 @test_ret_constant()
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %ret = call i32 @test_ret_constant()
+ ret i32 %ret
+}
>From fe11127cd7e9ed4669243502eda5991504b9809a Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
[llvm] [clang] [lld] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76553
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22 +0800
Subject: [PATCH 1/2] [FuncAttrs] Add pre-commit tests. NFC.
---
llvm/test/Transforms/FunctionAttrs/noundef.ll | 145 ++
1 file changed, 145 insertions(+)
create mode 100644 llvm/test/Transforms/FunctionAttrs/noundef.ll
diff --git a/llvm/test/Transforms/FunctionAttrs/noundef.ll
b/llvm/test/Transforms/FunctionAttrs/noundef.ll
new file mode 100644
index 00..9eca495e111e8f
--- /dev/null
+++ b/llvm/test/Transforms/FunctionAttrs/noundef.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 4
+; RUN: opt < %s -passes='function-attrs' -S | FileCheck %s
+
+define i32 @test_ret_constant() {
+; CHECK-LABEL: define i32 @test_ret_constant(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:ret i32 0
+;
+ ret i32 0
+}
+
+define i32 @test_ret_poison() {
+; CHECK-LABEL: define i32 @test_ret_poison(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 poison
+;
+ ret i32 poison
+}
+
+define i32 @test_ret_undef() {
+; CHECK-LABEL: define i32 @test_ret_undef(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 undef
+;
+ ret i32 undef
+}
+
+define i32 @test_ret_param(i32 %x) {
+; CHECK-LABEL: define i32 @test_ret_param(
+; CHECK-SAME: i32 returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_param(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_param(
+; CHECK-SAME: i32 noundef returned [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:ret i32 [[X]]
+;
+ ret i32 %x
+}
+
+define i32 @test_ret_noundef_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_noundef_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_create_poison_expr(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_create_poison_expr(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[Y]]
+;
+ %y = add nsw i32 %x, 1
+ ret i32 %y
+}
+
+define i32 @test_ret_freezed(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_freezed(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[Y:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:[[Z:%.*]] = freeze i32 [[Y]]
+; CHECK-NEXT:ret i32 [[Z]]
+;
+ %y = add nsw i32 %x, 1
+ %z = freeze i32 %y
+ ret i32 %z
+}
+
+define i32 @test_ret_control_flow(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_ret_control_flow_may_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_may_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 0
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+; TODO: use context-sensitive analysis
+define i32 @test_ret_control_flow_never_poison(i32 noundef %x) {
+; CHECK-LABEL: define i32 @test_ret_control_flow_never_poison(
+; CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:[[COND:%.*]] = icmp eq i32 [[X]], 2147483647
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:ret i32 2
+; CHECK: if.else:
+; CHECK-NEXT:[[RET:%.*]] = add nsw i32 [[X]], 1
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %cond = icmp eq i32 %x, 2147483647
+ br i1 %cond, label %if.then, label %if.else
+if.then:
+ ret i32 2
+if.else:
+ %ret = add nsw i32 %x, 1
+ ret i32 %ret
+}
+
+define i32 @test_noundef_prop() {
+; CHECK-LABEL: define i32 @test_noundef_prop(
+; CHECK-SAME: ) #[[ATTR0]] {
+; CHECK-NEXT:[[RET:%.*]] = call i32 @test_ret_constant()
+; CHECK-NEXT:ret i32 [[RET]]
+;
+ %ret = call i32 @test_ret_constant()
+ ret i32 %ret
+}
>From 46188dfe1a8069c94fc4628660889e070e6a82cb Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
[clang] [llvm] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -0,0 +1,112 @@ +// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s +// RVI20U32: "-target-cpu" "generic-rv32" +// RVI20U32: "-target-feature" "-a" +// RVI20U32: "-target-feature" "-c" +// RVI20U32: "-target-feature" "-d" +// RVI20U32: "-target-feature" "-f" +// RVI20U32: "-target-feature" "-m" +// RVI20U32: "-target-feature" "+rvi20u32" +// RVI20U32: "-target-abi" "ilp32" + +// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s +// RVI20U64: "-target-cpu" "generic-rv64" +// RVI20U64: "-target-feature" "-a" +// RVI20U64: "-target-feature" "-c" +// RVI20U64: "-target-feature" "-d" +// RVI20U64: "-target-feature" "-f" +// RVI20U64: "-target-feature" "-m" +// RVI20U64: "-target-feature" "+rvi20u64" +// RVI20U64: "-target-abi" "lp64" + +// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s +// RVA20U64: "-target-cpu" "generic-rv64" +// RVA20U64: "-target-feature" "+m" +// RVA20U64: "-target-feature" "+a" +// RVA20U64: "-target-feature" "+f" +// RVA20U64: "-target-feature" "+d" +// RVA20U64: "-target-feature" "+c" +// RVA20U64: "-target-feature" "+zicsr" +// RVA20U64: "-target-feature" "+rva20u64" +// RVA20U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s +// RVA20S64: "-target-cpu" "generic-rv64" +// RVA20S64: "-target-feature" "+m" +// RVA20S64: "-target-feature" "+a" +// RVA20S64: "-target-feature" "+f" +// RVA20S64: "-target-feature" "+d" +// RVA20S64: "-target-feature" "+c" +// RVA20S64: "-target-feature" "+zicsr" +// RVA20S64: "-target-feature" "+zifencei" +// RVA20S64: "-target-feature" "+rva20s64" +// RVA20S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s +// RVA22U64: "-target-cpu" "generic-rv64" +// RVA22U64: "-target-feature" "+m" +// RVA22U64: "-target-feature" "+a" +// RVA22U64: "-target-feature" "+f" +// RVA22U64: "-target-feature" "+d" +// RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+zicbom" +// RVA22U64: "-target-feature" "+zicbop" +// RVA22U64: "-target-feature" "+zicboz" +// RVA22U64: "-target-feature" "+zicsr" +// RVA22U64: "-target-feature" "+zihintpause" +// RVA22U64: "-target-feature" "+zfhmin" +// RVA22U64: "-target-feature" "+zba" +// RVA22U64: "-target-feature" "+zbb" +// RVA22U64: "-target-feature" "+zbs" +// RVA22U64: "-target-feature" "+zkt" +// RVA22U64: "-target-feature" "+rva22u64" +// RVA22U64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s +// RVA22S64: "-target-cpu" "generic-rv64" +// RVA22S64: "-target-feature" "+m" +// RVA22S64: "-target-feature" "+a" +// RVA22S64: "-target-feature" "+f" +// RVA22S64: "-target-feature" "+d" +// RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+zicbom" +// RVA22S64: "-target-feature" "+zicbop" +// RVA22S64: "-target-feature" "+zicboz" +// RVA22S64: "-target-feature" "+zicsr" +// RVA22S64: "-target-feature" "+zifencei" +// RVA22S64: "-target-feature" "+zihintpause" +// RVA22S64: "-target-feature" "+zfhmin" +// RVA22S64: "-target-feature" "+zba" +// RVA22S64: "-target-feature" "+zbb" +// RVA22S64: "-target-feature" "+zbs" +// RVA22S64: "-target-feature" "+zkt" +// RVA22S64: "-target-feature" "+svinval" +// RVA22S64: "-target-feature" "+svpbmt" +// RVA22S64: "-target-feature" "+rva22s64" +// RVA22S64: "-target-abi" "lp64d" + +// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s dtcxzyw wrote: ```suggestion // RUN: %clang -### -c %s 2>&1 -march=RVA22U64+zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s ``` > profiles format has the following BNF form > `"-march=""+"[option-ext]*`. https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RFC][RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -206,6 +210,17 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
};
+static const RISCVProfile SupportedProfiles[] = {
+{"rvi20u32", "rv32i"},
dtcxzyw wrote:
Profile names should use uppercase letters.
> e.g. `-march=RVA20U64` is a legal profile input, it will be expanded into:
`-march=rv64imafdc_zicsr_ziccif_ziccrse_ziccamoa_zicclsm_za128rs`,
which include all the mandatory extensions required by this profile.
`-march=RVA20U64+zba_zbb_zbc_zbs` is also a legal profile input, it will add
four new extensions after expanded profile strings:
`-march=rv64imafdc_zicsr_ziccif_ziccrse_ziccamoa_zicclsm_za128rs_zba_zbb_zbc_zbs`
and `-march=rva20u64` is an illegal profile input, it does not use uppercase
letters.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [FuncAttrs] Deduce `noundef` attributes for return values (PR #76553)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76553
This patch deduces `noundef` attributes for return values.
IIUC, a function returns `noundef` values iff all of its return values are
guaranteed not to be `undef` or `poison`.
Definition of `noundef` from LangRef:
```
noundef
This attribute applies to parameters and return values. If the value
representation contains any
undefined or poison bits, the behavior is undefined. Note that this does not
refer to padding
introduced by the type’s storage representation.
```
Alive2: https://alive2.llvm.org/ce/z/g8Eis6
Compile-time impact:
http://llvm-compile-time-tracker.com/compare.php?from=7f69c8b3a6c02ea32fefb16c2016dfa1ba994858=1dafc281ff8c04bb0a968fb3d898f08876dc59e0=instructions:u
|stage1-O3|stage1-ReleaseThinLTO|stage1-ReleaseLTO-g|stage1-O0-g|stage2-O3|stage2-O0-g|stage2-clang|
|--|--|--|--|--|--|--|
|+0.01%|+0.01%|-0.01%|+0.00%|+0.03%|+0.02%|+0.01%|
The motivation of this patch is to reduce the number of `freeze` insts and
enable more optimizations.
Example:
```
diff --git a/bench/flac/optimized/replaygain.c.ll
b/bench/flac/optimized/replaygain.c.ll
index fa826475..413bd717 100644
--- a/bench/flac/optimized/replaygain.c.ll
+++ b/bench/flac/optimized/replaygain.c.ll
@@ -63,7 +63,7 @@ entry:
declare i32 @InitGainAnalysis(i64 noundef) local_unnamed_addr #1
; Function Attrs: nounwind sspstrong uwtable
-define dso_local i32 @grabbag__replaygain_analyze(ptr nocapture noundef
readonly %input, i32 noundef %is_stereo, i32 noundef %bps, i32 noundef
%samples) local_unnamed_addr #0 {
+define dso_local noundef i32 @grabbag__replaygain_analyze(ptr nocapture
noundef readonly %input, i32 noundef %is_stereo, i32 noundef %bps, i32 noundef
%samples) local_unnamed_addr #0 {
entry:
%cmp = icmp eq i32 %bps, 16
br i1 %cmp, label %if.then, label %if.else71
@@ -337,7 +337,7 @@ entry:
declare float @GetTitleGain() local_unnamed_addr #1
; Function Attrs: nounwind sspstrong uwtable
-define dso_local ptr @grabbag__replaygain_analyze_file(ptr noundef %filename,
ptr nocapture noundef writeonly %title_gain, ptr nocapture noundef writeonly
%title_peak) local_unnamed_addr #0 {
+define dso_local noundef ptr @grabbag__replaygain_analyze_file(ptr noundef
%filename, ptr nocapture noundef writeonly %title_gain, ptr nocapture noundef
writeonly %title_peak) local_unnamed_addr #0 {
entry:
%instance = alloca %struct.DecoderInstance, align 4
%call = tail call ptr @FLAC__stream_decoder_new() #15
@@ -392,7 +392,7 @@ declare i32 @FLAC__stream_decoder_set_metadata_respond(ptr
noundef, i32 noundef)
declare i32 @FLAC__stream_decoder_init_file(ptr noundef, ptr noundef, ptr
noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #1
; Function Attrs: nounwind sspstrong uwtable
-define internal i32 @write_callback_(ptr nocapture readnone %decoder, ptr
nocapture noundef readonly %frame, ptr nocapture noundef readonly %buffer, ptr
nocapture noundef %client_data) #0 {
+define internal noundef i32 @write_callback_(ptr nocapture readnone %decoder,
ptr nocapture noundef readonly %frame, ptr nocapture noundef readonly %buffer,
ptr nocapture noundef %client_data) #0 {
entry:
%bits_per_sample1 = getelementptr inbounds %struct.FLAC__FrameHeader, ptr
%frame, i64 0, i32 4
%0 = load i32, ptr %bits_per_sample1, align 8
@@ -429,23 +429,16 @@ land.lhs.true14: ; preds
= %land.lhs.true11
%cmp16 = icmp eq i32 %2, %8
br i1 %cmp16, label %if.end, label %if.end.thread
-if.end.thread:; preds = %land.lhs.true,
%land.lhs.true14, %land.lhs.true11, %land.lhs.true8, %entry
- store i32 1, ptr %error, align 4
- br label %9
-
if.end: ; preds = %land.lhs.true14
%conv = zext i1 %cmp to i32
%call = tail call i32 @grabbag__replaygain_analyze(ptr noundef %buffer, i32
noundef %conv, i32 noundef %0, i32 noundef %3), !range !14
- %call.fr = freeze i32 %call
- %lnot.ext = xor i32 %call.fr, 1
- store i32 %lnot.ext, ptr %error, align 4
- %tobool22.not = icmp ne i32 %lnot.ext, 0
- %spec.select = zext i1 %tobool22.not to i32
- br label %9
-
-9:; preds = %if.end,
%if.end.thread
- %10 = phi i32 [ 1, %if.end.thread ], [ %spec.select, %if.end ]
- ret i32 %10
+ %lnot.ext = xor i32 %call, 1
+ br label %if.end.thread
+
+if.end.thread:; preds = %entry,
%land.lhs.true8, %land.lhs.true11, %land.lhs.true14, %land.lhs.true, %if.end
+ %storemerge = phi i32 [ %lnot.ext, %if.end ], [ 1, %land.lhs.true ], [ 1,
%land.lhs.true14 ], [ 1, %land.lhs.true11 ], [ 1, %land.lhs.true8 ], [ 1,
%entry ]
+ store i32 %storemerge, ptr %error, align 4
+ ret i32 %storemerge
}
; Function Attrs: nounwind sspstrong uwtable
```
>From 30dcc33c4ea3ab50397a7adbe85fe977d4a400bd Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 29 Dec 2023 14:27:22
[clang] [llvm] [FuncAttrs] Infer `norecurse` for funcs with calls to `nocallback` callees (PR #76372)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76372 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [FuncAttrs] Infer `norecurse` for funcs with calls to `nocallback` callees (PR #76372)
dtcxzyw wrote: > There is a failing clang test. Fixed. https://github.com/llvm/llvm-project/pull/76372 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [FuncAttrs] Infer `norecurse` for funcs with calls to `nocallback` callees (PR #76372)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76372
>From 5ceb22715cdcfc52b77b451110295ea083c09327 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 26 Dec 2023 05:10:06 +0800
Subject: [PATCH] [FuncAttrs] Infer `norecurse` for funcs with calls to
`nocallback` callees
---
.../RISCV/rvv-intrinsics-handcrafted/vlenb.c | 24 +--
llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 5 +++-
.../TypeBasedAliasAnalysis/functionattrs.ll | 12 --
.../Transforms/FunctionAttrs/argmemonly.ll| 6 ++---
.../Transforms/FunctionAttrs/convergent.ll| 2 +-
.../FunctionAttrs/int_sideeffect.ll | 4 ++--
.../FunctionAttrs/make-buffer-rsrc.ll | 2 +-
.../Transforms/FunctionAttrs/nocapture.ll | 16 ++---
.../FunctionAttrs/nofree-attributor.ll| 4 ++--
.../Transforms/FunctionAttrs/norecurse.ll | 17 ++---
llvm/test/Transforms/FunctionAttrs/nosync.ll | 6 ++---
.../Transforms/FunctionAttrs/readattrs.ll | 4 ++--
.../Transforms/FunctionAttrs/writeonly.ll | 18 +++---
13 files changed, 61 insertions(+), 59 deletions(-)
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
index 9d95acc33dddcd..582d5fd812bc34 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
@@ -21,19 +21,19 @@ unsigned long test_vlenb(void) {
return __riscv_vlenb();
}
//.
-// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
-// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind
willreturn memory(read) }
+// RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
+// RV32: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree
nosync nounwind willreturn memory(read) }
//.
-// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind
willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
-// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind
willreturn memory(read) }
+// RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
+// RV64: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree
nosync nounwind willreturn memory(read) }
//.
-// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
-// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
-// RV32: !2 = !{i32 8, !"SmallDataLimit", i32 0}
-// RV32: !3 = !{!"vlenb"}
+// RV32: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// RV32: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: [[META2:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
+// RV32: [[META3]] = !{!"vlenb"}
//.
-// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
-// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
-// RV64: !2 = !{i32 8, !"SmallDataLimit", i32 0}
-// RV64: !3 = !{!"vlenb"}
+// RV64: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// RV64: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: [[META2:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
+// RV64: [[META3]] = !{!"vlenb"}
//.
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 7c277518b21dbf..9ce9f8451a95fa 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -1629,7 +1629,10 @@ static void addNoRecurseAttrs(const SCCNodeSet ,
for (auto : BB.instructionsWithoutDebug())
if (auto *CB = dyn_cast()) {
Function *Callee = CB->getCalledFunction();
-if (!Callee || Callee == F || !Callee->doesNotRecurse())
+if (!Callee || Callee == F ||
+(!Callee->doesNotRecurse() &&
+ !(Callee->isDeclaration() &&
+ Callee->hasFnAttribute(Attribute::NoCallback
// Function calls a potentially recursive function.
return;
}
diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
b/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
index 86e7f8c113d1d8..bea56a72bdeaef
[llvm] [clang] Revert "InstCombine: Fold is.fpclass(x, fcInf) to fabs+fcmp" (PR #76338)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/76338
>From a646e872e72bab7b143db7496adfeb633b882dc4 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 25 Dec 2023 01:39:27 +0800
Subject: [PATCH] Revert "InstCombine: Fold is.fpclass(x, fcInf) to fabs+fcmp"
This reverts commit 2b582440c16c72b6b021ea5c212ceda3bdfb2b9b.
---
clang/test/CodeGen/isfpclass.c| 23 -
clang/test/Headers/__clang_hip_math.hip | 40 ++-
.../InstCombine/InstCombineCalls.cpp | 18 ---
llvm/test/Transforms/InstCombine/and-fcmp.ll | 9 ++--
.../combine-is.fpclass-and-fcmp.ll| 26 --
.../create-class-from-logic-fcmp.ll | 30 ---
.../test/Transforms/InstCombine/is_fpclass.ll | 51 ---
7 files changed, 72 insertions(+), 125 deletions(-)
diff --git a/clang/test/CodeGen/isfpclass.c b/clang/test/CodeGen/isfpclass.c
index 34873c08e04f87..08c2633266dbd5 100644
--- a/clang/test/CodeGen/isfpclass.c
+++ b/clang/test/CodeGen/isfpclass.c
@@ -4,9 +4,8 @@
// CHECK-LABEL: define dso_local i1 @check_isfpclass_finite
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
-// CHECK-NEXT:[[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0
-// CHECK-NEXT:ret i1 [[TMP1]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 504)
+// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isfpclass_finite(float x) {
return __builtin_isfpclass(x, 504 /*Finite*/);
@@ -15,7 +14,7 @@ _Bool check_isfpclass_finite(float x) {
// CHECK-LABEL: define dso_local i1 @check_isfpclass_finite_strict
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 504) #[[ATTR6:[0-9]+]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 504) #[[ATTR5:[0-9]+]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isfpclass_finite_strict(float x) {
@@ -36,7 +35,7 @@ _Bool check_isfpclass_nan_f32(float x) {
// CHECK-LABEL: define dso_local i1 @check_isfpclass_nan_f32_strict
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 3) #[[ATTR6]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 3) #[[ATTR5]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isfpclass_nan_f32_strict(float x) {
@@ -57,7 +56,7 @@ _Bool check_isfpclass_snan_f64(double x) {
// CHECK-LABEL: define dso_local i1 @check_isfpclass_snan_f64_strict
// CHECK-SAME: (double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double
[[X]], i32 1) #[[ATTR6]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double
[[X]], i32 1) #[[ATTR5]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isfpclass_snan_f64_strict(double x) {
@@ -78,7 +77,7 @@ _Bool check_isfpclass_zero_f16(_Float16 x) {
// CHECK-LABEL: define dso_local i1 @check_isfpclass_zero_f16_strict
// CHECK-SAME: (half noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f16(half [[X]],
i32 96) #[[ATTR6]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f16(half [[X]],
i32 96) #[[ATTR5]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isfpclass_zero_f16_strict(_Float16 x) {
@@ -89,7 +88,7 @@ _Bool check_isfpclass_zero_f16_strict(_Float16 x) {
// CHECK-LABEL: define dso_local i1 @check_isnan
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 3) #[[ATTR6]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 3) #[[ATTR5]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isnan(float x) {
@@ -100,7 +99,7 @@ _Bool check_isnan(float x) {
// CHECK-LABEL: define dso_local i1 @check_isinf
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 516) #[[ATTR6]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 516) #[[ATTR5]]
// CHECK-NEXT:ret i1 [[TMP0]]
//
_Bool check_isinf(float x) {
@@ -111,7 +110,7 @@ _Bool check_isinf(float x) {
// CHECK-LABEL: define dso_local i1 @check_isfinite
// CHECK-SAME: (float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float
[[X]], i32 504)
[clang] [Clang][RISCV] Add missing support for `__riscv_clmulr_32/64` in `riscv_bitmanip.h` (PR #76289)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76289 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Use `__builtin_popcount` in `__riscv_cpop_32/64` (PR #76286)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76286 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add missing support for `__builtin_riscv_cpop_32/64` (PR #76256)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/76256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add missing support for `__riscv_clmulr_32/64` in `riscv_bitmanip.h` (PR #76289)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76289
This patch adds support for `__riscv_clmulr_32/64` in `riscv_bitmanip.h`.
It also fixes the extension requirements of `clmul/clmulh`.
Thank @Liaoshihua for reporting this!
>From bad9203e4416f02eb03475b8874db7a999d83657 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 23 Dec 2023 22:26:29 +0800
Subject: [PATCH 1/2] [Clang][RISCV] Add missing support for
`__riscv_clmulr_32/64` in `riscv_bitmanip.h`
---
clang/lib/Headers/riscv_bitmanip.h | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Headers/riscv_bitmanip.h
b/clang/lib/Headers/riscv_bitmanip.h
index 1a81cc8618c975..ee388de735f770 100644
--- a/clang/lib/Headers/riscv_bitmanip.h
+++ b/clang/lib/Headers/riscv_bitmanip.h
@@ -120,7 +120,23 @@ __riscv_zip_32(uint32_t __x) {
#endif
#endif // defined(__riscv_zbkb)
-#if defined(__riscv_zbkc)
+#if defined(__riscv_zbc)
+#if __riscv_xlen == 32
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+__riscv_clmulr_32(uint32_t __x, uint32_t __y) {
+ return __builtin_riscv_clmulr_32(__x, __y);
+}
+#endif
+
+#if __riscv_xlen == 64
+static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
+__riscv_clmulr_64(uint64_t __x, uint64_t __y) {
+ return __builtin_riscv_clmulr_64(__x, __y);
+}
+#endif
+#endif // defined(__riscv_zbc)
+
+#if defined(__riscv_zbkc) || defined(__riscv_zbc)
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__riscv_clmul_32(uint32_t __x, uint32_t __y) {
return __builtin_riscv_clmul_32(__x, __y);
@@ -144,7 +160,7 @@ __riscv_clmulh_64(uint64_t __x, uint64_t __y) {
return __builtin_riscv_clmulh_64(__x, __y);
}
#endif
-#endif // defined(__riscv_zbkc)
+#endif // defined(__riscv_zbkc) || defined(__riscv_zbc)
#if defined(__riscv_zbkx)
#if __riscv_xlen == 32
>From dee8cafe3c364c55dbf6bd6ce07cb65ea5522d93 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 23 Dec 2023 22:27:31 +0800
Subject: [PATCH 2/2] [Clang][RISCV] Use riscv_bitmanip.h in zbc.c. NFC.
---
clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
index ae9153eff155e1..93db3a482ef2bc 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
@@ -6,7 +6,7 @@
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN: | FileCheck %s -check-prefix=RV64ZBC
-#include
+#include
#if __riscv_xlen == 64
// RV64ZBC-LABEL: @clmul_64(
@@ -15,7 +15,7 @@
// RV64ZBC-NEXT:ret i64 [[TMP0]]
//
uint64_t clmul_64(uint64_t a, uint64_t b) {
- return __builtin_riscv_clmul_64(a, b);
+ return __riscv_clmul_64(a, b);
}
// RV64ZBC-LABEL: @clmulh_64(
@@ -24,7 +24,7 @@ uint64_t clmul_64(uint64_t a, uint64_t b) {
// RV64ZBC-NEXT:ret i64 [[TMP0]]
//
uint64_t clmulh_64(uint64_t a, uint64_t b) {
- return __builtin_riscv_clmulh_64(a, b);
+ return __riscv_clmulh_64(a, b);
}
// RV64ZBC-LABEL: @clmulr_64(
@@ -33,7 +33,7 @@ uint64_t clmulh_64(uint64_t a, uint64_t b) {
// RV64ZBC-NEXT:ret i64 [[TMP0]]
//
uint64_t clmulr_64(uint64_t a, uint64_t b) {
- return __builtin_riscv_clmulr_64(a, b);
+ return __riscv_clmulr_64(a, b);
}
#endif
@@ -48,7 +48,7 @@ uint64_t clmulr_64(uint64_t a, uint64_t b) {
// RV64ZBC-NEXT:ret i32 [[TMP0]]
//
uint32_t clmul_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmul_32(a, b);
+ return __riscv_clmul_32(a, b);
}
#if __riscv_xlen == 32
@@ -58,7 +58,7 @@ uint32_t clmul_32(uint32_t a, uint32_t b) {
// RV32ZBC-NEXT:ret i32 [[TMP0]]
//
uint32_t clmulh_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmulh_32(a, b);
+ return __riscv_clmulh_32(a, b);
}
// RV32ZBC-LABEL: @clmulr_32(
@@ -67,6 +67,6 @@ uint32_t clmulh_32(uint32_t a, uint32_t b) {
// RV32ZBC-NEXT:ret i32 [[TMP0]]
//
uint32_t clmulr_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmulr_32(a, b);
+ return __riscv_clmulr_32(a, b);
}
#endif
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[clang] [Clang][RISCV] Use `__builtin_popcount` in `__riscv_cpop_32/64` (PR #76286)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76286
This patch replaces `__builtin_riscv_cpop_32/64` with `__builtin_popcount(ll)`
because `__builtin_riscv_cpop_32/64` is not implemented in clang.
Thank @Liaoshihua for reporting this!
It is an alternative to #76256.
>From b9c654fcc9b25fdfbd1a323f4c3820a367378e19 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 23 Dec 2023 21:56:09 +0800
Subject: [PATCH] [Clang][RISCV] Use `__builtin_popcount` in
`__riscv_cpop_32/64`
---
clang/lib/Headers/riscv_bitmanip.h| 4 +--
clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c | 34 ---
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Headers/riscv_bitmanip.h
b/clang/lib/Headers/riscv_bitmanip.h
index 1a81cc8618c975..044cbaa037e43a 100644
--- a/clang/lib/Headers/riscv_bitmanip.h
+++ b/clang/lib/Headers/riscv_bitmanip.h
@@ -34,7 +34,7 @@ __riscv_ctz_32(uint32_t __x) {
static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
__riscv_cpop_32(uint32_t __x) {
- return __builtin_riscv_cpop_32(__x);
+ return __builtin_popcount(__x);
}
#if __riscv_xlen == 64
@@ -55,7 +55,7 @@ __riscv_ctz_64(uint64_t __x) {
static __inline__ unsigned __attribute__((__always_inline__, __nodebug__))
__riscv_cpop_64(uint64_t __x) {
- return __builtin_riscv_cpop_64(__x);
+ return __builtin_popcountll(__x);
}
#endif
#endif // defined(__riscv_zbb)
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
index 5edbc578e82e9a..fbc51b4bf144ae 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
@@ -51,8 +51,8 @@ unsigned int clz_32(uint32_t a) {
// RV64ZBB-LABEL: @clz_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT:[[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1
false)
-// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP0]] to i32
-// RV64ZBB-NEXT:ret i32 [[CAST]]
+// RV64ZBB-NEXT:[[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
+// RV64ZBB-NEXT:ret i32 [[CAST_I]]
//
unsigned int clz_64(uint64_t a) {
return __riscv_clz_64(a);
@@ -77,10 +77,36 @@ unsigned int ctz_32(uint32_t a) {
// RV64ZBB-LABEL: @ctz_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT:[[TMP0:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1
false)
-// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP0]] to i32
-// RV64ZBB-NEXT:ret i32 [[CAST]]
+// RV64ZBB-NEXT:[[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
+// RV64ZBB-NEXT:ret i32 [[CAST_I]]
//
unsigned int ctz_64(uint64_t a) {
return __riscv_ctz_64(a);
}
#endif
+
+// RV32ZBB-LABEL: @cpop_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT:ret i32 [[TMP0]]
+//
+// RV64ZBB-LABEL: @cpop_32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]])
+// RV64ZBB-NEXT:ret i32 [[TMP0]]
+//
+unsigned int cpop_32(uint32_t a) {
+ return __riscv_cpop_32(a);
+}
+
+#if __riscv_xlen == 64
+// RV64ZBB-LABEL: @cpop_64(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT:[[TMP0:%.*]] = call i64 @llvm.ctpop.i64(i64 [[A:%.*]])
+// RV64ZBB-NEXT:[[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32
+// RV64ZBB-NEXT:ret i32 [[CAST_I]]
+//
+unsigned int cpop_64(uint64_t a) {
+ return __riscv_cpop_64(a);
+}
+#endif
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[clang] [Clang][RISCV] Add missing support for `__builtin_riscv_cpop_32/64` (PR #76256)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/76256
This patch adds support for `__builtin_riscv_cpop_32/64`, which are used by
`riscv_bitmanip.h`.
See also
https://github.com/llvm/llvm-project/blob/04c473bea3e0f135432698fcaafab52e1fe1b5ec/clang/lib/Headers/riscv_bitmanip.h#L35-L60.
Thank @Liaoshihua for reporting this!
>From a69599fcda5f1a4df13ec0bfe3432ba39ef09246 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 23 Dec 2023 01:21:39 +0800
Subject: [PATCH] [Clang][RISCV] Add missing support for
__builtin_riscv_cpop_32/64
---
clang/include/clang/Basic/BuiltinsRISCV.def | 2 ++
clang/lib/CodeGen/CGBuiltin.cpp | 10 +++
clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c | 26 +++
3 files changed, 38 insertions(+)
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82eade..1df1c53733cfa1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -22,6 +22,8 @@ TARGET_BUILTIN(__builtin_riscv_clz_32, "UiUi", "nc",
"zbb|xtheadbb")
TARGET_BUILTIN(__builtin_riscv_clz_64, "UiUWi", "nc", "zbb|xtheadbb,64bit")
TARGET_BUILTIN(__builtin_riscv_ctz_32, "UiUi", "nc", "zbb")
TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_cpop_32, "UiUi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_cpop_64, "UiUWi", "nc", "zbb,64bit")
// Zbc or Zbkc extension
TARGET_BUILTIN(__builtin_riscv_clmul_32, "UiUiUi", "nc", "zbc|zbkc")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 5081062da2862e..64210e76ed2218 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20696,6 +20696,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
case RISCV::BI__builtin_riscv_clz_64:
case RISCV::BI__builtin_riscv_ctz_32:
case RISCV::BI__builtin_riscv_ctz_64:
+ case RISCV::BI__builtin_riscv_cpop_32:
+ case RISCV::BI__builtin_riscv_cpop_64:
case RISCV::BI__builtin_riscv_clmul_32:
case RISCV::BI__builtin_riscv_clmul_64:
case RISCV::BI__builtin_riscv_clmulh_32:
@@ -20735,6 +20737,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
"cast");
return Result;
}
+case RISCV::BI__builtin_riscv_cpop_32:
+case RISCV::BI__builtin_riscv_cpop_64: {
+ Value *Result = Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, Ops[0]);
+ if (Result->getType() != ResultType)
+Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/ true,
+ "cast");
+ return Result;
+}
// Zbc
case RISCV::BI__builtin_riscv_clmul_32:
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
index 3a421f8c6cd421..a5715e330172bd 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
@@ -82,3 +82,29 @@ unsigned int ctz_64(unsigned long a) {
return __builtin_riscv_ctz_64(a);
}
#endif
+
+// RV32ZBB-LABEL: @cpop_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT:ret i32 [[TMP0]]
+//
+// RV64ZBB-LABEL: @cpop_32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT:[[TMP0:%.*]] = call i32 @llvm.ctpop.i32(i32 [[A:%.*]])
+// RV64ZBB-NEXT:ret i32 [[TMP0]]
+//
+unsigned int cpop_32(unsigned int a) {
+ return __builtin_riscv_cpop_32(a);
+}
+
+#if __riscv_xlen == 64
+// RV64ZBB-LABEL: @cpop_64(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT:[[TMP0:%.*]] = call i64 @llvm.ctpop.i64(i64 [[A:%.*]])
+// RV64ZBB-NEXT:[[CAST:%.*]] = trunc i64 [[TMP0]] to i32
+// RV64ZBB-NEXT:ret i32 [[CAST]]
+//
+unsigned int cpop_64(unsigned long a) {
+ return __builtin_riscv_cpop_64(a);
+}
+#endif
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[llvm] [flang] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote: > arrayidx We should teach `foldCmpLoadFromIndexedGlobal` to handle constant GEPs with i8 source element type. https://github.com/llvm/llvm-project/pull/68882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [flang] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote:
> @nikic Could you please have a look at
> [dtcxzyw/llvm-opt-benchmark#17](https://github.com/dtcxzyw/llvm-opt-benchmark/pull/17)?
> One regression:
>
> ```
> diff --git a/bench/brotli/optimized/compound_dictionary.c.ll
> b/bench/brotli/optimized/compound_dictionary.c.ll
> index 21fd37fd..b9894810 100644
> --- a/bench/brotli/optimized/compound_dictionary.c.ll
> +++ b/bench/brotli/optimized/compound_dictionary.c.ll
> @@ -3,9 +3,6 @@ source_filename =
> "bench/brotli/original/compound_dictionary.c.ll"
> target datalayout =
> "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
> target triple = "x86_64-unknown-linux-gnu"
>
> -%struct.PreparedDictionary = type { i32, i32, i32, i32, i32, i32 }
> -%struct.CompoundDictionary = type { i64, i64, [16 x ptr], [16 x ptr], [16 x
> i64], i64, [16 x ptr] }
> -
> ; Function Attrs: nounwind uwtable
> define hidden ptr @CreatePreparedDictionary(ptr noundef %m, ptr noundef
> %source, i64 noundef %source_size) local_unnamed_addr #0 {
> entry:
> @@ -168,25 +165,29 @@ cond.true119.i: ;
> preds = %for.end106.i
>
> cond.end123.i:; preds = %cond.true119.i,
> %for.end106.i
>%cond124.i = phi ptr [ %call121.i, %cond.true119.i ], [ null,
> %for.end106.i ]
> - %arrayidx125.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 1
> + %arrayidx125.i = getelementptr inbounds i8, ptr %cond124.i, i64 24
>%arrayidx127.i = getelementptr inbounds i32, ptr %arrayidx125.i, i64
> %idxprom.i
>%arrayidx129.i = getelementptr inbounds i16, ptr %arrayidx127.i, i64
> %idxprom26.i
>%arrayidx131.i = getelementptr inbounds i32, ptr %arrayidx129.i, i64
> %conv113.i
>store i32 -558043677, ptr %cond124.i, align 4
> - %num_items.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 0, i32 1
> + %num_items.i = getelementptr inbounds i8, ptr %cond124.i, i64 4
>store i32 %add100.i, ptr %num_items.i, align 4
>%conv132.i = trunc i64 %source_size to i32
> - %source_size133.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 0, i32 2
> + %source_size133.i = getelementptr inbounds i8, ptr %cond124.i, i64 8
>store i32 %conv132.i, ptr %source_size133.i, align 4
> - %hash_bits134.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 0, i32 3
> + %hash_bits134.i = getelementptr inbounds i8, ptr %cond124.i, i64 12
>store i32 40, ptr %hash_bits134.i, align 4
> - %bucket_bits135.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 0, i32 4
> + %bucket_bits135.i = getelementptr inbounds i8, ptr %cond124.i, i64 16
>store i32 %bucket_bits.0.lcssa, ptr %bucket_bits135.i, align 4
> - %slot_bits136.i = getelementptr inbounds %struct.PreparedDictionary, ptr
> %cond124.i, i64 0, i32 5
> + %slot_bits136.i = getelementptr inbounds i8, ptr %cond124.i, i64 20
>store i32 %slot_bits.0.lcssa, ptr %slot_bits136.i, align 4
>store ptr %source, ptr %arrayidx131.i, align 1
>br label %for.body140.i
>
> +for.cond151.preheader.i: ; preds = %for.body140.i
> + %invariant.gep.i = getelementptr i8, ptr %arrayidx129.i, i64 -4
> + br label %for.body154.i
> +
> for.body140.i:; preds = %for.body140.i,
> %cond.end123.i
>%indvars.iv145.i = phi i64 [ 0, %cond.end123.i ], [ %indvars.iv.next146.i,
> %for.body140.i ]
>%total_items.1139.i = phi i32 [ 0, %cond.end123.i ], [ %add145.i,
> %for.body140.i ]
> @@ -198,10 +199,10 @@ for.body140.i:;
> preds = %for.body140.i, %con
>store i32 0, ptr %arrayidx144.i, align 4
>%indvars.iv.next146.i = add nuw nsw i64 %indvars.iv145.i, 1
>%exitcond150.not.i = icmp eq i64 %indvars.iv.next146.i, %idxprom.i
> - br i1 %exitcond150.not.i, label %for.body154.i, label %for.body140.i,
> !llvm.loop !9
> + br i1 %exitcond150.not.i, label %for.cond151.preheader.i, label
> %for.body140.i, !llvm.loop !9
>
> -for.body154.i:; preds = %for.body140.i,
> %for.inc204.i
> - %indvars.iv152.i = phi i64 [ %indvars.iv.next153.i, %for.inc204.i ], [ 0,
> %for.body140.i ]
> +for.body154.i:; preds = %for.inc204.i,
> %for.cond151.preheader.i
> + %indvars.iv152.i = phi i64 [ 0, %for.cond151.preheader.i ], [
> %indvars.iv.next153.i, %for.inc204.i ]
>%5 = trunc i64 %indvars.iv152.i to i32
>%and155.i = and i32 %sub3.i, %5
>%arrayidx158.i = getelementptr inbounds i16, ptr %arrayidx25.i, i64
> %indvars.iv152.i
> @@ -243,7 +244,7 @@ for.body194.i:; preds
> = %for.body194.i, %if.
>%pos.0.in140.i = phi ptr [ %arrayidx189.i, %if.end177.i ], [
> %arrayidx198.i, %for.body194.i ]
>%pos.0.i = load i32, ptr %pos.0.in140.i, align 4
>%inc195.i = add nuw nsw i64 %cursor.0142.i, 1
>
[flang] [llvm] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote: An unique regression: ``` diff --git a/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll b/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll index 534c0a07..85a097fc 100644 --- a/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll +++ b/bench/openssl/optimized/hexstr_test-bin-hexstr_test.ll @@ -48,7 +48,7 @@ entry: %idxprom = sext i32 %test_index to i64 %arrayidx = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom %0 = load ptr, ptr %arrayidx, align 16 - %sep = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 3 + %sep = getelementptr inbounds i8, ptr %arrayidx, i64 24 %1 = load i8, ptr %sep, align 8 %call = call ptr @ossl_hexstr2buf_sep(ptr noundef %0, ptr noundef nonnull %len, i8 noundef signext %1) #2 %call1 = call i32 @test_ptr(ptr noundef nonnull @.str.3, i32 noundef 71, ptr noundef nonnull @.str.4, ptr noundef %call) #2 @@ -57,9 +57,9 @@ entry: lor.lhs.false:; preds = %entry %2 = load i64, ptr %len, align 8 - %expected = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 1 + %expected = getelementptr inbounds i8, ptr %arrayidx, i64 8 %3 = load ptr, ptr %expected, align 8 - %expected_len = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 2 + %expected_len = getelementptr inbounds i8, ptr %arrayidx, i64 16 %4 = load i64, ptr %expected_len, align 16 %call2 = call i32 @test_mem_eq(ptr noundef nonnull @.str.3, i32 noundef 72, ptr noundef nonnull @.str.5, ptr noundef nonnull @.str.6, ptr noundef %call, i64 noundef %2, ptr noundef %3, i64 noundef %4) #2 %tobool3.not = icmp eq i32 %call2, 0 @@ -93,8 +93,9 @@ entry: store i64 0, ptr %len, align 8 %idxprom = sext i32 %test_index to i64 %arrayidx = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom - %0 = and i32 %test_index, -2 - %cmp.not = icmp eq i32 %0, 2 + %sep = getelementptr inbounds i8, ptr %arrayidx, i64 24 + %0 = load i8, ptr %sep, align 8 + %cmp.not = icmp eq i8 %0, 95 %1 = load ptr, ptr %arrayidx, align 16 %call28 = call ptr @OPENSSL_hexstr2buf(ptr noundef %1, ptr noundef nonnull %len) #2 br i1 %cmp.not, label %if.else26, label %if.then @@ -106,9 +107,9 @@ if.then: ; preds = %entry lor.lhs.false:; preds = %if.then %2 = load i64, ptr %len, align 8 - %expected = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 1 + %expected = getelementptr inbounds i8, ptr %arrayidx, i64 8 %3 = load ptr, ptr %expected, align 8 - %expected_len = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 2 + %expected_len = getelementptr inbounds i8, ptr %arrayidx, i64 16 %4 = load i64, ptr %expected_len, align 16 %call3 = call i32 @test_mem_eq(ptr noundef nonnull @.str.3, i32 noundef 94, ptr noundef nonnull @.str.5, ptr noundef nonnull @.str.6, ptr noundef %call28, i64 noundef %2, ptr noundef %3, i64 noundef %4) #2 %tobool4.not = icmp eq i32 %call3, 0 @@ -122,7 +123,7 @@ lor.lhs.false5: ; preds = %lor.lhs.false br i1 %tobool8.not, label %err, label %if.end if.end: ; preds = %lor.lhs.false5 - %cmp12 = icmp ult i32 %test_index, 2 + %cmp12 = icmp eq i8 %0, 58 br i1 %cmp12, label %if.then14, label %if.else if.then14:; preds = %if.end @@ -171,9 +172,9 @@ entry: land.lhs.true:; preds = %entry %1 = load i64, ptr %len, align 8 - %expected = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 1 + %expected = getelementptr inbounds i8, ptr %arrayidx, i64 8 %2 = load ptr, ptr %expected, align 8 - %expected_len = getelementptr inbounds [6 x %struct.testdata], ptr @tbl_testdata, i64 0, i64 %idxprom, i32 2 + %expected_len = getelementptr inbounds i8, ptr %arrayidx, i64 16 %3 = load i64, ptr %expected_len, align 16 %call3 = call i32 @test_mem_eq(ptr noundef nonnull @.str.3, i32 noundef 122, ptr noundef nonnull @.str.5, ptr noundef nonnull @.str.6, ptr noundef nonnull %buf, i64 noundef %1, ptr noundef %2, i64 noundef %3) #2 %tobool4.not = icmp eq i32 %call3, 0 ``` https://github.com/llvm/llvm-project/pull/68882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [llvm] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote: > @dtcxzyw GitHub can't display the diff, and struggles to clone the repo. Can > you share the diffs for just the mentioned files? I have posted the diff between optimized IRs. https://github.com/llvm/llvm-project/pull/68882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote: Another example: ``` diff --git a/bench/hermes/optimized/Sorting.cpp.ll b/bench/hermes/optimized/Sorting.cpp.ll index 1a808c47..e03089ca 100644 --- a/bench/hermes/optimized/Sorting.cpp.ll +++ b/bench/hermes/optimized/Sorting.cpp.ll @@ -41,20 +41,22 @@ if.end: ; preds = %entry %call5.i.i.i.i.i.i = tail call noalias noundef nonnull ptr @_Znwm(i64 noundef %mul.i.i.i.i.i.i) #9 store ptr %call5.i.i.i.i.i.i, ptr %index, align 8 %add.ptr.i.i.i = getelementptr inbounds i32, ptr %call5.i.i.i.i.i.i, i64 %conv - %_M_end_of_storage.i.i.i = getelementptr inbounds %"struct.std::_Vector_base>::_Vector_impl_data", ptr %index, i64 0, i32 2 + %_M_end_of_storage.i.i.i = getelementptr inbounds i8, ptr %index, i64 16 store ptr %add.ptr.i.i.i, ptr %_M_end_of_storage.i.i.i, align 8 store i32 0, ptr %call5.i.i.i.i.i.i, align 4 - %incdec.ptr.i.i.i.i.i = getelementptr i32, ptr %call5.i.i.i.i.i.i, i64 1 - %cmp.i.i.i.i.i.i.i = icmp eq i32 %sub, 1 + %incdec.ptr.i.i.i.i.i = getelementptr i8, ptr %call5.i.i.i.i.i.i, i64 4 + %sub.i.i.i.i.i = add nsw i64 %conv, -1 + %cmp.i.i.i.i.i.i.i = icmp eq i64 %sub.i.i.i.i.i, 0 br i1 %cmp.i.i.i.i.i.i.i, label %_ZNSt6vectorIjSaIjEEC2EmRKS0_.exit, label %if.end.i.i.i.i.i.i.i if.end.i.i.i.i.i.i.i: ; preds = %if.end %1 = add nsw i64 %mul.i.i.i.i.i.i, -4 tail call void @llvm.memset.p0.i64(ptr align 4 %incdec.ptr.i.i.i.i.i, i8 0, i64 %1, i1 false) + %add.ptr.i.i.i.i.i.i.i = getelementptr inbounds i32, ptr %incdec.ptr.i.i.i.i.i, i64 %sub.i.i.i.i.i br label %_ZNSt6vectorIjSaIjEEC2EmRKS0_.exit _ZNSt6vectorIjSaIjEEC2EmRKS0_.exit: ; preds = %if.end, %if.end.i.i.i.i.i.i.i - %__first.addr.0.i.i.i.i.i = phi ptr [ %incdec.ptr.i.i.i.i.i, %if.end ], [ %add.ptr.i.i.i, %if.end.i.i.i.i.i.i.i ] + %__first.addr.0.i.i.i.i.i = phi ptr [ %incdec.ptr.i.i.i.i.i, %if.end ], [ %add.ptr.i.i.i.i.i.i.i, %if.end.i.i.i.i.i.i.i ] store ptr %__first.addr.0.i.i.i.i.i, ptr %0, align 8 %cmp116.not = icmp eq i32 %end, %begin br i1 %cmp116.not, label %for.end, label %for.body ``` https://github.com/llvm/llvm-project/pull/68882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [llvm] [clang] [InstCombine] Canonicalize constant GEPs to i8 source element type (PR #68882)
dtcxzyw wrote:
@nikic Could you please have a look at
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/17?
One regression:
```
diff --git a/bench/brotli/optimized/compound_dictionary.c.ll
b/bench/brotli/optimized/compound_dictionary.c.ll
index 21fd37fd..b9894810 100644
--- a/bench/brotli/optimized/compound_dictionary.c.ll
+++ b/bench/brotli/optimized/compound_dictionary.c.ll
@@ -3,9 +3,6 @@ source_filename =
"bench/brotli/original/compound_dictionary.c.ll"
target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
-%struct.PreparedDictionary = type { i32, i32, i32, i32, i32, i32 }
-%struct.CompoundDictionary = type { i64, i64, [16 x ptr], [16 x ptr], [16 x
i64], i64, [16 x ptr] }
-
; Function Attrs: nounwind uwtable
define hidden ptr @CreatePreparedDictionary(ptr noundef %m, ptr noundef
%source, i64 noundef %source_size) local_unnamed_addr #0 {
entry:
@@ -168,25 +165,29 @@ cond.true119.i: ; preds
= %for.end106.i
cond.end123.i:; preds = %cond.true119.i,
%for.end106.i
%cond124.i = phi ptr [ %call121.i, %cond.true119.i ], [ null, %for.end106.i ]
- %arrayidx125.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 1
+ %arrayidx125.i = getelementptr inbounds i8, ptr %cond124.i, i64 24
%arrayidx127.i = getelementptr inbounds i32, ptr %arrayidx125.i, i64
%idxprom.i
%arrayidx129.i = getelementptr inbounds i16, ptr %arrayidx127.i, i64
%idxprom26.i
%arrayidx131.i = getelementptr inbounds i32, ptr %arrayidx129.i, i64
%conv113.i
store i32 -558043677, ptr %cond124.i, align 4
- %num_items.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 0, i32 1
+ %num_items.i = getelementptr inbounds i8, ptr %cond124.i, i64 4
store i32 %add100.i, ptr %num_items.i, align 4
%conv132.i = trunc i64 %source_size to i32
- %source_size133.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 0, i32 2
+ %source_size133.i = getelementptr inbounds i8, ptr %cond124.i, i64 8
store i32 %conv132.i, ptr %source_size133.i, align 4
- %hash_bits134.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 0, i32 3
+ %hash_bits134.i = getelementptr inbounds i8, ptr %cond124.i, i64 12
store i32 40, ptr %hash_bits134.i, align 4
- %bucket_bits135.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 0, i32 4
+ %bucket_bits135.i = getelementptr inbounds i8, ptr %cond124.i, i64 16
store i32 %bucket_bits.0.lcssa, ptr %bucket_bits135.i, align 4
- %slot_bits136.i = getelementptr inbounds %struct.PreparedDictionary, ptr
%cond124.i, i64 0, i32 5
+ %slot_bits136.i = getelementptr inbounds i8, ptr %cond124.i, i64 20
store i32 %slot_bits.0.lcssa, ptr %slot_bits136.i, align 4
store ptr %source, ptr %arrayidx131.i, align 1
br label %for.body140.i
+for.cond151.preheader.i: ; preds = %for.body140.i
+ %invariant.gep.i = getelementptr i8, ptr %arrayidx129.i, i64 -4
+ br label %for.body154.i
+
for.body140.i:; preds = %for.body140.i,
%cond.end123.i
%indvars.iv145.i = phi i64 [ 0, %cond.end123.i ], [ %indvars.iv.next146.i,
%for.body140.i ]
%total_items.1139.i = phi i32 [ 0, %cond.end123.i ], [ %add145.i,
%for.body140.i ]
@@ -198,10 +199,10 @@ for.body140.i:; preds
= %for.body140.i, %con
store i32 0, ptr %arrayidx144.i, align 4
%indvars.iv.next146.i = add nuw nsw i64 %indvars.iv145.i, 1
%exitcond150.not.i = icmp eq i64 %indvars.iv.next146.i, %idxprom.i
- br i1 %exitcond150.not.i, label %for.body154.i, label %for.body140.i,
!llvm.loop !9
+ br i1 %exitcond150.not.i, label %for.cond151.preheader.i, label
%for.body140.i, !llvm.loop !9
-for.body154.i:; preds = %for.body140.i,
%for.inc204.i
- %indvars.iv152.i = phi i64 [ %indvars.iv.next153.i, %for.inc204.i ], [ 0,
%for.body140.i ]
+for.body154.i:; preds = %for.inc204.i,
%for.cond151.preheader.i
+ %indvars.iv152.i = phi i64 [ 0, %for.cond151.preheader.i ], [
%indvars.iv.next153.i, %for.inc204.i ]
%5 = trunc i64 %indvars.iv152.i to i32
%and155.i = and i32 %sub3.i, %5
%arrayidx158.i = getelementptr inbounds i16, ptr %arrayidx25.i, i64
%indvars.iv152.i
@@ -243,7 +244,7 @@ for.body194.i:; preds =
%for.body194.i, %if.
%pos.0.in140.i = phi ptr [ %arrayidx189.i, %if.end177.i ], [ %arrayidx198.i,
%for.body194.i ]
%pos.0.i = load i32, ptr %pos.0.in140.i, align 4
%inc195.i = add nuw nsw i64 %cursor.0142.i, 1
- %arrayidx196.i = getelementptr i32, ptr %arrayidx129.i, i64 %cursor.0142.i
+ %arrayidx196.i = getelementptr inbounds i32, ptr %arrayidx129.i, i64
%cursor.0142.i
store i32 %pos.0.i, ptr %arrayidx196.i, align 4
%idxprom197.i = zext
[clang] [clang] static operators should evaluate object argument (PR #68485)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/68485 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for experimental Zimop extension (PR #74824)
dtcxzyw wrote: I guess you should split it into patch series. + [ ] MC support (and docs) + [ ] Sched support + [ ] ISel support + [ ] Builtin intrinsic support in clang https://github.com/llvm/llvm-project/pull/74824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
https://github.com/dtcxzyw approved this pull request. The regression in `Shootout-C++-ary2` may be caused by ThinLTO. But I think it is OK to go ahead and merge :) https://github.com/llvm/llvm-project/pull/73662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
dtcxzyw wrote: Looks like the regression in `DILATE` has been addressed. Could you please have a look at `MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode`? https://github.com/llvm/llvm-project/pull/73662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
dtcxzyw wrote: Could you please rebase this patch on https://github.com/llvm/llvm-project/pull/74246 and add a test for https://github.com/llvm/llvm-project/issues/74242? https://github.com/llvm/llvm-project/pull/73662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
dtcxzyw wrote: My CI detected some significant regressions caused by this patch: https://github.com/dtcxzyw/llvm-ci/pull/839#issuecomment-1836976355 https://github.com/llvm/llvm-project/pull/73662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
https://github.com/dtcxzyw approved this pull request. The implementation looks good to me. Waiting for the result of my CI. https://github.com/dtcxzyw/llvm-ci/actions/runs/7066692655 @goldsteinn Any comments? https://github.com/llvm/llvm-project/pull/73662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
@@ -75,7 +75,8 @@ define void @idom_sign_bit_check_edge_dominates_select(i64
%a, i64 %b) {
; CHECK: land.lhs.true:
; CHECK-NEXT:br label [[LOR_END:%.*]]
; CHECK: lor.rhs:
-; CHECK-NEXT:[[CMP3_NOT:%.*]] = icmp eq i64 [[A]], [[B:%.*]]
+; CHECK-NEXT:[[SELECT:%.*]] = call i64 @llvm.umax.i64(i64 [[A]], i64 5)
dtcxzyw wrote:
Regression?
https://github.com/llvm/llvm-project/pull/73662
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[clang] [llvm] [ValueTracking] Add dominating condition support in computeKnownBits() (PR #73662)
@@ -0,0 +1,74 @@
+//===- DomConditionCache.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "llvm/Analysis/DomConditionCache.h"
+#include "llvm/IR/PatternMatch.h"
+
+using namespace llvm;
+using namespace llvm::PatternMatch;
+
+// TODO: This code is very similar to findAffectedValues() in
+// AssumptionCache, but currently specialized to just the patterns that
+// computeKnownBits() supports, and without the notion of result elem indices
+// that are AC specific. Deduplicate this code once we have a clearer picture
+// of how much they can be shared.
+static void findAffectedValues(Value *Cond,
+ SmallVectorImpl ) {
+ auto AddAffected = [](Value *V) {
+if (isa(V) || isa(V)) {
+ Affected.push_back(V);
+} else if (auto *I = dyn_cast(V)) {
+ Affected.push_back(I);
+
+ // Peek through unary operators to find the source of the condition.
+ Value *Op;
+ if (match(I, m_PtrToInt(m_Value(Op {
+if (isa(Op) || isa(Op))
+ Affected.push_back(Op);
+ }
+}
+ };
+
+ ICmpInst::Predicate Pred;
+ Value *A;
+ Constant *C;
+ if (match(Cond, m_ICmp(Pred, m_Value(A), m_Constant(C {
+AddAffected(A);
+
+if (Pred == ICmpInst::ICMP_EQ) {
+ Value *X;
+ // (X & C) or (X | C) or (X ^ C).
+ // (X << C) or (X >>_s C) or (X >>_u C).
+ if (match(A, m_BitwiseLogic(m_Value(X), m_ConstantInt())) ||
+ match(A, m_Shift(m_Value(X), m_ConstantInt(
+AddAffected(X);
+} else if (Pred == ICmpInst::ICMP_NE) {
+ Value *X;
+ // Handle (X & pow2 != 0).
+ if (match(A, m_And(m_Value(X), m_Power2())) && match(C, m_Zero()))
+AddAffected(X);
+} else if (Pred == ICmpInst::ICMP_ULT) {
dtcxzyw wrote:
```suggestion
} else {
```
Does it also hold for other predicates?
https://github.com/llvm/llvm-project/blob/81e3e7e5d455f85e070a27763c578df493716ae9/llvm/lib/Analysis/ValueTracking.cpp#L701-L710
https://github.com/llvm/llvm-project/pull/73662
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[clang-tools-extra] [clang] [llvm] [InstCombine] Convert or concat to fshl if opposite or concat exists (PR #68502)
@@ -2840,6 +2841,46 @@ static Instruction *matchFunnelShift(Instruction ,
InstCombinerImpl ) {
return nullptr;
FShiftArgs = {ShVal0, ShVal1, ShAmt};
+ } else if (isa(Or0) || isa(Or1)) {
+// If there are two 'or' instructions concat variables in opposite order,
+// the latter one can be safely convert to fshl.
+//
+// LowHigh = or (shl (zext Low), Width - ZextHighShlAmt), (zext High)
+// HighLow = or (shl (zext High), ZextHighShlAmt), (zext Low)
+// ->
+// HighLow = fshl LowHigh, LowHigh, ZextHighShlAmt
+if (!isa(Or1))
+ std::swap(Or0, Or1);
+
+Value *High, *ZextHigh, *Low;
+const APInt *ZextHighShlAmt;
+if (!match(Or0,
+ m_OneUse(m_Shl(m_Value(ZextHigh), m_APInt(ZextHighShlAmt)
+ return nullptr;
+
+if (!match(Or1, m_ZExt(m_Value(Low))) ||
+!match(ZextHigh, m_ZExt(m_Value(High
dtcxzyw wrote:
I think we don't need to check `zext`. An example without `zext`:
https://alive2.llvm.org/ce/z/MytePb
https://github.com/llvm/llvm-project/pull/68502
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[llvm] [clang] [InstCombine] Use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [InstCombine] Use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw approved this pull request. LGTM. Thank you! Do you have the access to merge PR? https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,145 @@ +; RUN: opt < %s --O3 -S | FileCheck %s dtcxzyw wrote: My command: `bin/opt -S -O3 -print-changed min_max.ll` Then I got IR after the SROA pass :) https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw commented: LGTM https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,111 @@
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
+;; short vecreduce_smin_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i < n; ++i)
+;; p = p > v[i] ? v[i] : p;
+;; return p;
+;; }
+;
+;; short vecreduce_smax_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i < n; ++i)
+;; p = p < v[i] ? v[i] : p;
+;; return p;
+;; }
+
+define i16 @vecreduce_smin_v2i16(i32 %n, ptr %v) {
+; CHECK-LABEL: define i16 @vecreduce_smin_v2i16(
+; CHECK:@llvm.smin.v2i16
+
+entry:
+ br label %for.cond
+
+for.cond: ; preds = %for.inc, %entry
+ %p.0 = phi i16 [ 0, %entry ], [ %conv8, %for.inc ]
+ %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+ %cmp = icmp slt i32 %i.0, %n
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body: ; preds = %for.cond
+ %conv = sext i16 %p.0 to i32
+ %idxprom = sext i32 %i.0 to i64
+ %arrayidx = getelementptr inbounds i16, ptr %v, i64 %idxprom
+ %0 = load i16, ptr %arrayidx, align 2
+ %conv1 = sext i16 %0 to i32
+ %cmp2 = icmp sgt i32 %conv, %conv1
+ br i1 %cmp2, label %cond.true, label %cond.false
+
+cond.true:; preds = %for.body
+ %idxprom4 = sext i32 %i.0 to i64
+ %arrayidx5 = getelementptr inbounds i16, ptr %v, i64 %idxprom4
+ %1 = load i16, ptr %arrayidx5, align 2
+ %conv6 = sext i16 %1 to i32
+ br label %cond.end
+
+cond.false: ; preds = %for.body
+ %conv7 = sext i16 %p.0 to i32
+ br label %cond.end
+
+cond.end: ; preds = %cond.false,
%cond.true
+ %cond = phi i32 [ %conv6, %cond.true ], [ %conv7, %cond.false ]
+ %conv8 = trunc i32 %cond to i16
+ br label %for.inc
+
+for.inc: ; preds = %cond.end
+ %inc = add nsw i32 %i.0, 1
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ ret i16 %p.0
+}
+
+define signext i16 @vecreduce_smax_v2i16(i32 noundef %n, ptr noundef %v) {
dtcxzyw wrote:
```suggestion
define i16 @vecreduce_smax_v2i16(i32 %n, ptr %v) {
```
https://github.com/llvm/llvm-project/pull/70845
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[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw edited https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
+;; short vecreduce_smin_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i < n; ++i)
+;; p = p > v[i] ? v[i] : p;
+;; return p;
+;; }
+;
+;; short vecreduce_smax_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i < n; ++i)
+;; p = p < v[i] ? v[i] : p;
+;; return p;
+;; }
+
+define i16 @vecreduce_smin_v2i16(i32 %n, ptr %v) {
+; CHECK-LABEL: define i16 @vecreduce_smin_v2i16(
+; CHECK:@llvm.smin.v2i16
dtcxzyw wrote:
Oh, it makes sense. Just checking `smin/smax` intrinsics is OK.
https://github.com/llvm/llvm-project/pull/70845
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[llvm] [clang-tools-extra] [clang] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
dtcxzyw wrote: > Oh nice, I'm running into something similar in #71657. Are all these dead > ADDIs coming from the backwards local postpass? Yes. I believe this PR can address the issue. https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
```
define i16 @vecreduce_smin_v2i16(i32 %n, ptr %v) {
entry:
br label %for.cond
for.cond:
%p.0 = phi i16 [ 0, %entry ], [ %conv8, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp slt i32 %i.0, %n
br i1 %cmp, label %for.body, label %for.end
for.body:
%conv = sext i16 %p.0 to i32
%idxprom = sext i32 %i.0 to i64
%arrayidx = getelementptr inbounds i16, ptr %v, i64 %idxprom
%0 = load i16, ptr %arrayidx, align 2
%conv1 = sext i16 %0 to i32
%cmp2 = icmp sgt i32 %conv, %conv1
br i1 %cmp2, label %cond.true, label %cond.false
cond.true:
%idxprom4 = sext i32 %i.0 to i64
%arrayidx5 = getelementptr inbounds i16, ptr %v, i64 %idxprom4
%1 = load i16, ptr %arrayidx5, align 2
%conv6 = sext i16 %1 to i32
br label %cond.end
cond.false:
%conv7 = sext i16 %p.0 to i32
br label %cond.end
cond.end:
%cond = phi i32 [ %conv6, %cond.true ], [ %conv7, %cond.false ]
%conv8 = trunc i32 %cond to i16
br label %for.inc
for.inc:
%inc = add nsw i32 %i.0, 1
br label %for.cond
for.end:
ret i16 %p.0
}
define i16 @vecreduce_smax_v2i16(i32 %n, ptr %v) {
entry:
br label %for.cond
for.cond:
%p.0 = phi i16 [ 0, %entry ], [ %conv8, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp slt i32 %i.0, %n
br i1 %cmp, label %for.body, label %for.end
for.body:
%conv = sext i16 %p.0 to i32
%idxprom = sext i32 %i.0 to i64
%arrayidx = getelementptr inbounds i16, ptr %v, i64 %idxprom
%0 = load i16, ptr %arrayidx, align 2
%conv1 = sext i16 %0 to i32
%cmp2 = icmp slt i32 %conv, %conv1
br i1 %cmp2, label %cond.true, label %cond.false
cond.true:
%idxprom4 = sext i32 %i.0 to i64
%arrayidx5 = getelementptr inbounds i16, ptr %v, i64 %idxprom4
%1 = load i16, ptr %arrayidx5, align 2
%conv6 = sext i16 %1 to i32
br label %cond.end
cond.false:
%conv7 = sext i16 %p.0 to i32
br label %cond.end
cond.end:
%cond = phi i32 [ %conv6, %cond.true ], [ %conv7, %cond.false ]
%conv8 = trunc i32 %cond to i16
br label %for.inc
for.inc:
%inc = add nsw i32 %i.0, 1
br label %for.cond
for.end:
ret i16 %p.0
}
```
https://github.com/llvm/llvm-project/pull/70845
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[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw requested changes to this pull request. https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,145 @@ +; RUN: opt < %s --O3 -S | FileCheck %s dtcxzyw wrote: ```suggestion ; RUN: opt < %s -O3 -S | FileCheck %s ``` https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,145 @@ +; RUN: opt < %s --O3 -S | FileCheck %s dtcxzyw wrote: Could you please: 1. Convert this IR into SSA form as @nikic mentioned. 2. Drop unused attributes. 3. Re-generate tests with `llvm/utils/update_test_checks.py`. https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw edited https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [InstCombine] Infer zext nneg flag (PR #71534)
dtcxzyw wrote: Reduced test case: https://godbolt.org/z/d4ETPhbno https://github.com/llvm/llvm-project/pull/71534 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
dtcxzyw wrote:
Please drop unused `signext` and `noundef` flags.
https://github.com/llvm/llvm-project/pull/70845
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[clang] [llvm] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: define signext i32 @sext_sext(
+; CHECK-SAME: i16 [[X:%.*]], i16 [[Y:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[CMP2:%.*]] = icmp sgt i16 [[X]], [[Y]]
+; CHECK-NEXT:br i1 [[CMP2]], label [[COND_TRUE:%.*]], label
[[COND_FALSE:%.*]]
+; CHECK: cond.true:
+; CHECK-NEXT:br label [[COND_END:%.*]]
+; CHECK: cond.false:
+; CHECK-NEXT:br label [[COND_END]]
+; CHECK: cond.end:
+; CHECK-NEXT:[[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ 1,
[[COND_FALSE]] ]
+; CHECK-NEXT:ret i32 [[COND]]
+;
+entry:
+ %conv = sext i16 %x to i32
+ %conv1 = sext i16 %y to i32
+ %cmp2 = icmp sgt i32 %conv, %conv1
+ br i1 %cmp2, label %cond.true, label %cond.false
+
+cond.true:; preds = %for.body
+ br label %cond.end
+
+cond.false: ; preds = %for.body
+ br label %cond.end
+
+cond.end: ; preds = %cond.false,
%cond.true
+ %cond = phi i32 [ 0, %cond.true ], [ 1, %cond.false ]
+ ret i32 %cond
+}
+
+
+define signext i32 @zext_zext(i16 %x, i16 %y) {
+; CHECK-LABEL: define signext i32 @zext_zext(
+; CHECK-SAME: i16 [[X:%.*]], i16 [[Y:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[CMP2:%.*]] = icmp ugt i16 [[X]], [[Y]]
+; CHECK-NEXT:br i1 [[CMP2]], label [[COND_TRUE:%.*]], label
[[COND_FALSE:%.*]]
+; CHECK: cond.true:
+; CHECK-NEXT:br label [[COND_END:%.*]]
+; CHECK: cond.false:
+; CHECK-NEXT:br label [[COND_END]]
+; CHECK: cond.end:
+; CHECK-NEXT:[[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ 1,
[[COND_FALSE]] ]
+; CHECK-NEXT:ret i32 [[COND]]
+;
+entry:
+ %conv = zext i16 %x to i32
+ %conv1 = zext i16 %y to i32
+ %cmp2 = icmp sgt i32 %conv, %conv1
+ br i1 %cmp2, label %cond.true, label %cond.false
+
+cond.true:; preds = %for.body
+ br label %cond.end
+
+cond.false: ; preds = %for.body
+ br label %cond.end
+
+cond.end: ; preds = %cond.false,
%cond.true
+ %cond = phi i32 [ 0, %cond.true ], [ 1, %cond.false ]
+ ret i32 %cond
+}
+
+
+define signext i16 @zext_positive_and_sext(i32 noundef %n, ptr noundef %v) {
+; CHECK-LABEL: define signext i16 @zext_positive_and_sext(
+; CHECK-SAME: i32 noundef [[N:%.*]], ptr noundef [[V:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT:br label [[FOR_COND:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT:[[P_0:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [
[[COND_OFF0:%.*]], [[COND_END:%.*]] ]
+; CHECK-NEXT:[[I_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC:%.*]],
[[COND_END]] ]
+; CHECK-NEXT:[[CMP:%.*]] = icmp slt i32 [[I_0]], [[N]]
+; CHECK-NEXT:br i1 [[CMP]], label [[FOR_BODY:%.*]], label
[[FOR_COND_CLEANUP:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT:[[IDXPROM:%.*]] = zext nneg i32 [[I_0]] to i64
+; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr i16, ptr [[V]], i64
[[IDXPROM]]
+; CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+; CHECK-NEXT:[[CMP2:%.*]] = icmp slt i16 [[P_0]], [[TMP0]]
+; CHECK-NEXT:br i1 [[CMP2]], label [[COND_TRUE:%.*]], label
[[COND_FALSE:%.*]]
+; CHECK: cond.true:
+; CHECK-NEXT:br label [[COND_END]]
+; CHECK: cond.false:
+; CHECK-NEXT:br label [[COND_END]]
+; CHECK: for.cond.cleanup:
+; CHECK-NEXT:ret i16 [[P_0]]
+; CHECK: cond.end:
+; CHECK-NEXT:[[COND_OFF0]] = phi i16 [ [[TMP0]], [[COND_TRUE]] ], [
[[P_0]], [[COND_FALSE]] ]
+; CHECK-NEXT:[[INC]] = add nuw nsw i32 [[I_0]], 1
+; CHECK-NEXT:br label [[FOR_COND]]
+;
+entry:
+ br label %for.cond
+
+for.cond: ; preds = %cond.end, %entry
+ %p.0 = phi i16 [ 0, %entry ], [ %conv8, %cond.end ]
+ %i.0 = phi i32 [ 0, %entry ], [ %inc, %cond.end ]
+ %cmp = icmp slt i32 %i.0, %n
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.body: ; preds = %for.cond
+ %conv = zext nneg i16 %p.0 to i32;; %p.0 is always
positive here
+ %idxprom = sext i32 %i.0 to i64
+ %arrayidx = getelementptr i16, ptr %v, i64 %idxprom
+ %0 = load i16, ptr %arrayidx, align 2
+ %conv1 = sext i16 %0 to i32
+ %cmp2 = icmp slt i32 %conv, %conv1
+ br i1 %cmp2, label %cond.true, label %cond.false
+
+cond.true:; preds = %for.body
+ br label %cond.end
+
+cond.false: ; preds = %for.body
+ br label %cond.end
+
+for.cond.cleanup: ; preds = %for.cond
+ ret i16 %p.0
+
+cond.end: ; preds = %cond.false,
[clang] [llvm] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw requested changes to this pull request. https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -0,0 +1,126 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
+
+define signext i16 @vecreduce_smax_v2i16(i32 noundef %0, ptr noundef %1) #0 {
dtcxzyw wrote:
Could you please reduce the test case and move it into `InstCombine`?
https://github.com/llvm/llvm-project/pull/70845
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[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
https://github.com/dtcxzyw edited https://github.com/llvm/llvm-project/pull/70845 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Instcombine] use zext's nneg flag for icmp folding (PR #70845)
@@ -5587,11 +5587,20 @@ Instruction
*InstCombinerImpl::foldICmpWithZextOrSext(ICmpInst ) {
return new ICmpInst(ICmp.getPredicate(), Builder.CreateOr(X, Y),
Constant::getNullValue(X->getType()));
+ // Treat "zext nneg" as "sext"
+ auto *NonNegInst0 = dyn_cast(ICmp.getOperand(0));
+ auto *NonNegInst1 = dyn_cast(ICmp.getOperand(1));
+
+ bool IsNonNeg0 = NonNegInst0 && NonNegInst0->hasNonNeg();
+ bool IsNonNeg1 = NonNegInst1 && NonNegInst1->hasNonNeg();
+
// If we have mismatched casts, treat the zext of a non-negative source
as
// a sext to simulate matching casts. Otherwise, we are done.
// TODO: Can we handle some predicates (equality) without non-negative?
- if ((IsZext0 && isKnownNonNegative(X, DL, 0, , , )) ||
- (IsZext1 && isKnownNonNegative(Y, DL, 0, , , )))
+ if ((IsZext0 &&
+ (IsNonNeg0 || isKnownNonNegative(X, DL, 0, , , ))) ||
dtcxzyw wrote:
Why not check the `nneg` flag in `isKnownNonNegative`?
https://github.com/llvm/llvm-project/pull/70845
___
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[clang] [llvm] [InstCombine] Infer zext nneg flag (PR #71534)
https://github.com/dtcxzyw approved this pull request. LGTM. Thanks! We can improve the compile time by adding `nneg` flag during the zext creation (e.g., `cttz(zext(x)) -> zext nneg(cttz(x))`). https://github.com/llvm/llvm-project/pull/71534 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[polly] [llvm] [clang] [mlir] [NFC] Remove Type::getInt8PtrTy (PR #71029)
dtcxzyw wrote: Please also update existing uses in `lldb`. Buildbot failure: https://lab.llvm.org/buildbot/#/builders/68/builds/63101 https://github.com/llvm/llvm-project/pull/71029 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From 1222b8bda348af58f4921a45d8cddca726875bb9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
Co-authored-by: SForeKeeper
---
clang/test/Driver/riscv-cpus.c| 14 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 21 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature"
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd"
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed"
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck
-check-prefix=MTUNE-VEYRON-V1 %s
// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu |
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck
-check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket,
sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5465e0c998ca6f8..a3dbcda3638f8f4 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -244,3 +244,24 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
FeatureStdExtZicboz,
FeatureVendorXVentanaCondOps],
[TuneVentanaVeyron]>;
+
+def
[clang] [llvm] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
dtcxzyw wrote: Ping. @preames Any more comments? https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
dtcxzyw wrote: Rebased on top of #70241. https://github.com/llvm/llvm-project/pull/70232 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70232
>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu
Co-authored-by: SForeKeeper
---
clang/test/Driver/riscv-cpus.c| 14 +
clang/test/Misc/target-invalid-cpu-note.c | 4 +-
llvm/lib/Target/RISCV/RISCV.td| 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 21 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 307 ++
.../llvm-mca/RISCV/XiangShan/cascade-fma.s| 53 ++
.../llvm-mca/RISCV/XiangShan/gpr-bypass.s | 527 ++
.../llvm-mca/RISCV/XiangShan/load-to-alu.s| 73 +++
8 files changed, 998 insertions(+), 2 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature"
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd"
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed"
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck
-check-prefix=MTUNE-VEYRON-V1 %s
// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu |
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck
-check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic,
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
dtcxzyw wrote: Any more questions about XiangShan? If there is no question, I will merge this PR tomorrow. https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
dtcxzyw wrote: > LGTM in general, except one question: will zicbom and zicboz be in the final > RTL? You can find the full implementation of `zicbom` and `zicboz` here: https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25. cc @poemonsense https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
@@ -20,6 +20,17 @@ // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s +// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" dtcxzyw wrote: Fixed. Please move to #70294 to review the processor definition part. https://github.com/llvm/llvm-project/pull/70232 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
Co-authored-by: SForeKeeper
---
clang/test/Driver/riscv-cpus.c| 14 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 21 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature"
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd"
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed"
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck
-check-prefix=MTUNE-VEYRON-V1 %s
// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu |
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck
-check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket,
sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e4008d145ffa572..427e15bea2f8dce 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -243,3 +243,24 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
FeatureStdExtZicbop,
FeatureStdExtZicboz,
FeatureVendorXVentanaCondOps]>;
+
+def
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
dtcxzyw wrote: > Can you separate out the basic processor definition (using NoSchedModel), and > a patch which adds the scheduling model? We can at least get the processor > definition landed while we iterate on the scheduling related pieces. > > edit: For clarity, I'm requesting that the basic processor definition and > test updates be made into its own pull request, and that this pull request be > reserved for adding the schedule model on top. Posted as #70294. https://github.com/llvm/llvm-project/pull/70232 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/), NanHu
core supports
`RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`.
I found that NanHu also supports `zicbom` and `zicboz`. You can find them in
the [source
code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436).
Features supported by NanHu have been confirmed by @poemonsense.
See also #70232.
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH] [RISCV] Add processor definition for XiangShan-NanHu
Co-authored-by: SForeKeeper
---
clang/test/Driver/riscv-cpus.c| 14 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 21 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature"
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb"
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd"
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed"
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck
-check-prefix=MTUNE-VEYRON-V1 %s
// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu |
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
// Check mtune alias CPU has resolved to the right CPU according XLEN.
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck
-check-prefix=MTUNE-GENERIC-32 %s
// MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74,
sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54,
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-s21, sifive-s51, sifive-s54,
[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
dtcxzyw wrote:
Posted as #70241.
https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/70232 [XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source high-performance RISC-V processor. This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the XiangShan processor series. Overview: https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/ It is based on the patch [D122556](https://reviews.llvm.org/D122556) by @SForeKeeper. The original patch hasn't been updated for a long time and it is out of sync with the current RTL design. Now ICT-CAS is about to complete the tape-out of NanHu core according to @poemonsense. So I posted this PR to add support for it. [Move elimination](https://github.com/dtcxzyw/llvm-project/commit/59f6e22bf12f67d799af641853fec76c0aa8#diff-32270ea35a510b9a116a50cf5b922c46c194da7b0e0afe76576b8b2bef06556d) and macro fusions will be supported in subsequent PRs. >From 46644679be9cf1d2fdb75c70a27aefc1fd1488da Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Thu, 26 Oct 2023 00:23:32 +0800 Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu Co-authored-by: SForeKeeper --- clang/test/Driver/riscv-cpus.c| 14 + clang/test/Misc/target-invalid-cpu-note.c | 4 +- llvm/lib/Target/RISCV/RISCV.td| 1 + llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 2 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 21 + llvm/lib/Target/RISCV/RISCVSchedRocket.td | 2 + llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 2 + .../Target/RISCV/RISCVSchedSyntacoreSCR1.td | 2 + .../Target/RISCV/RISCVSchedXiangShanNanHu.td | 307 ++ llvm/lib/Target/RISCV/RISCVSchedule.td| 2 + .../llvm-mca/RISCV/XiangShan/cascade-fma.s| 53 ++ .../llvm-mca/RISCV/XiangShan/gpr-bypass.s | 527 ++ .../llvm-mca/RISCV/XiangShan/load-to-alu.s| 73 +++ 14 files changed, 1008 insertions(+), 4 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 3eaceedce685fc6..70f0a63336bd478 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -20,6 +20,17 @@ // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s +// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh" +// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval" +// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d" + // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s @@ -62,6 +73,9 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s +// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" + // Check mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s // MTUNE-GENERIC-32: "-tune-cpu" "generic" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index b2a04ebdbce628f..8e91eb4c62dd259 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -85,7 +85,7 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -//
[clang] [Clang] Handle real and imaginary parts of complex lvalue in `APValue::printPretty` (PR #69252)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/69252 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Handle real and imaginary parts of complex lvalue in `APValue::printPretty` (PR #69252)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 6e34e74e8e8046aaa086869e8a8aecb781dd3b3b Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/test/CodeGen/complex.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index 6233529a18f8b8d..b50d607d00c0167 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,3 +113,8 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
+// PR69218
+int t10(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
>From 07a9bd8da0602bedc7603752a3af26f89d3e9a2b Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:19:11 +0800
Subject: [PATCH 2/3] [Clang] Handle real and imaginary part of complex lvalue
in `APValue::printPretty`
---
clang/lib/AST/APValue.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/AST/APValue.cpp b/clang/lib/AST/APValue.cpp
index ef424215182280b..d08c2936b56dd45 100644
--- a/clang/lib/AST/APValue.cpp
+++ b/clang/lib/AST/APValue.cpp
@@ -841,6 +841,10 @@ void APValue::printPretty(raw_ostream , const
PrintingPolicy ,
Out << *VD;
ElemTy = VD->getType();
}
+ } else if (ElemTy->isAnyComplexType()) {
+// The lvalue refers to a complex type
+Out << (Path[I].getAsArrayIndex() == 0 ? ".real" : ".imag");
+ElemTy = ElemTy->castAs()->getElementType();
} else {
// The lvalue must refer to an array.
Out << '[' << Path[I].getAsArrayIndex() << ']';
>From b6ad30530cba4aaa94002691b97208abdb24533e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 23 Oct 2023 20:20:40 +0800
Subject: [PATCH 3/3] fixup! [Clang] Handle real and imaginary part of complex
lvalue in `APValue::printPretty`
Add release notes.
Move the test from CodeGen to Sema.
---
clang/docs/ReleaseNotes.rst| 2 ++
clang/test/CodeGen/complex.c | 5 -
clang/test/Sema/complex-imag.c | 6 ++
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1315eaffcd4850e..c292e012c4548d9 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -474,6 +474,8 @@ Bug Fixes in This Version
- Clang now accepts anonymous members initialized with designated initializers
inside templates.
Fixes (`#65143 `_)
+- Fix crash in formatting the real/imaginary part of a complex lvalue.
+ Fixes (`#69218 `_)
Bug Fixes to Compiler Builtins
^^
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index b50d607d00c0167..6233529a18f8b8d 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,8 +113,3 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
-// PR69218
-int t10(void) {
- float _Complex a;
- return (0 < &__real__ a) && (0 < &__imag__ a);
-}
diff --git a/clang/test/Sema/complex-imag.c b/clang/test/Sema/complex-imag.c
index 69121271f4b7876..8014addf4d3a40c 100644
--- a/clang/test/Sema/complex-imag.c
+++ b/clang/test/Sema/complex-imag.c
@@ -27,3 +27,9 @@ void f4(void) {
double *c = &__real a;
double *d = &__imag a;
}
+
+// PR69218
+int f5(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
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[clang] [Clang] Handle real and imaginary parts of complex lvalue in `APValue::printPretty` (PR #69252)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/test/CodeGen/complex.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index 6233529a18f8b8d..b50d607d00c0167 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,3 +113,8 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
+// PR69218
+int t10(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
>From c76a511cf1ad72eff3725bf24700f00a2f6fc014 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:19:11 +0800
Subject: [PATCH 2/3] [Clang] Handle real and imaginary part of complex lvalue
in `APValue::printPretty`
---
clang/lib/AST/APValue.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/AST/APValue.cpp b/clang/lib/AST/APValue.cpp
index ef424215182280b..d08c2936b56dd45 100644
--- a/clang/lib/AST/APValue.cpp
+++ b/clang/lib/AST/APValue.cpp
@@ -841,6 +841,10 @@ void APValue::printPretty(raw_ostream , const
PrintingPolicy ,
Out << *VD;
ElemTy = VD->getType();
}
+ } else if (ElemTy->isAnyComplexType()) {
+// The lvalue refers to a complex type
+Out << (Path[I].getAsArrayIndex() == 0 ? ".real" : ".imag");
+ElemTy = ElemTy->castAs()->getElementType();
} else {
// The lvalue must refer to an array.
Out << '[' << Path[I].getAsArrayIndex() << ']';
>From 5020b3ffbaedc0b9bb6e820259b69ccbb6f95436 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 23 Oct 2023 20:20:40 +0800
Subject: [PATCH 3/3] fixup! [Clang] Handle real and imaginary part of complex
lvalue in `APValue::printPretty`
Add release notes.
Move the test from CodeGen to Sema.
---
clang/docs/ReleaseNotes.rst| 2 ++
clang/test/CodeGen/complex.c | 5 -
clang/test/Sema/complex-imag.c | 6 ++
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 9782c123f4c9372..a49162f2845e802 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -397,6 +397,8 @@ Bug Fixes in This Version
operator in C. No longer issuing a confusing diagnostic along the lines of
"incompatible operand types ('foo' and 'foo')" with extensions such as matrix
types. Fixes (`#69008 `_)
+- Fix crash in formatting the real/imaginary part of a complex lvalue.
+ Fixes (`#69218 `_)
Bug Fixes to Compiler Builtins
^^
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index b50d607d00c0167..6233529a18f8b8d 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,8 +113,3 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
-// PR69218
-int t10(void) {
- float _Complex a;
- return (0 < &__real__ a) && (0 < &__imag__ a);
-}
diff --git a/clang/test/Sema/complex-imag.c b/clang/test/Sema/complex-imag.c
index 69121271f4b7876..8014addf4d3a40c 100644
--- a/clang/test/Sema/complex-imag.c
+++ b/clang/test/Sema/complex-imag.c
@@ -27,3 +27,9 @@ void f4(void) {
double *c = &__real a;
double *d = &__imag a;
}
+
+// PR69218
+int f5(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
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[clang] [Clang] Handle real and imaginary parts of complex lvalue in `APValue::printPretty` (PR #69252)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/test/CodeGen/complex.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index 6233529a18f8b8d..b50d607d00c0167 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,3 +113,8 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
+// PR69218
+int t10(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
>From c76a511cf1ad72eff3725bf24700f00a2f6fc014 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:19:11 +0800
Subject: [PATCH 2/3] [Clang] Handle real and imaginary part of complex lvalue
in `APValue::printPretty`
---
clang/lib/AST/APValue.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/AST/APValue.cpp b/clang/lib/AST/APValue.cpp
index ef424215182280b..d08c2936b56dd45 100644
--- a/clang/lib/AST/APValue.cpp
+++ b/clang/lib/AST/APValue.cpp
@@ -841,6 +841,10 @@ void APValue::printPretty(raw_ostream , const
PrintingPolicy ,
Out << *VD;
ElemTy = VD->getType();
}
+ } else if (ElemTy->isAnyComplexType()) {
+// The lvalue refers to a complex type
+Out << (Path[I].getAsArrayIndex() == 0 ? ".real" : ".imag");
+ElemTy = ElemTy->castAs()->getElementType();
} else {
// The lvalue must refer to an array.
Out << '[' << Path[I].getAsArrayIndex() << ']';
>From f4a026599226b1742f9bab4c6899bffc6cae92de Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 23 Oct 2023 20:20:40 +0800
Subject: [PATCH 3/3] fixup! [Clang] Handle real and imaginary part of complex
lvalue in `APValue::printPretty`
Add release notes.
Move the test from CodeGen to Sema.
---
clang/docs/ReleaseNotes.rst| 2 ++
clang/test/CodeGen/complex.c | 6 --
clang/test/Sema/complex-imag.c | 6 ++
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 9782c123f4c9372..a49162f2845e802 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -397,6 +397,8 @@ Bug Fixes in This Version
operator in C. No longer issuing a confusing diagnostic along the lines of
"incompatible operand types ('foo' and 'foo')" with extensions such as matrix
types. Fixes (`#69008 `_)
+- Fix crash in formatting the real/imaginary part of a complex lvalue.
+ Fixes (`#69218 `_)
Bug Fixes to Compiler Builtins
^^
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index b50d607d00c0167..455c81abb86fd2a 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -112,9 +112,3 @@ void t92(void) {
// Check for proper codegen
(0 ? (_Complex double) 2.0f : 2.0f);
}
-
-// PR69218
-int t10(void) {
- float _Complex a;
- return (0 < &__real__ a) && (0 < &__imag__ a);
-}
diff --git a/clang/test/Sema/complex-imag.c b/clang/test/Sema/complex-imag.c
index 69121271f4b7876..8014addf4d3a40c 100644
--- a/clang/test/Sema/complex-imag.c
+++ b/clang/test/Sema/complex-imag.c
@@ -27,3 +27,9 @@ void f4(void) {
double *c = &__real a;
double *d = &__imag a;
}
+
+// PR69218
+int f5(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
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[clang-tools-extra] [ConstantRange] Handle `Intrinsic::cttz` (PR #67917)
dtcxzyw wrote: @nikic Any comments about this PR? https://github.com/llvm/llvm-project/pull/67917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ConstantRange] Handle `Intrinsic::cttz` (PR #67917)
dtcxzyw wrote: @nikic Any comments about this PR? https://github.com/llvm/llvm-project/pull/67917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [ConstantRange] Handle `Intrinsic::cttz` (PR #67917)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/67917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [ConstantRange] Handle `Intrinsic::cttz` (PR #67917)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/67917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [InstCombine] Add combines/simplifications for `llvm.ptrmask` (PR #67166)
@@ -6411,6 +6411,41 @@ static Value *simplifyBinaryIntrinsic(Function *F, Value
*Op0, Value *Op1,
return Constant::getNullValue(ReturnType);
break;
}
+ case Intrinsic::ptrmask: {
+if (isa(Op0) || isa(Op1))
+ return PoisonValue::get(Op0->getType());
+
+// NOTE: We can't apply this simplifications based on the value of Op1
+// because we need to preserve provenance.
+if (Q.isUndefValue(Op0) || match(Op0, m_Zero()))
+ return Constant::getNullValue(Op0->getType());
+
+if (Op1->getType()->getScalarSizeInBits() ==
+Q.DL.getPointerTypeSizeInBits(Op0->getType())) {
+ if (match(Op1, m_PtrToInt(m_Specific(Op0
+return Op0;
+
+ // NOTE: We may have attributes associated with the return value of the
+ // llvm.ptrmask intrinsic that will be lost when we just return the
+ // operand. We should try to preserve them.
+ if (match(Op1, m_AllOnes()) || Q.isUndefValue(Op1))
+return Op0;
+
+ Constant *C;
+ if (match(Op1, m_ImmConstant(C))) {
+KnownBits PtrKnown =
+computeKnownBits(Op0, Q.DL, /*Depth=*/0, Q.AC, Q.CxtI, Q.DT);
dtcxzyw wrote:
```suggestion
KnownBits PtrKnown = computeKnownBits(Op0, /*Depth=*/0, Q);
```
See also new ValueTracking helper functions introduced by
be57381a4a08b0b6a89d5b5fdec0880b202e99f4.
https://github.com/llvm/llvm-project/pull/67166
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[clang] [Clang] Handle real and imaginary parts of complex lvalue in `APValue::printPretty` (PR #69252)
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/69252
This patch handles formatting of real and imaginary parts of complex lvalue.
Fixes #69218.
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/2] [Clang] Add pre-commit tests for PR69218. NFC.
---
clang/test/CodeGen/complex.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/clang/test/CodeGen/complex.c b/clang/test/CodeGen/complex.c
index 6233529a18f8b8d..b50d607d00c0167 100644
--- a/clang/test/CodeGen/complex.c
+++ b/clang/test/CodeGen/complex.c
@@ -113,3 +113,8 @@ void t92(void) {
(0 ? (_Complex double) 2.0f : 2.0f);
}
+// PR69218
+int t10(void) {
+ float _Complex a;
+ return (0 < &__real__ a) && (0 < &__imag__ a);
+}
>From c76a511cf1ad72eff3725bf24700f00a2f6fc014 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:19:11 +0800
Subject: [PATCH 2/2] [Clang] Handle real and imaginary part of complex lvalue
in `APValue::printPretty`
---
clang/lib/AST/APValue.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/AST/APValue.cpp b/clang/lib/AST/APValue.cpp
index ef424215182280b..d08c2936b56dd45 100644
--- a/clang/lib/AST/APValue.cpp
+++ b/clang/lib/AST/APValue.cpp
@@ -841,6 +841,10 @@ void APValue::printPretty(raw_ostream , const
PrintingPolicy ,
Out << *VD;
ElemTy = VD->getType();
}
+ } else if (ElemTy->isAnyComplexType()) {
+// The lvalue refers to a complex type
+Out << (Path[I].getAsArrayIndex() == 0 ? ".real" : ".imag");
+ElemTy = ElemTy->castAs()->getElementType();
} else {
// The lvalue must refer to an array.
Out << '[' << Path[I].getAsArrayIndex() << ']';
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[clang-tools-extra] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
dtcxzyw wrote: Ping. https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 411ceac - [Clang] Fix tautological assertion in `Sema::CheckX86BuiltinTileDuplicate`
Author: Yingwei Zheng Date: 2023-10-13T15:19:35+08:00 New Revision: 411ceacf4351bd3af9db75b859063864b19e71e1 URL: https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1 DIFF: https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1.diff LOG: [Clang] Fix tautological assertion in `Sema::CheckX86BuiltinTileDuplicate` Closes #68958. Added: Modified: clang/lib/Sema/SemaChecking.cpp Removed: diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 1b2f8cf296d16b6..cd61459cfbb13d6 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6047,7 +6047,7 @@ bool Sema::CheckX86BuiltinTileDuplicate(CallExpr *TheCall, if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) return true; int ArgExtValue = Result.getExtValue(); -assert((ArgExtValue >= TileRegLow || ArgExtValue <= TileRegHigh) && +assert((ArgExtValue >= TileRegLow && ArgExtValue <= TileRegHigh) && "Incorrect tile register num."); if (ArgValues.test(ArgExtValue)) return Diag(TheCall->getBeginLoc(), ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y` when Y is a power of 2 (PR #67915)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/67915 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
dtcxzyw wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
dtcxzyw wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Fix the condition of checking signature in getIndex (PR #67403)
https://github.com/dtcxzyw approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/67403 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [InstCombine] Simplify the pattern `a ne/eq (zext/sext (a ne/eq c))` (PR #65852)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/65852 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [InstCombine] Simplify the pattern `a ne/eq (zext/sext (a ne/eq c))` (PR #65852)
https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/65852 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y` when Y is a power of 2 (PR #67915)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH 1/2] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y`
when Y is a power of 2
---
.../InstCombine/InstCombineAndOrXor.cpp | 8
llvm/test/Transforms/InstCombine/and.ll | 44 +--
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index cbdab3e9c5fb91d..4322cc96f5a2b6c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2250,6 +2250,14 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator
) {
return SelectInst::Create(Cmp, ConstantInt::getNullValue(Ty), Y);
}
+ // Canonicalize:
+ // (X +/- Y) & Y --> ~X & Y when Y is a power of 2.
+ if (match(, m_c_And(m_Value(Y), m_OneUse(m_CombineOr(
+m_c_Add(m_Value(X), m_Deferred(Y)),
+m_Sub(m_Value(X), m_Deferred(Y)) &&
+ isKnownToBeAPowerOfTwo(Y, /*OrZero*/ true, /*Depth*/ 0, ))
+return BinaryOperator::CreateAnd(Builder.CreateNot(X), Y);
+
const APInt *C;
if (match(Op1, m_APInt(C))) {
const APInt *XorC;
diff --git a/llvm/test/Transforms/InstCombine/and.ll
b/llvm/test/Transforms/InstCombine/and.ll
index 90f027010e2aea6..eb39ff9014ff3a4 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -1595,8 +1595,8 @@ define <2 x i8> @flip_masked_bit_uniform(<2 x i8> %A) {
define <2 x i8> @flip_masked_bit_undef(<2 x i8> %A) {
; CHECK-LABEL: @flip_masked_bit_undef(
-; CHECK-NEXT:[[B:%.*]] = add <2 x i8> [[A:%.*]],
-; CHECK-NEXT:[[C:%.*]] = and <2 x i8> [[B]],
+; CHECK-NEXT:[[TMP1:%.*]] = xor <2 x i8> [[A:%.*]],
+; CHECK-NEXT:[[C:%.*]] = and <2 x i8> [[TMP1]],
; CHECK-NEXT:ret <2 x i8> [[C]]
;
%B = add <2 x i8> %A,
@@ -1606,8 +1606,8 @@ define <2 x i8> @flip_masked_bit_undef(<2 x i8> %A) {
define <2 x i8> @flip_masked_bit_nonuniform(<2 x i8> %A) {
; CHECK-LABEL: @flip_masked_bit_nonuniform(
-; CHECK-NEXT:[[B:%.*]] = add <2 x i8> [[A:%.*]],
-; CHECK-NEXT:[[C:%.*]] = and <2 x i8> [[B]],
+; CHECK-NEXT:[[TMP1:%.*]] = xor <2 x i8> [[A:%.*]],
+; CHECK-NEXT:[[C:%.*]] = and <2 x i8> [[TMP1]],
; CHECK-NEXT:ret <2 x i8> [[C]]
;
%B = add <2 x i8> %A,
@@ -2546,3 +2546,39 @@ define i32 @and_zext_eq_zero(i32 %A, i32 %C) {
%5 = and i32 %2, %4
ret i32 %5
}
+
+define i32 @canonicalize_and_add_power2_or_zero(i32 %x, i32 %y) {
+; CHECK-LABEL: @canonicalize_and_add_power2_or_zero(
+; CHECK-NEXT:[[NY:%.*]] = sub i32 0, [[Y:%.*]]
+; CHECK-NEXT:[[P2:%.*]] = and i32 [[NY]], [[Y]]
+; CHECK-NEXT:call void @use32(i32 [[P2]])
+; CHECK-NEXT:[[TMP1:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT:[[AND:%.*]] = and i32 [[P2]], [[TMP1]]
+; CHECK-NEXT:ret i32 [[AND]]
+;
+ %ny = sub i32 0, %y
+ %p2 = and i32 %y, %ny
+ call void @use32(i32 %p2) ; keep p2
+
+ %val = add i32 %x, %p2
+ %and = and i32 %val, %p2
+ ret i32 %and
+}
+
+define i32 @canonicalize_and_sub_power2_or_zero(i32 %x, i32 %y) {
+; CHECK-LABEL: @canonicalize_and_sub_power2_or_zero(
+; CHECK-NEXT:[[NY:%.*]] = sub i32 0, [[Y:%.*]]
+; CHECK-NEXT:[[P2:%.*]] = and i32 [[NY]], [[Y]]
+; CHECK-NEXT:call void @use32(i32 [[P2]])
+; CHECK-NEXT:[[TMP1:%.*]] = xor i32 [[X:%.*]], -1
+; CHECK-NEXT:[[AND:%.*]] = and i32 [[P2]], [[TMP1]]
+; CHECK-NEXT:ret i32 [[AND]]
+;
+ %ny = sub i32 0, %y
+ %p2 = and i32 %y, %ny
+ call void @use32(i32 %p2) ; keep p2
+
+ %val = sub i32 %x, %p2
+ %and = and i32 %val, %p2
+ ret i32 %and
+}
>From b64ca5b5f743e6a935f4ea09154c3a08c6e65c47 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Fri, 6 Oct 2023 17:32:46 +0800
Subject: [PATCH 2/2] fixup! [InstCombine] Canonicalize `(X +/- Y) & Y` into
`~X & Y` when Y is a power of 2
Add additional tests.
---
llvm/test/Transforms/InstCombine/and.ll | 123
1 file changed, 123 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/and.ll
b/llvm/test/Transforms/InstCombine/and.ll
index eb39ff9014ff3a4..989640ed41f2d2e 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -2582,3 +2582,126 @@ define i32 @canonicalize_and_sub_power2_or_zero(i32 %x,
i32 %y) {
%and = and i32 %val, %p2
ret i32 %and
}
+
+define i32 @canonicalize_and_add_power2_or_zero_commuted1(i32 %x, i32 %y) {
+; CHECK-LABEL: @canonicalize_and_add_power2_or_zero_commuted1(
+; CHECK-NEXT:[[NY:%.*]] = sub i32 0, [[Y:%.*]]
+; CHECK-NEXT:[[P2:%.*]] = and i32 [[NY]], [[Y]]
+; CHECK-NEXT:call void @use32(i32 [[P2]])
+; CHECK-NEXT:[[TMP1:%.*]] = xor i32 [[X:%.*]],
