RE: [PATCH 1/7] drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.

[Zhu, Rex]

Hi Gražvydas,

Only in case dpm was disabled, we didn't initialize hwmgr and hwmgr->hwmgr_func.
In this case, we just use smu to load firmware. All the power feature will be 
disabled.
And the sysfs and debugfs files will not be initialized.


Best Regards
Rex
-Original Message-
From: Grazvydas Ignotas [mailto:nota...@gmail.com] 
Sent: Wednesday, November 02, 2016 9:17 PM
To: Zhu, Rex
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/7] drm/amdgpu/powerplay: pp module only enable smu when 
dpm disabled.

On Wed, Nov 2, 2016 at 12:27 PM, Rex Zhu  wrote:
> Change-Id: I3288a5a4bbca122d59b81e7635be5e5aeda8abeb
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  6 +--
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 51 
> +--
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  2 +
>  3 files changed, 44 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index fa6baf3..e2f0507 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle)
> ret = adev->powerplay.ip_funcs->sw_init(
> adev->powerplay.pp_handle);
>
> -   if (adev->pp_enabled)
> -   adev->pm.dpm_enabled = true;
> -
> return ret;
>  }
>
> @@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle)
> ret = adev->powerplay.ip_funcs->hw_init(
> adev->powerplay.pp_handle);
>
> +   if (amdgpu_dpm != 0)
> +   adev->pm.dpm_enabled = true;
> +
> return ret;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 1f49764..4a4f97b 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -41,7 +41,7 @@
>  #define PP_CHECK_HW(hwmgr) \
> do {\
> if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
> -   return -EINVAL; \
> +   return 0;   \

Is that really the right thing to do? With it functions like
pp_dpm_get_fan_speed_percent() pp_dpm_read_sensor() will succeed but not set 
the values and callers will use uninitialized data (leak kernel stack contents, 
so it can be considered a security issue even).

Gražvydas
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RE: [PATCH 0/7] mise patches for powerplay module

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, November 02, 2016 6:28 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 0/7] mise patches for powerplay module
> 
> 
> Rex Zhu (7):
>   drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.
>   drm/amd/powerplay: use mask bit for deepsleep/power tune feature.
>   drm/amdgpu: use mask bit for deep sleep feature on dpm.
>   drm/amdgpu: delete duplicate module parameter.
>   drm/amd/powerplay: fix code style
>   drm/amd/powerplay: enable voltage control by default for dgpu.
>   drm/amd/powerplay: delete duplicate code in smu7_hwmgr.c

Series is:
Reviewed-by: Alex Deucher 

> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 14 +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c  |  6 +--
>  drivers/gpu/drm/amd/amdgpu/ci_dpm.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/cz_dpm.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/kv_dpm.c|  2 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 51
> +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 13 +++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  7 ---
>  .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c   |  5 ++-
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  2 +
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 -
>  13 files changed, 66 insertions(+), 46 deletions(-)
> 
> --
> 1.9.1
> 
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RE: [1/4] amdgpu: add the function to get the marketing name (v2)

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, November 01, 2016 11:51 PM
> To: Alex Deucher
> Cc: Zhang, Jerry; amd-gfx@lists.freedesktop.org
> Subject: Re: [1/4] amdgpu: add the function to get the marketing name (v2)
> 
> On 01/11/16 06:34 PM, Michel Dänzer wrote:
> > On 13/09/16 12:14 AM, Alex Deucher wrote:
> >> From: Junwei Zhang 
> >>
> >> This function is used to look up the marking name
> >> for a specific board.
> >>
> >> v2: agd: Squash in subsequent updates to the table.
> >
> > As is, this breaks make check:
> >
> >
> >> +struct amdgpu_asic_id_table_t {
> >
> > Make this static, so the amdgpu_asic_id_table_t symbol doesn't get
> > exported from libdrm_amdgpu.
> >
> > BTW, is there any particular reason for putting this table in a separate
> > header file?
> >
> >
> >> @@ -303,3 +304,17 @@ int
> amdgpu_device_deinitialize(amdgpu_device_handle dev)
> >>amdgpu_device_reference(, NULL);
> >>return 0;
> >>  }
> >> +
> >> +const char *amdgpu_get_marketing_name(amdgpu_device_handle
> dev)
> >
> > amdgpu_get_marketing_name needs to be added to amdgpu-symbols-
> check.
> >
> >
> >> +  if ((t->did == dev->info.asic_id) &&
> >> +  (t->rid == dev->info.pci_rev_id))
> >
> > Wrong indentation of the second line.
> >
> >
> > With these issues fixed,
> >
> > Reviewed-by: Michel Dänzer 
> >
> > Would be nice to land this in master soon, as we're going to use it in
> > xf86-video-amdgpu: https://patchwork.freedesktop.org/patch/119501/
> 
> Junwei, if it's okay with you, I can amend the patch and push it to master.

You might double check the internal git tree and pick up any additional 
marketing names that were added since I pulled those patches.

Alex

> 
> 
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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RE: [PATCH xf86-video-amdgpu] Check Xorg version at runtime instead of build time in two places

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, November 01, 2016 11:44 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-amdgpu] Check Xorg version at runtime instead
> of build time in two places
> 
> From: Michel Dänzer 
> 
> This means that all possible paths can be handled as intended, no matter
> which Xorg version the driver happened to be compiled against.
> 
> (Ported from radeon commit 350a2645a1b127227ff294c0b62d2d0fd48a)
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  man/amdgpu.man| 2 +-
>  src/amdgpu_kms.c  | 6 +-
>  src/drmmode_display.c | 8 
>  3 files changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/man/amdgpu.man b/man/amdgpu.man
> index 93244a4..948cd70 100644
> --- a/man/amdgpu.man
> +++ b/man/amdgpu.man
> @@ -65,7 +65,7 @@ will assign xrandr outputs LVDS and VGA-0 to this
> instance of the driver.
>  Define the maximum level of DRI to enable. Valid values are 2 for DRI2 or 3
> for DRI3.
>  The default is
>  .B 3 for DRI3
> -if the driver was compiled for Xorg >= 1.18.3, otherwise
> +if the Xorg version is >= 1.18.3, otherwise
>  .B 2 for DRI2.
>  .TP
>  .BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index acf3a7d..b21cd37 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -1713,11 +1713,7 @@ Bool
> AMDGPUScreenInit_KMS(SCREEN_INIT_ARGS_DECL)
>   }
>  #endif
> 
> -#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,18,3,0,0)
> - value = TRUE;
> -#else
> - value = FALSE;
> -#endif
> + value = xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0);
>   from = X_DEFAULT;
> 
>   if (info->use_glamor) {
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index f514866..2d36881 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -607,10 +607,10 @@ drmmode_can_use_hw_cursor(xf86CrtcPtr crtc)
>   return FALSE;
>  #endif
> 
> -#if defined(AMDGPU_PIXMAP_SHARING) && \
> - XORG_VERSION_CURRENT <=
> XORG_VERSION_NUMERIC(1,18,99,901,0)
> - /* HW cursor not supported with RandR 1.4 multihead */
> - if (!xorg_list_is_empty(>scrn->pScreen->pixmap_dirty_list))
> +#if defined(AMDGPU_PIXMAP_SHARING)
> + /* HW cursor not supported with RandR 1.4 multihead up to
> 1.18.99.901 */
> + if (xorgGetVersion() <= XORG_VERSION_NUMERIC(1,18,99,901,0)
> &&
> + !xorg_list_is_empty(>scrn->pScreen->pixmap_dirty_list))
>   return FALSE;
>  #endif
> 
> --
> 2.10.2
> 
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Re: [PATCH 1/7] drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.

[Grazvydas Ignotas]

On Wed, Nov 2, 2016 at 12:27 PM, Rex Zhu  wrote:
> Change-Id: I3288a5a4bbca122d59b81e7635be5e5aeda8abeb
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  6 +--
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 51 
> +--
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  2 +
>  3 files changed, 44 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index fa6baf3..e2f0507 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle)
> ret = adev->powerplay.ip_funcs->sw_init(
> adev->powerplay.pp_handle);
>
> -   if (adev->pp_enabled)
> -   adev->pm.dpm_enabled = true;
> -
> return ret;
>  }
>
> @@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle)
> ret = adev->powerplay.ip_funcs->hw_init(
> adev->powerplay.pp_handle);
>
> +   if (amdgpu_dpm != 0)
> +   adev->pm.dpm_enabled = true;
> +
> return ret;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 1f49764..4a4f97b 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -41,7 +41,7 @@
>  #define PP_CHECK_HW(hwmgr) \
> do {\
> if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
> -   return -EINVAL; \
> +   return 0;   \

Is that really the right thing to do? With it functions like
pp_dpm_get_fan_speed_percent() pp_dpm_read_sensor() will succeed but
not set the values and callers will use uninitialized data (leak
kernel stack contents, so it can be considered a security issue even).

Gražvydas
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Re: [PATCH v2] drm/amdgpu:no gpu scheduler for KIQ

[Christian König]

Am 02.11.2016 um 12:48 schrieb Trigger Huang:

KIQ is used for interaction between driver and
CP, and not exposed to outside client, as such it
doesn't need to be handled by GPU scheduler.

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Signed-off-by: Trigger Huang 


Even if you only fix a small mistake it is usually good practice to 
increase the version number of the patch, e.g. you would use v3 in this 
case and write a one liner what was wrong in the commit message.


But that's only a nit pick, so patch is Reviewed-by: Christian König 
 anyway.


Regards,
Christian.



Changes in v2:
  - According to Alex's suggestion, wrapping the scheduler setup
conditionally instead of returning early.
  - Use another simple method to check if is a KIQ ring.

---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 39 +--
  1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 77b34ec..5772ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring 
*ring,
if (!ring->fence_drv.fences)
return -ENOMEM;
  
-	timeout = msecs_to_jiffies(amdgpu_lockup_timeout);

-   if (timeout == 0) {
-   /*
-* FIXME:
-* Delayed workqueue cannot use it directly,
-* so the scheduler will not use delayed workqueue if
-* MAX_SCHEDULE_TIMEOUT is set.
-* Currently keep it simple and silly.
-*/
-   timeout = MAX_SCHEDULE_TIMEOUT;
-   }
-   r = amd_sched_init(>sched, _sched_ops,
-  num_hw_submission,
-  timeout, ring->name);
-   if (r) {
-   DRM_ERROR("Failed to create scheduler on ring %s.\n",
- ring->name);
-   return r;
+   /* No need to setup the GPU scheduler for KIQ ring */
+   if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
+   timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
+   if (timeout == 0) {
+   /*
+* FIXME:
+* Delayed workqueue cannot use it directly,
+* so the scheduler will not use delayed workqueue if
+* MAX_SCHEDULE_TIMEOUT is set.
+* Currently keep it simple and silly.
+*/
+   timeout = MAX_SCHEDULE_TIMEOUT;
+   }
+   r = amd_sched_init(>sched, _sched_ops,
+  num_hw_submission,
+  timeout, ring->name);
+   if (r) {
+   DRM_ERROR("Failed to create scheduler on ring %s.\n",
+ ring->name);
+   return r;
+   }
}
  
  	return 0;



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[PATCH V2] drm/amdgpu:bypass avfs event manager for sriov

[Trigger Huang]

This patch is used for virtualization support. In virtualization case,
the initialization sequences are not totally the same as
non-Virtualization's. The avfs event manager should be bypassed if in
SRIOV virtualization case. At the same, this patch will also bypass
starting SMC within SRIOV in FIJI, so the SMU firmware loading will be
avoid, which is required in SRIOV.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang Yu 
Signed-off-by: Trigger Huang 

Changes in v2:
 - Modify the commit log. This patch will also bypass starting SMC
   within SRIOV in FIJI. The same operation will be applied on Tonga
   in the other patch.

---
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index b86e48f..26eff56 100755
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -396,7 +396,8 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 
/* Only start SMC if SMC RAM is not running */
-   if (!smu7_is_smc_ram_running(smumgr)) {
+   if (!(smu7_is_smc_ram_running(smumgr)
+   || cgs_is_virtualization_enabled(smumgr->device))) {
fiji_avfs_event_mgr(smumgr, false);
 
/* Check if SMU is running in protected mode */
@@ -443,6 +444,9 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr 
*smumgr)
uint32_t efuse = 0;
uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
 
+   if (cgs_is_virtualization_enabled(smumgr->device))
+   return 0;
+
if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
mask, )) {
if (efuse)
-- 
2.7.4

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RE: [V2] drm/amdgpu:no gpu scheduler for KIQ

[Huang, Trigger]

Sorry please just ignore this patch, since I made a small mistake, I will sent 
again soon.

Thanks & Best Wishes,
Trigger Huang

-Original Message-
From: Trigger Huang [mailto:trigger.hu...@amd.com] 
Sent: Wednesday, November 02, 2016 7:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Trigger ; Liu, Monk ; Yu, 
Xiangliang 
Subject: [V2] drm/amdgpu:no gpu scheduler for KIQ

KIQ is used for interaction between driver and CP, and not exposed to outside 
client, as such it doesn't need to be handled by GPU scheduler.

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Signed-off-by: Trigger Huang 

Changes in v2:
 - According to Alex's suggestion, wrapping the scheduler setup
   conditionally instead of returning early.
 - Use another simple method to check if is a KIQ ring.

Change-Id: Iba09b6dfb6515e5de5fc48c4e8904e8a0ec5f22b
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 39 +--
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 77b34ec..5772ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring 
*ring,
if (!ring->fence_drv.fences)
return -ENOMEM;
 
-   timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
-   if (timeout == 0) {
-   /*
-* FIXME:
-* Delayed workqueue cannot use it directly,
-* so the scheduler will not use delayed workqueue if
-* MAX_SCHEDULE_TIMEOUT is set.
-* Currently keep it simple and silly.
-*/
-   timeout = MAX_SCHEDULE_TIMEOUT;
-   }
-   r = amd_sched_init(>sched, _sched_ops,
-  num_hw_submission,
-  timeout, ring->name);
-   if (r) {
-   DRM_ERROR("Failed to create scheduler on ring %s.\n",
- ring->name);
-   return r;
+   /* No need to setup the GPU scheduler for KIQ ring */
+   if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
+   timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
+   if (timeout == 0) {
+   /*
+* FIXME:
+* Delayed workqueue cannot use it directly,
+* so the scheduler will not use delayed workqueue if
+* MAX_SCHEDULE_TIMEOUT is set.
+* Currently keep it simple and silly.
+*/
+   timeout = MAX_SCHEDULE_TIMEOUT;
+   }
+   r = amd_sched_init(>sched, _sched_ops,
+  num_hw_submission,
+  timeout, ring->name);
+   if (r) {
+   DRM_ERROR("Failed to create scheduler on ring %s.\n",
+ ring->name);
+   return r;
+   }
}
 
return 0;
--
2.7.4

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[PATCH 0/7] mise patches for powerplay module

[Rex Zhu]

Rex Zhu (7):
  drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.
  drm/amd/powerplay: use mask bit for deepsleep/power tune feature.
  drm/amdgpu: use mask bit for deep sleep feature on dpm.
  drm/amdgpu: delete duplicate module parameter.
  drm/amd/powerplay: fix code style
  drm/amd/powerplay: enable voltage control by default for dgpu.
  drm/amd/powerplay: delete duplicate code in smu7_hwmgr.c

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 14 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c  |  6 +--
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/cz_dpm.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c|  2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 51 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 13 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  7 ---
 .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c   |  5 ++-
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  2 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 -
 13 files changed, 66 insertions(+), 46 deletions(-)

-- 
1.9.1

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[PATCH 5/7] drm/amd/powerplay: fix code style

[Rex Zhu]

Change-Id: Idf3029dd61469c544c8431ba2220f61a21f98549
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 41b634f..26477f0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -603,9 +603,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t 
n)
return 0;
 }
 
-static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t 
target_tdp)
+static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
+   uint32_t target_tdp)
 {
-   return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
+   return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
 }
 
-- 
1.9.1

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[PATCH 7/7] drm/amd/powerplay: delete duplicate code in smu7_hwmgr.c

[Rex Zhu]

Voltage Controller have been enabled (SMC message)
before ULV enablement.

Change-Id: I4833c8d53611c8b93712254d5a152ae8e98a7d78
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a50765d..e220465 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -993,13 +993,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
SWRST_COMMAND_1, RESETLC, 0x0);
 
-   PP_ASSERT_WITH_CODE(
-   (0 == smum_send_msg_to_smc(hwmgr->smumgr,
-   PPSMC_MSG_Voltage_Cntl_Enable)),
-   "Failed to enable voltage DPM during DPM Start 
Function!",
-   return -EINVAL);
-
-
if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
return -EINVAL;
-- 
1.9.1

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[PATCH 6/7] drm/amd/powerplay: enable voltage control by default for dgpu.

[Rex Zhu]

Change-Id: I085da4cef174adb7b170dac03a684867b3d80044
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index febee26..356b7c4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct 
pp_instance *handle)
switch (hwmgr->chip_id) {
case CHIP_TOPAZ:
topaz_set_asic_special_caps(hwmgr);
-   hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-   PP_VBI_TIME_SUPPORT_MASK |
+   hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
hwmgr->pp_table_version = PP_TABLE_V0;
break;
case CHIP_TONGA:
tonga_set_asic_special_caps(hwmgr);
-   hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-   PP_VBI_TIME_SUPPORT_MASK);
+   hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
break;
case CHIP_FIJI:
fiji_set_asic_special_caps(hwmgr);
-   hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-   PP_VBI_TIME_SUPPORT_MASK |
+   hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
break;
case CHIP_POLARIS11:
-- 
1.9.1

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[PATCH 4/7] drm/amdgpu: delete duplicate module parameter.

[Rex Zhu]

Change-Id: I8b05ce1ad9cd2898a18eba3fa5f5ae3ba3627a2f
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +++---
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8d0c689..fb535e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -94,13 +94,13 @@ extern int amdgpu_dal;
 extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
 extern int amdgpu_powerplay;
-extern int amdgpu_powercontainment;
+extern int amdgpu_no_evict;
+extern int amdgpu_direct_gma_size;
 extern unsigned amdgpu_pcie_gen_cap;
 extern unsigned amdgpu_pcie_lane_cap;
 extern unsigned amdgpu_cg_mask;
 extern unsigned amdgpu_pg_mask;
 extern char *amdgpu_disable_cu;
-extern int amdgpu_sclk_deep_sleep_en;
 extern char *amdgpu_virtual_display;
 extern unsigned amdgpu_pp_feature_mask;
 extern int amdgpu_vram_page_split;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index eb418a0..ef6d24f 100755
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -92,8 +92,8 @@ int amdgpu_dal = -1;
 int amdgpu_sched_jobs = 32;
 int amdgpu_sched_hw_submission = 2;
 int amdgpu_powerplay = -1;
-int amdgpu_powercontainment = 1;
-int amdgpu_sclk_deep_sleep_en = 1;
+int amdgpu_no_evict = 0;
+int amdgpu_direct_gma_size = 0;
 unsigned amdgpu_pcie_gen_cap = 0;
 unsigned amdgpu_pcie_lane_cap = 0;
 unsigned amdgpu_cg_mask = 0x;
@@ -186,14 +186,14 @@ module_param_named(sched_hw_submission, 
amdgpu_sched_hw_submission, int, 0444);
 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 
= auto (default))");
 module_param_named(powerplay, amdgpu_powerplay, int, 0444);
 
-MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 
= disable)");
-module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
-
 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
 
-MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = 
disable)");
-module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444);
+MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = 
enable, 0 = disable (default))");
+module_param_named(no_evict, amdgpu_no_evict, int, 0444);
+
+MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
+module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
 
 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
-- 
1.9.1

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[PATCH 2/7] drm/amd/powerplay: use mask bit for deepsleep/power tune feature.

[Rex Zhu]

Change-Id: I42a6b99634ac67eeef16361be949eb535d0a9b26
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++--
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 2ada52f..febee26 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -685,14 +685,14 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 
 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 {
-   if (amdgpu_sclk_deep_sleep_en)
+   if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
else
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
 
-   if (amdgpu_powercontainment) {
+   if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 36effa1..a57410b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -38,8 +38,6 @@ struct pp_hwmgr;
 struct phm_fan_speed_info;
 struct pp_atomctrl_voltage_table;
 
-extern int amdgpu_powercontainment;
-extern int amdgpu_sclk_deep_sleep_en;
 extern unsigned amdgpu_pp_feature_mask;
 
 #define VOLTAGE_SCALE 4
-- 
1.9.1

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[PATCH 3/7] drm/amdgpu: use mask bit for deep sleep feature on dpm.

[Rex Zhu]

Change-Id: Ie7a8392755089b0f1d78d94bf7ba59b682619b06
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 2 ++
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index e45bd05..955d6f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -52,6 +52,8 @@ enum amdgpu_dpm_event_src {
AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
 };
 
+#define SCLK_DEEP_SLEEP_MASK 0x8
+
 struct amdgpu_ps {
u32 caps; /* vbios flags */
u32 class; /* vbios flags */
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1caff75..bd690a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5896,7 +5896,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
pi->pcie_dpm_key_disabled = 0;
pi->thermal_sclk_dpm_enabled = 0;
 
-   if (amdgpu_sclk_deep_sleep_en)
+   if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 352b5fa..41fa351 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
pi->caps_td_ramping = true;
pi->caps_tcp_ramping = true;
}
-   if (amdgpu_sclk_deep_sleep_en)
+   if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 61172d4..5a1bc35 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
pi->caps_tcp_ramping = true;
}
 
-   if (amdgpu_sclk_deep_sleep_en)
+   if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
pi->caps_sclk_ds = true;
else
pi->caps_sclk_ds = false;
-- 
1.9.1

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