RE: [PATCH 1/4] drm/atomic: Save flip flags in drm_plane_state

2017-01-25 Thread Grodzovsky, Andrey 


> -Original Message-
> From: Cheng, Tony
> Sent: Monday, January 23, 2017 2:49 PM
> To: Daniel Vetter; Grodzovsky, Andrey
> Cc: Deucher, Alexander; nouv...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> daniel.vet...@intel.com; dc_upstream
> Subject: RE: [PATCH 1/4] drm/atomic: Save flip flags in drm_plane_state
> 
> 
> 
> > -Original Message-
> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On
> > Behalf Of Daniel Vetter
> > Sent: Monday, January 23, 2017 3:55 AM
> > To: Grodzovsky, Andrey 
> > Cc: Deucher, Alexander ;
> > nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; daniel.vet...@intel.com
> > Subject: Re: [PATCH 1/4] drm/atomic: Save flip flags in
> > drm_plane_state
> >
> > On Mon, Jan 16, 2017 at 10:44:55AM -0500, Andrey Grodzovsky wrote:
> > > Allows using atomic flip helpers for drivers using ASYNC flip.
> > > Remove ASYNC_FLIP restriction in helpers and caches the page flip
> > > flags in drm_plane_state to be used in the low level drivers.
> > >
> > > Signed-off-by: Andrey Grodzovsky 
> >
> > It's mostly guesswork, but I think we should have the flip flags in
> > the crtc, not in each plane. Similar to how we move the event from planes
> to crtc.
> > -Daniel
> 
Do you mean here crtc or crtc_state ?

> What does ASYNC flip mean?  HW flip as soon as possible and result in tearing
> on screen?  If so I could imaging some use case where you have some UI
> control/menu overlay on top, and some game running on a underlay plane,
> and the game want to be able to flip as soon as possible.  Or Daniel do you
> think ASYNC property will apply to all planes in CRTC?
> 
Also the client code both in nouveau and AMD/DAL iterates over new planes and 
their new states
so it seems to me easier to retrieve the parameter from the plane_state and not 
adding loop
to find matching crtc or its  state, especially if it's before 
drm_atomic_helper_swap_state is called,
 when crtc->state still points to the old state ...
[Grodzovsky, Andrey] 
> >
> > > ---
> > >  drivers/gpu/drm/drm_atomic_helper.c | 10 +++---
> > >  include/drm/drm_plane.h |  8 
> > >  2 files changed, 11 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c
> > > index a4e5477..f83dc43 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -2737,7 +2737,8 @@ static int page_flip_common(
> > >   struct drm_atomic_state *state,
> > >   struct drm_crtc *crtc,
> > >   struct drm_framebuffer *fb,
> > > - struct drm_pending_vblank_event *event)
> > > + struct drm_pending_vblank_event *event,
> > > + uint32_t flags)
> > >  {
> > >   struct drm_plane *plane = crtc->primary;
> > >   struct drm_plane_state *plane_state; @@ -2754,6 +2755,7 @@ static
> > > int page_flip_common(
> > >   if (IS_ERR(plane_state))
> > >   return PTR_ERR(plane_state);
> > >
> > > + plane_state->pflip_flags = flags;
> > >
> > >   ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
> > >   if (ret != 0)
> > > @@ -2800,9 +2802,6 @@ int drm_atomic_helper_page_flip(struct
> > > drm_crtc
> > *crtc,
> > >   struct drm_atomic_state *state;
> > >   int ret = 0;
> > >
> > > - if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> > > - return -EINVAL;
> > > -
> > >   state = drm_atomic_state_alloc(plane->dev);
> > >   if (!state)
> > >   return -ENOMEM;
> > > @@ -2865,9 +2864,6 @@ int drm_atomic_helper_page_flip_target(
> > >   struct drm_crtc_state *crtc_state;
> > >   int ret = 0;
> > >
> > > - if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
> > > - return -EINVAL;
> > > -
> > >   state = drm_atomic_state_alloc(plane->dev);
> > >   if (!state)
> > >   return -ENOMEM;
> > > diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index
> > > db3bbde..86d8ffc 100644
> > > --- a/include/drm/drm_plane.h
> > > +++ b/include/drm/drm_plane.h
> > > @@ -122,6 +122,14 @@ struct drm_plane_state {
> > >*/
> > >   bool visible;
> > >
> > > +
> > > + /**
> > > +  * @pflip_flags:
> > > +  *
> > > +  * Flip related config options
> > > +  */
> > > + u32 pflip_flags;
> > > +
> > >   struct drm_atomic_state *state;
> > >  };
> > >
> > > --
> > > 1.9.1
> > >
> > > ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> >

[PATCH 2/2] drm/amdgpu: handle vfct with multiple vbios images

2017-01-25 Thread Alex Deucher 
The vfct table can contain multiple vbios images if the
platform contains multiple GPUs. Noticed by netkas on
phoronix forums.  This patch fixes those platforms.

Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 66 
 1 file changed, 34 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 2602ea1..d9def01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -358,8 +358,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device 
*adev)
struct acpi_table_header *hdr;
acpi_size tbl_size;
UEFI_ACPI_VFCT *vfct;
-   GOP_VBIOS_CONTENT *vbios;
-   VFCT_IMAGE_HEADER *vhdr;
+   unsigned offset;
 
if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, )))
return false;
@@ -370,42 +369,45 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device 
*adev)
}
 
vfct = (UEFI_ACPI_VFCT *)hdr;
-   if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
-   DRM_ERROR("ACPI VFCT table present but broken (too short 
#2)\n");
-   return false;
-   }
+   offset = vfct->VBIOSImageOffset;
 
-   vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
-   vhdr = >VbiosHeader;
-   DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size 
%d\n",
-   vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
-   vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
-
-   if (vhdr->PCIBus != adev->pdev->bus->number ||
-   vhdr->PCIDevice != PCI_SLOT(adev->pdev->devfn) ||
-   vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn) ||
-   vhdr->VendorID != adev->pdev->vendor ||
-   vhdr->DeviceID != adev->pdev->device) {
-   DRM_INFO("ACPI VFCT table is not for this card\n");
-   return false;
-   }
+   while (offset < tbl_size) {
+   GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + 
offset);
+   VFCT_IMAGE_HEADER *vhdr = >VbiosHeader;
 
-   if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + 
vhdr->ImageLength > tbl_size) {
-   DRM_ERROR("ACPI VFCT image truncated\n");
-   return false;
-   }
+   offset += sizeof(VFCT_IMAGE_HEADER);
+   if (offset > tbl_size) {
+   DRM_ERROR("ACPI VFCT image header truncated\n");
+   return false;
+   }
 
-   adev->bios = kmemdup(>VbiosContent,
-   vhdr->ImageLength,
-   GFP_KERNEL);
+   offset += vhdr->ImageLength;
+   if (offset > tbl_size) {
+   DRM_ERROR("ACPI VFCT image truncated\n");
+   return false;
+   }
 
-   if (!check_atom_bios(adev->bios, vhdr->ImageLength)) {
-   kfree(adev->bios);
-   return false;
+   if (vhdr->ImageLength &&
+   vhdr->PCIBus == adev->pdev->bus->number &&
+   vhdr->PCIDevice == PCI_SLOT(adev->pdev->devfn) &&
+   vhdr->PCIFunction == PCI_FUNC(adev->pdev->devfn) &&
+   vhdr->VendorID == adev->pdev->vendor &&
+   vhdr->DeviceID == adev->pdev->device) {
+   adev->bios = kmemdup(>VbiosContent,
+vhdr->ImageLength,
+GFP_KERNEL);
+
+   if (!check_atom_bios(adev->bios, vhdr->ImageLength)) {
+   kfree(adev->bios);
+   return false;
+   }
+   adev->bios_size = vhdr->ImageLength;
+   return true;
+   }
}
-   adev->bios_size = vhdr->ImageLength;
 
-   return true;
+   DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+   return false;
 }
 #else
 static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
-- 
2.5.5

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[PATCH 5/5] drm/amd/display: Rename atomic_commit parameter.

2017-01-25 Thread Harry Wentland 
From: Andrey Grodzovsky 

This parameter name is misleading. It's previous
meaning confuses with ASYNC (immidiate flip)
which is totatlly different thing then nonblocking
commit.

Change-Id: Ia8ed1fad025b9b1344a470eff100da9cb1c46d31
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index a26749854ec7..865ee1ecce4f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2481,7 +2481,7 @@ static void remove_stream(struct amdgpu_device *adev, 
struct amdgpu_crtc *acrtc)
 int amdgpu_dm_atomic_commit(
struct drm_device *dev,
struct drm_atomic_state *state,
-   bool async)
+   bool nonblock)
 {
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_display_manager *dm = >dm;
@@ -2510,7 +2510,7 @@ int amdgpu_dm_atomic_commit(
 * we should not pin/unpin the fb here, it should be done in
 * amdgpu_crtc_flip and from the vblank irq handler.
 */
-   if (!async) {
+   if (!nonblock) {
ret = drm_atomic_helper_prepare_planes(dev, state);
if (ret)
return ret;
@@ -2849,7 +2849,7 @@ int amdgpu_dm_atomic_commit(
/* In this state all old framebuffers would be unpinned */
 
/* TODO: Revisit when we support true asynchronous commit.*/
-   if (!async)
+   if (!nonblock)
drm_atomic_helper_cleanup_planes(dev, state);
 
drm_atomic_state_free(state);
-- 
2.9.3

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[PATCH 3/5] drm/amd/display: fix timing trace debug print

2017-01-25 Thread Harry Wentland 
From: Dmytro Laktyushkin 

Change-Id: I560277a2348cbae9306d454e17ebf93136568034
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  4 +++-
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 18 --
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c627b907528c..c863bffab989 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1563,9 +1563,11 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
if (update_type == UPDATE_TYPE_FULL) {
/* only apply for top pipe */
-   if (!pipe_ctx->top_pipe)
+   if (!pipe_ctx->top_pipe) {

core_dc->hwss.apply_ctx_for_surface(core_dc,
 surface, context);
+   context_timing_trace(dc, 
>res_ctx);
+   }
} else if (updates[i].flip_addr)
core_dc->hwss.update_plane_addr(core_dc, 
pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 959c3f372e73..85ddf5fc4291 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -279,20 +279,26 @@ void context_timing_trace(
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dal_logger *logger =  core_dc->ctx->logger;
+   int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
 
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[i];
-   int h_pos = 0;
-   int v_pos = 0;
 
if (pipe_ctx->stream == NULL)
continue;
 
-   pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, _pos, _pos);
-   TIMING_TRACE("Pipe_%d   H_tot:%d  V_tot:%d   H_pos:%d  
V_pos:%d\n",
-   pipe_ctx->pipe_idx,
+   pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, _pos[i], 
_pos[i]);
+   }
+   for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[i];
+
+   if (pipe_ctx->stream == NULL)
+   continue;
+
+   TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  
V_pos:%d\n",
+   pipe_ctx->tg->inst,
pipe_ctx->stream->public.timing.h_total,
pipe_ctx->stream->public.timing.v_total,
-   h_pos, v_pos);
+   h_pos[i], v_pos[i]);
}
 }
-- 
2.9.3

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[PATCH 4/5] drm/amd/display: Make sure to update address without flip

2017-01-25 Thread Harry Wentland 
Change-Id: Ic0abfbe1e635ccd58596f7c4e9105d2787c10f31
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c863bffab989..75718151356d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1568,7 +1568,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 surface, context);
context_timing_trace(dc, 
>res_ctx);
}
-   } else if (updates[i].flip_addr)
+   }
+
+   if (updates[i].flip_addr)
core_dc->hwss.update_plane_addr(core_dc, 
pipe_ctx);
 
if (update_type == UPDATE_TYPE_FAST)
-- 
2.9.3

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[PATCH 2/5] drm/amd/display: Fix Warnings

2017-01-25 Thread Harry Wentland 
From: Amy Zhang 

- Remove mixed declarations and unused variables

Change-Id: I98a34d8e4f02231db56d33571590f6943ed5d58e
Signed-off-by: Amy Zhang 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 24 +-
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ce56f23806bc..c3e0865f3148 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -581,12 +581,10 @@ static bool convert_to_custom_float(
 static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func
*output_tf, struct pwl_params *regamma_params)
 {
-   if (output_tf == NULL || regamma_params == NULL)
-   return false;
-
-   struct gamma_curve *arr_curve_points = regamma_params->arr_curve_points;
-   struct curve_points *arr_points = regamma_params->arr_points;
-   struct pwl_result_data *rgb_resulted = regamma_params->rgb_resulted;
+   struct curve_points *arr_points;
+   struct pwl_result_data *rgb_resulted;
+   struct pwl_result_data *rgb;
+   struct pwl_result_data *rgb_plus_1;
struct fixed31_32 y_r;
struct fixed31_32 y_g;
struct fixed31_32 y_b;
@@ -594,8 +592,14 @@ static bool dce110_translate_regamma_to_hw_format(const 
struct dc_transfer_func
struct fixed31_32 y3_max;
 
int32_t segment_start, segment_end;
-   uint32_t i, j, k, seg_distr[16], increment, start_index;
-   uint32_t hw_points = 0;
+   uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
+
+   if (output_tf == NULL || regamma_params == NULL)
+   return false;
+
+   arr_points = regamma_params->arr_points;
+   rgb_resulted = regamma_params->rgb_resulted;
+   hw_points = 0;
 
memset(regamma_params, 0, sizeof(struct pwl_params));
 
@@ -742,8 +746,8 @@ static bool dce110_translate_regamma_to_hw_format(const 
struct dc_transfer_func
regamma_params->arr_curve_points[k].segments_num =
seg_distr[k];
 
-   struct pwl_result_data *rgb = rgb_resulted;
-   struct pwl_result_data *rgb_plus_1 = rgb_resulted + 1;
+   rgb = rgb_resulted;
+   rgb_plus_1 = rgb_resulted + 1;
 
i = 1;
 
-- 
2.9.3

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[PATCH 1/5] drm/amd/display: enable color gamma programming

2017-01-25 Thread Harry Wentland 
From: Tony Cheng 

Change-Id: I430d3d8dd5054e456215035875831f6aae827cb0
Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 6 --
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 -
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 01d614781def..c627b907528c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1498,9 +1498,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
}
}
 
-   if (dc->debug.disable_color_module)
-   continue;  /* skip below color updates */
-
if (updates[i].gamma &&
updates[i].gamma != surface->public.gamma_correction) {
if (surface->public.gamma_correction != NULL)
@@ -1579,9 +1576,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
if (cur_pipe_ctx->surface == pipe_ctx->surface)
is_new_pipe_surface = false;
 
-   if (dc->debug.disable_color_module)
-   continue;  /* skip below color updates */
-
if (is_new_pipe_surface ||
updates[i].in_transfer_func)
core_dc->hwss.set_input_transfer_func(
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c3aca8d44d4c..f485f70bf3ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -147,7 +147,6 @@ struct dc_debug {
bool disable_dfs_bypass;
bool disable_clock_gate;
bool disable_dmcu;
-   bool disable_color_module;
 };
 
 struct dc {
-- 
2.9.3

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Re: [PATCH] drm/amd/powerplay: header should be defining _SMU7_CLOCK_POWER_GATING_H_

2017-01-25 Thread Alex Deucher 
On Wed, Jan 25, 2017 at 7:07 AM, Colin King  wrote:
> From: Colin Ian King 
>
> _SMU7_CLOCK_POWER_GATING_H_ is being used as a header guard, followed by
> a #define of a different macro.  Define _SMU7_CLOCK_POWER_GATING_H_ instead
> to fix this.
>
> Signed-off-by: Colin Ian King 

Thanks for the patch.  Nicolas beat you to it:
https://lists.freedesktop.org/archives/dri-devel/2017-January/130477.html


Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> index d52a28c..c96ed9e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> @@ -22,7 +22,7 @@
>   */
>
>  #ifndef _SMU7_CLOCK_POWER_GATING_H_
> -#define _SMU7_CLOCK__POWER_GATING_H_
> +#define _SMU7_CLOCK_POWER_GATING_H_
>
>  #include "smu7_hwmgr.h"
>  #include "pp_asicblocks.h"
> --
> 2.10.2
>
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[PATCH] drm/amd/powerplay: header should be defining _SMU7_CLOCK_POWER_GATING_H_

2017-01-25 Thread Colin King 
From: Colin Ian King 

_SMU7_CLOCK_POWER_GATING_H_ is being used as a header guard, followed by
a #define of a different macro.  Define _SMU7_CLOCK_POWER_GATING_H_ instead
to fix this.

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index d52a28c..c96ed9e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -22,7 +22,7 @@
  */
 
 #ifndef _SMU7_CLOCK_POWER_GATING_H_
-#define _SMU7_CLOCK__POWER_GATING_H_
+#define _SMU7_CLOCK_POWER_GATING_H_
 
 #include "smu7_hwmgr.h"
 #include "pp_asicblocks.h"
-- 
2.10.2

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Re: [PATCH] drm/amd/powerplay: header should be defining _SMU7_CLOCK_POWER_GATING_H_

2017-01-25 Thread Zhu, Rex 
Thanks.


Reviewed-by: Rex Zhu 


Best Regards

Rex


From: Colin King 
Sent: Wednesday, January 25, 2017 8:07 PM
To: Deucher, Alexander; Koenig, Christian; David Airlie; Wang, Ken; Daenzer, 
Michel; Zhu, Rex; amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: kernel-janit...@vger.kernel.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amd/powerplay: header should be defining 
_SMU7_CLOCK_POWER_GATING_H_

From: Colin Ian King 

_SMU7_CLOCK_POWER_GATING_H_ is being used as a header guard, followed by
a #define of a different macro.  Define _SMU7_CLOCK_POWER_GATING_H_ instead
to fix this.

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index d52a28c..c96ed9e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -22,7 +22,7 @@
  */

 #ifndef _SMU7_CLOCK_POWER_GATING_H_
-#define _SMU7_CLOCK__POWER_GATING_H_
+#define _SMU7_CLOCK_POWER_GATING_H_

 #include "smu7_hwmgr.h"
 #include "pp_asicblocks.h"
--
2.10.2

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Re: [PATCH] drm/amdgpu: drop pitcairn dpm quirks

2017-01-25 Thread Christian König 

Am 25.01.2017 um 00:26 schrieb Alex Deucher:

No longer necessary with the new 58 mc ucode.

Signed-off-by: Alex Deucher 


Nice to have those finally resolved. Series is Reviewed-by: Christian 
König .



---
  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 47 +
  1 file changed, 1 insertion(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 4f12da1..ab2dd59 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3009,29 +3009,6 @@ static int si_init_smc_spll_table(struct amdgpu_device 
*adev)
return ret;
  }
  
-struct si_dpm_quirk {

-   u32 chip_vendor;
-   u32 chip_device;
-   u32 subsys_vendor;
-   u32 subsys_device;
-   u32 max_sclk;
-   u32 max_mclk;
-};
-
-/* cards with dpm stability problems */
-static struct si_dpm_quirk si_dpm_quirk_list[] = {
-   /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 12 },
-   { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 12 },
-   { 0, 0, 0, 0 },
-};
-
  static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
   u16 vce_voltage)
  {
@@ -3477,18 +3454,8 @@ static void si_apply_state_adjust_rules(struct 
amdgpu_device *adev,
u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
u32 max_sclk = 0, max_mclk = 0;
int i;
-   struct si_dpm_quirk *p = si_dpm_quirk_list;
  
-	/* limit all SI kickers */

-   if (adev->asic_type == CHIP_PITCAIRN) {
-   if ((adev->pdev->revision == 0x81) ||
-   (adev->pdev->device == 0x6810) ||
-   (adev->pdev->device == 0x6811) ||
-   (adev->pdev->device == 0x6816) ||
-   (adev->pdev->device == 0x6817) ||
-   (adev->pdev->device == 0x6806))
-   max_mclk = 12;
-   } else if (adev->asic_type == CHIP_HAINAN) {
+   if (adev->asic_type == CHIP_HAINAN) {
if ((adev->pdev->revision == 0x81) ||
(adev->pdev->revision == 0x83) ||
(adev->pdev->revision == 0xC3) ||
@@ -3498,18 +3465,6 @@ static void si_apply_state_adjust_rules(struct 
amdgpu_device *adev,
max_sclk = 75000;
}
}
-   /* Apply dpm quirks */
-   while (p && p->chip_device != 0) {
-   if (adev->pdev->vendor == p->chip_vendor &&
-   adev->pdev->device == p->chip_device &&
-   adev->pdev->subsystem_vendor == p->subsys_vendor &&
-   adev->pdev->subsystem_device == p->subsys_device) {
-   max_sclk = p->max_sclk;
-   max_mclk = p->max_mclk;
-   break;
-   }
-   ++p;
-   }
  
  	if (rps->vce_active) {

rps->evclk = 
adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;



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Re: [PATCH 1/2] drm/amdgpu: remove unused header si_reg.h

2017-01-25 Thread Christian König 

Am 25.01.2017 um 00:02 schrieb Alex Deucher:

All of these are available elsewhere.

Signed-off-by: Alex Deucher 


Acked-by: Christian König  for the series.


---
  drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h | 105 ---
  1 file changed, 105 deletions(-)
  delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h 
b/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
deleted file mode 100644
index 895c8e2..000
--- a/drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2010 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-#ifndef __SI_REG_H__
-#define __SI_REG_H__
-
-/* SI */
-#define SI_DC_GPIO_HPD_MASK  0x196c
-#define SI_DC_GPIO_HPD_A 0x196d
-#define SI_DC_GPIO_HPD_EN0x196e
-#define SI_DC_GPIO_HPD_Y 0x196f
-
-#define SI_GRPH_CONTROL  0x1a01
-#   define SI_GRPH_DEPTH(x)  (((x) & 0x3) << 0)
-#   define SI_GRPH_DEPTH_8BPP0
-#   define SI_GRPH_DEPTH_16BPP   1
-#   define SI_GRPH_DEPTH_32BPP   2
-#   define SI_GRPH_NUM_BANKS(x)  (((x) & 0x3) << 2)
-#   define SI_ADDR_SURF_2_BANK   0
-#   define SI_ADDR_SURF_4_BANK   1
-#   define SI_ADDR_SURF_8_BANK   2
-#   define SI_ADDR_SURF_16_BANK  3
-#   define SI_GRPH_Z(x)  (((x) & 0x3) << 4)
-#   define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
-#   define SI_ADDR_SURF_BANK_WIDTH_1 0
-#   define SI_ADDR_SURF_BANK_WIDTH_2 1
-#   define SI_ADDR_SURF_BANK_WIDTH_4 2
-#   define SI_ADDR_SURF_BANK_WIDTH_8 3
-#   define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
-/* 8 BPP */
-#   define SI_GRPH_FORMAT_INDEXED0
-/* 16 BPP */
-#   define SI_GRPH_FORMAT_ARGB1555   0
-#   define SI_GRPH_FORMAT_ARGB5651
-#   define SI_GRPH_FORMAT_ARGB   2
-#   define SI_GRPH_FORMAT_AI88   3
-#   define SI_GRPH_FORMAT_MONO16 4
-#   define SI_GRPH_FORMAT_BGRA5551   5
-/* 32 BPP */
-#   define SI_GRPH_FORMAT_ARGB   0
-#   define SI_GRPH_FORMAT_ARGB21010101
-#   define SI_GRPH_FORMAT_32BPP_DIG  2
-#   define SI_GRPH_FORMAT_8B_ARGB2101010 3
-#   define SI_GRPH_FORMAT_BGRA10101024
-#   define SI_GRPH_FORMAT_8B_BGRA1010102 5
-#   define SI_GRPH_FORMAT_RGB10  6
-#   define SI_GRPH_FORMAT_BGR10  7
-#   define SI_GRPH_BANK_HEIGHT(x)(((x) & 0x3) << 11)
-#   define SI_ADDR_SURF_BANK_HEIGHT_10
-#   define SI_ADDR_SURF_BANK_HEIGHT_21
-#   define SI_ADDR_SURF_BANK_HEIGHT_42
-#   define SI_ADDR_SURF_BANK_HEIGHT_83
-#   define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
-#   define SI_ADDR_SURF_TILE_SPLIT_64B   0
-#   define SI_ADDR_SURF_TILE_SPLIT_128B  1
-#   define SI_ADDR_SURF_TILE_SPLIT_256B  2
-#   define SI_ADDR_SURF_TILE_SPLIT_512B  3
-#   define SI_ADDR_SURF_TILE_SPLIT_1KB   4
-#   define SI_ADDR_SURF_TILE_SPLIT_2KB   5
-#   define SI_ADDR_SURF_TILE_SPLIT_4KB   6
-#   define SI_GRPH_MACRO_TILE_ASPECT(x)  (((x) & 0x3) << 18)
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
-#   define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
-#   define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
-#   define