RE: [PATCH 1/6] drm/amdgpu:add PSP block only load_type=PSP

[Yu, Xiangliang]

Reviewed-by: Xiangliang Yu  for the series.


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, April 05, 2017 5:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk 
> Subject: [PATCH 1/6] drm/amdgpu:add PSP block only load_type=PSP
> 
> SRIOV currently only can load ucode directly, and PSP block is not supported
> by VF temporarily.
> 
> will remove this restrict and use PSP load all ucode even for SRIOV later
> 
> Change-Id: I6df5c4088c7c72d01928d5af8bfe5520447619ba
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 06afbcc..2955c0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -497,7 +497,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
>   amdgpu_ip_block_add(adev, _v1_0_ip_block);
>   amdgpu_ip_block_add(adev, _v9_0_ip_block);
>   amdgpu_ip_block_add(adev, _ih_ip_block);
> - amdgpu_ip_block_add(adev, _v3_1_ip_block);
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> + amdgpu_ip_block_add(adev, _v3_1_ip_block);
>   if (!amdgpu_sriov_vf(adev))
>   amdgpu_ip_block_add(adev,
> _pp_ip_block);
>   if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> --
> 2.7.4
> 
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Re: [PATCH 1/2] drm/amdgpu/gfx8: enable cp/rlc ints after we disable clockgating

[Alex Deucher]

Ping?

On Tue, Mar 14, 2017 at 3:32 PM, Alex Deucher  wrote:
> Even if we disable clockgating, we still need to make sure the
> cp/rlc interrupts are enabled for powergating which might still
> be enabled.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index a53e36c..c9d9913 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6258,6 +6258,8 @@ static void 
> gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>   RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
> if (temp != data)
> WREG32(mmRLC_CGCG_CGLS_CTRL, data);
> +   /* enable interrupts again for PG */
> +   gfx_v8_0_enable_gui_idle_interrupt(adev, true);
> }
>
> gfx_v8_0_wait_for_rlc_serdes(adev);
> --
> 2.5.5
>
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[PATCH] drm/amdgpu: move bios scratch reg restore for soc15

[Alex Deucher]

It needs to happen after asic_init as asic_init expects
the registers to be in the default power up state.

This should fix S3 on vega10.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d78c523..18e1ddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2247,9 +2247,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
return r;
}
}
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_restore(adev);
-   else
+   if (!adev->is_atom_fw)
amdgpu_atombios_scratch_regs_restore(adev);
 
/* post card */
@@ -2259,6 +2257,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
DRM_ERROR("amdgpu asic init failed\n");
}
 
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_restore(adev);
+
r = amdgpu_resume(adev);
if (r) {
DRM_ERROR("amdgpu_resume failed (%d).\n", r);
@@ -2641,12 +2642,12 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
else
amdgpu_atombios_scratch_regs_save(adev);
r = amdgpu_asic_reset(adev);
-   if (adev->is_atom_fw)
-   amdgpu_atomfirmware_scratch_regs_restore(adev);
-   else
+   if (!adev->is_atom_fw)
amdgpu_atombios_scratch_regs_restore(adev);
/* post card */
amdgpu_atom_asic_init(adev->mode_info.atom_context);
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_restore(adev);
 
if (!r) {
dev_info(adev->dev, "GPU reset succeeded, trying to 
resume\n");
-- 
2.5.5

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RE: [PATCH] drm/amd/display: fix NULL pointer dereference.

[Quan, Evan]

The issue seems already fixed by the following commit
{{{
commit 52184bbf4773512d7c83fe21a0b4b4ec4be27caf
Author: Jordan Lazare 
Date:   Wed Apr 5 15:05:51 2017 -0400

drm/amd/display: fix nullptr on vega initialization

Change-Id: Ic5062d9b9e7ad3406c8ed0acfe0e2f222ce17634
Signed-off-by: Jordan Lazare 
Reviewed-by: Tony Cheng 
Reviewed-by: Roman Li 
}}}

Regards,
Evan
>-Original Message-
>From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rex Zhu
>Sent: Wednesday, April 05, 2017 3:55 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhu, Rex 
>Subject: [PATCH] drm/amd/display: fix NULL pointer dereference.
>
>on vega10, driver can run into a NULL-pointer dereference.
>
>Change-Id: I8e2de5343f804d6e736f620ff6d3d6e6488fb970
>Signed-off-by: Rex Zhu 
>---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>index 62be159..8f5951f 100644
>--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>@@ -1095,7 +1095,8 @@ int amdgpu_dm_initialize_drm_device(struct
>amdgpu_device *adev)
>   DRM_ERROR("KMS: Failed to allocate surface\n");
>   goto fail_free_planes;
>   }
>-  mode_info->planes[i]->plane_type = mode_info-
>>plane_type[i];
>+  if (mode_info->plane_type != NULL)
>+  mode_info->planes[i]->plane_type = mode_info-
>>plane_type[i];
>   if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) {
>   DRM_ERROR("KMS: Failed to initialize plane\n");
>   goto fail_free_planes;
>--
>1.9.1
>
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RE: [PATCH] drm/amd/display: fix NULL pointer dereference.

[Zhang, Jerry]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Rex Zhu
> Sent: Wednesday, April 05, 2017 15:55
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amd/display: fix NULL pointer dereference.
> 
> on vega10, driver can run into a NULL-pointer dereference.
> 
> Change-Id: I8e2de5343f804d6e736f620ff6d3d6e6488fb970
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 62be159..8f5951f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1095,7 +1095,8 @@ int amdgpu_dm_initialize_drm_device(struct
> amdgpu_device *adev)
>   DRM_ERROR("KMS: Failed to allocate surface\n");
>   goto fail_free_planes;
>   }
> - mode_info->planes[i]->plane_type = mode_info->plane_type[i];
> + if (mode_info->plane_type != NULL)

We can simplify it like:
if (mode_info->plane_type)

With that fix,   
Reviewed-by: Junwei Zhang 

> + mode_info->planes[i]->plane_type = mode_info-
> >plane_type[i];
>   if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) {
>   DRM_ERROR("KMS: Failed to initialize plane\n");
>   goto fail_free_planes;
> --
> 1.9.1
> 
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[PATCH 1/2] drm/amdgpu: Avoid using signed integer to store pointer value

[Alex Xie]

Change-Id: I861ba3c85c182fdb6b89533029b3272191f331f5
Signed-off-by: Alex Xie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index c02db01f6..9bdd5d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -237,7 +237,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_bo_list *args = data;
uint32_t handle = args->in.list_handle;
-   const void __user *uptr = (const void*)(long)args->in.bo_info_ptr;
+   const void __user *uptr = (const void*)(uintptr_t)args->in.bo_info_ptr;
 
struct drm_amdgpu_bo_list_entry *info;
struct amdgpu_bo_list *list;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e4dc21f..0386015 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -719,7 +719,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
switch (args->op) {
case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
struct drm_amdgpu_gem_create_in info;
-   void __user *out = (void __user *)(long)args->value;
+   void __user *out = (void __user *)(uintptr_t)args->value;
 
info.bo_size = robj->gem_base.size;
info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f8d8636..1006d7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -237,7 +237,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_info *info = data;
struct amdgpu_mode_info *minfo = >mode_info;
-   void __user *out = (void __user *)(long)info->return_pointer;
+   void __user *out = (void __user *)(uintptr_t)info->return_pointer;
uint32_t size = info->return_size;
struct drm_crtc *crtc;
uint32_t ui32 = 0;
-- 
1.9.1

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[PATCH 2/2] drm/amdgpu: use uintptr_t instead of unsigned long to store pointer

[Alex Xie]

Change-Id: Ic1cb6252482bcf9602c7700c3db075b9edf20e2a
Signed-off-by: Alex Xie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3389f1b..a91aa57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -161,7 +161,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
}
 
/* get chunks */
-   chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
+   chunk_array_user = (uint64_t __user *)(uintptr_t)(cs->in.chunks);
if (copy_from_user(chunk_array, chunk_array_user,
   sizeof(uint64_t)*cs->in.num_chunks)) {
ret = -EFAULT;
@@ -181,7 +181,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
struct drm_amdgpu_cs_chunk user_chunk;
uint32_t __user *cdata;
 
-   chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
+   chunk_ptr = (void __user *)(uintptr_t)chunk_array[i];
if (copy_from_user(_chunk, chunk_ptr,
   sizeof(struct drm_amdgpu_cs_chunk))) {
ret = -EFAULT;
@@ -192,7 +192,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
p->chunks[i].length_dw = user_chunk.length_dw;
 
size = p->chunks[i].length_dw;
-   cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
+   cdata = (void __user *)(uintptr_t)user_chunk.chunk_data;
 
p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
if (p->chunks[i].kdata == NULL) {
@@ -1339,7 +1339,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, 
void *data,
if (fences == NULL)
return -ENOMEM;
 
-   fences_user = (void __user *)(unsigned long)(wait->in.fences);
+   fences_user = (void __user *)(uintptr_t)(wait->in.fences);
if (copy_from_user(fences, fences_user,
sizeof(struct drm_amdgpu_fence) * fence_count)) {
r = -EFAULT;
-- 
1.9.1

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RE: [PATCH] drm/amdgpu: Fix compilation warning

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Alex Xie
> Sent: Wednesday, April 05, 2017 5:31 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xie, AlexBin
> Subject: [PATCH] drm/amdgpu: Fix compilation warning
> 
> Change-Id: Ia251723599024fe258b018a53078d340af01207e
> Signed-off-by: Alex Xie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 30d5c42..8f18d14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -853,7 +853,7 @@ static int gmc_v6_0_sw_init(void *handle)
>   adev->vm_manager.block_size = amdgpu_vm_block_size;
>   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
> 
> - DRM_INFO("vm size is %d GB, block size is %d-bit\n",
> + DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
>   adev->vm_manager.vm_size, adev-
> >vm_manager.block_size);
> 
>   adev->mc.mc_mask = 0xffULL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 7113765..b86b454 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1007,7 +1007,7 @@ static int gmc_v7_0_sw_init(void *handle)
>   adev->vm_manager.block_size = amdgpu_vm_block_size;
>   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
> 
> - DRM_INFO("vm size is %d GB, block size is %d-bit\n",
> + DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
>   adev->vm_manager.vm_size, adev-
> >vm_manager.block_size);
> 
>   /* Set the internal MC address mask
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index b3d1f1b..108a20e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1091,7 +1091,7 @@ static int gmc_v8_0_sw_init(void *handle)
>   adev->vm_manager.block_size = amdgpu_vm_block_size;
>   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
> 
> - DRM_INFO("vm size is %d GB, block size is %d-bit\n",
> + DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
>   adev->vm_manager.vm_size, adev-
> >vm_manager.block_size);
> 
>   /* Set the internal MC address mask
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index e1637d5..6329be8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -566,7 +566,7 @@ static int gmc_v9_0_sw_init(void *handle)
>   adev->vm_manager.block_size = 9;
>   }
> 
> - DRM_INFO("vm size is %d GB, block size is %d-bit\n",
> + DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
>   adev->vm_manager.vm_size, adev-
> >vm_manager.block_size);
> 
>   /* This interrupt is VMC page fault.*/
> --
> 1.9.1
> 
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[PATCH] drm/amdgpu: Fix compilation warning

[Alex Xie]

Change-Id: Ia251723599024fe258b018a53078d340af01207e
Signed-off-by: Alex Xie 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30d5c42..8f18d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -853,7 +853,7 @@ static int gmc_v6_0_sw_init(void *handle)
adev->vm_manager.block_size = amdgpu_vm_block_size;
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-   DRM_INFO("vm size is %d GB, block size is %d-bit\n",
+   DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
adev->vm_manager.vm_size, adev->vm_manager.block_size);
 
adev->mc.mc_mask = 0xffULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 7113765..b86b454 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1007,7 +1007,7 @@ static int gmc_v7_0_sw_init(void *handle)
adev->vm_manager.block_size = amdgpu_vm_block_size;
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-   DRM_INFO("vm size is %d GB, block size is %d-bit\n",
+   DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
adev->vm_manager.vm_size, adev->vm_manager.block_size);
 
/* Set the internal MC address mask
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index b3d1f1b..108a20e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1091,7 +1091,7 @@ static int gmc_v8_0_sw_init(void *handle)
adev->vm_manager.block_size = amdgpu_vm_block_size;
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-   DRM_INFO("vm size is %d GB, block size is %d-bit\n",
+   DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
adev->vm_manager.vm_size, adev->vm_manager.block_size);
 
/* Set the internal MC address mask
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e1637d5..6329be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -566,7 +566,7 @@ static int gmc_v9_0_sw_init(void *handle)
adev->vm_manager.block_size = 9;
}
 
-   DRM_INFO("vm size is %d GB, block size is %d-bit\n",
+   DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
adev->vm_manager.vm_size, adev->vm_manager.block_size);
 
/* This interrupt is VMC page fault.*/
-- 
1.9.1

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Re: [PATCH 4/5] drm/amdgpu: assign VM invalidation engine manually

[Alex Deucher]

On Wed, Apr 5, 2017 at 12:21 PM, Christian König
 wrote:
> From: Christian König 
>
> For Vega10 we have 18 VM invalidation engines for each VMHUB.
>
> Start to assign them manually to the rings.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 12 
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  2 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c|  4 ++--
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c|  2 +-
>  6 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 45bb87b..5786cc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -179,6 +179,7 @@ struct amdgpu_ring {
> unsignedcond_exe_offs;
> u64 cond_exe_gpu_addr;
> volatile u32*cond_exe_cpu_addr;
> +   unsignedvm_inv_eng;
>  #if defined(CONFIG_DEBUG_FS)
> struct dentry *ent;
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index dce2950..79bfbbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3150,7 +3150,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
> struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_GFXHUB];
> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -   unsigned eng = ring->idx;
> +   unsigned eng = ring->vm_inv_eng;
>
> pd_addr = pd_addr | 0x1; /* valid bit */
> /* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index e1637d5..4f6000b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -386,6 +386,18 @@ static int gmc_v9_0_early_init(void *handle)
>  static int gmc_v9_0_late_init(void *handle)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +   unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 0 };
> +   unsigned i;
> +
> +   for(i = 0; i < adev->num_rings; ++i) {
> +   struct amdgpu_ring *ring = adev->rings[i];
> +   unsigned vmhub = ring->funcs->vmhub;
> +
> +   ring->vm_inv_eng = vm_inv_eng[vmhub]++;
> +   dev_info(adev->dev, "ring %u uses VM inv eng %u on hub %u\n",
> +ring->idx, ring->vm_inv_eng, ring->funcs->vmhub);
> +   }
> +
> return amdgpu_irq_get(adev, >mc.vm_fault, 0);
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 06826a0..90440e0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1041,7 +1041,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
>  {
> struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
> uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -   unsigned eng = ring->idx;
> +   unsigned eng = ring->vm_inv_eng;
>
> pd_addr = pd_addr | 0x1; /* valid bit */
> /* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 772c0f2..cc4f8f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1037,7 +1037,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
> struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
> uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> uint32_t data0, data1, mask;
> -   unsigned eng = ring->idx;
> +   unsigned eng = ring->vm_inv_eng;
>
> pd_addr = pd_addr | 0x1; /* valid bit */
> /* now only use physical base address of PDE and valid */
> @@ -1078,7 +1078,7 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct 
> amdgpu_ring *ring,
>  {
> struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
> uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -   unsigned eng = ring->idx;
> +   unsigned eng = ring->vm_inv_eng;
>
> pd_addr = pd_addr | 0x1; /* valid bit */
> /* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 5e4f243..66474e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ 

Re: [PATCH 1/5] drm/amdgpu: add VMHUB to ring association

[Alex Deucher]

On Wed, Apr 5, 2017 at 12:21 PM, Christian König
 wrote:
> From: Christian König 
>
> Add the info which ring belonging to which VMHUB.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 3 +++
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 2 ++
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 1 +
>  5 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7479e47..45bb87b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
> uint32_talign_mask;
> u32 nop;
> boolsupport_64bit_ptrs;
> +   unsignedvmhub;
>
> /* ring read/write ptr handling */
> u64 (*get_rptr)(struct amdgpu_ring *ring);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index a967879..1cc006a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3673,6 +3673,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_gfx = {
> .align_mask = 0xff,
> .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> .support_64bit_ptrs = true,
> +   .vmhub = AMDGPU_GFXHUB,
> .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
> .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
> .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
> @@ -3717,6 +3718,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_compute = {
> .align_mask = 0xff,
> .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> .support_64bit_ptrs = true,
> +   .vmhub = AMDGPU_GFXHUB,
> .get_rptr = gfx_v9_0_ring_get_rptr_compute,
> .get_wptr = gfx_v9_0_ring_get_wptr_compute,
> .set_wptr = gfx_v9_0_ring_set_wptr_compute,
> @@ -3746,6 +3748,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_kiq = {
> .align_mask = 0xff,
> .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> .support_64bit_ptrs = true,
> +   .vmhub = AMDGPU_GFXHUB,
> .get_rptr = gfx_v9_0_ring_get_rptr_compute,
> .get_wptr = gfx_v9_0_ring_get_wptr_compute,
> .set_wptr = gfx_v9_0_ring_set_wptr_compute,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index d40eb31..8cbb49d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs 
> sdma_v4_0_ring_funcs = {
> .align_mask = 0xf,
> .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> .support_64bit_ptrs = true,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = sdma_v4_0_ring_get_rptr,
> .get_wptr = sdma_v4_0_ring_get_wptr,
> .set_wptr = sdma_v4_0_ring_set_wptr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 819148a..fa80465 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v7_0_ring_vm_funcs = {
> .align_mask = 0xf,
> .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
> .support_64bit_ptrs = false,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = uvd_v7_0_ring_get_rptr,
> .get_wptr = uvd_v7_0_ring_get_wptr,
> .set_wptr = uvd_v7_0_ring_set_wptr,
> @@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v7_0_enc_ring_vm_funcs = {
> .align_mask = 0x3f,
> .nop = HEVC_ENC_CMD_NO_OP,
> .support_64bit_ptrs = false,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = uvd_v7_0_enc_ring_get_rptr,
> .get_wptr = uvd_v7_0_enc_ring_get_wptr,
> .set_wptr = uvd_v7_0_enc_ring_set_wptr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 8dde83f..6374133 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs 
> vce_v4_0_ring_vm_funcs = {
> .align_mask = 0x3f,
> .nop = VCE_CMD_NO_OP,
> .support_64bit_ptrs = false,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = vce_v4_0_ring_get_rptr,
> .get_wptr = vce_v4_0_ring_get_wptr,
> .set_wptr = vce_v4_0_ring_set_wptr,
> --
> 2.5.0
>
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Re: [PATCH 2/5] drm/amdgpu: separate VMID flush tracking per hub

[Alex Deucher]

On Wed, Apr 5, 2017 at 12:21 PM, Christian König
 wrote:
> From: Christian König 
>
> Rather inefficient, but this way we only need to flush the current hub.
>
> I wonder if we shouldn't make nails with heads and separate the VMID ranges 
> completely.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 36 
> --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  6 +++---
>  2 files changed, 24 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 8785420..6fd1952 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -406,6 +406,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
> amdgpu_ring *ring,
>   struct amdgpu_job *job)
>  {
> struct amdgpu_device *adev = ring->adev;
> +   unsigned vmhub = ring->funcs->vmhub;
> uint64_t fence_context = adev->fence_context + ring->idx;
> struct fence *updates = sync->last_vm_update;
> struct amdgpu_vm_id *id, *idle;
> @@ -480,17 +481,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
> amdgpu_ring *ring,
> if (atomic64_read(>owner) != vm->client_id)
> continue;
>
> -   if (job->vm_pd_addr != id->pd_gpu_addr)
> +   if (job->vm_pd_addr != id->pd_gpu_addr[vmhub])
> continue;
>
> -   if (!id->last_flush)
> +   if (!id->last_flush[vmhub])
> continue;
>
> -   if (id->last_flush->context != fence_context &&
> -   !fence_is_signaled(id->last_flush))
> +   if (id->last_flush[vmhub]->context != fence_context &&
> +   !fence_is_signaled(id->last_flush[vmhub]))
> continue;
>
> -   flushed  = id->flushed_updates;
> +   flushed  = id->flushed_updates[vmhub];
> if (updates &&
> (!flushed || fence_is_later(updates, flushed)))
> continue;
> @@ -522,13 +523,15 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
> amdgpu_ring *ring,
> if (r)
> goto error;
>
> -   fence_put(id->last_flush);
> -   id->last_flush = NULL;
> +   for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {

Would it be worth storing the number of vm_hubs per chip and using
that as the limit?  That way we wouldn't loop multiple times for older
asics with only one hub.

Alex


> +   fence_put(id->last_flush[i]);
> +   id->last_flush[i] = NULL;
> +   }
>
> -   fence_put(id->flushed_updates);
> -   id->flushed_updates = fence_get(updates);
> +   fence_put(id->flushed_updates[vmhub]);
> +   id->flushed_updates[vmhub] = fence_get(updates);
>
> -   id->pd_gpu_addr = job->vm_pd_addr;
> +   id->pd_gpu_addr[vmhub] = job->vm_pd_addr;
> id->current_gpu_reset_count = atomic_read(>gpu_reset_counter);
> list_move_tail(>list, >vm_manager.ids_lru);
> atomic64_set(>owner, vm->client_id);
> @@ -591,6 +594,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
> amdgpu_job *job)
>  {
> struct amdgpu_device *adev = ring->adev;
> struct amdgpu_vm_id *id = >vm_manager.ids[job->vm_id];
> +   unsigned vmhub = ring->funcs->vmhub;
> bool gds_switch_needed = ring->funcs->emit_gds_switch && (
> id->gds_base != job->gds_base ||
> id->gds_size != job->gds_size ||
> @@ -629,8 +633,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
> amdgpu_job *job)
> return r;
>
> mutex_lock(>vm_manager.lock);
> -   fence_put(id->last_flush);
> -   id->last_flush = fence;
> +   fence_put(id->last_flush[vmhub]);
> +   id->last_flush[vmhub] = fence;
> mutex_unlock(>vm_manager.lock);
> }
>
> @@ -2234,13 +2238,15 @@ void amdgpu_vm_manager_init(struct amdgpu_device 
> *adev)
>   */
>  void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
>  {
> -   unsigned i;
> +   unsigned i, j;
>
> for (i = 0; i < AMDGPU_NUM_VM; ++i) {
> struct amdgpu_vm_id *id = >vm_manager.ids[i];
>
> amdgpu_sync_free(>vm_manager.ids[i].active);
> -   fence_put(id->flushed_updates);
> -   fence_put(id->last_flush);
> +   for (j = 0; j < AMDGPU_MAX_VMHUBS; ++j) {
> +   fence_put(id->flushed_updates[j]);
> +   fence_put(id->last_flush[j]);
> +   }
> }
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 7d01372..d61dd83 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ 

Re: [PATCH 3/5] drm/amdgpu: invalidate only the currently needed VMHUB

[Alex Deucher]

On Wed, Apr 5, 2017 at 12:21 PM, Christian König
 wrote:
> From: Christian König 
>
> Drop invalidating both hubs from each engine.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  36 +--
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  60 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 111 
> +++--
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  57 -
>  4 files changed, 118 insertions(+), 146 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1cc006a..dce2950 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3147,35 +3147,29 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct 
> amdgpu_ring *ring)
>  static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vm_id, uint64_t pd_addr)
>  {
> +   struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_GFXHUB];

Should use use ring->vmhub here rather than hardcoding
AMDGPU_GFXHUB/AMDGPU_MMHUB?  Same question for all the other IP below.
With that fixed:
Reviewed-by: Alex Deucher 



> int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> unsigned eng = ring->idx;
> -   unsigned i;
>
> pd_addr = pd_addr | 0x1; /* valid bit */
> /* now only use physical base address of PDE and valid */
> BUG_ON(pd_addr & 0x003EULL);
>
> -   for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
> -   struct amdgpu_vmhub *hub = >adev->vmhub[i];
> -
> -   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> -  hub->ctx0_ptb_addr_lo32
> -  + (2 * vm_id),
> -  lower_32_bits(pd_addr));
> +   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> +  hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
> +  lower_32_bits(pd_addr));
>
> -   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> -  hub->ctx0_ptb_addr_hi32
> -  + (2 * vm_id),
> -  upper_32_bits(pd_addr));
> +   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> +  hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
> +  upper_32_bits(pd_addr));
>
> -   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> -  hub->vm_inv_eng0_req + eng, req);
> +   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
> +  hub->vm_inv_eng0_req + eng, req);
>
> -   /* wait for the invalidate to complete */
> -   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
> - eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
> -   }
> +   /* wait for the invalidate to complete */
> +   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
> + eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
>
> /* compute doesn't have PFP */
> if (usepfp) {
> @@ -3680,7 +3674,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_gfx = {
> .emit_frame_size = /* totally 242 maximum if 16 IBs */
> 5 +  /* COND_EXEC */
> 7 +  /* PIPELINE_SYNC */
> -   46 + /* VM_FLUSH */
> +   24 + /* VM_FLUSH */
> 8 +  /* FENCE for VM_FLUSH */
> 20 + /* GDS switch */
> 4 + /* double SWITCH_BUFFER,
> @@ -3727,7 +3721,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_compute = {
> 7 + /* gfx_v9_0_ring_emit_hdp_flush */
> 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
> 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
> -   64 + /* gfx_v9_0_ring_emit_vm_flush */
> +   24 + /* gfx_v9_0_ring_emit_vm_flush */
> 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm 
> fence */
> .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
> .emit_ib = gfx_v9_0_ring_emit_ib_compute,
> @@ -3757,7 +3751,7 @@ static const struct amdgpu_ring_funcs 
> gfx_v9_0_ring_funcs_kiq = {
> 7 + /* gfx_v9_0_ring_emit_hdp_flush */
> 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
> 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
> -   64 + /* gfx_v9_0_ring_emit_vm_flush */
> +   24 + /* gfx_v9_0_ring_emit_vm_flush */
> 8 + 8 + 8, /* 

Re: [PATCH 10/10] drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()

[Alex Deucher]

On Wed, Apr 5, 2017 at 9:26 AM, Tom St Denis  wrote:
> Use new WREG32_FIELD15 macro
>
> Signed-off-by: Tom St Denis 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2dd32466919d..33df0dbe7052 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1288,9 +1288,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device 
> *adev)
> u32 tmp;
> int i;
>
> -   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
> -   tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
> -   WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
> +   WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
>
> gfx_v9_0_tiling_mode_table_init(adev);
>
> --
> 2.12.0
>
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Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Tom St Denis]

On 05/04/17 11:34 AM, Andres Rodriguez wrote:

Hey Tom,

If it's the same as your old firmware you might be missing an extra
step. I usually just run the kernel 'make install' as that usually take
care of the distro specific quirks.


I manually load the module but for sanity I did a make install and it 
didn't change the rlc/smc versions.


Tom




On Apr 5, 2017 9:56 AM, "Deucher, Alexander" > wrote:

> -Original Message-
> From: StDenis, Tom
> Sent: Wednesday, April 05, 2017 9:14 AM
> To: Alex Deucher
> Cc: Andres Rodriguez; Deucher, Alexander; Tom St Denis; amd-
> g...@lists.freedesktop.org 
> Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"
>
> On 05/04/17 09:06 AM, Alex Deucher wrote:
> > On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis
>
> wrote:
> >> My firmware is
> >>
> >> fw.VCE == .feature==0 .firmware==0x34040300
> >> fw.UVD == .feature==0 .firmware==0x015b0b00
> >> fw.MC == .feature==0 .firmware==0x
> >> fw.ME == .feature==46 .firmware==0x00a1
> >> fw.PFP == .feature==46 .firmware==0x00eb
> >> fw.CE == .feature==46 .firmware==0x0086
> >> fw.RLC == .feature==1 .firmware==0x009c
> >> fw.MEC == .feature==46 .firmware==0x02c1
> >> fw.MEC2 == .feature==46 .firmware==0x02c1
> >> fw.SOS == .feature==0 .firmware==0x
> >> fw.ASD == .feature==0 .firmware==0x
> >> fw.SMC == .feature==0 .firmware==0x
> >> fw.SDMA0 == .feature==0 .firmware==0x0022
> >> fw.SDMA1 == .feature==0 .firmware==0x0022
> >>
> >> It seems like our all-open is behind what he has for SDMA, SMC,
RLC but
> >> ahead for others?  Bizarre.
> >
> > Can you try the upstream ucode?  That is what Andres is using.
> > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-

> firmware.git
>
> Copying the tip of master from that to my /lib/firmware/ results
in the
> same firmware versions being loaded.
>

Same as you or same as Andres?

Alex

> >
> > Alex
> >
> >>
> >> Tom
> >>
> >>
> >> On 04/04/17 04:17 PM, Andres Rodriguez wrote:
> >>>
> >>> This should be the the linux-firmware repository @ commit
> >>> 6d3bc8886517d171068fd1263176b8b5c51df204
> >>>
> >>> I reverted back to that firmware since I didn't want to deal with
> >>> possible bugs when testing my patches.
> >>>
> >>> Regards,
> >>> Andres
> >>>
> >>> On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
> >>> >
wrote:
> >
> > -Original Message-
> > From: Andres Rodriguez [mailto:andre...@gmail.com
]
> > Sent: Tuesday, April 04, 2017 4:01 PM
> > To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
> > g...@lists.freedesktop.org 
> > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES
> packet"
> >
> > This is my info in case that is useful:
> >
> >  umr.version == ea8e49bb15ed
> >
> >  fw.VCE == .feature==0 .firmware==0x34040300
> >  fw.UVD == .feature==0 .firmware==0x014f1000
> >  fw.MC == .feature==0 .firmware==0x
> >  fw.ME == .feature==37 .firmware==0x0094
> >  fw.PFP == .feature==37 .firmware==0x00dc
> >  fw.CE == .feature==37 .firmware==0x0080
> >  fw.RLC == .feature==1 .firmware==0x010e
> >  fw.MEC == .feature==37 .firmware==0x02a2
> >  fw.MEC2 == .feature==37 .firmware==0x02a2
> >  fw.SOS == .feature==0 .firmware==0x
> >  fw.ASD == .feature==0 .firmware==0x
> >  fw.SMC == .feature==0 .firmware==0x00170f00
> >  fw.SDMA0 == .feature==31 .firmware==0x0036
> >  fw.SDMA1 == .feature==0 .firmware==0x0036
> >
> >  asic.instance == 0
> >
> >
> >  gfx.max_shader_engines == 4
> >  gfx.max_tile_pipes == 8
> >  gfx.max_cu_per_sh == 9
> >  gfx.max_sh_per_se == 1
> >  gfx.max_backends_per_se == 2
> >  gfx.max_texture_channel_caches == 8
> >  gfx.max_gprs == 256
> >  gfx.max_gs_threads == 32
> >  gfx.max_hw_contexts == 8
> >  gfx.sc_prim_fifo_size_frontend == 32
> >  

Re: [PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()

[Tom St Denis]

On 05/04/17 10:15 AM, Christian König wrote:

Am 05.04.2017 um 15:26 schrieb Tom St Denis:

Introduce WREG32_FIELD15 macro for SOC15 architectures.

Signed-off-by: Tom St Denis 


Reviewed-by: Christian König 


For the series or just 1/10?

Tom




---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++
  2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d0a3987b221a..04c84332cc58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,9 @@ bool amdgpu_device_has_dc_support(struct
amdgpu_device *adev);
  #define WREG32_FIELD_OFFSET(reg, offset, field, val)\
  WREG32(mm##reg + offset, (RREG32(mm##reg + offset) &
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  +#define WREG32_FIELD15(ip, idx, reg, field, val)\
+WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg),
(RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg,
field)) | (val) << REG_FIELD_SHIFT(reg, field))
+
  /*
   * BIOS helpers.
   */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a967879524bc..3888743bc868 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3975,9 +3975,7 @@ static int gfx_v9_0_init_queue(struct
amdgpu_ring *ring)
 ring->pipe,
 ring->queue, 0);
  /* disable wptr polling */
-tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
-tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
+WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
/* write the EOP addr */
  BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other
cases eop address */
@@ -4121,11 +4119,8 @@ static int gfx_v9_0_init_queue(struct
amdgpu_ring *ring)
  amdgpu_bo_kunmap(ring->mqd_obj);
  amdgpu_bo_unreserve(ring->mqd_obj);
  -if (use_doorbell) {
-tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
-tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
-}
+if (use_doorbell)
+WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
return 0;
  }





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[PATCH 3/5] drm/amdgpu: invalidate only the currently needed VMHUB

[Christian König]

From: Christian König 

Drop invalidating both hubs from each engine.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  36 +--
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  60 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 111 +++--
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  57 -
 4 files changed, 118 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1cc006a..dce2950 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3147,35 +3147,29 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct 
amdgpu_ring *ring)
 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr)
 {
+   struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_GFXHUB];
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
unsigned eng = ring->idx;
-   unsigned i;
 
pd_addr = pd_addr | 0x1; /* valid bit */
/* now only use physical base address of PDE and valid */
BUG_ON(pd_addr & 0x003EULL);
 
-   for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-   struct amdgpu_vmhub *hub = >adev->vmhub[i];
-
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->ctx0_ptb_addr_lo32
-  + (2 * vm_id),
-  lower_32_bits(pd_addr));
+   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+  hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
+  lower_32_bits(pd_addr));
 
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->ctx0_ptb_addr_hi32
-  + (2 * vm_id),
-  upper_32_bits(pd_addr));
+   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+  hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
+  upper_32_bits(pd_addr));
 
-   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-  hub->vm_inv_eng0_req + eng, req);
+   gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+  hub->vm_inv_eng0_req + eng, req);
 
-   /* wait for the invalidate to complete */
-   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
- eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
-   }
+   /* wait for the invalidate to complete */
+   gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
+ eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
 
/* compute doesn't have PFP */
if (usepfp) {
@@ -3680,7 +3674,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_gfx = {
.emit_frame_size = /* totally 242 maximum if 16 IBs */
5 +  /* COND_EXEC */
7 +  /* PIPELINE_SYNC */
-   46 + /* VM_FLUSH */
+   24 + /* VM_FLUSH */
8 +  /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -3727,7 +3721,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-   64 + /* gfx_v9_0_ring_emit_vm_flush */
+   24 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm 
fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -3757,7 +3751,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_kiq = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-   64 + /* gfx_v9_0_ring_emit_vm_flush */
+   24 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, 
vm fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 8cbb49d..06826a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1039,44 +1039,40 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct 
amdgpu_ring 

[PATCH 5/5] drm/amdgpu: allow concurrent VM flushes

[Christian König]

From: Christian König 

Enable concurrent VM flushes for Vega10.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 51 +++---
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6fd1952..1bb2f8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -462,11 +462,12 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
}
kfree(fences);
 
-   job->vm_needs_flush = true;
+   job->vm_needs_flush = false;
/* Check if we can use a VMID already assigned to this VM */
i = ring->idx;
do {
struct fence *flushed;
+   bool needs_flush = false;
 
id = vm->ids[i++];
if (i == AMDGPU_MAX_RINGS)
@@ -484,16 +485,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (job->vm_pd_addr != id->pd_gpu_addr[vmhub])
continue;
 
-   if (!id->last_flush[vmhub])
-   continue;
-
-   if (id->last_flush[vmhub]->context != fence_context &&
-   !fence_is_signaled(id->last_flush[vmhub]))
-   continue;
+   if (!id->last_flush[vmhub] ||
+   (id->last_flush[vmhub]->context != fence_context &&
+!fence_is_signaled(id->last_flush[vmhub])))
+   needs_flush = true;
 
flushed  = id->flushed_updates[vmhub];
-   if (updates &&
-   (!flushed || fence_is_later(updates, flushed)))
+   if (updates && (!flushed || fence_is_later(updates, flushed)))
+   needs_flush = true;
+
+   /* Concurrent flushes are only possible starting with Vega10 */
+   if (adev->asic_type < CHIP_VEGA10 && needs_flush)
continue;
 
/* Good we can use this VMID. Remember this submission as
@@ -503,15 +505,15 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (r)
goto error;
 
-   list_move_tail(>list, >vm_manager.ids_lru);
-   vm->ids[ring->idx] = id;
-
-   job->vm_id = id - adev->vm_manager.ids;
-   job->vm_needs_flush = false;
-   trace_amdgpu_vm_grab_id(vm, ring->idx, job);
+   if (updates && (!flushed || fence_is_later(updates, flushed))) {
+   fence_put(id->flushed_updates[vmhub]);
+   id->flushed_updates[vmhub] = fence_get(updates);
+   }
 
-   mutex_unlock(>vm_manager.lock);
-   return 0;
+   if (needs_flush)
+   goto needs_flush;
+   else
+   goto no_flush_needed;
 
} while (i != ring->idx);
 
@@ -523,18 +525,21 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (r)
goto error;
 
+   id->pd_gpu_addr[vmhub] = job->vm_pd_addr;
+   fence_put(id->flushed_updates[vmhub]);
+   id->flushed_updates[vmhub] = fence_get(updates);
+   id->current_gpu_reset_count = atomic_read(>gpu_reset_counter);
+   atomic64_set(>owner, vm->client_id);
+
+needs_flush:
+   job->vm_needs_flush = true;
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
fence_put(id->last_flush[i]);
id->last_flush[i] = NULL;
}
 
-   fence_put(id->flushed_updates[vmhub]);
-   id->flushed_updates[vmhub] = fence_get(updates);
-
-   id->pd_gpu_addr[vmhub] = job->vm_pd_addr;
-   id->current_gpu_reset_count = atomic_read(>gpu_reset_counter);
+no_flush_needed:
list_move_tail(>list, >vm_manager.ids_lru);
-   atomic64_set(>owner, vm->client_id);
vm->ids[ring->idx] = id;
 
job->vm_id = id - adev->vm_manager.ids;
-- 
2.5.0

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[PATCH 1/5] drm/amdgpu: add VMHUB to ring association

[Christian König]

From: Christian König 

Add the info which ring belonging to which VMHUB.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 2 ++
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 1 +
 5 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7479e47..45bb87b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
uint32_talign_mask;
u32 nop;
boolsupport_64bit_ptrs;
+   unsignedvmhub;
 
/* ring read/write ptr handling */
u64 (*get_rptr)(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a967879..1cc006a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3673,6 +3673,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_gfx = {
.align_mask = 0xff,
.nop = PACKET3(PACKET3_NOP, 0x3FFF),
.support_64bit_ptrs = true,
+   .vmhub = AMDGPU_GFXHUB,
.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
@@ -3717,6 +3718,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.align_mask = 0xff,
.nop = PACKET3(PACKET3_NOP, 0x3FFF),
.support_64bit_ptrs = true,
+   .vmhub = AMDGPU_GFXHUB,
.get_rptr = gfx_v9_0_ring_get_rptr_compute,
.get_wptr = gfx_v9_0_ring_get_wptr_compute,
.set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@ -3746,6 +3748,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_kiq = {
.align_mask = 0xff,
.nop = PACKET3(PACKET3_NOP, 0x3FFF),
.support_64bit_ptrs = true,
+   .vmhub = AMDGPU_GFXHUB,
.get_rptr = gfx_v9_0_ring_get_rptr_compute,
.get_wptr = gfx_v9_0_ring_get_wptr_compute,
.set_wptr = gfx_v9_0_ring_set_wptr_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index d40eb31..8cbb49d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs 
sdma_v4_0_ring_funcs = {
.align_mask = 0xf,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
+   .vmhub = AMDGPU_MMHUB,
.get_rptr = sdma_v4_0_ring_get_rptr,
.get_wptr = sdma_v4_0_ring_get_wptr,
.set_wptr = sdma_v4_0_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 819148a..fa80465 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.align_mask = 0xf,
.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
.support_64bit_ptrs = false,
+   .vmhub = AMDGPU_MMHUB,
.get_rptr = uvd_v7_0_ring_get_rptr,
.get_wptr = uvd_v7_0_ring_get_wptr,
.set_wptr = uvd_v7_0_ring_set_wptr,
@@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_enc_ring_vm_funcs = {
.align_mask = 0x3f,
.nop = HEVC_ENC_CMD_NO_OP,
.support_64bit_ptrs = false,
+   .vmhub = AMDGPU_MMHUB,
.get_rptr = uvd_v7_0_enc_ring_get_rptr,
.get_wptr = uvd_v7_0_enc_ring_get_wptr,
.set_wptr = uvd_v7_0_enc_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 8dde83f..6374133 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs 
vce_v4_0_ring_vm_funcs = {
.align_mask = 0x3f,
.nop = VCE_CMD_NO_OP,
.support_64bit_ptrs = false,
+   .vmhub = AMDGPU_MMHUB,
.get_rptr = vce_v4_0_ring_get_rptr,
.get_wptr = vce_v4_0_ring_get_wptr,
.set_wptr = vce_v4_0_ring_set_wptr,
-- 
2.5.0

___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/amdgpu: separate VMID flush tracking per hub

[Christian König]

From: Christian König 

Rather inefficient, but this way we only need to flush the current hub.

I wonder if we shouldn't make nails with heads and separate the VMID ranges 
completely.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 36 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  6 +++---
 2 files changed, 24 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8785420..6fd1952 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -406,6 +406,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
  struct amdgpu_job *job)
 {
struct amdgpu_device *adev = ring->adev;
+   unsigned vmhub = ring->funcs->vmhub;
uint64_t fence_context = adev->fence_context + ring->idx;
struct fence *updates = sync->last_vm_update;
struct amdgpu_vm_id *id, *idle;
@@ -480,17 +481,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (atomic64_read(>owner) != vm->client_id)
continue;
 
-   if (job->vm_pd_addr != id->pd_gpu_addr)
+   if (job->vm_pd_addr != id->pd_gpu_addr[vmhub])
continue;
 
-   if (!id->last_flush)
+   if (!id->last_flush[vmhub])
continue;
 
-   if (id->last_flush->context != fence_context &&
-   !fence_is_signaled(id->last_flush))
+   if (id->last_flush[vmhub]->context != fence_context &&
+   !fence_is_signaled(id->last_flush[vmhub]))
continue;
 
-   flushed  = id->flushed_updates;
+   flushed  = id->flushed_updates[vmhub];
if (updates &&
(!flushed || fence_is_later(updates, flushed)))
continue;
@@ -522,13 +523,15 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct 
amdgpu_ring *ring,
if (r)
goto error;
 
-   fence_put(id->last_flush);
-   id->last_flush = NULL;
+   for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+   fence_put(id->last_flush[i]);
+   id->last_flush[i] = NULL;
+   }
 
-   fence_put(id->flushed_updates);
-   id->flushed_updates = fence_get(updates);
+   fence_put(id->flushed_updates[vmhub]);
+   id->flushed_updates[vmhub] = fence_get(updates);
 
-   id->pd_gpu_addr = job->vm_pd_addr;
+   id->pd_gpu_addr[vmhub] = job->vm_pd_addr;
id->current_gpu_reset_count = atomic_read(>gpu_reset_counter);
list_move_tail(>list, >vm_manager.ids_lru);
atomic64_set(>owner, vm->client_id);
@@ -591,6 +594,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job)
 {
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vm_id *id = >vm_manager.ids[job->vm_id];
+   unsigned vmhub = ring->funcs->vmhub;
bool gds_switch_needed = ring->funcs->emit_gds_switch && (
id->gds_base != job->gds_base ||
id->gds_size != job->gds_size ||
@@ -629,8 +633,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job)
return r;
 
mutex_lock(>vm_manager.lock);
-   fence_put(id->last_flush);
-   id->last_flush = fence;
+   fence_put(id->last_flush[vmhub]);
+   id->last_flush[vmhub] = fence;
mutex_unlock(>vm_manager.lock);
}
 
@@ -2234,13 +2238,15 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
  */
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
 {
-   unsigned i;
+   unsigned i, j;
 
for (i = 0; i < AMDGPU_NUM_VM; ++i) {
struct amdgpu_vm_id *id = >vm_manager.ids[i];
 
amdgpu_sync_free(>vm_manager.ids[i].active);
-   fence_put(id->flushed_updates);
-   fence_put(id->last_flush);
+   for (j = 0; j < AMDGPU_MAX_VMHUBS; ++j) {
+   fence_put(id->flushed_updates[j]);
+   fence_put(id->last_flush[j]);
+   }
}
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 7d01372..d61dd83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -132,12 +132,12 @@ struct amdgpu_vm {
 struct amdgpu_vm_id {
struct list_headlist;
struct amdgpu_sync  active;
-   struct fence*last_flush;
+   struct fence*last_flush[AMDGPU_MAX_VMHUBS];
atomic64_t  owner;
 
-   uint64_tpd_gpu_addr;
+   uint64_tpd_gpu_addr[AMDGPU_MAX_VMHUBS];
/* last flushed PD/PT 

[PATCH 4/5] drm/amdgpu: assign VM invalidation engine manually

[Christian König]

From: Christian König 

For Vega10 we have 18 VM invalidation engines for each VMHUB.

Start to assign them manually to the rings.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 12 
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c|  4 ++--
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c|  2 +-
 6 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 45bb87b..5786cc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -179,6 +179,7 @@ struct amdgpu_ring {
unsignedcond_exe_offs;
u64 cond_exe_gpu_addr;
volatile u32*cond_exe_cpu_addr;
+   unsignedvm_inv_eng;
 #if defined(CONFIG_DEBUG_FS)
struct dentry *ent;
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dce2950..79bfbbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3150,7 +3150,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_GFXHUB];
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-   unsigned eng = ring->idx;
+   unsigned eng = ring->vm_inv_eng;
 
pd_addr = pd_addr | 0x1; /* valid bit */
/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e1637d5..4f6000b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -386,6 +386,18 @@ static int gmc_v9_0_early_init(void *handle)
 static int gmc_v9_0_late_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 0 };
+   unsigned i;
+
+   for(i = 0; i < adev->num_rings; ++i) {
+   struct amdgpu_ring *ring = adev->rings[i];
+   unsigned vmhub = ring->funcs->vmhub;
+
+   ring->vm_inv_eng = vm_inv_eng[vmhub]++;
+   dev_info(adev->dev, "ring %u uses VM inv eng %u on hub %u\n",
+ring->idx, ring->vm_inv_eng, ring->funcs->vmhub);
+   }
+
return amdgpu_irq_get(adev, >mc.vm_fault, 0);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 06826a0..90440e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1041,7 +1041,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 {
struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-   unsigned eng = ring->idx;
+   unsigned eng = ring->vm_inv_eng;
 
pd_addr = pd_addr | 0x1; /* valid bit */
/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 772c0f2..cc4f8f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1037,7 +1037,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
uint32_t data0, data1, mask;
-   unsigned eng = ring->idx;
+   unsigned eng = ring->vm_inv_eng;
 
pd_addr = pd_addr | 0x1; /* valid bit */
/* now only use physical base address of PDE and valid */
@@ -1078,7 +1078,7 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct 
amdgpu_ring *ring,
 {
struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-   unsigned eng = ring->idx;
+   unsigned eng = ring->vm_inv_eng;
 
pd_addr = pd_addr | 0x1; /* valid bit */
/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 5e4f243..66474e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -975,7 +975,7 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
 {
struct amdgpu_vmhub *hub = >adev->vmhub[AMDGPU_MMHUB];
uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-   unsigned eng = ring->idx;
+   unsigned eng = ring->vm_inv_eng;
 
pd_addr = pd_addr 

Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[William Lewis]

On 04/05/2017 01:43 AM, Junwei Zhang wrote:
> By default, the value is set by individual gmc.
> if a specific value is input, it overrides the global value for all
>
> Signed-off-by: Junwei Zhang 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 
> ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
>   7 files changed, 74 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 65021df..d7f75ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, 
> uint32_t reg, uint32_t v,
>   bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
>   bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>   
> +uint32_t amdgpu_get_block_size(int vm_size);
> +
>   /*
>* Registers read & write functions.
>*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1d0c742..2f91c2f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
>   return (arg & (arg - 1)) == 0;
>   }
>   
> -static void amdgpu_get_block_size(struct amdgpu_device *adev)
> +uint32_t amdgpu_get_block_size(int vm_size)
> +{
> + /* Total bits covered by PD + PTs */
> + unsigned bits = ilog2(vm_size) + 18;
> +
> + /* Make sure the PD is 4K in size up to 8GB address space.
> +Above that split equal between PD and PTs */
> + if (vm_size <= 8)
> + return (bits - 9);
> + else
> + return ((bits + 3) / 2);
> +}
> +
> +static void amdgpu_check_block_size(struct amdgpu_device *adev)
>   {
>   /* defines number of bits in page table versus page directory,
>* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
>* page table and the remaining bits are in the page directory */
> - if (amdgpu_vm_block_size == -1) {
> -
> - /* Total bits covered by PD + PTs */
> - unsigned bits = ilog2(amdgpu_vm_size) + 18;
> -
> - /* Make sure the PD is 4K in size up to 8GB address space.
> -Above that split equal between PD and PTs */
> - if (amdgpu_vm_size <= 8)
> - amdgpu_vm_block_size = bits - 9;
> - else
> - amdgpu_vm_block_size = (bits + 3) / 2;
> + if (amdgpu_vm_block_size == -1)
> + return;
>   
> - } else if (amdgpu_vm_block_size < 9) {
> + if (amdgpu_vm_block_size < 9) {
>   dev_warn(adev->dev, "VM page table size (%d) too small\n",
>amdgpu_vm_block_size);
> - amdgpu_vm_block_size = 9;
> + goto def_value;
>   }
>   
>   if (amdgpu_vm_block_size > 24 ||
>   (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
>   dev_warn(adev->dev, "VM page table size (%d) too large\n",
>amdgpu_vm_block_size);
> - amdgpu_vm_block_size = 9;
> + goto def_value;
>   }
> +
> + return;
> +
> +def_value:
> + amdgpu_vm_block_size = -1;
>   }
>   
>   static void amdgpu_check_vm_size(struct amdgpu_device *adev)
> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device 
> *adev)
>   return;
>   
>   def_value:
> - amdgpu_vm_size = 8;
> - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
> + amdgpu_vm_size = -1;;
There's an extraneous semicolon here.
>   }
>   
>   /**
> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device 
> *adev)
>   
>   amdgpu_check_vm_size(adev);
>   
> - amdgpu_get_block_size(adev);
> + amdgpu_check_block_size(adev);
>   
>   if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
>   !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index bfd945b..6238e2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -86,7 +86,7 @@
>   unsigned amdgpu_ip_block_mask = 0x;
>   int amdgpu_bapm = -1;
>   int amdgpu_deep_color = 0;
> -int amdgpu_vm_size = 64;
> +int amdgpu_vm_size = -1;
>   int amdgpu_vm_block_size = -1;
>   int amdgpu_vm_fault_stop = 0;
>   int amdgpu_vm_debug = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
> 

RE: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Andres Rodriguez]

Hey Tom,

If it's the same as your old firmware you might be missing an extra step. I
usually just run the kernel 'make install' as that usually take care of the
distro specific quirks.

Regards,
Andres

On Apr 5, 2017 9:56 AM, "Deucher, Alexander" 
wrote:

> > -Original Message-
> > From: StDenis, Tom
> > Sent: Wednesday, April 05, 2017 9:14 AM
> > To: Alex Deucher
> > Cc: Andres Rodriguez; Deucher, Alexander; Tom St Denis; amd-
> > g...@lists.freedesktop.org
> > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"
> >
> > On 05/04/17 09:06 AM, Alex Deucher wrote:
> > > On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis 
> > wrote:
> > >> My firmware is
> > >>
> > >> fw.VCE == .feature==0 .firmware==0x34040300
> > >> fw.UVD == .feature==0 .firmware==0x015b0b00
> > >> fw.MC == .feature==0 .firmware==0x
> > >> fw.ME == .feature==46 .firmware==0x00a1
> > >> fw.PFP == .feature==46 .firmware==0x00eb
> > >> fw.CE == .feature==46 .firmware==0x0086
> > >> fw.RLC == .feature==1 .firmware==0x009c
> > >> fw.MEC == .feature==46 .firmware==0x02c1
> > >> fw.MEC2 == .feature==46 .firmware==0x02c1
> > >> fw.SOS == .feature==0 .firmware==0x
> > >> fw.ASD == .feature==0 .firmware==0x
> > >> fw.SMC == .feature==0 .firmware==0x
> > >> fw.SDMA0 == .feature==0 .firmware==0x0022
> > >> fw.SDMA1 == .feature==0 .firmware==0x0022
> > >>
> > >> It seems like our all-open is behind what he has for SDMA, SMC, RLC
> but
> > >> ahead for others?  Bizarre.
> > >
> > > Can you try the upstream ucode?  That is what Andres is using.
> > > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-
> > firmware.git
> >
> > Copying the tip of master from that to my /lib/firmware/ results in the
> > same firmware versions being loaded.
> >
>
> Same as you or same as Andres?
>
> Alex
>
> > >
> > > Alex
> > >
> > >>
> > >> Tom
> > >>
> > >>
> > >> On 04/04/17 04:17 PM, Andres Rodriguez wrote:
> > >>>
> > >>> This should be the the linux-firmware repository @ commit
> > >>> 6d3bc8886517d171068fd1263176b8b5c51df204
> > >>>
> > >>> I reverted back to that firmware since I didn't want to deal with
> > >>> possible bugs when testing my patches.
> > >>>
> > >>> Regards,
> > >>> Andres
> > >>>
> > >>> On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
> > >>>  wrote:
> > >
> > > -Original Message-
> > > From: Andres Rodriguez [mailto:andre...@gmail.com]
> > > Sent: Tuesday, April 04, 2017 4:01 PM
> > > To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
> > > g...@lists.freedesktop.org
> > > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES
> > packet"
> > >
> > > This is my info in case that is useful:
> > >
> > >  umr.version == ea8e49bb15ed
> > >
> > >  fw.VCE == .feature==0 .firmware==0x34040300
> > >  fw.UVD == .feature==0 .firmware==0x014f1000
> > >  fw.MC == .feature==0 .firmware==0x
> > >  fw.ME == .feature==37 .firmware==0x0094
> > >  fw.PFP == .feature==37 .firmware==0x00dc
> > >  fw.CE == .feature==37 .firmware==0x0080
> > >  fw.RLC == .feature==1 .firmware==0x010e
> > >  fw.MEC == .feature==37 .firmware==0x02a2
> > >  fw.MEC2 == .feature==37 .firmware==0x02a2
> > >  fw.SOS == .feature==0 .firmware==0x
> > >  fw.ASD == .feature==0 .firmware==0x
> > >  fw.SMC == .feature==0 .firmware==0x00170f00
> > >  fw.SDMA0 == .feature==31 .firmware==0x0036
> > >  fw.SDMA1 == .feature==0 .firmware==0x0036
> > >
> > >  asic.instance == 0
> > >
> > >
> > >  gfx.max_shader_engines == 4
> > >  gfx.max_tile_pipes == 8
> > >  gfx.max_cu_per_sh == 9
> > >  gfx.max_sh_per_se == 1
> > >  gfx.max_backends_per_se == 2
> > >  gfx.max_texture_channel_caches == 8
> > >  gfx.max_gprs == 256
> > >  gfx.max_gs_threads == 32
> > >  gfx.max_hw_contexts == 8
> > >  gfx.sc_prim_fifo_size_frontend == 32
> > >  gfx.sc_prim_fifo_size_backend == 256
> > >  gfx.sc_hiz_tile_fifo_size == 48
> > >  gfx.sc_earlyz_tile_fifo_size == 304
> > >  gfx.num_tile_pipes == 8
> > >  gfx.backend_enable_mask == 255
> > >  gfx.mem_max_burst_length_bytes == 256
> > >  gfx.mem_row_size_in_kb == 4
> > >  gfx.shader_engine_tile_size == 32
> > >  gfx.num_gpus == 1
> > >  gfx.multi_gpu_tile_size == 64
> > >  gfx.mc_arb_ramcfg == 24738
> > >  gfx.gb_addr_config == 570494979
> > >  gfx.num_rbs == 8
> > >  gfx.family = 130, Volcanic Islands
> > >  gfx.rev_id == 0001
> > >  

Re: [PATCH] radeonsi: add new polaris10 pci id

[Nicolai Hähnle]

On 05.04.2017 15:46, Alex Deucher wrote:

Cc: 13.0 17.0 
Signed-off-by: Alex Deucher 


Reviewed-by: Nicolai Hähnle 


---
 include/pci_ids/radeonsi_pci_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index f4139ea..1058682 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -202,6 +202,7 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
 CHIPSET(0x67CA, POLARIS10_, POLARIS10)
 CHIPSET(0x67CC, POLARIS10_, POLARIS10)
 CHIPSET(0x67CF, POLARIS10_, POLARIS10)
+CHIPSET(0x67D0, POLARIS10_, POLARIS10)
 CHIPSET(0x67DF, POLARIS10_, POLARIS10)

 CHIPSET(0x98E4, STONEY_, STONEY)




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Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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RE: [PATCH] iommu/amd: flush IOTLB for specific domains only

[Nath, Arindam]

>-Original Message-
>From: Daniel Drake [mailto:dr...@endlessm.com]
>Sent: Thursday, March 30, 2017 7:15 PM
>To: Nath, Arindam
>Cc: j...@8bytes.org; Deucher, Alexander; Bridgman, John; amd-
>g...@lists.freedesktop.org; io...@lists.linux-foundation.org; Suthikulpanit,
>Suravee; Linux Upstreaming Team
>Subject: Re: [PATCH] iommu/amd: flush IOTLB for specific domains only
>
>On Thu, Mar 30, 2017 at 12:23 AM, Nath, Arindam 
>wrote:
>> Daniel, did you get chance to test this patch?
>
>Not yet. Should we test it alone or alongside "PCI: Blacklist AMD
>Stoney GPU devices for ATS"?

Daniel, any luck with this patch?

Thanks,
Arindam

>
>Thanks
>Daniel
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Re: [PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()

[Christian König]

Am 05.04.2017 um 15:26 schrieb Tom St Denis:

Introduce WREG32_FIELD15 macro for SOC15 architectures.

Signed-off-by: Tom St Denis 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++
  2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d0a3987b221a..04c84332cc58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,9 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
*adev);
  #define WREG32_FIELD_OFFSET(reg, offset, field, val)  \
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, 
field)) | (val) << REG_FIELD_SHIFT(reg, field))
  
+#define WREG32_FIELD15(ip, idx, reg, field, val)	\

+   WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, 
mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+
  /*
   * BIOS helpers.
   */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a967879524bc..3888743bc868 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3975,9 +3975,7 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
   ring->pipe,
   ring->queue, 0);
/* disable wptr polling */
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
+   WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
  
  	/* write the EOP addr */

BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases 
eop address */
@@ -4121,11 +4119,8 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
amdgpu_bo_kunmap(ring->mqd_obj);
amdgpu_bo_unreserve(ring->mqd_obj);
  
-	if (use_doorbell) {

-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
-   }
+   if (use_doorbell)
+   WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
  
  	return 0;

  }



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RE: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Deucher, Alexander]

> -Original Message-
> From: StDenis, Tom
> Sent: Wednesday, April 05, 2017 9:14 AM
> To: Alex Deucher
> Cc: Andres Rodriguez; Deucher, Alexander; Tom St Denis; amd-
> g...@lists.freedesktop.org
> Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"
> 
> On 05/04/17 09:06 AM, Alex Deucher wrote:
> > On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis 
> wrote:
> >> My firmware is
> >>
> >> fw.VCE == .feature==0 .firmware==0x34040300
> >> fw.UVD == .feature==0 .firmware==0x015b0b00
> >> fw.MC == .feature==0 .firmware==0x
> >> fw.ME == .feature==46 .firmware==0x00a1
> >> fw.PFP == .feature==46 .firmware==0x00eb
> >> fw.CE == .feature==46 .firmware==0x0086
> >> fw.RLC == .feature==1 .firmware==0x009c
> >> fw.MEC == .feature==46 .firmware==0x02c1
> >> fw.MEC2 == .feature==46 .firmware==0x02c1
> >> fw.SOS == .feature==0 .firmware==0x
> >> fw.ASD == .feature==0 .firmware==0x
> >> fw.SMC == .feature==0 .firmware==0x
> >> fw.SDMA0 == .feature==0 .firmware==0x0022
> >> fw.SDMA1 == .feature==0 .firmware==0x0022
> >>
> >> It seems like our all-open is behind what he has for SDMA, SMC, RLC but
> >> ahead for others?  Bizarre.
> >
> > Can you try the upstream ucode?  That is what Andres is using.
> > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-
> firmware.git
> 
> Copying the tip of master from that to my /lib/firmware/ results in the
> same firmware versions being loaded.
> 

Same as you or same as Andres?

Alex

> >
> > Alex
> >
> >>
> >> Tom
> >>
> >>
> >> On 04/04/17 04:17 PM, Andres Rodriguez wrote:
> >>>
> >>> This should be the the linux-firmware repository @ commit
> >>> 6d3bc8886517d171068fd1263176b8b5c51df204
> >>>
> >>> I reverted back to that firmware since I didn't want to deal with
> >>> possible bugs when testing my patches.
> >>>
> >>> Regards,
> >>> Andres
> >>>
> >>> On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
> >>>  wrote:
> >
> > -Original Message-
> > From: Andres Rodriguez [mailto:andre...@gmail.com]
> > Sent: Tuesday, April 04, 2017 4:01 PM
> > To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
> > g...@lists.freedesktop.org
> > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES
> packet"
> >
> > This is my info in case that is useful:
> >
> >  umr.version == ea8e49bb15ed
> >
> >  fw.VCE == .feature==0 .firmware==0x34040300
> >  fw.UVD == .feature==0 .firmware==0x014f1000
> >  fw.MC == .feature==0 .firmware==0x
> >  fw.ME == .feature==37 .firmware==0x0094
> >  fw.PFP == .feature==37 .firmware==0x00dc
> >  fw.CE == .feature==37 .firmware==0x0080
> >  fw.RLC == .feature==1 .firmware==0x010e
> >  fw.MEC == .feature==37 .firmware==0x02a2
> >  fw.MEC2 == .feature==37 .firmware==0x02a2
> >  fw.SOS == .feature==0 .firmware==0x
> >  fw.ASD == .feature==0 .firmware==0x
> >  fw.SMC == .feature==0 .firmware==0x00170f00
> >  fw.SDMA0 == .feature==31 .firmware==0x0036
> >  fw.SDMA1 == .feature==0 .firmware==0x0036
> >
> >  asic.instance == 0
> >
> >
> >  gfx.max_shader_engines == 4
> >  gfx.max_tile_pipes == 8
> >  gfx.max_cu_per_sh == 9
> >  gfx.max_sh_per_se == 1
> >  gfx.max_backends_per_se == 2
> >  gfx.max_texture_channel_caches == 8
> >  gfx.max_gprs == 256
> >  gfx.max_gs_threads == 32
> >  gfx.max_hw_contexts == 8
> >  gfx.sc_prim_fifo_size_frontend == 32
> >  gfx.sc_prim_fifo_size_backend == 256
> >  gfx.sc_hiz_tile_fifo_size == 48
> >  gfx.sc_earlyz_tile_fifo_size == 304
> >  gfx.num_tile_pipes == 8
> >  gfx.backend_enable_mask == 255
> >  gfx.mem_max_burst_length_bytes == 256
> >  gfx.mem_row_size_in_kb == 4
> >  gfx.shader_engine_tile_size == 32
> >  gfx.num_gpus == 1
> >  gfx.multi_gpu_tile_size == 64
> >  gfx.mc_arb_ramcfg == 24738
> >  gfx.gb_addr_config == 570494979
> >  gfx.num_rbs == 8
> >  gfx.family = 130, Volcanic Islands
> >  gfx.rev_id == 0001
> >  gfx.external_rev_id == 0051
> >  gfx.cg_flags == 003fffcd
> >  AMD_CG_SUPPORT_GFX_MGCG
> >  AMD_CG_SUPPORT_GFX_CGCG
> >  AMD_CG_SUPPORT_GFX_CGLS
> >  AMD_CG_SUPPORT_GFX_CP_LS
> >  AMD_CG_SUPPORT_GFX_RLC_LS
> >  AMD_CG_SUPPORT_MC_LS
> >  AMD_CG_SUPPORT_MC_MGCG
> >  AMD_CG_SUPPORT_SDMA_LS
> >  AMD_CG_SUPPORT_SDMA_MGCG
> >  AMD_CG_SUPPORT_BIF_LS
> >  

Re: [Mesa-dev] [PATCH] radeonsi: add new polaris10 pci id

[Christian König]

Am 05.04.2017 um 15:46 schrieb Alex Deucher:

Cc: 13.0 17.0 
Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  include/pci_ids/radeonsi_pci_ids.h | 1 +
  1 file changed, 1 insertion(+)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index f4139ea..1058682 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -202,6 +202,7 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
  CHIPSET(0x67CA, POLARIS10_, POLARIS10)
  CHIPSET(0x67CC, POLARIS10_, POLARIS10)
  CHIPSET(0x67CF, POLARIS10_, POLARIS10)
+CHIPSET(0x67D0, POLARIS10_, POLARIS10)
  CHIPSET(0x67DF, POLARIS10_, POLARIS10)
  
  CHIPSET(0x98E4, STONEY_, STONEY)



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[PATCH] radeonsi: add new polaris10 pci id

[Alex Deucher]

Cc: 13.0 17.0 
Signed-off-by: Alex Deucher 
---
 include/pci_ids/radeonsi_pci_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index f4139ea..1058682 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -202,6 +202,7 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10)
 CHIPSET(0x67CA, POLARIS10_, POLARIS10)
 CHIPSET(0x67CC, POLARIS10_, POLARIS10)
 CHIPSET(0x67CF, POLARIS10_, POLARIS10)
+CHIPSET(0x67D0, POLARIS10_, POLARIS10)
 CHIPSET(0x67DF, POLARIS10_, POLARIS10)
 
 CHIPSET(0x98E4, STONEY_, STONEY)
-- 
2.5.5

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Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[Christian König]

Am 05.04.2017 um 15:32 schrieb Alex Deucher:

On Wed, Apr 5, 2017 at 5:01 AM, Christian König  wrote:

Am 05.04.2017 um 08:43 schrieb Junwei Zhang:

By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all

Signed-off-by: Junwei Zhang 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44
++
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
   7 files changed, 74 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 65021df..d7f75ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev,
uint32_t reg, uint32_t v,
   bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
   bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
   +uint32_t amdgpu_get_block_size(int vm_size);
+
   /*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..2f91c2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
 return (arg & (arg - 1)) == 0;
   }
   -static void amdgpu_get_block_size(struct amdgpu_device *adev)
+uint32_t amdgpu_get_block_size(int vm_size)
+{
+   /* Total bits covered by PD + PTs */
+   unsigned bits = ilog2(vm_size) + 18;
+
+   /* Make sure the PD is 4K in size up to 8GB address space.
+  Above that split equal between PD and PTs */
+   if (vm_size <= 8)
+   return (bits - 9);
+   else
+   return ((bits + 3) / 2);
+}


Please move that helper into amdgpu_vmc.c.



+
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
   {
 /* defines number of bits in page table versus page directory,
  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
  * page table and the remaining bits are in the page directory */
-   if (amdgpu_vm_block_size == -1) {
-
-   /* Total bits covered by PD + PTs */
-   unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
-   /* Make sure the PD is 4K in size up to 8GB address space.
-  Above that split equal between PD and PTs */
-   if (amdgpu_vm_size <= 8)
-   amdgpu_vm_block_size = bits - 9;
-   else
-   amdgpu_vm_block_size = (bits + 3) / 2;
+   if (amdgpu_vm_block_size == -1)
+   return;
   - } else if (amdgpu_vm_block_size < 9) {
+   if (amdgpu_vm_block_size < 9) {
 dev_warn(adev->dev, "VM page table size (%d) too small\n",
  amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
 }
 if (amdgpu_vm_block_size > 24 ||
 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
 dev_warn(adev->dev, "VM page table size (%d) too large\n",
  amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
 }
+
+   return;
+
+def_value:
+   amdgpu_vm_block_size = -1;
   }
 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct
amdgpu_device *adev)
 return;
 def_value:
-   amdgpu_vm_size = 8;
-   dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+   amdgpu_vm_size = -1;;
   }
 /**
@@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct
amdgpu_device *adev)
 amdgpu_check_vm_size(adev);
   - amdgpu_get_block_size(adev);
+   amdgpu_check_block_size(adev);
 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16
||
 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
   unsigned amdgpu_ip_block_mask = 0x;
   int amdgpu_bapm = -1;
   int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
   int amdgpu_vm_block_size = -1;
   int amdgpu_vm_fault_stop = 0;
   int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[Alex Deucher]

On Wed, Apr 5, 2017 at 5:01 AM, Christian König  wrote:
> Am 05.04.2017 um 08:43 schrieb Junwei Zhang:
>>
>> By default, the value is set by individual gmc.
>> if a specific value is input, it overrides the global value for all
>>
>> Signed-off-by: Junwei Zhang 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44
>> ++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
>>   7 files changed, 74 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 65021df..d7f75ce 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev,
>> uint32_t reg, uint32_t v,
>>   bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
>>   bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>>   +uint32_t amdgpu_get_block_size(int vm_size);
>> +
>>   /*
>>* Registers read & write functions.
>>*/
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 1d0c742..2f91c2f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
>> return (arg & (arg - 1)) == 0;
>>   }
>>   -static void amdgpu_get_block_size(struct amdgpu_device *adev)
>> +uint32_t amdgpu_get_block_size(int vm_size)
>> +{
>> +   /* Total bits covered by PD + PTs */
>> +   unsigned bits = ilog2(vm_size) + 18;
>> +
>> +   /* Make sure the PD is 4K in size up to 8GB address space.
>> +  Above that split equal between PD and PTs */
>> +   if (vm_size <= 8)
>> +   return (bits - 9);
>> +   else
>> +   return ((bits + 3) / 2);
>> +}
>
>
> Please move that helper into amdgpu_vmc.c.
>
>
>> +
>> +static void amdgpu_check_block_size(struct amdgpu_device *adev)
>>   {
>> /* defines number of bits in page table versus page directory,
>>  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
>>  * page table and the remaining bits are in the page directory */
>> -   if (amdgpu_vm_block_size == -1) {
>> -
>> -   /* Total bits covered by PD + PTs */
>> -   unsigned bits = ilog2(amdgpu_vm_size) + 18;
>> -
>> -   /* Make sure the PD is 4K in size up to 8GB address space.
>> -  Above that split equal between PD and PTs */
>> -   if (amdgpu_vm_size <= 8)
>> -   amdgpu_vm_block_size = bits - 9;
>> -   else
>> -   amdgpu_vm_block_size = (bits + 3) / 2;
>> +   if (amdgpu_vm_block_size == -1)
>> +   return;
>>   - } else if (amdgpu_vm_block_size < 9) {
>> +   if (amdgpu_vm_block_size < 9) {
>> dev_warn(adev->dev, "VM page table size (%d) too small\n",
>>  amdgpu_vm_block_size);
>> -   amdgpu_vm_block_size = 9;
>> +   goto def_value;
>> }
>> if (amdgpu_vm_block_size > 24 ||
>> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
>> dev_warn(adev->dev, "VM page table size (%d) too large\n",
>>  amdgpu_vm_block_size);
>> -   amdgpu_vm_block_size = 9;
>> +   goto def_value;
>> }
>> +
>> +   return;
>> +
>> +def_value:
>> +   amdgpu_vm_block_size = -1;
>>   }
>> static void amdgpu_check_vm_size(struct amdgpu_device *adev)
>> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct
>> amdgpu_device *adev)
>> return;
>> def_value:
>> -   amdgpu_vm_size = 8;
>> -   dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
>> +   amdgpu_vm_size = -1;;
>>   }
>> /**
>> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct
>> amdgpu_device *adev)
>> amdgpu_check_vm_size(adev);
>>   - amdgpu_get_block_size(adev);
>> +   amdgpu_check_block_size(adev);
>> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16
>> ||
>> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index bfd945b..6238e2e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -86,7 +86,7 @@
>>   unsigned amdgpu_ip_block_mask = 0x;
>>   int amdgpu_bapm = -1;
>>  

Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[Alex Deucher]

On Wed, Apr 5, 2017 at 2:43 AM, Junwei Zhang  wrote:
> By default, the value is set by individual gmc.
> if a specific value is input, it overrides the global value for all
>
> Signed-off-by: Junwei Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 
> ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
>  7 files changed, 74 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 65021df..d7f75ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, 
> uint32_t reg, uint32_t v,
>  bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
>  bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>
> +uint32_t amdgpu_get_block_size(int vm_size);
> +
>  /*
>   * Registers read & write functions.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1d0c742..2f91c2f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
> return (arg & (arg - 1)) == 0;
>  }
>
> -static void amdgpu_get_block_size(struct amdgpu_device *adev)
> +uint32_t amdgpu_get_block_size(int vm_size)
> +{
> +   /* Total bits covered by PD + PTs */
> +   unsigned bits = ilog2(vm_size) + 18;
> +
> +   /* Make sure the PD is 4K in size up to 8GB address space.
> +  Above that split equal between PD and PTs */
> +   if (vm_size <= 8)
> +   return (bits - 9);
> +   else
> +   return ((bits + 3) / 2);
> +}
> +
> +static void amdgpu_check_block_size(struct amdgpu_device *adev)
>  {
> /* defines number of bits in page table versus page directory,
>  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
>  * page table and the remaining bits are in the page directory */
> -   if (amdgpu_vm_block_size == -1) {
> -
> -   /* Total bits covered by PD + PTs */
> -   unsigned bits = ilog2(amdgpu_vm_size) + 18;
> -
> -   /* Make sure the PD is 4K in size up to 8GB address space.
> -  Above that split equal between PD and PTs */
> -   if (amdgpu_vm_size <= 8)
> -   amdgpu_vm_block_size = bits - 9;
> -   else
> -   amdgpu_vm_block_size = (bits + 3) / 2;
> +   if (amdgpu_vm_block_size == -1)
> +   return;
>
> -   } else if (amdgpu_vm_block_size < 9) {
> +   if (amdgpu_vm_block_size < 9) {
> dev_warn(adev->dev, "VM page table size (%d) too small\n",
>  amdgpu_vm_block_size);
> -   amdgpu_vm_block_size = 9;
> +   goto def_value;
> }
>
> if (amdgpu_vm_block_size > 24 ||
> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
> dev_warn(adev->dev, "VM page table size (%d) too large\n",
>  amdgpu_vm_block_size);
> -   amdgpu_vm_block_size = 9;
> +   goto def_value;
> }
> +
> +   return;
> +
> +def_value:
> +   amdgpu_vm_block_size = -1;
>  }
>
>  static void amdgpu_check_vm_size(struct amdgpu_device *adev)
> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device 
> *adev)
> return;
>
>  def_value:
> -   amdgpu_vm_size = 8;
> -   dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
> +   amdgpu_vm_size = -1;;
>  }
>
>  /**
> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device 
> *adev)
>
> amdgpu_check_vm_size(adev);
>
> -   amdgpu_get_block_size(adev);
> +   amdgpu_check_block_size(adev);
>
> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index bfd945b..6238e2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -86,7 +86,7 @@
>  unsigned amdgpu_ip_block_mask = 0x;
>  int amdgpu_bapm = -1;
>  int amdgpu_deep_color = 0;
> -int amdgpu_vm_size = 64;
> +int amdgpu_vm_size = -1;
>  int amdgpu_vm_block_size = -1;
>  int amdgpu_vm_fault_stop = 0;
>  int amdgpu_vm_debug = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 

[PATCH 02/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()

[Tom St Denis]

Use new WREG32_FIELD15 macro.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3888743bc868..714fd0f228cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3473,21 +3473,12 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct 
amdgpu_device *adev,
  unsigned type,
  enum amdgpu_interrupt_state state)
 {
-   u32 cp_int_cntl;
-
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
-   cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-   cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-   PRIV_INSTR_INT_ENABLE, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
-   break;
case AMDGPU_IRQ_STATE_ENABLE:
-   cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-   cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-   PRIV_INSTR_INT_ENABLE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
-   break;
+   WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
+  PRIV_INSTR_INT_ENABLE,
+  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
default:
break;
}
-- 
2.12.0

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[PATCH 08/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()

[Tom St Denis]

Use new WREG32_FIELD15 macro

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6bc9856e67a7..80700356474c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1410,10 +1410,8 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device 
*adev)
 #ifdef AMDGPU_RLC_DEBUG_RETRY
u32 rlc_ucode_ver;
 #endif
-   u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
 
-   tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
+   WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
 
/* carrizo do enable cp interrupt after cp inited */
if (!(adev->flags & AMD_IS_APU))
-- 
2.12.0

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[PATCH 10/10] drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()

[Tom St Denis]

Use new WREG32_FIELD15 macro

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2dd32466919d..33df0dbe7052 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1288,9 +1288,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
u32 tmp;
int i;
 
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
-   tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
+   WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
 
gfx_v9_0_tiling_mode_table_init(adev);
 
-- 
2.12.0

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[PATCH 06/10] drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()

[Tom St Denis]

Use new WREG32_FIELD macro

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ebd35af7f400..49527c0c2696 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2020,13 +2020,10 @@ static int gfx_v9_0_kiq_init_register(struct 
amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
struct v9_mqd *mqd = ring->mqd_ptr;
-   uint32_t tmp;
int j;
 
/* disable wptr polling */
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
+   WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
 
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
   mqd->cp_hqd_eop_base_addr_lo);
@@ -2118,11 +2115,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring 
*ring)
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE),
   mqd->cp_hqd_active);
 
-   if (ring->use_doorbell) {
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
-   }
+   if (ring->use_doorbell)
+   WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
 
return 0;
 }
-- 
2.12.0

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[PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()

[Tom St Denis]

Introduce WREG32_FIELD15 macro for SOC15 architectures.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d0a3987b221a..04c84332cc58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,9 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
*adev);
 #define WREG32_FIELD_OFFSET(reg, offset, field, val)   \
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & 
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 
+#define WREG32_FIELD15(ip, idx, reg, field, val)   \
+   WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, 
idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, 
field))
+
 /*
  * BIOS helpers.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a967879524bc..3888743bc868 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3975,9 +3975,7 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
   ring->pipe,
   ring->queue, 0);
/* disable wptr polling */
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
+   WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
 
/* write the EOP addr */
BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases 
eop address */
@@ -4121,11 +4119,8 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
amdgpu_bo_kunmap(ring->mqd_obj);
amdgpu_bo_unreserve(ring->mqd_obj);
 
-   if (use_doorbell) {
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
-   tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
-   }
+   if (use_doorbell)
+   WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
 
return 0;
 }
-- 
2.12.0

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[PATCH 03/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state()

[Tom St Denis]

Use new WREG32_FIELD15 macro.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++---
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 714fd0f228cf..257d0d320f54 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3446,20 +3446,12 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct 
amdgpu_device *adev,
 unsigned type,
 enum amdgpu_interrupt_state state)
 {
-   u32 cp_int_cntl;
-
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
-   cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-   cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-   PRIV_REG_INT_ENABLE, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
-   break;
case AMDGPU_IRQ_STATE_ENABLE:
-   cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, 
mmCP_INT_CNTL_RING0));
-   cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
-   PRIV_REG_INT_ENABLE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), 
cp_int_cntl);
+   WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
+  PRIV_REG_INT_ENABLE,
+  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
break;
default:
break;
-- 
2.12.0

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[PATCH 07/10] drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable()

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 49527c0c2696..6bc9856e67a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1497,14 +1497,10 @@ static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device 
*adev, bool enable)
int i;
u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
 
-   if (enable) {
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
-   } else {
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
-   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
+   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
+   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
+   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
+   if (!enable) {
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
adev->gfx.gfx_ring[i].ready = false;
}
-- 
2.12.0

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[PATCH 05/10] drm/amd/amdgpu: Drop gfx_v9_0_print_status()

[Tom St Denis]

It's not used in gfx 6/7/8 so drop it from gfx 9 as well.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 175 +-
 1 file changed, 1 insertion(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ee75e584ba75..ebd35af7f400 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2366,177 +2366,6 @@ static int gfx_v9_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
 }
 
-static void gfx_v9_0_print_status(void *handle)
-{
-   int i;
-   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-   dev_info(adev->dev, "GFX 9.x registers\n");
-   dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)));
-   dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)));
-   dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)));
-   dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)));
-   dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)));
-   dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)));
-   dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 
0, mmCP_STAT)));
-   dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)));
-   dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)));
-   dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)));
-   dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)));
-   dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)));
-   dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", 
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)));
-   dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", 
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT)));
-   dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)));
-   dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", 
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)));
-
-   for (i = 0; i < 32; i++) {
-   dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
-i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + 
i*4));
-   }
-   for (i = 0; i < 16; i++) {
-   dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
-i, RREG32(SOC15_REG_OFFSET(GC, 0, 
mmGB_MACROTILE_MODE0) + i*4));
-   }
-   for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
-   dev_info(adev->dev, "  se: %d\n", i);
-   gfx_v9_0_select_se_sh(adev, i, 0x, 0x);
-   dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, 
mmPA_SC_RASTER_CONFIG)));
-   dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, 
mmPA_SC_RASTER_CONFIG_1)));
-   }
-   gfx_v9_0_select_se_sh(adev, 0x, 0x, 0x);
-
-   dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)));
-
-   dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS)));
-   dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1)));
-   dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX)));
-   dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)));
-   dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)));
-   dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG)));
-   dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)));
-   dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3)));
-   dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
-RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL)));
-   dev_info(adev->dev, "  

[PATCH 09/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset()

[Tom St Denis]

Use new WREG32_FIELD15 macro

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 80700356474c..2dd32466919d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1395,13 +1395,9 @@ void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
 
 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
 {
-   u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
-
-   tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
+   WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
-   tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
+   WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
udelay(50);
 }
 
-- 
2.12.0

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Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Tom St Denis]

On 05/04/17 09:06 AM, Alex Deucher wrote:

On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis  wrote:

My firmware is

fw.VCE == .feature==0 .firmware==0x34040300
fw.UVD == .feature==0 .firmware==0x015b0b00
fw.MC == .feature==0 .firmware==0x
fw.ME == .feature==46 .firmware==0x00a1
fw.PFP == .feature==46 .firmware==0x00eb
fw.CE == .feature==46 .firmware==0x0086
fw.RLC == .feature==1 .firmware==0x009c
fw.MEC == .feature==46 .firmware==0x02c1
fw.MEC2 == .feature==46 .firmware==0x02c1
fw.SOS == .feature==0 .firmware==0x
fw.ASD == .feature==0 .firmware==0x
fw.SMC == .feature==0 .firmware==0x
fw.SDMA0 == .feature==0 .firmware==0x0022
fw.SDMA1 == .feature==0 .firmware==0x0022

It seems like our all-open is behind what he has for SDMA, SMC, RLC but
ahead for others?  Bizarre.


Can you try the upstream ucode?  That is what Andres is using.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git


Copying the tip of master from that to my /lib/firmware/ results in the 
same firmware versions being loaded.




Alex



Tom


On 04/04/17 04:17 PM, Andres Rodriguez wrote:


This should be the the linux-firmware repository @ commit
6d3bc8886517d171068fd1263176b8b5c51df204

I reverted back to that firmware since I didn't want to deal with
possible bugs when testing my patches.

Regards,
Andres

On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
 wrote:


-Original Message-
From: Andres Rodriguez [mailto:andre...@gmail.com]
Sent: Tuesday, April 04, 2017 4:01 PM
To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
g...@lists.freedesktop.org
Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

This is my info in case that is useful:

 umr.version == ea8e49bb15ed

 fw.VCE == .feature==0 .firmware==0x34040300
 fw.UVD == .feature==0 .firmware==0x014f1000
 fw.MC == .feature==0 .firmware==0x
 fw.ME == .feature==37 .firmware==0x0094
 fw.PFP == .feature==37 .firmware==0x00dc
 fw.CE == .feature==37 .firmware==0x0080
 fw.RLC == .feature==1 .firmware==0x010e
 fw.MEC == .feature==37 .firmware==0x02a2
 fw.MEC2 == .feature==37 .firmware==0x02a2
 fw.SOS == .feature==0 .firmware==0x
 fw.ASD == .feature==0 .firmware==0x
 fw.SMC == .feature==0 .firmware==0x00170f00
 fw.SDMA0 == .feature==31 .firmware==0x0036
 fw.SDMA1 == .feature==0 .firmware==0x0036

 asic.instance == 0


 gfx.max_shader_engines == 4
 gfx.max_tile_pipes == 8
 gfx.max_cu_per_sh == 9
 gfx.max_sh_per_se == 1
 gfx.max_backends_per_se == 2
 gfx.max_texture_channel_caches == 8
 gfx.max_gprs == 256
 gfx.max_gs_threads == 32
 gfx.max_hw_contexts == 8
 gfx.sc_prim_fifo_size_frontend == 32
 gfx.sc_prim_fifo_size_backend == 256
 gfx.sc_hiz_tile_fifo_size == 48
 gfx.sc_earlyz_tile_fifo_size == 304
 gfx.num_tile_pipes == 8
 gfx.backend_enable_mask == 255
 gfx.mem_max_burst_length_bytes == 256
 gfx.mem_row_size_in_kb == 4
 gfx.shader_engine_tile_size == 32
 gfx.num_gpus == 1
 gfx.multi_gpu_tile_size == 64
 gfx.mc_arb_ramcfg == 24738
 gfx.gb_addr_config == 570494979
 gfx.num_rbs == 8
 gfx.family = 130, Volcanic Islands
 gfx.rev_id == 0001
 gfx.external_rev_id == 0051
 gfx.cg_flags == 003fffcd
 AMD_CG_SUPPORT_GFX_MGCG
 AMD_CG_SUPPORT_GFX_CGCG
 AMD_CG_SUPPORT_GFX_CGLS
 AMD_CG_SUPPORT_GFX_CP_LS
 AMD_CG_SUPPORT_GFX_RLC_LS
 AMD_CG_SUPPORT_MC_LS
 AMD_CG_SUPPORT_MC_MGCG
 AMD_CG_SUPPORT_SDMA_LS
 AMD_CG_SUPPORT_SDMA_MGCG
 AMD_CG_SUPPORT_BIF_LS
 AMD_CG_SUPPORT_UVD_MGCG
 AMD_CG_SUPPORT_VCE_MGCG
 AMD_CG_SUPPORT_HDP_LS
 AMD_CG_SUPPORT_HDP_MGCG
 AMD_CG_SUPPORT_ROM_MGCG
 gfx.pg_flags == 



Is this the stock firmware from upstream or the stuff I pointed you to
yesterday on my fdo site?

Alex



Regards,
Andres

On 2017-04-04 03:59 PM, Tom St Denis wrote:


I'm using the latest from all open (our internal FC24 repo).  I'll
fetch
the exact later with "umr -c".

Tom

On Tue, Apr 4, 2017 at 3:48 PM Deucher, Alexander





wrote:


-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On


Behalf


Of Andres Rodriguez
Sent: Tuesday, April 04, 2017 3:39 PM
To: StDenis, Tom; amd-gfx@lists.freedesktop.org
Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES


packet"





On 2017-04-04 08:27 AM, Tom St Denis wrote:


On 03/04/17 04:25 PM, Andres Rodriguez wrote:


Commit e579f56 results in a KCQ initialization error for polaris10
cards. Providing the full SET_RESOURCES packet instead of the


truncated


version 

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Alex Deucher]

On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis  wrote:
> My firmware is
>
> fw.VCE == .feature==0 .firmware==0x34040300
> fw.UVD == .feature==0 .firmware==0x015b0b00
> fw.MC == .feature==0 .firmware==0x
> fw.ME == .feature==46 .firmware==0x00a1
> fw.PFP == .feature==46 .firmware==0x00eb
> fw.CE == .feature==46 .firmware==0x0086
> fw.RLC == .feature==1 .firmware==0x009c
> fw.MEC == .feature==46 .firmware==0x02c1
> fw.MEC2 == .feature==46 .firmware==0x02c1
> fw.SOS == .feature==0 .firmware==0x
> fw.ASD == .feature==0 .firmware==0x
> fw.SMC == .feature==0 .firmware==0x
> fw.SDMA0 == .feature==0 .firmware==0x0022
> fw.SDMA1 == .feature==0 .firmware==0x0022
>
> It seems like our all-open is behind what he has for SDMA, SMC, RLC but
> ahead for others?  Bizarre.

Can you try the upstream ucode?  That is what Andres is using.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git

Alex

>
> Tom
>
>
> On 04/04/17 04:17 PM, Andres Rodriguez wrote:
>>
>> This should be the the linux-firmware repository @ commit
>> 6d3bc8886517d171068fd1263176b8b5c51df204
>>
>> I reverted back to that firmware since I didn't want to deal with
>> possible bugs when testing my patches.
>>
>> Regards,
>> Andres
>>
>> On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
>>  wrote:

 -Original Message-
 From: Andres Rodriguez [mailto:andre...@gmail.com]
 Sent: Tuesday, April 04, 2017 4:01 PM
 To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
 g...@lists.freedesktop.org
 Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

 This is my info in case that is useful:

  umr.version == ea8e49bb15ed

  fw.VCE == .feature==0 .firmware==0x34040300
  fw.UVD == .feature==0 .firmware==0x014f1000
  fw.MC == .feature==0 .firmware==0x
  fw.ME == .feature==37 .firmware==0x0094
  fw.PFP == .feature==37 .firmware==0x00dc
  fw.CE == .feature==37 .firmware==0x0080
  fw.RLC == .feature==1 .firmware==0x010e
  fw.MEC == .feature==37 .firmware==0x02a2
  fw.MEC2 == .feature==37 .firmware==0x02a2
  fw.SOS == .feature==0 .firmware==0x
  fw.ASD == .feature==0 .firmware==0x
  fw.SMC == .feature==0 .firmware==0x00170f00
  fw.SDMA0 == .feature==31 .firmware==0x0036
  fw.SDMA1 == .feature==0 .firmware==0x0036

  asic.instance == 0


  gfx.max_shader_engines == 4
  gfx.max_tile_pipes == 8
  gfx.max_cu_per_sh == 9
  gfx.max_sh_per_se == 1
  gfx.max_backends_per_se == 2
  gfx.max_texture_channel_caches == 8
  gfx.max_gprs == 256
  gfx.max_gs_threads == 32
  gfx.max_hw_contexts == 8
  gfx.sc_prim_fifo_size_frontend == 32
  gfx.sc_prim_fifo_size_backend == 256
  gfx.sc_hiz_tile_fifo_size == 48
  gfx.sc_earlyz_tile_fifo_size == 304
  gfx.num_tile_pipes == 8
  gfx.backend_enable_mask == 255
  gfx.mem_max_burst_length_bytes == 256
  gfx.mem_row_size_in_kb == 4
  gfx.shader_engine_tile_size == 32
  gfx.num_gpus == 1
  gfx.multi_gpu_tile_size == 64
  gfx.mc_arb_ramcfg == 24738
  gfx.gb_addr_config == 570494979
  gfx.num_rbs == 8
  gfx.family = 130, Volcanic Islands
  gfx.rev_id == 0001
  gfx.external_rev_id == 0051
  gfx.cg_flags == 003fffcd
  AMD_CG_SUPPORT_GFX_MGCG
  AMD_CG_SUPPORT_GFX_CGCG
  AMD_CG_SUPPORT_GFX_CGLS
  AMD_CG_SUPPORT_GFX_CP_LS
  AMD_CG_SUPPORT_GFX_RLC_LS
  AMD_CG_SUPPORT_MC_LS
  AMD_CG_SUPPORT_MC_MGCG
  AMD_CG_SUPPORT_SDMA_LS
  AMD_CG_SUPPORT_SDMA_MGCG
  AMD_CG_SUPPORT_BIF_LS
  AMD_CG_SUPPORT_UVD_MGCG
  AMD_CG_SUPPORT_VCE_MGCG
  AMD_CG_SUPPORT_HDP_LS
  AMD_CG_SUPPORT_HDP_MGCG
  AMD_CG_SUPPORT_ROM_MGCG
  gfx.pg_flags == 
>>>
>>>
>>> Is this the stock firmware from upstream or the stuff I pointed you to
>>> yesterday on my fdo site?
>>>
>>> Alex
>>>

 Regards,
 Andres

 On 2017-04-04 03:59 PM, Tom St Denis wrote:
>
> I'm using the latest from all open (our internal FC24 repo).  I'll
> fetch
> the exact later with "umr -c".
>
> Tom
>
> On Tue, Apr 4, 2017 at 3:48 PM Deucher, Alexander

 
>
> wrote:
>
>>> -Original Message-
>>> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On

 Behalf
>>>
>>> Of Andres 

Re: [PATCH 6/6] drm/amdgpu:invoke new implemented AI MB func

[Alex Deucher]

On Wed, Apr 5, 2017 at 5:11 AM, Monk Liu  wrote:
> Change-Id: I70035e7946e2f66804ae5c3bc846d148c633a057
> Signed-off-by: Monk Liu 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 20 +++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 2955c0c..35db2c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -569,6 +569,7 @@ static int soc15_common_early_init(void *handle)
>
> if (amdgpu_sriov_vf(adev)) {
> amdgpu_virt_init_setting(adev);
> +   xgpu_ai_mailbox_set_irq_funcs(adev);
> }
>
> /*
> @@ -621,8 +622,23 @@ static int soc15_common_early_init(void *handle)
> return 0;
>  }
>
> +static int soc15_common_late_init(void *handle)
> +{
> +   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +
> +   if (amdgpu_sriov_vf(adev))
> +   xgpu_ai_mailbox_get_irq(adev);
> +
> +   return 0;
> +}
> +
>  static int soc15_common_sw_init(void *handle)
>  {
> +   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +
> +   if (amdgpu_sriov_vf(adev))
> +   xgpu_ai_mailbox_add_irq_id(adev);
> +
> return 0;
>  }
>
> @@ -653,6 +669,8 @@ static int soc15_common_hw_fini(void *handle)
>
> /* disable the doorbell aperture */
> soc15_enable_doorbell_aperture(adev, false);
> +   if (amdgpu_sriov_vf(adev))
> +   xgpu_ai_mailbox_put_irq(adev);
>
> return 0;
>  }
> @@ -866,7 +884,7 @@ static int soc15_common_set_powergating_state(void 
> *handle,
>  const struct amd_ip_funcs soc15_common_ip_funcs = {
> .name = "soc15_common",
> .early_init = soc15_common_early_init,
> -   .late_init = NULL,
> +   .late_init = soc15_common_late_init,
> .sw_init = soc15_common_sw_init,
> .sw_fini = soc15_common_sw_fini,
> .hw_init = soc15_common_hw_init,
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: fix over allocating of IRQ sources

[Alex Deucher]

On Wed, Apr 5, 2017 at 5:47 AM, Christian König  wrote:
> From: Christian König 
>
> We need an array of pointers to IRQ sources, not an array of sources.
>
> Signed-off-by: Christian König 
> Reported-by: Dan Carpenter 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 1309886..f8a6c95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -327,9 +327,10 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev,
> return -EINVAL;
>
> if (!adev->irq.client[client_id].sources) {
> -   adev->irq.client[client_id].sources = 
> kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
> - sizeof(struct 
> amdgpu_irq_src),
> - GFP_KERNEL);
> +   adev->irq.client[client_id].sources =
> +   kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
> +   sizeof(struct amdgpu_irq_src *),
> +   GFP_KERNEL);
> if (!adev->irq.client[client_id].sources)
> return -ENOMEM;
> }
> --
> 2.5.0
>
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Re: [PATCH] drm/amdgpu: fix 64bit division

[Alex Deucher]

On Wed, Apr 5, 2017 at 5:39 AM, Christian König  wrote:
> From: Christian König 
>
> Added with "handle CPU access for split VRAM buffers".
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 10b793a..c91f13b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -551,9 +551,9 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct 
> ttm_buffer_object *bo,
>  {
> struct drm_mm_node *mm = bo->mem.mm_node;
> uint64_t size = mm->size;
> +   unsigned long offset = page_offset;
>
> -   mm += page_offset / size;
> -   page_offset %= size;
> +   page_offset = do_div(offset, size);
> return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
>  }
>
> --
> 2.5.0
>
> ___
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Re: [PATCH] drm/amdgpu/smu9: update to latest driver interface

[Alex Deucher]

On Tue, Apr 4, 2017 at 11:58 PM, Evan Quan  wrote:
> Signed-off-by: Evan Quan 
> Signed-off-by: Alex Deucher 


Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 57 
> --
>  1 file changed, 53 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h 
> b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
> index aee0214..2037910 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
> @@ -30,7 +30,9 @@
>   * SMU TEAM: Always increment the interface version if
>   * any structure is changed in this file
>   */
> -#define SMU9_DRIVER_IF_VERSION 0xa
> +#define SMU9_DRIVER_IF_VERSION 0xB
> +
> +#define PPTABLE_V10_SMU_VERSION 1
>
>  #define NUM_GFXCLK_DPM_LEVELS  8
>  #define NUM_UVD_DPM_LEVELS 8
> @@ -87,6 +89,11 @@ typedef struct {
>int32_t a0;
>int32_t a1;
>int32_t a2;
> +
> +  uint8_t a0_shift;
> +  uint8_t a1_shift;
> +  uint8_t a2_shift;
> +  uint8_t padding;
>  } GbVdroopTable_t;
>
>  typedef struct {
> @@ -293,7 +300,9 @@ typedef struct {
>uint16_t Platform_sigma;
>uint16_t PSM_Age_CompFactor;
>
> -  uint32_t Reserved[20];
> +  uint32_t DpmLevelPowerDelta;
> +
> +  uint32_t Reserved[19];
>
>/* Padding - ignore */
>uint32_t MmHubPadding[7]; /* SMU internal use */
> @@ -350,8 +359,8 @@ typedef struct {
>  typedef struct {
>uint16_t avgPsmCount[30];
>uint16_t minPsmCount[30];
> -  uint16_t avgPsmVoltage[30]; /* in mV with 2 fractional bits */
> -  uint16_t minPsmVoltage[30]; /* in mV with 2 fractional bits */
> +  floatavgPsmVoltage[30];
> +  floatminPsmVoltage[30];
>
>uint32_t MmHubPadding[7]; /* SMU internal use */
>  } AvfsDebugTable_t;
> @@ -414,5 +423,45 @@ typedef struct {
>  #define UCLK_SWITCH_SLOW 0
>  #define UCLK_SWITCH_FAST 1
>
> +/* GFX DIDT Configuration */
> +#define SQ_Enable_MASK 0x1
> +#define SQ_IR_MASK 0x2
> +#define SQ_PCC_MASK 0x4
> +#define SQ_EDC_MASK 0x8
> +
> +#define TCP_Enable_MASK 0x100
> +#define TCP_IR_MASK 0x200
> +#define TCP_PCC_MASK 0x400
> +#define TCP_EDC_MASK 0x800
> +
> +#define TD_Enable_MASK 0x1
> +#define TD_IR_MASK 0x2
> +#define TD_PCC_MASK 0x4
> +#define TD_EDC_MASK 0x8
> +
> +#define DB_Enable_MASK 0x100
> +#define DB_IR_MASK 0x200
> +#define DB_PCC_MASK 0x400
> +#define DB_EDC_MASK 0x800
> +
> +#define SQ_Enable_SHIFT 0
> +#define SQ_IR_SHIFT 1
> +#define SQ_PCC_SHIFT 2
> +#define SQ_EDC_SHIFT 3
> +
> +#define TCP_Enable_SHIFT 8
> +#define TCP_IR_SHIFT 9
> +#define TCP_PCC_SHIFT 10
> +#define TCP_EDC_SHIFT 11
> +
> +#define TD_Enable_SHIFT 16
> +#define TD_IR_SHIFT 17
> +#define TD_PCC_SHIFT 18
> +#define TD_EDC_SHIFT 19
> +
> +#define DB_Enable_SHIFT 24
> +#define DB_IR_SHIFT 25
> +#define DB_PCC_SHIFT 26
> +#define DB_EDC_SHIFT 27
>
>  #endif
> --
> 2.7.4
>
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Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

[Tom St Denis]

My firmware is

fw.VCE == .feature==0 .firmware==0x34040300
fw.UVD == .feature==0 .firmware==0x015b0b00
fw.MC == .feature==0 .firmware==0x
fw.ME == .feature==46 .firmware==0x00a1
fw.PFP == .feature==46 .firmware==0x00eb
fw.CE == .feature==46 .firmware==0x0086
fw.RLC == .feature==1 .firmware==0x009c
fw.MEC == .feature==46 .firmware==0x02c1
fw.MEC2 == .feature==46 .firmware==0x02c1
fw.SOS == .feature==0 .firmware==0x
fw.ASD == .feature==0 .firmware==0x
fw.SMC == .feature==0 .firmware==0x
fw.SDMA0 == .feature==0 .firmware==0x0022
fw.SDMA1 == .feature==0 .firmware==0x0022

It seems like our all-open is behind what he has for SDMA, SMC, RLC but 
ahead for others?  Bizarre.


Tom

On 04/04/17 04:17 PM, Andres Rodriguez wrote:

This should be the the linux-firmware repository @ commit
6d3bc8886517d171068fd1263176b8b5c51df204

I reverted back to that firmware since I didn't want to deal with
possible bugs when testing my patches.

Regards,
Andres

On Tue, Apr 4, 2017 at 4:03 PM, Deucher, Alexander
 wrote:

-Original Message-
From: Andres Rodriguez [mailto:andre...@gmail.com]
Sent: Tuesday, April 04, 2017 4:01 PM
To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd-
g...@lists.freedesktop.org
Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

This is my info in case that is useful:

 umr.version == ea8e49bb15ed

 fw.VCE == .feature==0 .firmware==0x34040300
 fw.UVD == .feature==0 .firmware==0x014f1000
 fw.MC == .feature==0 .firmware==0x
 fw.ME == .feature==37 .firmware==0x0094
 fw.PFP == .feature==37 .firmware==0x00dc
 fw.CE == .feature==37 .firmware==0x0080
 fw.RLC == .feature==1 .firmware==0x010e
 fw.MEC == .feature==37 .firmware==0x02a2
 fw.MEC2 == .feature==37 .firmware==0x02a2
 fw.SOS == .feature==0 .firmware==0x
 fw.ASD == .feature==0 .firmware==0x
 fw.SMC == .feature==0 .firmware==0x00170f00
 fw.SDMA0 == .feature==31 .firmware==0x0036
 fw.SDMA1 == .feature==0 .firmware==0x0036

 asic.instance == 0


 gfx.max_shader_engines == 4
 gfx.max_tile_pipes == 8
 gfx.max_cu_per_sh == 9
 gfx.max_sh_per_se == 1
 gfx.max_backends_per_se == 2
 gfx.max_texture_channel_caches == 8
 gfx.max_gprs == 256
 gfx.max_gs_threads == 32
 gfx.max_hw_contexts == 8
 gfx.sc_prim_fifo_size_frontend == 32
 gfx.sc_prim_fifo_size_backend == 256
 gfx.sc_hiz_tile_fifo_size == 48
 gfx.sc_earlyz_tile_fifo_size == 304
 gfx.num_tile_pipes == 8
 gfx.backend_enable_mask == 255
 gfx.mem_max_burst_length_bytes == 256
 gfx.mem_row_size_in_kb == 4
 gfx.shader_engine_tile_size == 32
 gfx.num_gpus == 1
 gfx.multi_gpu_tile_size == 64
 gfx.mc_arb_ramcfg == 24738
 gfx.gb_addr_config == 570494979
 gfx.num_rbs == 8
 gfx.family = 130, Volcanic Islands
 gfx.rev_id == 0001
 gfx.external_rev_id == 0051
 gfx.cg_flags == 003fffcd
 AMD_CG_SUPPORT_GFX_MGCG
 AMD_CG_SUPPORT_GFX_CGCG
 AMD_CG_SUPPORT_GFX_CGLS
 AMD_CG_SUPPORT_GFX_CP_LS
 AMD_CG_SUPPORT_GFX_RLC_LS
 AMD_CG_SUPPORT_MC_LS
 AMD_CG_SUPPORT_MC_MGCG
 AMD_CG_SUPPORT_SDMA_LS
 AMD_CG_SUPPORT_SDMA_MGCG
 AMD_CG_SUPPORT_BIF_LS
 AMD_CG_SUPPORT_UVD_MGCG
 AMD_CG_SUPPORT_VCE_MGCG
 AMD_CG_SUPPORT_HDP_LS
 AMD_CG_SUPPORT_HDP_MGCG
 AMD_CG_SUPPORT_ROM_MGCG
 gfx.pg_flags == 


Is this the stock firmware from upstream or the stuff I pointed you to 
yesterday on my fdo site?

Alex



Regards,
Andres

On 2017-04-04 03:59 PM, Tom St Denis wrote:

I'm using the latest from all open (our internal FC24 repo).  I'll fetch
the exact later with "umr -c".

Tom

On Tue, Apr 4, 2017 at 3:48 PM Deucher, Alexander



wrote:


-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On

Behalf

Of Andres Rodriguez
Sent: Tuesday, April 04, 2017 3:39 PM
To: StDenis, Tom; amd-gfx@lists.freedesktop.org
Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES

packet"




On 2017-04-04 08:27 AM, Tom St Denis wrote:

On 03/04/17 04:25 PM, Andres Rodriguez wrote:

Commit e579f56 results in a KCQ initialization error for polaris10
cards. Providing the full SET_RESOURCES packet instead of the

truncated

version fixes the problem.

I think this patch may have been one of the stabs at fixing the KCQ
suspend/resume errors. I *think* it may no longer be needed if that

is

the case.

Sending this mostly as an FYI to get the patch removed from the

4.12-wip

This reverts commit e579f564c333a7eaddf7e12b1b8414410c36e80f.
---
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
  1 file changed, 5 

[PATCH] drm/amdgpu: fix over allocating of IRQ sources

[Christian König]

From: Christian König 

We need an array of pointers to IRQ sources, not an array of sources.

Signed-off-by: Christian König 
Reported-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 1309886..f8a6c95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -327,9 +327,10 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev,
return -EINVAL;
 
if (!adev->irq.client[client_id].sources) {
-   adev->irq.client[client_id].sources = 
kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
- sizeof(struct 
amdgpu_irq_src),
- GFP_KERNEL);
+   adev->irq.client[client_id].sources =
+   kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
+   sizeof(struct amdgpu_irq_src *),
+   GFP_KERNEL);
if (!adev->irq.client[client_id].sources)
return -ENOMEM;
}
-- 
2.5.0

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[PATCH] drm/amdgpu: fix 64bit division

[Christian König]

From: Christian König 

Added with "handle CPU access for split VRAM buffers".

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 10b793a..c91f13b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -551,9 +551,9 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct 
ttm_buffer_object *bo,
 {
struct drm_mm_node *mm = bo->mem.mm_node;
uint64_t size = mm->size;
+   unsigned long offset = page_offset;
 
-   mm += page_offset / size;
-   page_offset %= size;
+   page_offset = do_div(offset, size);
return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 }
 
-- 
2.5.0

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[PATCH 4/6] drm/amdgpu:implement the reset MB func for vega10

[Monk Liu]

they are lack in the bringup stage, we need them for GPU reset
feature.

Change-Id: I43165a223277f77a6e85d8c28749b690d7f8d51e
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 133 ++
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   5 ++
 2 files changed, 138 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 740c0f8..1493301 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -28,6 +28,7 @@
 #include "vega10/GC/gc_9_0_offset.h"
 #include "vega10/GC/gc_9_0_sh_mask.h"
 #include "soc15.h"
+#include "vega10_ih.h"
 #include "soc15_common.h"
 #include "mxgpu_ai.h"
 
@@ -180,6 +181,11 @@ static int xgpu_ai_send_access_requests(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int xgpu_ai_request_reset(struct amdgpu_device *adev)
+{
+   return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
+}
+
 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,
   bool init)
 {
@@ -201,7 +207,134 @@ static int xgpu_ai_release_full_gpu_access(struct 
amdgpu_device *adev,
return r;
 }
 
+static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
+   struct amdgpu_irq_src *source,
+   struct amdgpu_iv_entry *entry)
+{
+   DRM_DEBUG("get ack intr and do nothing.\n");
+   return 0;
+}
+
+static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,
+   struct amdgpu_irq_src *source,
+   unsigned type,
+   enum amdgpu_interrupt_state state)
+{
+   u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_MAILBOX_INT_CNTL));
+
+   tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
+   (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), 
tmp);
+
+   return 0;
+}
+
+static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
+{
+   struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, 
flr_work);
+   struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, 
virt);
+
+   /* wait until RCV_MSG become 3 */
+   if (xgpu_ai_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
+   pr_err("failed to recieve FLR_CMPL\n");
+   return;
+   }
+
+   /* Trigger recovery due to world switch failure */
+   amdgpu_sriov_gpu_reset(adev, false);
+}
+
+static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *src,
+  unsigned type,
+  enum amdgpu_interrupt_state state)
+{
+   u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_MAILBOX_INT_CNTL));
+
+   tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
+   (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), 
tmp);
+
+   return 0;
+}
+
+static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *source,
+  struct amdgpu_iv_entry *entry)
+{
+   int r;
+
+   /* see what event we get */
+   r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
+
+   /* only handle FLR_NOTIFY now */
+   if (!r)
+   schedule_work(>virt.flr_work);
+
+   return 0;
+}
+
+static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = {
+   .set = xgpu_ai_set_mailbox_ack_irq,
+   .process = xgpu_ai_mailbox_ack_irq,
+};
+
+static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = {
+   .set = xgpu_ai_set_mailbox_rcv_irq,
+   .process = xgpu_ai_mailbox_rcv_irq,
+};
+
+void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)
+{
+   adev->virt.ack_irq.num_types = 1;
+   adev->virt.ack_irq.funcs = _ai_mailbox_ack_irq_funcs;
+   adev->virt.rcv_irq.num_types = 1;
+   adev->virt.rcv_irq.funcs = _ai_mailbox_rcv_irq_funcs;
+}
+
+int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
+{
+   int r;
+
+   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, 
>virt.rcv_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, 
>virt.ack_irq);
+   if (r) {
+   amdgpu_irq_put(adev, >virt.rcv_irq, 0);
+   return r;
+   }
+
+   return 0;
+}
+
+int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)
+{
+   int r;
+
+   r = amdgpu_irq_get(adev, >virt.rcv_irq, 0);
+   if (r)
+   return r;
+

Re: [PATCH 1/6] drm/amdgpu:add PSP block only load_type=PSP

[Christian König]

Am 05.04.2017 um 11:11 schrieb Monk Liu:

SRIOV currently only can load ucode directly, and PSP
block is not supported by VF temporarily.

will remove this restrict and use PSP load all ucode
even for SRIOV later

Change-Id: I6df5c4088c7c72d01928d5af8bfe5520447619ba
Signed-off-by: Monk Liu 


Reviewed-by: Christian König  for the whole 
series.



---
  drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 06afbcc..2955c0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -497,7 +497,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, _v1_0_ip_block);
amdgpu_ip_block_add(adev, _v9_0_ip_block);
amdgpu_ip_block_add(adev, _ih_ip_block);
-   amdgpu_ip_block_add(adev, _v3_1_ip_block);
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+   amdgpu_ip_block_add(adev, _v3_1_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, _pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))



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[PATCH 5/6] drm/amdgpu:timeout set to equal with VI

[Monk Liu]

Change-Id: I9d170ff4893e982a955f19a91764cdfed619bc85
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
index a9815b6..9aefc44 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
@@ -24,7 +24,7 @@
 #ifndef __MXGPU_AI_H__
 #define __MXGPU_AI_H__
 
-#define AI_MAILBOX_TIMEDOUT15
+#define AI_MAILBOX_TIMEDOUT5000
 
 enum idh_request {
IDH_REQ_GPU_INIT_ACCESS = 1,
-- 
2.7.4

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[PATCH 1/6] drm/amdgpu:add PSP block only load_type=PSP

[Monk Liu]

SRIOV currently only can load ucode directly, and PSP
block is not supported by VF temporarily.

will remove this restrict and use PSP load all ucode
even for SRIOV later

Change-Id: I6df5c4088c7c72d01928d5af8bfe5520447619ba
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 06afbcc..2955c0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -497,7 +497,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, _v1_0_ip_block);
amdgpu_ip_block_add(adev, _v9_0_ip_block);
amdgpu_ip_block_add(adev, _ih_ip_block);
-   amdgpu_ip_block_add(adev, _v3_1_ip_block);
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+   amdgpu_ip_block_add(adev, _v3_1_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, _pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[Christian König]

Am 05.04.2017 um 08:43 schrieb Junwei Zhang:

By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all

Signed-off-by: Junwei Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
  7 files changed, 74 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 65021df..d7f75ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t 
reg, uint32_t v,
  bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
  bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
  
+uint32_t amdgpu_get_block_size(int vm_size);

+
  /*
   * Registers read & write functions.
   */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..2f91c2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
  }
  
-static void amdgpu_get_block_size(struct amdgpu_device *adev)

+uint32_t amdgpu_get_block_size(int vm_size)
+{
+   /* Total bits covered by PD + PTs */
+   unsigned bits = ilog2(vm_size) + 18;
+
+   /* Make sure the PD is 4K in size up to 8GB address space.
+  Above that split equal between PD and PTs */
+   if (vm_size <= 8)
+   return (bits - 9);
+   else
+   return ((bits + 3) / 2);
+}


Please move that helper into amdgpu_vmc.c.


+
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
  {
/* defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 * page table and the remaining bits are in the page directory */
-   if (amdgpu_vm_block_size == -1) {
-
-   /* Total bits covered by PD + PTs */
-   unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
-   /* Make sure the PD is 4K in size up to 8GB address space.
-  Above that split equal between PD and PTs */
-   if (amdgpu_vm_size <= 8)
-   amdgpu_vm_block_size = bits - 9;
-   else
-   amdgpu_vm_block_size = (bits + 3) / 2;
+   if (amdgpu_vm_block_size == -1)
+   return;
  
-	} else if (amdgpu_vm_block_size < 9) {

+   if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
 amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
}
  
  	if (amdgpu_vm_block_size > 24 ||

(amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
dev_warn(adev->dev, "VM page table size (%d) too large\n",
 amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
}
+
+   return;
+
+def_value:
+   amdgpu_vm_block_size = -1;
  }
  
  static void amdgpu_check_vm_size(struct amdgpu_device *adev)

@@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device 
*adev)
return;
  
  def_value:

-   amdgpu_vm_size = 8;
-   dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+   amdgpu_vm_size = -1;;
  }
  
  /**

@@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device 
*adev)
  
  	amdgpu_check_vm_size(adev);
  
-	amdgpu_get_block_size(adev);

+   amdgpu_check_block_size(adev);
  
  	if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||

!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
  unsigned amdgpu_ip_block_mask = 0x;
  int amdgpu_bapm = -1;
  int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
  int amdgpu_vm_block_size = -1;
  int amdgpu_vm_fault_stop = 0;
  int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30d5c42..f46c52c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,8 +849,14 @@ static int 

[PATCH] drm/amd/display: fix NULL pointer dereference.

[Rex Zhu]

on vega10, driver can run into a NULL-pointer dereference.

Change-Id: I8e2de5343f804d6e736f620ff6d3d6e6488fb970
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 62be159..8f5951f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1095,7 +1095,8 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device 
*adev)
DRM_ERROR("KMS: Failed to allocate surface\n");
goto fail_free_planes;
}
-   mode_info->planes[i]->plane_type = mode_info->plane_type[i];
+   if (mode_info->plane_type != NULL)
+   mode_info->planes[i]->plane_type = 
mode_info->plane_type[i];
if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) {
DRM_ERROR("KMS: Failed to initialize plane\n");
goto fail_free_planes;
-- 
1.9.1

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[PATCH] drm/amdgpu: set vm size and block size by individual gmc by default

[Junwei Zhang]

By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 10 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 10 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 30 ++--
 7 files changed, 74 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 65021df..d7f75ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t 
reg, uint32_t v,
 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
 
+uint32_t amdgpu_get_block_size(int vm_size);
+
 /*
  * Registers read & write functions.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..2f91c2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
 }
 
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+uint32_t amdgpu_get_block_size(int vm_size)
+{
+   /* Total bits covered by PD + PTs */
+   unsigned bits = ilog2(vm_size) + 18;
+
+   /* Make sure the PD is 4K in size up to 8GB address space.
+  Above that split equal between PD and PTs */
+   if (vm_size <= 8)
+   return (bits - 9);
+   else
+   return ((bits + 3) / 2);
+}
+
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
 {
/* defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 * page table and the remaining bits are in the page directory */
-   if (amdgpu_vm_block_size == -1) {
-
-   /* Total bits covered by PD + PTs */
-   unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
-   /* Make sure the PD is 4K in size up to 8GB address space.
-  Above that split equal between PD and PTs */
-   if (amdgpu_vm_size <= 8)
-   amdgpu_vm_block_size = bits - 9;
-   else
-   amdgpu_vm_block_size = (bits + 3) / 2;
+   if (amdgpu_vm_block_size == -1)
+   return;
 
-   } else if (amdgpu_vm_block_size < 9) {
+   if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
 amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
}
 
if (amdgpu_vm_block_size > 24 ||
(amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
dev_warn(adev->dev, "VM page table size (%d) too large\n",
 amdgpu_vm_block_size);
-   amdgpu_vm_block_size = 9;
+   goto def_value;
}
+
+   return;
+
+def_value:
+   amdgpu_vm_block_size = -1;
 }
 
 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device 
*adev)
return;
 
 def_value:
-   amdgpu_vm_size = 8;
-   dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+   amdgpu_vm_size = -1;;
 }
 
 /**
@@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device 
*adev)
 
amdgpu_check_vm_size(adev);
 
-   amdgpu_get_block_size(adev);
+   amdgpu_check_block_size(adev);
 
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
 unsigned amdgpu_ip_block_mask = 0x;
 int amdgpu_bapm = -1;
 int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
 int amdgpu_vm_block_size = -1;
 int amdgpu_vm_fault_stop = 0;
 int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30d5c42..f46c52c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle)
if (r)
return r;
 
-   adev->vm_manager.vm_size = amdgpu_vm_size;