RE: [PATCH libdrm v2 1/1] amdgpu: move asic id table to a separate file
> If you add this here, you should add the ids file itself and make libdrm > install it too... ? Here the ids file is separate from libdrm. It is passed during compilation so that libdrm knows where to get it. > You can't use strtok() in a library. Any other thread may call strtok() > anytime too and screw you up. Right, better to call strtok_r() instead. > The manpage says len must be 0 before the first getline() call. Right, that shall be safer. >> + printf("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line); >debug leftover? This is to print out the ids file version. Thanks, Sam -Original Message- From: Grazvydas Ignotas [mailto:nota...@gmail.com] Sent: Friday, May 12, 2017 8:16 AM To: Li, Samuel Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie Subject: Re: [PATCH libdrm v2 1/1] amdgpu: move asic id table to a separate file On Fri, May 12, 2017 at 12:19 AM, Samuel Li wrote: > From: Xiaojie Yuan > > v2: fix an off by one error and leading white spaces > > Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9 > Reviewed-by: Junwei Zhang > Signed-off-by: Samuel Li > --- > amdgpu/Makefile.am | 2 + > amdgpu/Makefile.sources | 2 +- > amdgpu/amdgpu_asic_id.c | 198 > +++ > amdgpu/amdgpu_asic_id.h | 165 --- > amdgpu/amdgpu_device.c | 28 +-- > amdgpu/amdgpu_internal.h | 10 +++ > 6 files changed, 232 insertions(+), 173 deletions(-) create mode > 100644 amdgpu/amdgpu_asic_id.c delete mode 100644 > amdgpu/amdgpu_asic_id.h > > diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am index > cf7bc1b..ecf9e82 100644 > --- a/amdgpu/Makefile.am > +++ b/amdgpu/Makefile.am > @@ -30,6 +30,8 @@ AM_CFLAGS = \ > $(PTHREADSTUBS_CFLAGS) \ > -I$(top_srcdir)/include/drm > > +AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\" If you add this here, you should add the ids file itself and make libdrm install it too... > + > libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la libdrm_amdgpu_ladir > = $(libdir) libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 > -no-undefined diff --git a/amdgpu/Makefile.sources > b/amdgpu/Makefile.sources index 487b9e0..bc3abaa 100644 > --- a/amdgpu/Makefile.sources > +++ b/amdgpu/Makefile.sources > @@ -1,5 +1,5 @@ > LIBDRM_AMDGPU_FILES := \ > - amdgpu_asic_id.h \ > + amdgpu_asic_id.c \ > amdgpu_bo.c \ > amdgpu_cs.c \ > amdgpu_device.c \ > diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c new > file mode 100644 index 000..067f38c > --- /dev/null > +++ b/amdgpu/amdgpu_asic_id.c > @@ -0,0 +1,198 @@ > +/* > + * Copyright © 2017 Advanced Micro Devices, Inc. > + * All Rights Reserved. > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > +"Software"), > + * to deal in the Software without restriction, including without > +limitation > + * the rights to use, copy, modify, merge, publish, distribute, > +sublicense, > + * and/or sell copies of the Software, and to permit persons to whom > +the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be > +included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > +MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT > +SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, > +DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR > +OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE > +OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#ifdef HAVE_CONFIG_H > +#include "config.h" > +#endif > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "amdgpu_drm.h" > +#include "amdgpu_internal.h" > + > +static int parse_one_line(const char *line, struct amdgpu_asic_id > +*id) { > + char *buf; > + char *s_did; > + char *s_rid; > + char *s_name; > + char *endptr; > + int r = 0; > + > + buf = strdup(line); > + if (!buf) > + return -ENOMEM; > + > + /* ignore empty line and commented line */ > + if (strlen(line) == 0 || line[0] == '#') { > + r = -EAGAIN; > + goto out; > + } > + > + /* device id */ > + s_did = strtok(buf, ","); You can't use strtok() in a library. Any other thread may call strtok() anytime too and screw you up. > + if (!s_did) { > + r = -EINVAL; > + goto out; > + } > + > + id->did = strtol(s_did, &endptr, 16); > + if (*endptr) {
Re: Support for amdgpu VM update via CPU on large-bar systems
On 17-05-12 04:43 AM, Christian König wrote: > Am 12.05.2017 um 10:37 schrieb zhoucm1: >> >> >> >> If the sdma is faster, even they wait for finish, which time is >> shorter than CPU, isn't it? Of course, the precondition is sdma is >> exclusive. They can reserve a sdma for PT updating. >> > > No, if I understood Felix numbers correctly the setup and wait time > for SDMA is a bit (but not much) longer than doing it with the CPU. I'm skeptical of claims that SDMA is faster. Even when you use SDMA to write the page table, the CPU still has to do about the same amount of work writing PTEs into the SDMA IBs. SDMA can only save CPU time in certain cases: * Copying PTEs from GART table if they are on the same GPU (not possible on Vega10 due to different MTYPE bits) * Generating PTEs for contiguous VRAM BOs At least for system memory BOs writing the PTEs directly to write-combining VRAM should be faster than writing them to cached system memory IBs first and then kicking off an SDMA transfer and waiting for completion. > > What would really help is to fix the KFD design and work with async > page tables updates there as well. That problem goes much higher up the stack than just KFD. It would affect memory management interfaces in the HSA runtime and HCC. The basic idea is to make the GPU behave very similar to a CPU and to have multi-threaded code where some threads run on the CPU and others on the GPU almost seamlessly. You allocate memory and then you use the same pointer in your CPU and GPU threads. Exposing the messiness of asynchronous page table updates all the way up to the application would destroy that programming model. In this model, latency matters most. The longer it takes to kick off a parallel GPU processing job, the less efficient scaling you get from the GPUs parallel processing capabilities. Exposing asynchronous memory management up the stack would allow the application to hide the latency in some cases (if it can do other useful things in the mean time), but it doesn't make the latency disappear. An application that wants to hide memory management latency can do this, even with the existing programming model, by separating memory management and processing into separate threads. Regards, Felix ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/3] drm/amdgpu: cleanup adjust_mc_addr handling
Hi Christian, One comment inline [FK]. If this is not a problem, then feel free to add my R-B for the whole series. Kent, when we adopt this change, we need to convert the PDE back to an address, because KFD needs to fill just the page directory base address into the map_process HIQ packet. I think the existing amdgpu_amdkfd_gpuvm_get_process_page_dir already takes care of that just by right-shifting the address. Regards, Felix On 17-05-12 09:48 AM, Christian König wrote: > From: Christian König > > Rename adjust_mc_addr to get_vm_pde, check the address bits in one place and > move setting the valid bit in there as well. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +++-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 > -- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 + > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 ++ > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +++- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +++- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++ > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 + > drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 10 ++ > drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 + > 10 files changed, 46 insertions(+), 50 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index fadeb55..bc089eb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -309,8 +309,8 @@ struct amdgpu_gart_funcs { > /* set pte flags based per asic */ > uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, >uint32_t flags); > - /* adjust mc addr in fb for APU case */ > - u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); > + /* get the pde for a given mc addr */ > + u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); > uint32_t (*get_invalidate_req)(unsigned int vm_id); > }; > > @@ -1816,6 +1816,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) > #define amdgpu_asic_get_config_memsize(adev) > (adev)->asic_funcs->get_config_memsize((adev)) > #define amdgpu_gart_flush_gpu_tlb(adev, vmid) > (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) > #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) > (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) > +#define amdgpu_gart_get_vm_pde(adev, addr) > (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) > #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) > ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) > #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) > ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), > (incr))) > #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) > ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), > (incr), (flags))) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > index 88420dc..c10f3ce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > @@ -682,16 +682,6 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct > amdgpu_ring *ring) > return false; > } > > -static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) > -{ > - u64 addr = mc_addr; > - > - if (adev->gart.gart_funcs->adjust_mc_addr) > - addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr); > - > - return addr; > -} > - > bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, > struct amdgpu_job *job) > { > @@ -1034,19 +1024,17 @@ static int amdgpu_vm_update_level(struct > amdgpu_device *adev, > (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { > > if (count) { > - uint64_t pt_addr = > - amdgpu_vm_adjust_mc_addr(adev, last_pt); > + uint64_t entry; > > + entry = amdgpu_gart_get_vm_pde(adev, last_pt); > if (shadow) > amdgpu_vm_do_set_ptes(¶ms, > last_shadow, > - pt_addr, count, > - incr, > - AMDGPU_PTE_VALID); > + entry, count, > + incr, 0); [FK] For count >=3 this would result in an SDMA_OP_PTEPDE packet with flags=0 and the flags included in the address. Could SDMA mask out the flags bits from the address before it applies the flags? The SDMA 4.0 MA
Re: [PATCH 00/31] DC Patches May 12, 2017
Yeah, there's still a patch in the queue that should fix it. Just didn't make this push. Harry On 2017-05-12 11:53 AM, Tom St Denis wrote: Still getting noise in dmesg with DCN enabled on my carrizo/vega10 setup. It's otherwise fine. Tom On 12/05/17 11:20 AM, Harry Wentland wrote: * Fix deadlock when plugging MST display * Fix DVI->HDMI dongles * Bunch of raven bandwidth changes * Some more cleanup for i2c/aux Amy Zhang (1): drm/amd/display: Move output transfer function to stream updates Andrey Grodzovsky (4): drm/amd/display: i2c Remove link index. drm/amd/display: DP aux Remove link index. drm/amd/display: i2c/aux Remove link index. drm/amd/display: Fix race. Anthony Koo (2): drm/amd/display: use signal type to decide whether to set backlight drm/amd/display: Implement support for backlight optimization Charlene Liu (1): drm/amd/display: single channel bandwidth verses dual channel bandwidth Corbin McElhanney (1): drm/amd/display: fix freesync not working on raven Dmytro Laktyushkin (9): drm/amd/display: bw debug options now apply to dml as well drm/amd/display: prevent assert on error of 1 in calc_freesync_range drm/amd/display: refactor bw related variable structure in val_ctx drm/amd/display: switch to using calc_clk and cur_clk for dcn bw setting drm/amd/display: enable watermark range reporting to pplib drm/amd/display: fix scaling calculation for proper surface input format drm/amd/display: add yuv pixel formats to pixel_format_to_bpp() drm/amd/display: fix scaling info based surface update type check drm/amd/display: add explanation for surface_update_type Harry Wentland (6): drm/amd/display: Don't call PSR func if DMCU is off drm/amd/display: Keep DVI_SINGLE_LINK signal if low clk drm/amd/display: ifdef some code only needed for DCN drm/amd/display: Use MED update type if clip position changes drm/amd/display: Add mem_input header to non-DCN builds drm/amd/display: DCE12 num_timing_generators should be 6 Ken Chalmers (1): drm/amd/display: Continue with stream enable if DP link training fails. Leon Elazar (1): drm/amd/display: Allow MPO on Raven Pratik Vishwakarma (1): drm/amd/display: get_atomic_property missing for drm_connector_funcs Sun peng Li (1): drm/amd/display: Reverting locks around updating freesync property Tony Cheng (1): drm/amd/display: do not set_mpc_tree if tree is already setup Yongqiang Sun (2): drm/amd/display: Only apply ctx for specific surface. drm/amd/display: Add 64KB_S_T and 64KB_D_T swizzle mode. drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 38 +++--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 82 +--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h| 6 + drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 18 +-- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 131 +++ drivers/gpu/drm/amd/display/dc/core/dc.c | 140 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 59 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 69 ++ drivers/gpu/drm/amd/display/dc/dc.h| 51 +--- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 20 +-- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 36 -- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 11 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 12 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c| 9 +- .../drm/amd/display/dc/dce100/dce100_resource.c| 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c| 100 --- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 12 +- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 6 +- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 30 ++--- .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 6 +- .../drm/amd/display/dc/dce110/dce110_resource.c| 63 +- .../drm/amd/display/dc/dce112/dce112_resource.c| 63 +- .../drm/amd/display/dc/dce120/dce120_resource.c| 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 121 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 6 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 + drivers/gpu/drm/amd/display/dc/inc/core_types.h| 61 +++-- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 29 + drivers/gpu/drm/amd/display/dc/inc/hw/abm.h| 2 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h| 2 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 20 +-- drivers/gpu
RE: [PATCH 1/1] amdgpu: move asic id table to a separate file
My understanding is this is actually a data file. Similar to amdgpu firmware, which is also separate from the kernel source code. Sam -Original Message- From: Michel Dänzer [mailto:mic...@daenzer.net] Sent: Thursday, May 11, 2017 8:50 PM To: Li, Samuel Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate file On 12/05/17 06:13 AM, Li, Samuel wrote: > Submitted a request to create a new repo on freedesktop. What's the point of having a separate repository upstream? Can't we just keep it in the libdrm repository? -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/31] drm/amd/display: get_atomic_property missing for drm_connector_funcs
From: Pratik Vishwakarma DRM_IOCTL_MODE_GETCONNECTOR fails with EINVAL on enabling DRIVER_ATOMIC With this DRM_IOCTL_MODE_GETCONNECTOR returns all the connector properties. freesync_property and freesync_capable_property return 0 currently. TESTS(On Chromium OS on Stoney Only) * Builds without compilation errors. * 'atomictest' proceeds after applying patch and fails with vblank event timed out. * Chromium OS ui comes up. Change-Id: Ia020a085e27a95492b15934223f8da8ee6b635bf Signed-off-by: Pratik Vishwakarma Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 53 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h| 6 +++ 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 9e5ff1cf1fc2..1fd5d1a17019 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1367,6 +1367,56 @@ int amdgpu_dm_connector_atomic_set_property( return ret; } +int amdgpu_dm_connector_atomic_get_property( + struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct dm_connector_state *dm_state = + to_dm_connector_state(state); + int ret = -EINVAL; + + if (property == dev->mode_config.scaling_mode_property) { + switch (dm_state->scaling) { + case RMX_CENTER: + *val = DRM_MODE_SCALE_CENTER; + break; + case RMX_ASPECT: + *val = DRM_MODE_SCALE_ASPECT; + break; + case RMX_FULL: + *val = DRM_MODE_SCALE_FULLSCREEN; + break; + case RMX_OFF: + default: + *val = DRM_MODE_SCALE_NONE; + break; + } + ret = 0; + } else if (property == adev->mode_info.underscan_hborder_property) { + *val = dm_state->underscan_hborder; + ret = 0; + } else if (property == adev->mode_info.underscan_vborder_property) { + *val = dm_state->underscan_vborder; + ret = 0; + } else if (property == adev->mode_info.underscan_property) { + *val = dm_state->underscan_enable; + ret = 0; + } else if (property == adev->mode_info.freesync_property) { + //TODO + *val = 0; + ret = 0; + } else if (property == adev->mode_info.freesync_capable_property) { + //TODO + *val = 0; + ret = 0; + } + return ret; +} + void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); @@ -1438,7 +1488,8 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .destroy = amdgpu_dm_connector_destroy, .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, - .atomic_set_property = amdgpu_dm_connector_atomic_set_property + .atomic_set_property = amdgpu_dm_connector_atomic_set_property, + .atomic_get_property = amdgpu_dm_connector_atomic_get_property }; static struct drm_encoder *best_encoder(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index ab6d51dbbf4b..b69c86826b1a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -71,6 +71,12 @@ int amdgpu_dm_connector_atomic_set_property( struct drm_property *property, uint64_t val); +int amdgpu_dm_connector_atomic_get_property( + struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val); + int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); void amdgpu_dm_connector_init_helper( -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 26/31] drm/amd/display: Add mem_input header to non-DCN builds
Change-Id: I0446e77334b14287614b21fe847afe44e4c5bac4 Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 52ac6d19adec..46bd0318e6be 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -31,8 +31,8 @@ #include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mem_input.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mpc.h" #endif -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 27/31] drm/amd/display: DCE12 num_timing_generators should be 6
We should also use it to determine pipe count. Change-Id: I8ce59db6cbe6a2fe020a9797cd988dcfc79caa06 Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b6bdd1d52922..b13abb025e1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -426,7 +426,7 @@ static const struct bios_registers bios_regs = { }; static const struct resource_caps res_cap = { - .num_timing_generator = 3, + .num_timing_generator = 6, .num_audio = 7, .num_stream_encoder = 6, .num_pll = 6, @@ -909,7 +909,7 @@ static bool construct( pool->base.funcs = &dce120_res_pool_funcs; /* TODO: Fill more data from GreenlandAsicCapability.cpp */ - pool->base.pipe_count = 6; + pool->base.pipe_count = res_cap.num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; dc->public.caps.max_downscale_ratio = 200; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/31] drm/amd/display: do not set_mpc_tree if tree is already setup
From: Tony Cheng Change-Id: I7140155a62c2a25ba888cb02e93ecff5df54f61e Signed-off-by: Tony Cheng Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 30 +- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ece8c96f3636..41a6fa507982 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -828,7 +828,7 @@ static void reset_front_end_for_pipe( /* TODO: build stream pipes group id. For now, use stream otg * id as pipe group id */ - tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx]; + tree_cfg = &dc->current_context->res_ctx.mpc_tree[pipe_ctx->mpc_idx]; if (pipe_ctx->top_pipe == NULL) dcn10_delete_mpc_tree(mpc, tree_cfg); @@ -1523,6 +1523,8 @@ static void update_dchubp_dpp( struct tg_color black_color = {0}; struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc); + struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + /* depends on DML calculation, DPP clock value may change dynamically */ enable_dppclk( dc->ctx, @@ -1566,6 +1568,7 @@ static void update_dchubp_dpp( */ pipe_ctx->mpc_idx = pipe_ctx->tg->inst; tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx]; + /* enable when bottom pipe is present and * it does not share a surface with current pipe */ @@ -1576,21 +1579,29 @@ static void update_dchubp_dpp( pipe_ctx->scl_data.lb_params.alpha_en = 0; tree_cfg->mode = TOP_PASSTHRU; } - if (!pipe_ctx->top_pipe) { + if (!pipe_ctx->top_pipe && !cur_pipe_ctx->bottom_pipe) { /* primary pipe, set mpc tree index 0 only */ tree_cfg->num_pipes = 1; tree_cfg->opp_id = pipe_ctx->tg->inst; tree_cfg->dpp[0] = pipe_ctx->pipe_idx; tree_cfg->mpcc[0] = pipe_ctx->pipe_idx; - dcn10_set_mpc_tree(mpc, tree_cfg); - } else { - /* TODO: add position is hard code to 1 for now -* If more than 2 pipes are supported, calculate position -*/ + } + + if (!cur_pipe_ctx->top_pipe && !pipe_ctx->top_pipe) { + + if (!cur_pipe_ctx->bottom_pipe) + dcn10_set_mpc_tree(mpc, tree_cfg); + + } else if (!cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe) { + dcn10_add_dpp(mpc, tree_cfg, pipe_ctx->pipe_idx, pipe_ctx->pipe_idx, 1); + } else { + /* nothing to be done here */ + ASSERT(cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe); } + color_space = pipe_ctx->stream->public.output_color_space; color_space_to_black_color(dc, color_space, &black_color); dcn10_set_mpc_background_color(mpc, pipe_ctx->pipe_idx, &black_color); @@ -1641,13 +1652,18 @@ static void program_all_pipe_in_tree( pipe_ctx->mi, &context->watermarks, ref_clk_mhz); lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst); } + pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal; + pipe_ctx->tg->funcs->program_global_sync( pipe_ctx->tg); + + + update_dchubp_dpp(dc, pipe_ctx, context); } -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/31] drm/amd/display: Implement support for backlight optimization
From: Anthony Koo - Add functionality to get real hw backlight level as opposed to user level, meaning the level that takes into account backlight ramping over time and backlight reduction due to Varibright - Add backlight optimization which allows for a second OS state that is able to control ABM Change-Id: Ieff9c0d9083ee77d3eba3a7636d39bcbe689980a Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 13 +++-- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 393c43559825..cefffe164fe0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -60,7 +60,7 @@ struct abm_backlight_registers { static struct abm_backlight_registers stored_backlight_registers = {0}; -static unsigned int get_current_backlight(struct dce_abm *abm_dce) +static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce) { uint64_t current_backlight; uint32_t round_result; @@ -252,7 +252,7 @@ static void dmcu_set_backlight_level( static void dce_abm_init(struct abm *abm) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); - unsigned int backlight = get_current_backlight(abm_dce); + unsigned int backlight = get_current_backlight_16_bit(abm_dce); REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); @@ -289,6 +289,14 @@ static void dce_abm_init(struct abm *abm) ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); } +static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); + + return (backlight >> 8); +} + static bool dce_abm_set_level(struct abm *abm, uint32_t level) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); @@ -405,6 +413,7 @@ static const struct abm_funcs dce_funcs = { .set_abm_level = dce_abm_set_level, .init_backlight = dce_abm_init_backlight, .set_backlight_level = dce_abm_set_backlight_level, + .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit, .is_dmcu_initialized = is_dmcu_initialized }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index ceabbd3bf5f8..da465b3e98e8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -40,6 +40,7 @@ struct abm_funcs { unsigned int backlight_level, unsigned int frame_ramp, unsigned int controller_id); + unsigned int (*get_current_backlight_8_bit)(struct abm *abm); bool (*is_dmcu_initialized)(struct abm *abm); }; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 29/31] drm/amd/display: add yuv pixel formats to pixel_format_to_bpp()
From: Dmytro Laktyushkin Change-Id: I8a8430148070cb3356273c498516d73bfeb986c8 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1e6952bde25b..bc9808180346 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1051,8 +1051,13 @@ static bool is_surface_in_context( static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) { switch (format) { + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + return 12; case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: return 16; case SURFACE_PIXEL_FORMAT_GRPH_ARGB: case SURFACE_PIXEL_FORMAT_GRPH_ABGR: -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/31] drm/amd/display: DP aux Remove link index.
From: Andrey Grodzovsky Header change for DAL change under same name. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 013e796b0a40..b3a9fcc2cee2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -562,7 +562,7 @@ enum amdgpu_connector_dither { struct amdgpu_dm_dp_aux { struct drm_dp_aux aux; - uint32_t link_index; + struct ddc_service *ddc_service; }; struct amdgpu_i2c_adapter { -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 30/31] drm/amd/display: fix scaling info based surface update type check
From: Dmytro Laktyushkin Change-Id: I8747a1bb298e57824515f126990429dbbca05ecd Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 47 +--- 1 file changed, 13 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bc9808180346..6d56cb0c29cc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1122,45 +1122,24 @@ static enum surface_update_type get_plane_info_update_type( static enum surface_update_type get_scaling_info_update_type( const struct dc_surface_update *u) { - struct dc_scaling_info temp_scaling_info = { { 0 } }; - if (!u->scaling_info) return UPDATE_TYPE_FAST; - /* Copy all parameters that will cause a full update -* from current surface, the rest of the parameters -* from provided plane configuration. -* Perform memory compare and special validation -* for those that can cause fast/medium updates -*/ - - /* Full Update Parameters */ - temp_scaling_info.dst_rect = u->surface->dst_rect; - temp_scaling_info.src_rect = u->surface->src_rect; - temp_scaling_info.scaling_quality = u->surface->scaling_quality; - - /* Special validation required */ - temp_scaling_info.clip_rect = u->scaling_info->clip_rect; - - if (memcmp(u->scaling_info, &temp_scaling_info, - sizeof(struct dc_scaling_info)) != 0) + if (u->scaling_info->src_rect.width != u->surface->src_rect.width + || u->scaling_info->src_rect.height != u->surface->src_rect.height + || u->scaling_info->clip_rect.width != u->surface->clip_rect.width + || u->scaling_info->clip_rect.height != u->surface->clip_rect.height + || u->scaling_info->dst_rect.width != u->surface->dst_rect.width + || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) return UPDATE_TYPE_FULL; - /* Check Clip rectangles if not equal -* difference is in offsets == > UPDATE_TYPE_MED -* difference is in dimensions == > UPDATE_TYPE_FULL -*/ - if (memcmp(&u->scaling_info->clip_rect, - &u->surface->clip_rect, sizeof(struct rect)) != 0) { - if ((u->scaling_info->clip_rect.height == - u->surface->clip_rect.height) && - (u->scaling_info->clip_rect.width == - u->surface->clip_rect.width)) { - return UPDATE_TYPE_MED; - } else { - return UPDATE_TYPE_FULL; - } - } + if (u->scaling_info->src_rect.x != u->surface->src_rect.x + || u->scaling_info->src_rect.y != u->surface->src_rect.y + || u->scaling_info->clip_rect.x != u->surface->clip_rect.x + || u->scaling_info->clip_rect.y != u->surface->clip_rect.y + || u->scaling_info->dst_rect.x != u->surface->dst_rect.x + || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) + return UPDATE_TYPE_MED; return UPDATE_TYPE_FAST; } -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 20/31] drm/amd/display: Add 64KB_S_T and 64KB_D_T swizzle mode.
From: Yongqiang Sun Change-Id: I7e8bdb19296bb703e47d906c5213e7ad6e187cf4 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1b9edfda2b98..26587bcdba96 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -236,6 +236,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; case DC_SW_64KB_S: case DC_SW_64KB_S_X: + case DC_SW_64KB_S_T: input->src.is_display_sw = 0; input->src.macro_tile_size = dm_64k_tile; break; @@ -253,6 +254,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; case DC_SW_64KB_D: case DC_SW_64KB_D_X: + case DC_SW_64KB_D_T: input->src.is_display_sw = 1; input->src.macro_tile_size = dm_64k_tile; break; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 28/31] drm/amd/display: fix scaling calculation for proper surface input format
From: Dmytro Laktyushkin Change-Id: Icc68c0d9e6fc589492148a2bd122d34ada78555b Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 60 +++ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 20 2 files changed, 49 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9588217e0220..7ca03d1ad163 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -431,6 +431,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) const struct dc_surface *surface = &pipe_ctx->surface->public; const struct dc_stream *stream = &pipe_ctx->stream->public; struct scaler_data *data = &pipe_ctx->scl_data; + struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; @@ -444,6 +445,11 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) pri_split = false; sec_split = false; } + + if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) + rect_swap_helper(&surf_src); + /* The actual clip is an intersection between stream * source and surface clip */ @@ -463,18 +469,18 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) stream->src.y + stream->src.height - clip.y : surface->clip_rect.y + surface->clip_rect.height - clip.y ; - /* offset = src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio + /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio * num_pixels = clip.num_pix * scl_ratio */ - data->viewport.x = surface->src_rect.x + (clip.x - surface->dst_rect.x) * - surface->src_rect.width / surface->dst_rect.width; + data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) * + surf_src.width / surface->dst_rect.width; data->viewport.width = clip.width * - surface->src_rect.width / surface->dst_rect.width; + surf_src.width / surface->dst_rect.width; - data->viewport.y = surface->src_rect.y + (clip.y - surface->dst_rect.y) * - surface->src_rect.height / surface->dst_rect.height; + data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) * + surf_src.height / surface->dst_rect.height; data->viewport.height = clip.height * - surface->src_rect.height / surface->dst_rect.height; + surf_src.height / surface->dst_rect.height; /* Round down, compensate in init */ data->viewport_c.x = data->viewport.x / vpc_div; @@ -523,16 +529,21 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip { const struct dc_surface *surface = &pipe_ctx->surface->public; struct core_stream *stream = pipe_ctx->stream; - struct rect clip = surface->clip_rect; + struct rect surf_src = surface->src_rect; + struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; + if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || + pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) + rect_swap_helper(&surf_src); + pipe_ctx->scl_data.recout.x = stream->public.dst.x; - if (stream->public.src.x < clip.x) - pipe_ctx->scl_data.recout.x += (clip.x + if (stream->public.src.x < surf_clip.x) + pipe_ctx->scl_data.recout.x += (surf_clip.x - stream->public.src.x) * stream->public.dst.width / stream->public.src.width; - pipe_ctx->scl_data.recout.width = clip.width * + pipe_ctx->scl_data.recout.width = surf_clip.width * stream->public.dst.width / stream->public.src.width; if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > stream->public.dst.x + stream->public.dst.width) @@ -541,12 +552,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip - pipe_ctx->scl_data.recout.x; pipe_ctx->scl_data.recout.y = stream->public.dst.y; - if (stream->public.src.y < clip.y) - pipe_ctx->scl_data.recout.y += (clip.y + if (stream->public.src.y < surf_clip.y) + pipe_ctx->scl_data.recout.y += (surf_clip.y
[PATCH 22/31] drm/amd/display: single channel bandwidth verses dual channel bandwidth
From: Charlene Liu [Description] DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth Change-Id: I0761edfe3346a0a8162e3acbb4a193bcc313727d Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 26587bcdba96..6d8bc6c74a73 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -920,6 +920,10 @@ bool dcn_validate_bandwidth( calc_wm_sets_and_perf_params(context, v); context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 100 / (ddr4_dram_factor_single_Channel * v->number_of_channels)); + if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) { + context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 100 / 32); + } + context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin); context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin); context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); @@ -1178,8 +1182,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc) ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) && clks.num_levels != 0) { ASSERT(clks.num_levels >= 3); - dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.number_of_channels * - (clks.data[0].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; + dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0; if (clks.num_levels > 2) { dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels * (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; @@ -1240,7 +1243,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) kernel_fpu_begin(); max_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 100 / factor; nom_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 100 / factor; - min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 100 / factor; + min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 100 / 32; max_dcfclk_khz = dc->dcn_soc.dcfclkv_max0p9 * 1000; nom_dcfclk_khz = dc->dcn_soc.dcfclkv_nom0p8 * 1000; min_dcfclk_khz = dc->dcn_soc.dcfclkv_min0p65 * 1000; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 31/31] drm/amd/display: add explanation for surface_update_type
From: Dmytro Laktyushkin Change-Id: I7ce6668c865e9f8542a3bf5cc15d7474c0578eb5 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7dd145b6e927..9a19d6f5a6a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -434,9 +434,35 @@ bool dc_post_update_surfaces_to_stream( void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, int surface_count, const struct dc_stream *stream); +/* Surface update type is used by dc_update_surfaces_and_stream + * The update type is determined at the very beginning of the function based + * on parameters passed in and decides how much programming (or updating) is + * going to be done during the call. + * + * UPDATE_TYPE_FAST is used for really fast updates that do not require much + * logical calculations or hardware register programming. This update MUST be + * ISR safe on windows. Currently fast update will only be used to flip surface + * address. + * + * UPDATE_TYPE_MED is used for slower updates which require significant hw + * re-programming however do not affect bandwidth consumption or clock + * requirements. At present, this is the level at which front end updates + * that do not require us to run bw_calcs happen. These are in/out transfer func + * updates, viewport offset changes, recout size changes and pixel depth changes. + * This update can be done at ISR, but we want to minimize how often this happens. + * + * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our + * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front + * end related. Any time viewport dimensions, recout dimensions, scaling ratios or + * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do + * a full update. This cannot be done at ISR level and should be a rare event. + * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting + * underscan we don't expect to see this call at all. + */ + enum surface_update_type { UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ - UPDATE_TYPE_MED, /* a lot of programming needed. may need to alloc */ + UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ UPDATE_TYPE_FULL, /* may need to shuffle resources */ }; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/31] drm/amd/display: bw debug options now apply to dml as well
From: Dmytro Laktyushkin Change-Id: I998aadaee02116230951c3899e784708487225e5 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 41 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index eb81edf3afa9..22d98ef69a77 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -614,23 +614,49 @@ static void calc_wm_sets_and_perf_params( context->watermarks.d = context->watermarks.a; } -static void dcn_bw_apply_registry_override(struct core_dc *dc) +static bool dcn_bw_apply_registry_override(struct core_dc *dc) { + bool updated = false; + kernel_fpu_begin(); - if (dc->public.debug.sr_exit_time_ns) + if ((int)(dc->dcn_soc.sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns + && dc->public.debug.sr_exit_time_ns) { + updated = true; dc->dcn_soc.sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; - if (dc->public.debug.sr_enter_plus_exit_time_ns) + } + + if ((int)(dc->dcn_soc.sr_enter_plus_exit_time * 1000) + != dc->public.debug.sr_enter_plus_exit_time_ns + && dc->public.debug.sr_enter_plus_exit_time_ns) { + updated = true; dc->dcn_soc.sr_enter_plus_exit_time = dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; - if (dc->public.debug.urgent_latency_ns) + } + + if ((int)(dc->dcn_soc.urgent_latency * 1000) != dc->public.debug.urgent_latency_ns + && dc->public.debug.urgent_latency_ns) { + updated = true; dc->dcn_soc.urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; - if (dc->public.debug.percent_of_ideal_drambw) + } + + if ((int)(dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency * 1000) + != dc->public.debug.percent_of_ideal_drambw + && dc->public.debug.percent_of_ideal_drambw) { + updated = true; dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency = dc->public.debug.percent_of_ideal_drambw; - if (dc->public.debug.dram_clock_change_latency_ns) + } + + if ((int)(dc->dcn_soc.dram_clock_change_latency * 1000) + != dc->public.debug.dram_clock_change_latency_ns + && dc->public.debug.dram_clock_change_latency_ns) { + updated = true; dc->dcn_soc.dram_clock_change_latency = dc->public.debug.dram_clock_change_latency_ns / 1000.0; + } kernel_fpu_end(); + + return updated; } bool dcn_validate_bandwidth( @@ -642,7 +668,8 @@ bool dcn_validate_bandwidth( int i, input_idx; int vesa_sync_start, asic_blank_end, asic_blank_start; - dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public)); + if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) + dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); memset(v, 0, sizeof(*v)); kernel_fpu_begin(); -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/31] drm/amd/display: i2c/aux Remove link index.
From: Andrey Grodzovsky Link index is an unnecessery level of inderection when calling from kernel i2c/aux transfer into DAL. Change-Id: I3413e46e12a8134f6be521a39884688f6caa1b56 Signed-off-by: Andrey Grodzovsky Change-Id: If9962dc66a4e0298b02fdc61c9579c843f959cdd Signed-off-by: Andrey Grodzovsky --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 38 +++--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 22 + drivers/gpu/drm/amd/display/dc/core/dc.c | 19 --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 28 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +-- drivers/gpu/drm/amd/display/dc/dc.h| 9 ++--- drivers/gpu/drm/amd/display/dc/inc/core_types.h| 1 - 7 files changed, 58 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 0e79ba920b06..8c767ef5abf4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -33,6 +33,8 @@ #include "dc.h" #include "dm_helpers.h" +#include "dc_link_ddc.h" + /* #define TRACE_DPCD */ #ifdef TRACE_DPCD @@ -77,43 +79,41 @@ void log_dpcd(uint8_t type, static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { - struct pci_dev *pdev = to_pci_dev(aux->dev); - struct drm_device *drm_dev = pci_get_drvdata(pdev); - struct amdgpu_device *adev = drm_dev->dev_private; - struct dc *dc = adev->dm.dc; enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ? I2C_MOT_TRUE : I2C_MOT_FALSE; - bool res; + enum ddc_result res; switch (msg->request & ~DP_AUX_I2C_MOT) { case DP_AUX_NATIVE_READ: - res = dc_read_aux_dpcd( - dc, - TO_DM_AUX(aux)->link_index, + res = dal_ddc_service_read_dpcd_data( + TO_DM_AUX(aux)->ddc_service, + false, + I2C_MOT_UNDEF, msg->address, msg->buffer, msg->size); break; case DP_AUX_NATIVE_WRITE: - res = dc_write_aux_dpcd( - dc, - TO_DM_AUX(aux)->link_index, + res = dal_ddc_service_write_dpcd_data( + TO_DM_AUX(aux)->ddc_service, + false, + I2C_MOT_UNDEF, msg->address, msg->buffer, msg->size); break; case DP_AUX_I2C_READ: - res = dc_read_aux_i2c( - dc, - TO_DM_AUX(aux)->link_index, + res = dal_ddc_service_read_dpcd_data( + TO_DM_AUX(aux)->ddc_service, + true, mot, msg->address, msg->buffer, msg->size); break; case DP_AUX_I2C_WRITE: - res = dc_write_aux_i2c( - dc, - TO_DM_AUX(aux)->link_index, + res = dal_ddc_service_write_dpcd_data( + TO_DM_AUX(aux)->ddc_service, + true, mot, msg->address, msg->buffer, @@ -128,7 +128,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg msg->address, msg->buffer, msg->size, - res); + r == DDC_RESULT_SUCESSFULL); #endif return msg->size; @@ -446,7 +446,7 @@ void amdgpu_dm_initialize_dp_connector( aconnector->dm_dp_aux.aux.name = "dmdc"; aconnector->dm_dp_aux.aux.dev = dm->adev->dev; aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; - aconnector->dm_dp_aux.link_index = aconnector->connector_id; + aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_register(&aconnector->dm_dp_aux.aux); aconnector->mst_mgr.cbs = &dm_mst_cbs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 1fd5d1a17019..9ba16cc512cb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -51,6 +51,8 @@ #include "modules/inc/mod_freesy
[PATCH 16/31] drm/amd/display: Fix race.
From: Andrey Grodzovsky Problem : A race between two adjecent page flips makes the earlier one to release an alocated frame buffer for the subsequent one - since there are 2 frambuffer swapped back and forth between flips, the 'new' fb of the later flip is actually the 'previous' fb for the earlier flip. Fix: Don't set fb->address = 0 in cleanup hook, this is unnecessery and erases the newly cached adress that was set in prepare_fb of the second flip. Change-Id: I852ad2ee512e49dfc9c05e7488843d6a8915 Signed-off-by: Andrey Grodzovsky Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 6fddf31cc4e4..8aeb10786b94 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1795,9 +1795,7 @@ static void dm_plane_helper_cleanup_fb( amdgpu_bo_unpin(rbo); amdgpu_bo_unreserve(rbo); amdgpu_bo_unref(&rbo); - } - - afb->address = 0; + }; } int dm_create_validation_set_for_connector(struct drm_connector *connector, -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/31] drm/amd/display: Continue with stream enable if DP link training fails.
From: Ken Chalmers Not necessarily a fatal problem - some monitors will recover and show the stream anyway if link training fails. Change-Id: I9c6245066c3a8b80b8c40155086fe3c330752208 Signed-off-by: Ken Chalmers Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c| 21 + drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 5d374cb8128b..ffc0eeaad175 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1225,7 +1225,7 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) status = DC_OK; } else - status = DC_ERROR_UNEXPECTED; + status = DC_FAIL_DP_LINK_TRAINING; enable_stream_features(pipe_ctx); @@ -1833,9 +1833,22 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) { struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); - if (DC_OK != enable_link(pipe_ctx)) { - BREAK_TO_DEBUGGER(); - return; + enum dc_status status = enable_link(pipe_ctx); + + if (status != DC_OK) { + dm_logger_write(pipe_ctx->stream->ctx->logger, + LOG_WARNING, "enabling link %u failed: %d\n", + pipe_ctx->stream->sink->link->public.link_index, + status); + + /* Abort stream enable *unless* the failure was due to +* DP link training - some DP monitors will recover and +* show the stream anyway. +*/ + if (status != DC_FAIL_DP_LINK_TRAINING) { + BREAK_TO_DEBUGGER(); + return; + } } /* turn off otg test pattern if enable */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index 128617dabc4a..b5759c0e5a2f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -41,6 +41,7 @@ enum dc_status { DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11, DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */ DC_FAIL_SCALING = 13, + DC_FAIL_DP_LINK_TRAINING = 14, DC_ERROR_UNEXPECTED = -1 }; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 25/31] drm/amd/display: Move output transfer function to stream updates
From: Amy Zhang Change-Id: I110d0986279259a912c3b44545fbde52091b4690 Signed-off-by: Amy Zhang Reviewed-by: Anthony Koo Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 46 ++ drivers/gpu/drm/amd/display/dc/dc.h| 14 +++ .../amd/display/dc/dce110/dce110_hw_sequencer.c| 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 - 5 files changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3c2554381a25..1e6952bde25b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -201,11 +201,10 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, - const struct dc_stream **stream, int num_streams) +static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; @@ -1182,7 +1181,6 @@ static enum surface_update_type det_surface_update( overall_type = type; if (u->in_transfer_func || - u->out_transfer_func || u->hdr_static_metadata) { if (overall_type < UPDATE_TYPE_MED) overall_type = UPDATE_TYPE_MED; @@ -1279,8 +1277,28 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* update current stream with the new updates */ if (stream_update) { - stream->public.src = stream_update->src; - stream->public.dst = stream_update->dst; + if ((stream_update->src.height != 0) && + (stream_update->src.width != 0)) + stream->public.src = stream_update->src; + + if ((stream_update->dst.height != 0) && + (stream_update->dst.width != 0)) + stream->public.dst = stream_update->dst; + + if (stream_update->out_transfer_func && + stream_update->out_transfer_func != + dc_stream->out_transfer_func) { + if (stream_update->out_transfer_func->type != + TF_TYPE_UNKNOWN) { + if (dc_stream->out_transfer_func != NULL) + dc_transfer_func_release + (dc_stream->out_transfer_func); + dc_transfer_func_retain(stream_update-> + out_transfer_func); + stream->public.out_transfer_func = + stream_update->out_transfer_func; + } + } } /* save update parameters into surface */ @@ -1361,13 +1379,6 @@ void dc_update_surfaces_and_stream(struct dc *dc, srf_updates[i].in_transfer_func; } - if (srf_updates[i].out_transfer_func && - srf_updates[i].out_transfer_func != dc_stream->out_transfer_func) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release(dc_stream->out_transfer_func); - dc_transfer_func_retain(srf_updates[i].out_transfer_func); - stream->public.out_transfer_func = srf_updates[i].out_transfer_func; - } if (srf_updates[i].hdr_static_metadata) surface->public.hdr_static_ctx = *(srf_updates[i].hdr_static_metadata); @@ -1436,11 +1447,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, pipe_ctx, pipe_ctx->surface); if (is_new_pipe_surface || - srf_updates[i].out_transfer_func) + (stream_update != NULL && + stream_update->out_transfer_func != + NULL)) { core_dc->hwss.set_output_transfer_func( - pipe_ctx, - pipe_ctx->surface, - pipe_ctx->stream); + pipe_ctx, pipe_ctx->stream); + } if (srf_updates[i].hdr_static_metadata) {
[PATCH 24/31] drm/amd/display: fix freesync not working on raven
From: Corbin McElhanney Change-Id: I4e62756222da304a8ba378c2436ca8cda626273e Signed-off-by: Corbin McElhanney Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 05a086c7b31a..9a073bc55144 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1130,6 +1130,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, unsigned int stream_index, map_index; struct freesync_state *state; struct core_freesync *core_freesync = NULL; + struct dc_static_screen_events triggers = {0}; if (mod_freesync == NULL) return; @@ -1157,6 +1158,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, /* Update the stream */ update_stream(core_freesync, streams[stream_index]); + /* Calculate vmin/vmax and refresh rate for * current mode */ @@ -1164,6 +1166,14 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, core_freesync->map[map_index].caps-> min_refresh_in_micro_hz, state->nominal_refresh_rate_in_micro_hz); + + /* Update mask */ + triggers.overlay_update = true; + triggers.surface_update = true; + + core_freesync->dc->stream_funcs.set_static_screen_events( + core_freesync->dc, streams, num_streams, + &triggers); } } -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/31] drm/amd/display: Allow MPO on Raven
From: Leon Elazar Change-Id: Ib83bcc1d2cb23b409af8765b725f82d5ec5ca574 Signed-off-by: Leon Elazar Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 121eb3009445..41613ab5ca69 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1292,6 +1292,8 @@ static bool construct( dc->public.caps.i2c_speed_in_khz = 100; dc->public.caps.max_cursor_size = 256; + dc->public.caps.max_slave_planes = 1; + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->public.debug = debug_defaults_drv; else -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/31] drm/amd/display: Keep DVI_SINGLE_LINK signal if low clk
If user is using DVI->HDMI dongle dual link signal might pose a problem. Keep single link signal type if clk is lower than max tmds clk. Change-Id: I6ad1009bb195e0d1ba91a9801c6125778419f739 Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ae8b221c85aa..9588217e0220 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1283,9 +1283,12 @@ static void update_stream_signal(struct core_stream *stream) stream->signal = stream->public.output_signal; } - if (stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK && - stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ) - stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; + if (dc_is_dvi_signal(stream->signal)) { + if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ) + stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; + else + stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + } } bool resource_is_stream_unchanged( -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 23/31] drm/amd/display: enable watermark range reporting to pplib
From: Dmytro Laktyushkin Change-Id: I3ebf4168ab6669017c593d43707d812d20c4163b Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 41613ab5ca69..4e5b225a2a08 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -432,7 +432,7 @@ static const struct dc_debug debug_defaults_drv = { .force_abm_enable = false, .timing_trace = false, .disable_pplib_clock_request = true, - .disable_pplib_wm_range = true, + .disable_pplib_wm_range = false, #if defined(CONFIG_DRM_AMD_DC_DCN1_0) .use_dml_wm = false, .use_max_voltage = true -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/31] drm/amd/display: use signal type to decide whether to set backlight
From: Anthony Koo Change-Id: Ie7955fcbbd19540fee0cb656a8bae5cace7bc4aa Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 97cfd5bd3853..5d374cb8128b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1389,7 +1389,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, "New Backlight level: %d (0x%X)\n", level, level); - if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD) { + if (dc_is_embedded_signal(dc_link->connector_signal)) { if (stream != NULL) { core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/31] drm/amd/display: Reverting locks around updating freesync property
From: Sun peng Li Revert "SWDEV-114487 - dm/amdgpu: Add lock around updating freesync property" This reverts commit b54fd07f238a01f1155c9e2b378e148e5df2c548. Change-Id: Id0e10630bfc730eddcd964bdb654a9445d498032 Reviewed-by: Jordan Lazare Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 9ba16cc512cb..6fddf31cc4e4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1216,7 +1216,6 @@ static int amdgpu_freesync_update_property_atomic( dev = connector->dev; adev = dev->dev_private; - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); ret = drm_object_property_get_value( &connector->base, adev->mode_info.freesync_property, @@ -1226,8 +1225,6 @@ static int amdgpu_freesync_update_property_atomic( &connector->base, adev->mode_info.freesync_property, val_capable); - drm_modeset_unlock(&dev->mode_config.connection_mutex); - return ret; } -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/31] drm/amd/display: refactor bw related variable structure in val_ctx
From: Dmytro Laktyushkin Change-Id: I69c6358b9dd01f4cb399b017d4b23ffc67bb710a Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 18 ++--- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 79 +++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 12 ++-- .../amd/display/dc/dce100/dce100_hw_sequencer.c| 9 ++- .../drm/amd/display/dc/dce100/dce100_resource.c| 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c| 65 +- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 12 ++-- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 6 +- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 30 .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 6 +- .../drm/amd/display/dc/dce110/dce110_resource.c| 63 + .../drm/amd/display/dc/dce112/dce112_resource.c| 63 + .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 38 +-- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h| 56 +++ drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 29 +--- drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 20 -- 20 files changed, 269 insertions(+), 277 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 627b7582394a..87666987429e 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2557,7 +2557,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, */ static bool is_display_configuration_supported( const struct bw_calcs_vbios *vbios, - const struct bw_calcs_output *calcs_output) + const struct dce_bw_output *calcs_output) { uint32_t int_max_clk; @@ -2568,7 +2568,7 @@ static bool is_display_configuration_supported( int_max_clk = bw_fixed_to_int(vbios->high_sclk); int_max_clk *= 1000; /* MHz to kHz */ - if (calcs_output->required_sclk > int_max_clk) + if (calcs_output->sclk_khz > int_max_clk) return false; return true; @@ -2790,7 +2790,7 @@ bool bw_calcs(struct dc_context *ctx, const struct bw_calcs_vbios *vbios, const struct pipe_ctx pipe[], int pipe_count, - struct bw_calcs_output *calcs_output) + struct dce_bw_output *calcs_output) { struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data)); @@ -2831,20 +2831,20 @@ bool bw_calcs(struct dc_context *ctx, bw_int_to_fixed(1000))); calcs_output->blackout_recovery_time_us = bw_fixed_to_int(data->blackout_recovery_time); - calcs_output->required_sclk = + calcs_output->sclk_khz = bw_fixed_to_int(bw_mul(data->required_sclk, bw_int_to_fixed(1000))); - calcs_output->required_sclk_deep_sleep = + calcs_output->sclk_deep_sleep_khz = bw_fixed_to_int(bw_mul(data->sclk_deep_sleep, bw_int_to_fixed(1000))); if (yclk_lvl == 0) - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(low_yclk, bw_int_to_fixed(1000))); else if (yclk_lvl == 1) - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(mid_yclk, bw_int_to_fixed(1000))); else - calcs_output->required_yclk = bw_fixed_to_int( + calcs_output->yclk_khz = bw_fixed_to_int( bw_mul(high_yclk, bw_int_to_fixed(1000))); /* units: nanosecond, 16bit storage. */ @@ -3245,7 +3245,7 @@ bool bw_calcs(struct dc_context *ctx, calcs_output->cpup_state_change_enable = true; calcs_output->stutter_mode_enable = true; calcs_output->dispclk_khz = 0; - calcs_output->required_sclk = 0; + calcs_output->sclk_khz = 0; } dm_free(data); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 22d98ef69a77..1b9edfda2b98 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -470,17 +470,17 @@ static void dcn_dml_wm_override( a.cpstate = dml_wm_cst
[PATCH 08/31] drm/amd/display: Only apply ctx for specific surface.
From: Yongqiang Sun Change-Id: Ifcf2bba5d0ac0200ae406e27407afdf237d13aa2 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fb4eb4364bc7..ece8c96f3636 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1689,19 +1689,21 @@ static void dcn10_apply_ctx_for_surface( { int i; - memcpy(context->res_ctx.mpc_tree, - dc->current_context->res_ctx.mpc_tree, - sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count); - for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->surface) + if (!pipe_ctx->surface || pipe_ctx->surface != surface) continue; + /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) + if (!pipe_ctx->top_pipe) { + memcpy(context->res_ctx.mpc_tree, + dc->current_context->res_ctx.mpc_tree, + sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count); + program_all_pipe_in_tree(dc, pipe_ctx, context); + } } for (i = 0; i < dc->res_pool->pipe_count; i++) { -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/31] drm/amd/display: switch to using calc_clk and cur_clk for dcn bw setting
From: Dmytro Laktyushkin Change-Id: I9da890ac9e52292092f8579449550b8e79c8f1fb Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../amd/display/dc/dce110/dce110_hw_sequencer.c| 50 +++--- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 59 +- 2 files changed, 79 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 41aeceba5ae5..150c8a4e7b61 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1647,24 +1647,38 @@ enum dc_status dce110_apply_ctx_to_hw( apply_min_clocks(dc, context, &clocks_state, true); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.calc_clk.fclk_khz) { - struct dm_pp_clock_for_voltage_req clock; - - clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; - clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; - dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.calc_clk.fclk_khz = clock.clocks_in_khz; - } - if (context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.calc_clk.dcfclk_khz) { - struct dm_pp_clock_for_voltage_req clock; - - clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; - dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.calc_clk.dcfclk_khz = clock.clocks_in_khz; - } + if (resource_parse_asic_id(dc->ctx->asic_id) == DCN_VERSION_1_0) { + if (context->bw.dcn.calc_clk.fclk_khz + > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dcfclk_khz + > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dispclk_khz + > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dcn.calc_clk.dispclk_khz); + dc->current_context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + } + } else #endif if (context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index a62c4e72f21a..f5638ad6e9fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1429,6 +1429,9 @@ static void dcn10_power_on_fe( pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); + dc->current_context->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; if (dc_surface) { dm_logger_write(dc->ctx->logger, LOG_DC, @@ -1531,6 +1534,9 @@ static void update_dchubp_dpp( pipe_ctx->pipe_idx, pipe_ctx->pix_clk_params.requested_pix_clk, conte
[PATCH 02/31] drm/amd/display: Don't call PSR func if DMCU is off
Change-Id: I3e5b4f95429a959d0981ba57f23bd4d9fc60a604 Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c| 23 +++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 11 --- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 1 + 4 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 6f78403e2d64..95d042a15409 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -46,14 +46,6 @@ #include "dce/dce_11_0_enum.h" #include "dce/dce_11_0_sh_mask.h" -#ifndef mmDMCU_STATUS__UC_IN_RESET__SHIFT -#define mmDMCU_STATUS__UC_IN_RESET__SHIFT 0x0 -#endif - -#ifndef mmDMCU_STATUS__UC_IN_RESET_MASK -#define mmDMCU_STATUS__UC_IN_RESET_MASK 0x0001L -#endif - #define LINK_INFO(...) \ dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \ __VA_ARGS__) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 45a3079c0973..393c43559825 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -366,6 +366,16 @@ static bool dce_abm_init_backlight(struct abm *abm) return true; } +static bool is_dmcu_initialized(struct abm *abm) +{ + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + unsigned int dmcu_uc_reset; + + REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); + + return !dmcu_uc_reset; +} + static bool dce_abm_set_backlight_level( struct abm *abm, unsigned int backlight_level, @@ -373,23 +383,19 @@ static bool dce_abm_set_backlight_level( unsigned int controller_id) { struct dce_abm *abm_dce = TO_DCE_ABM(abm); - unsigned int dmcu_uc_reset; dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT, "New Backlight level: %d (0x%X)\n", backlight_level, backlight_level); - REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); - /* If DMCU is in reset state, DMCU is uninitialized */ - if (dmcu_uc_reset) { - driver_set_backlight_level(abm_dce, backlight_level); - } else { + if (is_dmcu_initialized(abm)) dmcu_set_backlight_level(abm_dce, backlight_level, frame_ramp, controller_id); - } + else + driver_set_backlight_level(abm_dce, backlight_level); return true; } @@ -398,7 +404,8 @@ static const struct abm_funcs dce_funcs = { .abm_init = dce_abm_init, .set_abm_level = dce_abm_set_level, .init_backlight = dce_abm_init_backlight, - .set_backlight_level = dce_abm_set_backlight_level + .set_backlight_level = dce_abm_set_backlight_level, + .is_dmcu_initialized = is_dmcu_initialized }; static void dce_abm_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 6e56d8308d66..8bc0d0ff3a2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,11 +29,15 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" +#include "core_dc.h" +#include "dce_abm.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dcn_calcs.h" #include "core_dc.h" #endif + + #define TO_DCE_CLOCKS(clocks)\ container_of(clocks, struct dce_disp_clk, base) @@ -374,6 +378,8 @@ static void dce112_set_clock( struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); struct bp_set_dce_clock_parameters dce_clk_params; struct dc_bios *bp = clk->ctx->dc_bios; + struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + struct abm *abm = core_dc->res_pool->abm; /* Prepare to program display clock*/ memset(&dce_clk_params, 0, sizeof(dce_clk_params)); @@ -404,9 +410,8 @@ static void dce112_set_clock( bp->funcs->set_dce_clock(bp, &dce_clk_params); -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - dce_psr_wait_loop(clk_dce, requested_clk_khz); -#endif + if (abm->funcs->is_dmcu_initialized(abm)) + dce_psr_wait_loop(clk_dce, requested_clk_khz); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index 7d07b7922391..ceabbd3bf5f8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -40,6 +40,7 @@ struct abm_funcs { unsigned int backlight_level, unsigned int frame_ramp, unsigned int controller_id); + bool (*is_dmcu_initialized)(struct abm *abm); }; #endif --
[PATCH 17/31] drm/amd/display: prevent assert on error of 1 in calc_freesync_range
From: Dmytro Laktyushkin Change-Id: I9d88231521821e01f79dc7aa942659ba240d1eac Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index c5330f3cc1de..05a086c7b31a 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -422,12 +422,14 @@ static void calc_freesync_range(struct core_freesync *core_freesync, /* In case of 4k free sync monitor, vmin or vmax cannot be less than vtotal */ if (state->freesync_range.vmin < vtotal) { - ASSERT(false); + /* Error of 1 is permissible */ + ASSERT((state->freesync_range.vmin + 1) >= vtotal); state->freesync_range.vmin = vtotal; } if (state->freesync_range.vmax < vtotal) { - ASSERT(false); + /* Error of 1 is permissible */ + ASSERT((state->freesync_range.vmax + 1) >= vtotal); state->freesync_range.vmax = vtotal; } -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 21/31] drm/amd/display: Use MED update type if clip position changes
Change-Id: I62c019ec028d66339dea98dbbae00da07873aa92 Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b30d4bc7b040..3c2554381a25 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1143,7 +1143,7 @@ static enum surface_update_type get_scaling_info_update_type( return UPDATE_TYPE_FULL; /* Check Clip rectangles if not equal -* difference is in offsets == > UPDATE_TYPE_FAST +* difference is in offsets == > UPDATE_TYPE_MED * difference is in dimensions == > UPDATE_TYPE_FULL */ if (memcmp(&u->scaling_info->clip_rect, @@ -1152,7 +1152,7 @@ static enum surface_update_type get_scaling_info_update_type( u->surface->clip_rect.height) && (u->scaling_info->clip_rect.width == u->surface->clip_rect.width)) { - return UPDATE_TYPE_FAST; + return UPDATE_TYPE_MED; } else { return UPDATE_TYPE_FULL; } @@ -1326,8 +1326,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, srf_updates[i].plane_info->dcc; } - /* not sure if we still need this */ - if (update_type == UPDATE_TYPE_FULL) { + if (update_type >= UPDATE_TYPE_MED) { for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 15/31] drm/amd/display: ifdef some code only needed for DCN
Change-Id: Ia910c1f4467c5bdbc7d1ee28ed9265c090cc184e Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 2 ++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index fcda3c7db818..919c6632ee3e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -31,8 +31,10 @@ #include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mem_input.h" #include "mpc.h" +#endif struct core_stream; @@ -256,7 +258,9 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct mpc *mpc; +#endif const struct resource_funcs *funcs; const struct resource_caps *res_cap; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 0f952e5b3ae8..1298d306db69 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -122,7 +122,9 @@ struct ipp_funcs { struct input_pixel_processor *ipp, const struct pwl_params *params); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) void (*ipp_destroy)(struct input_pixel_processor **ipp); +#endif }; #endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 64d43257db96..a101f4b5e0c7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -27,7 +27,9 @@ #define __DAL_OPP_H__ #include "hw_shared.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "dc_hw_types.h" +#endif #include "transform.h" struct fixed31_32; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/31] DC Patches May 12, 2017
* Fix deadlock when plugging MST display * Fix DVI->HDMI dongles * Bunch of raven bandwidth changes * Some more cleanup for i2c/aux Amy Zhang (1): drm/amd/display: Move output transfer function to stream updates Andrey Grodzovsky (4): drm/amd/display: i2c Remove link index. drm/amd/display: DP aux Remove link index. drm/amd/display: i2c/aux Remove link index. drm/amd/display: Fix race. Anthony Koo (2): drm/amd/display: use signal type to decide whether to set backlight drm/amd/display: Implement support for backlight optimization Charlene Liu (1): drm/amd/display: single channel bandwidth verses dual channel bandwidth Corbin McElhanney (1): drm/amd/display: fix freesync not working on raven Dmytro Laktyushkin (9): drm/amd/display: bw debug options now apply to dml as well drm/amd/display: prevent assert on error of 1 in calc_freesync_range drm/amd/display: refactor bw related variable structure in val_ctx drm/amd/display: switch to using calc_clk and cur_clk for dcn bw setting drm/amd/display: enable watermark range reporting to pplib drm/amd/display: fix scaling calculation for proper surface input format drm/amd/display: add yuv pixel formats to pixel_format_to_bpp() drm/amd/display: fix scaling info based surface update type check drm/amd/display: add explanation for surface_update_type Harry Wentland (6): drm/amd/display: Don't call PSR func if DMCU is off drm/amd/display: Keep DVI_SINGLE_LINK signal if low clk drm/amd/display: ifdef some code only needed for DCN drm/amd/display: Use MED update type if clip position changes drm/amd/display: Add mem_input header to non-DCN builds drm/amd/display: DCE12 num_timing_generators should be 6 Ken Chalmers (1): drm/amd/display: Continue with stream enable if DP link training fails. Leon Elazar (1): drm/amd/display: Allow MPO on Raven Pratik Vishwakarma (1): drm/amd/display: get_atomic_property missing for drm_connector_funcs Sun peng Li (1): drm/amd/display: Reverting locks around updating freesync property Tony Cheng (1): drm/amd/display: do not set_mpc_tree if tree is already setup Yongqiang Sun (2): drm/amd/display: Only apply ctx for specific surface. drm/amd/display: Add 64KB_S_T and 64KB_D_T swizzle mode. drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 38 +++--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 82 +--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h| 6 + drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 18 +-- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 131 +++ drivers/gpu/drm/amd/display/dc/core/dc.c | 140 - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 59 + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 69 ++ drivers/gpu/drm/amd/display/dc/dc.h| 51 +--- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 20 +-- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 36 -- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 11 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 6 +- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 12 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c| 9 +- .../drm/amd/display/dc/dce100/dce100_resource.c| 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c| 100 --- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 12 +- .../drm/amd/display/dc/dce110/dce110_mem_input.h | 6 +- .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 30 ++--- .../drm/amd/display/dc/dce110/dce110_mem_input_v.h | 6 +- .../drm/amd/display/dc/dce110/dce110_resource.c| 63 +- .../drm/amd/display/dc/dce112/dce112_resource.c| 63 +- .../drm/amd/display/dc/dce120/dce120_resource.c| 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 121 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 6 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +- drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 + drivers/gpu/drm/amd/display/dc/inc/core_types.h| 61 +++-- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 29 + drivers/gpu/drm/amd/display/dc/inc/hw/abm.h| 2 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h| 2 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 20 +-- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h| 2 + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 - .../drm/amd/display/modules/freesync/freesync.c| 16 ++- 39 files changed, 741 insertions(+), 514 deletions(-) -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/m
[PATCH 03/31] drm/amd/display: i2c Remove link index.
From: Andrey Grodzovsky Header change for DAL change under same name. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 9362a04eaa59..013e796b0a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -567,8 +567,8 @@ struct amdgpu_dm_dp_aux { struct amdgpu_i2c_adapter { struct i2c_adapter base; - struct amdgpu_display_manager *dm; - uint32_t link_index; + + struct ddc_service *ddc_service; }; #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/amdgpu: change default of amdgpu_vram_page_split to 512
From: Christian König 512 is enough for one PD entry on Vega10. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 26fce4d..130c45d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -93,7 +93,7 @@ int amdgpu_vm_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; -int amdgpu_vram_page_split = 1024; +int amdgpu_vram_page_split = 512; int amdgpu_exp_hw_support = 0; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm/amdgpu: move adjust adjust_mc_addr into the GFX9 vm_flush functions
From: Christian König That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1 + 5 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 3e97004..88420dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -760,11 +760,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) patch_offset = amdgpu_ring_init_cond_exec(ring); if (ring->funcs->emit_vm_flush && vm_flush_needed) { - u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); struct fence *fence; - trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr); - amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); + trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); + amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); r = amdgpu_fence_emit(ring, &fence); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f31f2a7..6dc75d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3759,6 +3759,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; + pd_addr = ring->adev->gart.gart_funcs->adjust_mc_addr(ring->adev, pd_addr); pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ BUG_ON(pd_addr & 0x003EULL); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index c3ee746..91cf7e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1143,6 +1143,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; + pd_addr = ring->adev->gart.gart_funcs->adjust_mc_addr(ring->adev, pd_addr); pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ BUG_ON(pd_addr & 0x003EULL); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 499ead3..22f42f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1316,6 +1316,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t data0, data1, mask; unsigned eng = ring->vm_inv_eng; + pd_addr = ring->adev->gart.gart_funcs->adjust_mc_addr(ring->adev, pd_addr); pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ BUG_ON(pd_addr & 0x003EULL); @@ -1357,6 +1358,7 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; + pd_addr = ring->adev->gart.gart_funcs->adjust_mc_addr(ring->adev, pd_addr); pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ BUG_ON(pd_addr & 0x003EULL); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index ada2d0a..07b2ac7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -926,6 +926,7 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); unsigned eng = ring->vm_inv_eng; + pd_addr = ring->adev->gart.gart_funcs->adjust_mc_addr(ring->adev, pd_addr); pd_addr = pd_addr | 0x1; /* valid bit */ /* now only use physical base address of PDE and valid */ BUG_ON(pd_addr & 0x003EULL); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] drm/amdgpu: cleanup adjust_mc_addr handling
From: Christian König Rename adjust_mc_addr to get_vm_pde, check the address bits in one place and move setting the valid bit in there as well. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 -- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 ++ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +++- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +++- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 10 ++ drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 + 10 files changed, 46 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fadeb55..bc089eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -309,8 +309,8 @@ struct amdgpu_gart_funcs { /* set pte flags based per asic */ uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, uint32_t flags); - /* adjust mc addr in fb for APU case */ - u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); + /* get the pde for a given mc addr */ + u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); uint32_t (*get_invalidate_req)(unsigned int vm_id); }; @@ -1816,6 +1816,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) +#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 88420dc..c10f3ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -682,16 +682,6 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) return false; } -static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) -{ - u64 addr = mc_addr; - - if (adev->gart.gart_funcs->adjust_mc_addr) - addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr); - - return addr; -} - bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job) { @@ -1034,19 +1024,17 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { if (count) { - uint64_t pt_addr = - amdgpu_vm_adjust_mc_addr(adev, last_pt); + uint64_t entry; + entry = amdgpu_gart_get_vm_pde(adev, last_pt); if (shadow) amdgpu_vm_do_set_ptes(¶ms, last_shadow, - pt_addr, count, - incr, - AMDGPU_PTE_VALID); + entry, count, + incr, 0); amdgpu_vm_do_set_ptes(¶ms, last_pde, - pt_addr, count, incr, - AMDGPU_PTE_VALID); + entry, count, incr, 0); } count = 1; @@ -1059,14 +1047,16 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, } if (count) { - uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); + uint64_t entry; + + entry = amdgpu_gart_get_vm_pde(adev, last_pt); if (vm->root.bo->shadow) - amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, - count, incr
Re: [PATCH 3/5] drm/syncobj: add sync_file interaction.
On Fri, May 12, 2017 at 10:34:55AM +1000, Dave Airlie wrote: > From: Dave Airlie > > This interface allows importing the fence from a sync_file into > an existing drm sync object, or exporting the fence attached to > an existing drm sync object into a new sync file object. > > This should only be used to interact with sync files where necessary. > > Signed-off-by: Dave Airlie With Daniel's comments taken into account, Reviewed-by: Sean Paul > --- > drivers/gpu/drm/drm_syncobj.c | 56 > +++ > include/uapi/drm/drm.h| 6 +++-- > 2 files changed, 60 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c > index 9a8c690..69ef20a 100644 > --- a/drivers/gpu/drm/drm_syncobj.c > +++ b/drivers/gpu/drm/drm_syncobj.c > @@ -52,6 +52,7 @@ > #include > #include > #include > +#include > > #include "drm_internal.h" > #include > @@ -290,6 +291,48 @@ static int drm_syncobj_fd_to_handle(struct drm_file > *file_private, > return 0; > } > > +int drm_syncobj_import_sync_file_fence(struct drm_file *file_private, > +int fd, int handle) > +{ > + struct dma_fence *fence = sync_file_get_fence(fd); > + if (!fence) > + return -EINVAL; > + > + return drm_syncobj_replace_fence(file_private, handle, fence); > +} > + > +int drm_syncobj_export_sync_file(struct drm_file *file_private, > + int handle, int *p_fd) > +{ > + int ret; > + struct dma_fence *fence; > + struct sync_file *sync_file; > + int fd = get_unused_fd_flags(O_CLOEXEC); > + > + if (fd < 0) > + return fd; > + > + ret = drm_syncobj_fence_get(file_private, handle, &fence); > + if (ret) > + goto err_put_fd; > + > + sync_file = sync_file_create(fence); > + if (!sync_file) { > + ret = -EINVAL; > + goto err_fence_put; > + } > + > + fd_install(fd, sync_file->file); > + > + dma_fence_put(fence); > + *p_fd = fd; > + return 0; > +err_fence_put: > + dma_fence_put(fence); > +err_put_fd: > + put_unused_fd(fd); > + return ret; > +} > /** > * drm_syncobj_open - initalizes syncobj file-private structures at devnode > open time > * @dev: drm_device which is being opened by userspace > @@ -372,6 +415,12 @@ drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, > void *data, > if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > return -ENODEV; > > + if (args->flags & DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE) > + return drm_syncobj_export_sync_file(file_private, args->handle, > + &args->fd); > + else if (args->flags) > + return -EINVAL; > + > return drm_syncobj_handle_to_fd(file_private, args->handle, > &args->fd); > } > @@ -385,6 +434,13 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, > void *data, > if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > return -ENODEV; > > + if (args->flags & DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE) > + return drm_syncobj_import_sync_file_fence(file_private, > + args->fd, > + args->handle); > + else if (args->flags) > + return -EINVAL; > + > return drm_syncobj_fd_to_handle(file_private, args->fd, > &args->handle); > } > diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h > index db9e35e..d0e05f4 100644 > --- a/include/uapi/drm/drm.h > +++ b/include/uapi/drm/drm.h > @@ -707,13 +707,15 @@ struct drm_syncobj_destroy { > __u32 pad; > }; > > +#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE (1 << 0) > +#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE (1 << 0) > struct drm_syncobj_handle { > __u32 handle; > /** Flags.. only applicable for handle->fd */ > - __u32 flags; > + __u32 fd_flags; > > __s32 fd; > - __u32 pad; > + __u32 flags; > }; > > /* timeout_ns is relative timeout in nanoseconds */ > -- > 2.9.3 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/5] drm/syncobj: add sync obj wait interface. (v2)
On Fri, May 12, 2017 at 10:34:54AM +1000, Dave Airlie wrote: > From: Dave Airlie > > This interface will allow sync object to be used to back > Vulkan fences. This API is pretty much the vulkan fence waiting > API, and I've ported the code from amdgpu. > > v2: accept relative timeout, pass remaining time back > to userspace. > > Signed-off-by: Dave Airlie Reviewed-by: Sean Paul > --- > drivers/gpu/drm/drm_internal.h | 2 + > drivers/gpu/drm/drm_ioctl.c| 2 + > drivers/gpu/drm/drm_syncobj.c | 139 > - > include/uapi/drm/drm.h | 12 > 4 files changed, 154 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h > index 44ef903..a508ad9 100644 > --- a/drivers/gpu/drm/drm_internal.h > +++ b/drivers/gpu/drm/drm_internal.h > @@ -156,3 +156,5 @@ int drm_syncobj_handle_to_fd_ioctl(struct drm_device > *dev, void *data, > struct drm_file *file_private); > int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, void *data, > struct drm_file *file_private); > +int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data, > +struct drm_file *file_private); > diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c > index 6da7adc..b142466 100644 > --- a/drivers/gpu/drm/drm_ioctl.c > +++ b/drivers/gpu/drm/drm_ioctl.c > @@ -653,6 +653,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = { > DRM_UNLOCKED|DRM_RENDER_ALLOW), > DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, > drm_syncobj_fd_to_handle_ioctl, > DRM_UNLOCKED|DRM_RENDER_ALLOW), > + DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl, > + DRM_UNLOCKED|DRM_RENDER_ALLOW), > }; > > #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) > diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c > index 835e987..9a8c690 100644 > --- a/drivers/gpu/drm/drm_syncobj.c > +++ b/drivers/gpu/drm/drm_syncobj.c > @@ -1,5 +1,7 @@ > /* > * Copyright 2017 Red Hat > + * Parts ported from amdgpu (fence wait code). > + * Copyright 2016 Advanced Micro Devices, Inc. > * > * Permission is hereby granted, free of charge, to any person obtaining a > * copy of this software and associated documentation files (the "Software"), > @@ -31,10 +33,13 @@ > * that contain an optional fence. The fence can be updated with a new > * fence, or be NULL. > * > + * syncobj's can be waited upon, where it will wait for the underlying > + * fence. > + * > * syncobj's can be export to fd's and back, these fd's are opaque and > * have no other use case, except passing the syncobj between processes. > * > - * TODO: sync_file interactions, waiting > + * TODO: sync_file interactions. > * > * Their primary use-case is to implement Vulkan fences and semaphores. > * > @@ -383,3 +388,135 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, > void *data, > return drm_syncobj_fd_to_handle(file_private, args->fd, > &args->handle); > } > + > +static int drm_syncobj_wait_all_fences(struct drm_device *dev, > +struct drm_file *file_private, > +struct drm_syncobj_wait *wait, > +uint32_t *handles) > +{ > + uint32_t i; > + int ret = 0; > + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); > + > + for (i = 0; i < wait->count_handles; i++) { > + struct dma_fence *fence; > + > + ret = drm_syncobj_fence_get(file_private, handles[i], > + &fence); > + if (ret) > + return ret; > + > + if (!fence) > + continue; > + > + ret = dma_fence_wait_timeout(fence, true, timeout); > + > + dma_fence_put(fence); > + if (ret < 0) > + return ret; > + if (ret == 0) > + break; > + timeout = ret; > + } > + > + if (ret > 0) > + wait->timeout_ns = jiffies_to_nsecs(ret); > + wait->out_status = (ret > 0); > + wait->first_signaled = 0; > + return 0; > +} > + > +static int drm_syncobj_wait_any_fence(struct drm_device *dev, > + struct drm_file *file_private, > + struct drm_syncobj_wait *wait, > + uint32_t *handles) > +{ > + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); > + struct dma_fence **array; > + uint32_t i; > + int ret; > + uint32_t first = ~0; > + > + /* Prepare the fence array */ > + array = kcalloc(wait->count_handles, > + sizeof(struct dma_fence *), GFP_KERNEL); > + > + if (array == NULL)
Re: [PATCH 1/5] drm: introduce sync objects (v2)
On Fri, May 12, 2017 at 10:34:53AM +1000, Dave Airlie wrote: > From: Dave Airlie > > Sync objects are new toplevel drm object, that contain a > pointer to a fence. This fence can be updated via command > submission ioctls via drivers. > > There is also a generic wait obj API modelled on the vulkan > wait API (with code modelled on some amdgpu code). > > These objects can be converted to an opaque fd that can be > passes between processes. > > v2: rename reference/unreference to put/get (Chris) > fix leaked reference (David Zhou) > drop mutex in favour of cmpxchg (Chris) > document drm_syncobj_fence_get > use ENOENT for syncobj lookup. > > Signed-off-by: Dave Airlie With Daniel's comments addressed, Reviewed-by: Sean Paul > > fixup > --- > Documentation/gpu/drm-internals.rst | 3 + > Documentation/gpu/drm-mm.rst| 6 + > drivers/gpu/drm/Makefile| 2 +- > drivers/gpu/drm/drm_fops.c | 8 + > drivers/gpu/drm/drm_internal.h | 13 ++ > drivers/gpu/drm/drm_ioctl.c | 12 ++ > drivers/gpu/drm/drm_syncobj.c | 385 > > include/drm/drmP.h | 5 + > include/drm/drm_drv.h | 1 + > include/drm/drm_syncobj.h | 87 > include/uapi/drm/drm.h | 25 +++ > 11 files changed, 546 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/drm_syncobj.c > create mode 100644 include/drm/drm_syncobj.h > > diff --git a/Documentation/gpu/drm-internals.rst > b/Documentation/gpu/drm-internals.rst > index e35920d..2ea3bce 100644 > --- a/Documentation/gpu/drm-internals.rst > +++ b/Documentation/gpu/drm-internals.rst > @@ -98,6 +98,9 @@ DRIVER_ATOMIC > implement appropriate obj->atomic_get_property() vfuncs for any > modeset objects with driver specific properties. > > +DRIVER_SYNCOBJ > +Driver support drm sync objects. > + > Major, Minor and Patchlevel > ~~~ > > diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst > index f5760b1..28aebe8 100644 > --- a/Documentation/gpu/drm-mm.rst > +++ b/Documentation/gpu/drm-mm.rst > @@ -483,3 +483,9 @@ DRM Cache Handling > > .. kernel-doc:: drivers/gpu/drm/drm_cache.c > :export: > + > +DRM Sync Objects > +=== > + > +.. kernel-doc:: drivers/gpu/drm/drm_syncobj.c > + :export: > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 3ee9579..b5e565c 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -16,7 +16,7 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ > drm_framebuffer.o drm_connector.o drm_blend.o \ > drm_encoder.o drm_mode_object.o drm_property.o \ > drm_plane.o drm_color_mgmt.o drm_print.o \ > - drm_dumb_buffers.o drm_mode_config.o > + drm_dumb_buffers.o drm_mode_config.o drm_syncobj.o > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o > drm-$(CONFIG_DRM_VM) += drm_vm.o > diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c > index afdf5b1..9a61df2 100644 > --- a/drivers/gpu/drm/drm_fops.c > +++ b/drivers/gpu/drm/drm_fops.c > @@ -219,6 +219,9 @@ static int drm_open_helper(struct file *filp, struct > drm_minor *minor) > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_open(dev, priv); > > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_open(priv); > + > if (drm_core_check_feature(dev, DRIVER_PRIME)) > drm_prime_init_file_private(&priv->prime); > > @@ -266,6 +269,8 @@ static int drm_open_helper(struct file *filp, struct > drm_minor *minor) > out_prime_destroy: > if (drm_core_check_feature(dev, DRIVER_PRIME)) > drm_prime_destroy_file_private(&priv->prime); > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_release(priv); > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_release(dev, priv); > put_pid(priv->pid); > @@ -400,6 +405,9 @@ int drm_release(struct inode *inode, struct file *filp) > drm_property_destroy_user_blobs(dev, file_priv); > } > > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_release(file_priv); > + > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_release(dev, file_priv); > > diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h > index f37388c..44ef903 100644 > --- a/drivers/gpu/drm/drm_internal.h > +++ b/drivers/gpu/drm/drm_internal.h > @@ -142,4 +142,17 @@ static inline int drm_debugfs_crtc_crc_add(struct > drm_crtc *crtc) > { > return 0; > } > + > #endif > + > +/* drm_syncobj.c */ > +void drm_syncobj_open(struct drm_file *file_private); > +void drm_syncobj_release(struct drm_file *file_private); > +int drm_syncobj_create_ioctl(struct drm_device *dev, void *data, > +
Re: [PATCH libdrm v2 1/1] amdgpu: move asic id table to a separate file
On Fri, May 12, 2017 at 12:19 AM, Samuel Li wrote: > From: Xiaojie Yuan > > v2: fix an off by one error and leading white spaces > > Change-Id: I12216da14910f5e2b0970bc1fafc2a20b0ef1ba9 > Reviewed-by: Junwei Zhang > Signed-off-by: Samuel Li > --- > amdgpu/Makefile.am | 2 + > amdgpu/Makefile.sources | 2 +- > amdgpu/amdgpu_asic_id.c | 198 > +++ > amdgpu/amdgpu_asic_id.h | 165 --- > amdgpu/amdgpu_device.c | 28 +-- > amdgpu/amdgpu_internal.h | 10 +++ > 6 files changed, 232 insertions(+), 173 deletions(-) > create mode 100644 amdgpu/amdgpu_asic_id.c > delete mode 100644 amdgpu/amdgpu_asic_id.h > > diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am > index cf7bc1b..ecf9e82 100644 > --- a/amdgpu/Makefile.am > +++ b/amdgpu/Makefile.am > @@ -30,6 +30,8 @@ AM_CFLAGS = \ > $(PTHREADSTUBS_CFLAGS) \ > -I$(top_srcdir)/include/drm > > +AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${datadir}/libdrm/amdgpu.ids\" If you add this here, you should add the ids file itself and make libdrm install it too... > + > libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la > libdrm_amdgpu_ladir = $(libdir) > libdrm_amdgpu_la_LDFLAGS = -version-number 1:0:0 -no-undefined > diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources > index 487b9e0..bc3abaa 100644 > --- a/amdgpu/Makefile.sources > +++ b/amdgpu/Makefile.sources > @@ -1,5 +1,5 @@ > LIBDRM_AMDGPU_FILES := \ > - amdgpu_asic_id.h \ > + amdgpu_asic_id.c \ > amdgpu_bo.c \ > amdgpu_cs.c \ > amdgpu_device.c \ > diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c > new file mode 100644 > index 000..067f38c > --- /dev/null > +++ b/amdgpu/amdgpu_asic_id.c > @@ -0,0 +1,198 @@ > +/* > + * Copyright © 2017 Advanced Micro Devices, Inc. > + * All Rights Reserved. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#ifdef HAVE_CONFIG_H > +#include "config.h" > +#endif > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "amdgpu_drm.h" > +#include "amdgpu_internal.h" > + > +static int parse_one_line(const char *line, struct amdgpu_asic_id *id) > +{ > + char *buf; > + char *s_did; > + char *s_rid; > + char *s_name; > + char *endptr; > + int r = 0; > + > + buf = strdup(line); > + if (!buf) > + return -ENOMEM; > + > + /* ignore empty line and commented line */ > + if (strlen(line) == 0 || line[0] == '#') { > + r = -EAGAIN; > + goto out; > + } > + > + /* device id */ > + s_did = strtok(buf, ","); You can't use strtok() in a library. Any other thread may call strtok() anytime too and screw you up. > + if (!s_did) { > + r = -EINVAL; > + goto out; > + } > + > + id->did = strtol(s_did, &endptr, 16); > + if (*endptr) { > + r = -EINVAL; > + goto out; > + } > + > + /* revision id */ > + s_rid = strtok(NULL, ","); > + if (!s_rid) { > + r = -EINVAL; > + goto out; > + } > + > + id->rid = strtol(s_rid, &endptr, 16); > + if (*endptr) { > + r = -EINVAL; > + goto out; > + } > + > + /* marketing name */ > + s_name = strtok(NULL, ","); > + if (!s_name) { > + r = -EINVAL; > + goto out; > + } > + > + id->marketing_name = strdup(s_name); > + if (id->marketing_name == NULL) { > + r = -EINVAL; > + goto out; > + } > + > +out: > + free(buf); > + > + return r; > +} > + > +int amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table) > +{ > + struct amdgpu_asic_id *asic_id_table; > + struct
Re: [PATCH] drm/amdgpu: correct wptr initialization for sdma
Am 12.05.2017 um 11:18 schrieb Yintian Tao: If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06 Signed-off-by: Yintian Tao Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index cfd968e..7b6d3e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); @@ -659,9 +660,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); - ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); - doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); if (ring->use_doorbell) { ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/3] GPU-DRM-Radeon: Fine-tuning for three function implementations
Hi Christian, On Wednesday 10 May 2017 13:30:37 Christian König wrote: > Am 10.05.2017 um 02:23 schrieb Michel Dänzer: > > On 03/05/17 09:46 PM, Christian König wrote: > >> Am 02.05.2017 um 22:04 schrieb SF Markus Elfring: > >>> From: Markus Elfring > >>> Date: Tue, 2 May 2017 22:00:02 +0200 > >>> > >>> Three update suggestions were taken into account > >>> from static source code analysis. > >>> > >>> Markus Elfring (3): > >>> Use seq_putc() in radeon_sa_bo_dump_debug_info() > >>> Use seq_puts() in radeon_debugfs_pm_info() > >>> Use seq_puts() in r100_debugfs_cp_csq_fifo() > >> > >> Reviewed-by: Christian König > > > > Based on > > https://lists.freedesktop.org/archives/dri-devel/2017-May/140837.html > > and followups, I'm afraid we'll have to make sure Markus' patches have > > been tested adequately before applying them. > > I can't judge the background of that decision, but at least those tree > patches for radeon looked trivial to me. > > I don't see much what could go wrong when merging them. For what it's worth, I've once applied a patch from Markus for the uvcvideo driver that seemed trivial but ended up introducing a breakage that I hadn't caught during review. I recommend rejecting Markus' patches that are not clear improvements, and carefully testing the others. > On the other hand you are right that trying to find hardware to test that > stuff could be challenging. -- Regards, Laurent Pinchart ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH umr] Add raven family to GFX sensors
Signed-off-by: Tom St Denis --- src/app/top.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/app/top.c b/src/app/top.c index a4d3aa8e699d..09ab5f40de0b 100644 --- a/src/app/top.c +++ b/src/app/top.c @@ -813,8 +813,8 @@ static void top_build_vi_program(struct umr_asic *asic) ENTRY(i++, "mmRLC_GPM_STAT", &stat_rlc_gpm_bits[0], &top_options.vi.gfxpwr, "GFX PWR"); // sensors - if (asic->config.gfx.family == 141) { - // Arctic Island Family + if (asic->config.gfx.family == 141 || asic->config.gfx.family == 142) { + // Arctic Island Family/Raven ENTRY_SENSOR(i++, "GFX_SCLK", &stat_ai_sensor_bits[0], &top_options.vi.sensors, "Sensors"); } else if (asic->config.gfx.family == 135) { // Carrizo/Stoney family -- 2.12.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/5] GFX9 KIQ
On 11/05/17 07:33 PM, Tom St Denis wrote: On 11/05/17 02:35 PM, Alex Deucher wrote: These are the laste of the gfx9 KIQ patches that haven't landed yet. Can someone with gfx9 capable hw test this (vega10 or raven)? This is needed to enable powergating on gfx9. Thanks, If nobody gets to it by morning I'll try it out first thing on my vega10 though my VBIOS might need updating... They don't apply on top of either 4.9 nor 4.11... Tom ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: correct wptr initialization for sdma
If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06 Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index cfd968e..a154faf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH xf86-video-amdgpu] Simplify tracking of PRIME scanout pixmap
From: Michel Dänzer Remember the shared pixmap passed to drmmode_set_scanout_pixmap for each CRTC, and just compare against that. Fixes leaving stale entries in ScreenRec::pixmap_dirty_list under some circumstances, which would usually result in use-after-free and a crash down the line. (Ported from radeon commit 7dc68e26755466f9056f8c72195ab8690660693d) Signed-off-by: Michel Dänzer --- src/amdgpu_kms.c | 7 ++- src/drmmode_display.c | 21 +++-- src/drmmode_display.h | 3 +++ 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c index 4df81f993..a418cf9d3 100644 --- a/src/amdgpu_kms.c +++ b/src/amdgpu_kms.c @@ -562,8 +562,7 @@ amdgpu_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; - if (drmmode_crtc->scanout[0].pixmap == dirty->slave_dst || - drmmode_crtc->scanout[1].pixmap == dirty->slave_dst) + if (drmmode_crtc->prime_scanout_pixmap == dirty->src) return xf86_crtc; } @@ -576,13 +575,11 @@ amdgpu_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) ScrnInfoPtr scrn = crtc->scrn; ScreenPtr screen = scrn->pScreen; drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - PixmapPtr scanoutpix = crtc->randr_crtc->scanout_pixmap; PixmapDirtyUpdatePtr dirty; Bool ret = FALSE; xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { - if (dirty->src == scanoutpix && dirty->slave_dst == - drmmode_crtc->scanout[scanout_id ^ drmmode_crtc->tear_free].pixmap) { + if (dirty->src == drmmode_crtc->prime_scanout_pixmap) { RegionPtr region; if (master_has_sync_shared_pixmap(scrn, dirty)) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index 9996d2f70..add8287a0 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -681,9 +681,7 @@ drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode, xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { - if (dirty->src == crtc->randr_crtc->scanout_pixmap && - dirty->slave_dst == - drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) { + if (dirty->src == drmmode_crtc->prime_scanout_pixmap) { dirty->slave_dst = drmmode_crtc->scanout[scanout_id].pixmap; break; @@ -838,7 +836,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, fb_id = drmmode->fb_id; #ifdef AMDGPU_PIXMAP_SHARING - if (crtc->randr_crtc && crtc->randr_crtc->scanout_pixmap) { + if (drmmode_crtc->prime_scanout_pixmap) { drmmode_crtc_prime_scanout_update(crtc, mode, scanout_id, &fb_id, &x, &y); } else @@ -1242,14 +1240,15 @@ static Bool drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix) PixmapDirtyUpdatePtr dirty; xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { - if (dirty->slave_dst != drmmode_crtc->scanout[scanout_id].pixmap) - continue; - - PixmapStopDirtyTracking(dirty->src, dirty->slave_dst); - drmmode_crtc_scanout_free(drmmode_crtc); - break; + if (dirty->src == drmmode_crtc->prime_scanout_pixmap) { + PixmapStopDirtyTracking(dirty->src, dirty->slave_dst); + break; + } } + drmmode_crtc_scanout_free(drmmode_crtc); + drmmode_crtc->prime_scanout_pixmap = NULL; + if (!ppix) return TRUE; @@ -1266,6 +1265,8 @@ static Bool drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix) return FALSE; } + drmmode_crtc->prime_scanout_pixmap = ppix; + #ifdef HAS_DIRTYTRACKING_ROTATION PixmapStartDirtyTracking(ppix, drmmode_crtc->scanout[scanout_id].pixmap, 0, 0, 0, 0, RR_Rotate_0); diff --git a/src/drmmode_display.h b/src/drmmode_display.h index 2d5698f61..6a57fd23b 100644 --- a/src/drmmode_display.h +++ b/src/drmmode_display.h @@ -83,6 +83,9 @@ typedef struct { unsigned scanout_id; Bool scanout_update_pending; Bool tear_free; + + PixmapPtr prime_scanout_pixmap; + int dpms_mode; /* For when a flip is pending when DPMS off requested */ int pending_dpms_mode; -- 2.11.0
[PATCH] drm/amdgpu: correct wptr initialization for sdma
If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06 Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index cfd968e..7b6d3e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); @@ -659,9 +660,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); - ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); - doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); if (ring->use_doorbell) { -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm: fourcc byteorder: brings header file comments in line with reality.
On Thu, May 11, 2017 at 11:23:11PM +0200, Pavel Machek wrote: > On Fri 2017-04-21 14:08:04, Ville Syrjälä wrote: > > On Fri, Apr 21, 2017 at 11:50:18AM +0200, Gerd Hoffmann wrote: > > > On Fr, 2017-04-21 at 12:25 +0300, Ville Syrjälä wrote: > > > > On Fri, Apr 21, 2017 at 09:58:24AM +0200, Gerd Hoffmann wrote: > > > > > While working on graphics support for virtual machines on ppc64 (which > > > > > exists in both little and big endian variants) I've figured the > > > > > comments > > > > > for various drm fourcc formats in the header file don't match reality. > > > > > > > > > > Comments says the RGB formats are little endian, but in practice they > > > > > are native endian. Look at the drm_mode_legacy_fb_format() helper. > > > > > It > > > > > maps -- for example -- bpp/depth 32/24 to DRM_FORMAT_XRGB, no > > > > > matter > > > > > whenever the machine is little endian or big endian. The users of > > > > > this > > > > > function (fbdev emulation, DRM_IOCTL_MODE_ADDFB) expect the > > > > > framebuffer > > > > > is native endian, not little endian. Most userspace also operates on > > > > > native endian only. > > > > > > > > I'm not a fan of "native". Native to what? "CPU" or "host" is what I'd > > > > call it. > > > > > > native == whatever the cpu is using. > > > > > > I personally find "native" more intuitive, but at the end of the day I > > > don't mind much. If people prefer "host" over "native" I'll change it. > > > > "native" to me feels more like "native to the GPU" since these things > > really are tied to the GPU not the CPU. That's also why I went with the > > explicit endianness originally so that the driver could properly declare > > what the GPU supports. > > You can easily have more than one GPU in the system. Plus these are > used by cameras / frame grabbers, too. So anything else than CPU > endianness is badly defined. The framebuffer has very little to do with the CPU. The display controller is the only consumer, and the producer could be whatever. -- Ville Syrjälä Intel OTC ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/5] drm/syncobj: add sync obj wait interface. (v2)
Am 12.05.2017 um 10:49 schrieb Chris Wilson: On Fri, May 12, 2017 at 10:34:54AM +1000, Dave Airlie wrote: +static int drm_syncobj_wait_all_fences(struct drm_device *dev, + struct drm_file *file_private, + struct drm_syncobj_wait *wait, + uint32_t *handles) +{ + uint32_t i; + int ret = 0; + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); + + for (i = 0; i < wait->count_handles; i++) { + struct dma_fence *fence; + + ret = drm_syncobj_fence_get(file_private, handles[i], + &fence); + if (ret) + return ret; + + if (!fence) + continue; + + ret = dma_fence_wait_timeout(fence, true, timeout); Doesn't handle -EINTR yet with timeout. If having a drmIoctl() that can't be tricked into turning a short waiting into an indefinite one is a goal. Yeah, Daniel summarized that once nicely by noting that timeouts should be absolute not relative. Christian. -Chris ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/5] drm/syncobj: add sync obj wait interface. (v2)
On Fri, May 12, 2017 at 10:34:54AM +1000, Dave Airlie wrote: > +static int drm_syncobj_wait_all_fences(struct drm_device *dev, > +struct drm_file *file_private, > +struct drm_syncobj_wait *wait, > +uint32_t *handles) > +{ > + uint32_t i; > + int ret = 0; > + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); > + > + for (i = 0; i < wait->count_handles; i++) { > + struct dma_fence *fence; > + > + ret = drm_syncobj_fence_get(file_private, handles[i], > + &fence); > + if (ret) > + return ret; > + > + if (!fence) > + continue; > + > + ret = dma_fence_wait_timeout(fence, true, timeout); Doesn't handle -EINTR yet with timeout. If having a drmIoctl() that can't be tricked into turning a short waiting into an indefinite one is a goal. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Support for amdgpu VM update via CPU on large-bar systems
On 2017年05月12日 16:43, Christian König wrote: Am 12.05.2017 um 10:37 schrieb zhoucm1: On 2017年05月12日 16:33, Christian König wrote: Am 12.05.2017 um 10:25 schrieb zhoucm1: On 2017年05月10日 05:47, Kasiviswanathan, Harish wrote: Hi, Please review the patch set that supports amdgpu VM update via CPU. This feature provides improved performance for compute (HSA) where mapping / unmapping is carried out (by Kernel) independent of command submissions (done directly by user space). This version doesn't support shadow copy of VM page tables for CPU based update. I think your improved performance is from less waiting for cs, generally, SDMA engine updating page table is faster than CPU, otherwise we don't need sdma for updating PT. So whether your this improvement proves we have some redundant sync when mapping / unmapping, if yes, we should fix that, then not sure if CPU method is need or not. The problem is that the KFD is designed synchronously for page table updates. In other words they need to wait for the update to finish and that takes time. Apart from that your comment is absolutely correct, we found that the SDMA is sometimes much faster to do the update than the CPU. If the sdma is faster, even they wait for finish, which time is shorter than CPU, isn't it? Of course, the precondition is sdma is exclusive. They can reserve a sdma for PT updating. No, if I understood Felix numbers correctly the setup and wait time for SDMA is a bit (but not much) longer than doing it with the CPU. What would really help is to fix the KFD design and work with async page tables updates there as well. OK, no problem, just curious. Regards, David Zhou Regards, Christian. Regards, David Zhou Regards, Christian. Regards, David Zhou Best Regards, Harish ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Support for amdgpu VM update via CPU on large-bar systems
Am 12.05.2017 um 10:37 schrieb zhoucm1: On 2017年05月12日 16:33, Christian König wrote: Am 12.05.2017 um 10:25 schrieb zhoucm1: On 2017年05月10日 05:47, Kasiviswanathan, Harish wrote: Hi, Please review the patch set that supports amdgpu VM update via CPU. This feature provides improved performance for compute (HSA) where mapping / unmapping is carried out (by Kernel) independent of command submissions (done directly by user space). This version doesn't support shadow copy of VM page tables for CPU based update. I think your improved performance is from less waiting for cs, generally, SDMA engine updating page table is faster than CPU, otherwise we don't need sdma for updating PT. So whether your this improvement proves we have some redundant sync when mapping / unmapping, if yes, we should fix that, then not sure if CPU method is need or not. The problem is that the KFD is designed synchronously for page table updates. In other words they need to wait for the update to finish and that takes time. Apart from that your comment is absolutely correct, we found that the SDMA is sometimes much faster to do the update than the CPU. If the sdma is faster, even they wait for finish, which time is shorter than CPU, isn't it? Of course, the precondition is sdma is exclusive. They can reserve a sdma for PT updating. No, if I understood Felix numbers correctly the setup and wait time for SDMA is a bit (but not much) longer than doing it with the CPU. What would really help is to fix the KFD design and work with async page tables updates there as well. Regards, Christian. Regards, David Zhou Regards, Christian. Regards, David Zhou Best Regards, Harish ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Support for amdgpu VM update via CPU on large-bar systems
On 2017年05月12日 16:33, Christian König wrote: Am 12.05.2017 um 10:25 schrieb zhoucm1: On 2017年05月10日 05:47, Kasiviswanathan, Harish wrote: Hi, Please review the patch set that supports amdgpu VM update via CPU. This feature provides improved performance for compute (HSA) where mapping / unmapping is carried out (by Kernel) independent of command submissions (done directly by user space). This version doesn't support shadow copy of VM page tables for CPU based update. I think your improved performance is from less waiting for cs, generally, SDMA engine updating page table is faster than CPU, otherwise we don't need sdma for updating PT. So whether your this improvement proves we have some redundant sync when mapping / unmapping, if yes, we should fix that, then not sure if CPU method is need or not. The problem is that the KFD is designed synchronously for page table updates. In other words they need to wait for the update to finish and that takes time. Apart from that your comment is absolutely correct, we found that the SDMA is sometimes much faster to do the update than the CPU. If the sdma is faster, even they wait for finish, which time is shorter than CPU, isn't it? Of course, the precondition is sdma is exclusive. They can reserve a sdma for PT updating. Regards, David Zhou Regards, Christian. Regards, David Zhou Best Regards, Harish ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 5/5] amdgpu: use drm sync objects for shared semaphores (v4)
Am 12.05.2017 um 02:34 schrieb Dave Airlie: From: Dave Airlie This creates a new command submission chunk for amdgpu to add in and out sync objects around the submission. Sync objects are managed via the drm syncobj ioctls. The command submission interface is enhanced with two new chunks, one for syncobj pre submission dependencies, and one for post submission sync obj signalling, and just takes a list of handles for each. This is based on work originally done by David Zhou at AMD, with input from Christian Konig on what things should look like. In theory VkFences could be backed with sync objects and just get passed into the cs as syncobj handles as well. NOTE: this interface addition needs a version bump to expose it to userspace. v1.1: keep file reference on import. v2: move to using syncobjs v2.1: change some APIs to just use p pointer. v3: make more robust against CS failures, we now add the wait sems but only remove them once the CS job has been submitted. v4: rewrite names of API and base on new syncobj code. Signed-off-by: Dave Airlie --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 81 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- include/uapi/drm/amdgpu_drm.h | 6 +++ 3 files changed, 87 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index df25b32..e86c832 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "amdgpu.h" #include "amdgpu_trace.h" @@ -217,6 +218,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) break; case AMDGPU_CHUNK_ID_DEPENDENCIES: + case AMDGPU_CHUNK_ID_SYNCOBJ_IN: + case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: break; default: @@ -1008,6 +1011,40 @@ static int amdgpu_process_fence_dep(struct amdgpu_cs_parser *p, return 0; } +static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, +uint32_t handle) +{ + int r; + struct dma_fence *fence; + r = drm_syncobj_fence_get(p->filp, handle, &fence); + if (r) + return r; + + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence); + dma_fence_put(fence); + + return r; +} + +static int amdgpu_process_syncobj_in_dep(struct amdgpu_cs_parser *p, +struct amdgpu_cs_chunk *chunk) +{ + unsigned num_deps; + int i, r; + struct drm_amdgpu_cs_chunk_sem *deps; + + deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; + num_deps = chunk->length_dw * 4 / + sizeof(struct drm_amdgpu_cs_chunk_sem); + + for (i = 0; i < num_deps; ++i) { + r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle); + if (r) + return r; + } + return 0; +} + static int amdgpu_cs_dependencies(struct amdgpu_device *adev, struct amdgpu_cs_parser *p) { @@ -1022,12 +1059,54 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, r = amdgpu_process_fence_dep(p, chunk); if (r) return r; + } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) { + r = amdgpu_process_syncobj_in_dep(p, chunk); + if (r) + return r; } } return 0; } +static int amdgpu_process_syncobj_out_dep(struct amdgpu_cs_parser *p, + struct amdgpu_cs_chunk *chunk) +{ + unsigned num_deps; + int i, r; + struct drm_amdgpu_cs_chunk_sem *deps; + + deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; + num_deps = chunk->length_dw * 4 / + sizeof(struct drm_amdgpu_cs_chunk_sem); + + for (i = 0; i < num_deps; ++i) { + r = drm_syncobj_replace_fence(p->filp, deps[i].handle, + p->fence); + if (r) + return r; + } + return 0; +} + +static int amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) +{ + int i, r; + + for (i = 0; i < p->nchunks; ++i) { + struct amdgpu_cs_chunk *chunk; + + chunk = &p->chunks[i]; + + if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) { + r = amdgpu_process_syncobj_out_dep(p, chunk); + if (r) + return r; + } + } + return 0; +} + static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) { @@ -1055,7 +1134,7 @
Re: Support for amdgpu VM update via CPU on large-bar systems
Am 12.05.2017 um 10:25 schrieb zhoucm1: On 2017年05月10日 05:47, Kasiviswanathan, Harish wrote: Hi, Please review the patch set that supports amdgpu VM update via CPU. This feature provides improved performance for compute (HSA) where mapping / unmapping is carried out (by Kernel) independent of command submissions (done directly by user space). This version doesn't support shadow copy of VM page tables for CPU based update. I think your improved performance is from less waiting for cs, generally, SDMA engine updating page table is faster than CPU, otherwise we don't need sdma for updating PT. So whether your this improvement proves we have some redundant sync when mapping / unmapping, if yes, we should fix that, then not sure if CPU method is need or not. The problem is that the KFD is designed synchronously for page table updates. In other words they need to wait for the update to finish and that takes time. Apart from that your comment is absolutely correct, we found that the SDMA is sometimes much faster to do the update than the CPU. Regards, Christian. Regards, David Zhou Best Regards, Harish ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: correct wptr initialization for sdma
Am 12.05.2017 um 10:21 schrieb Yintian Tao: If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06 Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index cfd968e..a154faf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; A bit below this code on line 662 ring->wptr is set to zero as well and mmSDMA0_GFX_RB_WPTR written once more. Please also fix this as well. Regards, Christian. WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/4] drm/amdgpu: Support page directory update via CPU
Am 12.05.2017 um 04:39 schrieb Harish Kasiviswanathan: If amdgpu.vm_update_context param is set to use CPU, then Page Directories will be updated by CPU instead of SDMA Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 141 +++-- 1 file changed, 99 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ff6cf33..63f0572 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -271,6 +271,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, uint64_t saddr, uint64_t eaddr, unsigned level) { + u64 flags; unsigned shift = (adev->vm_manager.num_level - level) * adev->vm_manager.block_size; unsigned pt_idx, from, to; @@ -299,6 +300,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, saddr = saddr & ((1 << shift) - 1); eaddr = eaddr & ((1 << shift) - 1); + flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + if (vm->is_vm_update_mode_cpu) + flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + else + flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_SHADOW); + /* walk over the address space and allocate the page tables */ for (pt_idx = from; pt_idx <= to; ++pt_idx) { struct reservation_object *resv = vm->root.bo->tbo.resv; @@ -310,10 +319,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, amdgpu_vm_bo_size(adev, level), AMDGPU_GPU_PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, -AMDGPU_GEM_CREATE_NO_CPU_ACCESS | -AMDGPU_GEM_CREATE_SHADOW | -AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | -AMDGPU_GEM_CREATE_VRAM_CLEARED, +flags, NULL, resv, &pt); if (r) return r; @@ -953,6 +959,34 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) return result; } +/** + * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU + * + * @params: see amdgpu_pte_update_params definition + * @pe: kmap addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: hw access flags + */ +static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint64_t flags) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + amdgpu_gart_set_pte_pde(params->adev, (void *)pe, + i, addr, flags); + addr += incr; + } + + mb(); + amdgpu_gart_flush_gpu_tlb(params->adev, 0); +} + + /* * amdgpu_vm_update_level - update a single level in the hierarchy * @@ -982,34 +1016,49 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, if (!parent->entries) return 0; - ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - /* padding, etc. */ - ndw = 64; + memset(¶ms, 0, sizeof(params)); + params.adev = adev; + shadow = parent->bo->shadow; - /* assume the worst case */ - ndw += parent->last_entry_used * 6; + WARN_ON(vm->is_vm_update_mode_cpu && shadow); + if (vm->is_vm_update_mode_cpu && !shadow) { + r = amdgpu_bo_kmap(parent->bo, (void **)&pd_addr); + if (r) + return r; Over night I thought more about this and to also enable the CPU update mode for GFX we indeed need the sync code here and in patch #4 as well. Sorry for the confusion, I didn't thought about that use case initially. I suggest to just add a helper for this to use here and in patch #4. With that fixed the patch is Reviewed-by: Christian König Regards, Christian. + params.func = amdgpu_vm_cpu_set_ptes; + } else { + if (shadow) { + r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + if (r) + return r; + } + ring = container_of(vm->entity.sched, struct amdgpu_ring, + sched); - pd_addr = amdgpu_b
Re: Support for amdgpu VM update via CPU on large-bar systems
On 2017年05月10日 05:47, Kasiviswanathan, Harish wrote: Hi, Please review the patch set that supports amdgpu VM update via CPU. This feature provides improved performance for compute (HSA) where mapping / unmapping is carried out (by Kernel) independent of command submissions (done directly by user space). This version doesn't support shadow copy of VM page tables for CPU based update. I think your improved performance is from less waiting for cs, generally, SDMA engine updating page table is faster than CPU, otherwise we don't need sdma for updating PT. So whether your this improvement proves we have some redundant sync when mapping / unmapping, if yes, we should fix that, then not sure if CPU method is need or not. Regards, David Zhou Best Regards, Harish ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 4/4] drm/amdgpu: Support page table update via CPU
Am 12.05.2017 um 04:39 schrieb Harish Kasiviswanathan: Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 82 +- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 63f0572..63b4696 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -79,6 +79,12 @@ struct amdgpu_pte_update_params { uint64_t flags); /* indicate update pt or its shadow */ bool shadow; + /* The next two are used during VM update by CPU +* DMA addresses to use for mapping +* Kernel pointer of PD/PT BO that needs to be updated +*/ + dma_addr_t *pages_addr; + void *kptr; }; /* Helper to disable partial resident texture feature from a fence callback */ @@ -975,10 +981,14 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, uint64_t flags) { unsigned int i; + uint64_t value; for (i = 0; i < count; i++) { + value = params->pages_addr ? + amdgpu_vm_map_gart(params->pages_addr, addr) : + addr; amdgpu_gart_set_pte_pde(params->adev, (void *)pe, - i, addr, flags); + i, value, flags); addr += incr; } @@ -1211,6 +1221,59 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, } /** + * amdgpu_vm_update_ptes_cpu - Update the page tables in the range + * start - @end using CPU. + * See amdgpu_vm_update_ptes for parameter description. + * + */ +static int amdgpu_vm_update_ptes_cpu(struct amdgpu_pte_update_params *params, +uint64_t start, uint64_t end, +uint64_t dst, uint64_t flags) +{ + struct amdgpu_device *adev = params->adev; + const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; + void *pe_ptr; + uint64_t addr; + struct amdgpu_bo *pt; + unsigned int nptes; + int r; + + /* initialize the variables */ + addr = start; + + /* walk over the address space and update the page tables */ + while (addr < end) { + pt = amdgpu_vm_get_pt(params, addr); + if (!pt) { + pr_err("PT not found, aborting update_ptes\n"); + return -EINVAL; + } + + WARN_ON(params->shadow); + + r = amdgpu_bo_kmap(pt, &pe_ptr); + if (r) + return r; As I wrote on the other patch as well we need some form of syncing here. Sorry for the confusion, I didn't thought about the GFX use case for this previously. Regards, Christian. + + pe_ptr += (addr & mask) * 8; + + if ((addr & ~mask) == (end & ~mask)) + nptes = end - addr; + else + nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); + + params->func(params, (uint64_t)pe_ptr, dst, nptes, +AMDGPU_GPU_PAGE_SIZE, flags); + + amdgpu_bo_kunmap(pt); + addr += nptes; + dst += nptes * AMDGPU_GPU_PAGE_SIZE; + } + + return 0; +} + +/** * amdgpu_vm_update_ptes - make sure that page tables are valid * * @params: see amdgpu_pte_update_params definition @@ -1236,6 +1299,10 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, unsigned nptes; /* next number of ptes to be updated */ uint64_t next_pe_start; + if (params->func == amdgpu_vm_cpu_set_ptes) + return amdgpu_vm_update_ptes_cpu(params, start, end, +dst, flags); + /* initialize the variables */ addr = start; pt = amdgpu_vm_get_pt(params, addr); @@ -1422,6 +1489,19 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, params.vm = vm; params.src = src; + if (vm->is_vm_update_mode_cpu) { + /* params.src is used as flag to indicate system Memory */ + if (pages_addr) + params.src = ~0; + + params.func = amdgpu_vm_cpu_set_ptes; + params.pages_addr = pages_addr; + params.shadow = false; + r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); + if (!r) + return r; + } + ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); /* sync to everything on unmapping */ ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/am
Re: [PATCH 2/4] drm/amdgpu: Add vm context module param
Am 12.05.2017 um 04:39 schrieb Harish Kasiviswanathan: Add VM context module param (amdgpu.vm_update_context) that can used to control how the VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU By default, only for large BAR system vm_update_context = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU. And for all all other systems (by default) vm_update_context = 0 Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 - drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 16 +++- 5 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fadeb55..d927153 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -94,6 +94,7 @@ extern int amdgpu_vm_block_size; extern int amdgpu_vm_fault_stop; extern int amdgpu_vm_debug; +extern int amdgpu_vm_update_context; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 26fce4d..f07bcae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -93,6 +93,7 @@ int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; +int amdgpu_vm_update_context = -1; int amdgpu_vram_page_split = 1024; int amdgpu_exp_hw_support = 0; int amdgpu_dc = -1; @@ -180,6 +181,9 @@ MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); +MODULE_PARM_DESC(vm_update_context, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); +module_param_named(vm_update_context, amdgpu_vm_update_context, int, 0444); + MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index d167949..c524053 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -774,7 +774,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto out_suspend; } - r = amdgpu_vm_init(adev, &fpriv->vm); + r = amdgpu_vm_init(adev, &fpriv->vm, + !!(amdgpu_vm_update_context & + AMDGPU_VM_USE_CPU_FOR_GFX)); if (r) { kfree(fpriv); goto out_suspend; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5d92e73..ff6cf33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -721,6 +721,11 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, return true; } +static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) +{ + return (adev->mc.real_vram_size == adev->mc.visible_vram_size); +} + /** * amdgpu_vm_flush - hardware flush the vm * @@ -2292,10 +2297,12 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) * * @adev: amdgpu_device pointer * @vm: requested vm + * @vm_update_mode: FALSE use SDMA, TRUE use CPU to update page tables * * Init @vm fields. */ -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, + bool vm_update_mode) { const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT(adev) * 8); @@ -2324,6 +2331,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) return r; + vm->is_vm_update_mode_cpu = vm_update_mode; + DRM_DEBUG_DRIVER("VM update mode is %s\n", +vm->is_vm_update_mode_cpu ? "CPU" : "SDMA"); + vm->last_dir_update = NULL; r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, @@ -2455,6 +2466,22 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) atomic64_set(&adev->vm_manager.client_counter, 0); spin_lock_init(&adev->vm_manager.prt_lock); atomic_set(&adev->vm_manager.num_prt_users, 0); + + /* If not overridden by the user, by default, only in large BAR systems +* Compute VM tables will be updated b
Re: [PATCH 2/5] drm/syncobj: add sync obj wait interface. (v2)
On Fri, May 12, 2017 at 10:34:54AM +1000, Dave Airlie wrote: > From: Dave Airlie > > This interface will allow sync object to be used to back > Vulkan fences. This API is pretty much the vulkan fence waiting > API, and I've ported the code from amdgpu. > > v2: accept relative timeout, pass remaining time back > to userspace. > > Signed-off-by: Dave Airlie Acked-by: Daniel Vetter > --- > drivers/gpu/drm/drm_internal.h | 2 + > drivers/gpu/drm/drm_ioctl.c| 2 + > drivers/gpu/drm/drm_syncobj.c | 139 > - > include/uapi/drm/drm.h | 12 > 4 files changed, 154 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h > index 44ef903..a508ad9 100644 > --- a/drivers/gpu/drm/drm_internal.h > +++ b/drivers/gpu/drm/drm_internal.h > @@ -156,3 +156,5 @@ int drm_syncobj_handle_to_fd_ioctl(struct drm_device > *dev, void *data, > struct drm_file *file_private); > int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, void *data, > struct drm_file *file_private); > +int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data, > +struct drm_file *file_private); > diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c > index 6da7adc..b142466 100644 > --- a/drivers/gpu/drm/drm_ioctl.c > +++ b/drivers/gpu/drm/drm_ioctl.c > @@ -653,6 +653,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = { > DRM_UNLOCKED|DRM_RENDER_ALLOW), > DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, > drm_syncobj_fd_to_handle_ioctl, > DRM_UNLOCKED|DRM_RENDER_ALLOW), > + DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl, > + DRM_UNLOCKED|DRM_RENDER_ALLOW), > }; > > #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) > diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c > index 835e987..9a8c690 100644 > --- a/drivers/gpu/drm/drm_syncobj.c > +++ b/drivers/gpu/drm/drm_syncobj.c > @@ -1,5 +1,7 @@ > /* > * Copyright 2017 Red Hat > + * Parts ported from amdgpu (fence wait code). > + * Copyright 2016 Advanced Micro Devices, Inc. > * > * Permission is hereby granted, free of charge, to any person obtaining a > * copy of this software and associated documentation files (the "Software"), > @@ -31,10 +33,13 @@ > * that contain an optional fence. The fence can be updated with a new > * fence, or be NULL. > * > + * syncobj's can be waited upon, where it will wait for the underlying > + * fence. > + * > * syncobj's can be export to fd's and back, these fd's are opaque and > * have no other use case, except passing the syncobj between processes. > * > - * TODO: sync_file interactions, waiting > + * TODO: sync_file interactions. > * > * Their primary use-case is to implement Vulkan fences and semaphores. > * > @@ -383,3 +388,135 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, > void *data, > return drm_syncobj_fd_to_handle(file_private, args->fd, > &args->handle); > } > + > +static int drm_syncobj_wait_all_fences(struct drm_device *dev, > +struct drm_file *file_private, > +struct drm_syncobj_wait *wait, > +uint32_t *handles) > +{ > + uint32_t i; > + int ret = 0; > + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); > + > + for (i = 0; i < wait->count_handles; i++) { > + struct dma_fence *fence; > + > + ret = drm_syncobj_fence_get(file_private, handles[i], > + &fence); > + if (ret) > + return ret; > + > + if (!fence) > + continue; > + > + ret = dma_fence_wait_timeout(fence, true, timeout); > + > + dma_fence_put(fence); > + if (ret < 0) > + return ret; > + if (ret == 0) > + break; > + timeout = ret; > + } > + > + if (ret > 0) > + wait->timeout_ns = jiffies_to_nsecs(ret); > + wait->out_status = (ret > 0); > + wait->first_signaled = 0; > + return 0; > +} > + > +static int drm_syncobj_wait_any_fence(struct drm_device *dev, > + struct drm_file *file_private, > + struct drm_syncobj_wait *wait, > + uint32_t *handles) > +{ > + unsigned long timeout = nsecs_to_jiffies(wait->timeout_ns); > + struct dma_fence **array; > + uint32_t i; > + int ret; > + uint32_t first = ~0; > + > + /* Prepare the fence array */ > + array = kcalloc(wait->count_handles, > + sizeof(struct dma_fence *), GFP_KERNEL); > + > + if (array == NULL)
Re: [PATCH 1/5] drm: introduce sync objects (v2)
On Fri, May 12, 2017 at 10:34:53AM +1000, Dave Airlie wrote: > From: Dave Airlie > > Sync objects are new toplevel drm object, that contain a > pointer to a fence. This fence can be updated via command > submission ioctls via drivers. > > There is also a generic wait obj API modelled on the vulkan > wait API (with code modelled on some amdgpu code). > > These objects can be converted to an opaque fd that can be > passes between processes. > > v2: rename reference/unreference to put/get (Chris) > fix leaked reference (David Zhou) > drop mutex in favour of cmpxchg (Chris) > document drm_syncobj_fence_get > use ENOENT for syncobj lookup. > > Signed-off-by: Dave Airlie > > fixup Found a few ioctl and other nits, with those addressed Acked-by: Daniel Vetter > --- > Documentation/gpu/drm-internals.rst | 3 + > Documentation/gpu/drm-mm.rst| 6 + > drivers/gpu/drm/Makefile| 2 +- > drivers/gpu/drm/drm_fops.c | 8 + > drivers/gpu/drm/drm_internal.h | 13 ++ > drivers/gpu/drm/drm_ioctl.c | 12 ++ > drivers/gpu/drm/drm_syncobj.c | 385 > > include/drm/drmP.h | 5 + > include/drm/drm_drv.h | 1 + > include/drm/drm_syncobj.h | 87 > include/uapi/drm/drm.h | 25 +++ > 11 files changed, 546 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/drm_syncobj.c > create mode 100644 include/drm/drm_syncobj.h > > diff --git a/Documentation/gpu/drm-internals.rst > b/Documentation/gpu/drm-internals.rst > index e35920d..2ea3bce 100644 > --- a/Documentation/gpu/drm-internals.rst > +++ b/Documentation/gpu/drm-internals.rst > @@ -98,6 +98,9 @@ DRIVER_ATOMIC > implement appropriate obj->atomic_get_property() vfuncs for any > modeset objects with driver specific properties. > > +DRIVER_SYNCOBJ > +Driver support drm sync objects. > + > Major, Minor and Patchlevel > ~~~ > > diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst > index f5760b1..28aebe8 100644 > --- a/Documentation/gpu/drm-mm.rst > +++ b/Documentation/gpu/drm-mm.rst > @@ -483,3 +483,9 @@ DRM Cache Handling > > .. kernel-doc:: drivers/gpu/drm/drm_cache.c > :export: > + > +DRM Sync Objects > +=== > + > +.. kernel-doc:: drivers/gpu/drm/drm_syncobj.c > + :export: You're missing parts of your pretty kernel-doc! .. kernel-doc:: drivers/gpu/drm/drm_syncobj.c :doc: Overview .. kernel-doc:: include/drm/drm_syncobj.h :export: .. kernel-doc:: drivers/gpu/drm/drm_syncobj.c :export: > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 3ee9579..b5e565c 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -16,7 +16,7 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ > drm_framebuffer.o drm_connector.o drm_blend.o \ > drm_encoder.o drm_mode_object.o drm_property.o \ > drm_plane.o drm_color_mgmt.o drm_print.o \ > - drm_dumb_buffers.o drm_mode_config.o > + drm_dumb_buffers.o drm_mode_config.o drm_syncobj.o > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o > drm-$(CONFIG_DRM_VM) += drm_vm.o > diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c > index afdf5b1..9a61df2 100644 > --- a/drivers/gpu/drm/drm_fops.c > +++ b/drivers/gpu/drm/drm_fops.c > @@ -219,6 +219,9 @@ static int drm_open_helper(struct file *filp, struct > drm_minor *minor) > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_open(dev, priv); > > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_open(priv); > + > if (drm_core_check_feature(dev, DRIVER_PRIME)) > drm_prime_init_file_private(&priv->prime); > > @@ -266,6 +269,8 @@ static int drm_open_helper(struct file *filp, struct > drm_minor *minor) > out_prime_destroy: > if (drm_core_check_feature(dev, DRIVER_PRIME)) > drm_prime_destroy_file_private(&priv->prime); > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_release(priv); > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_release(dev, priv); > put_pid(priv->pid); > @@ -400,6 +405,9 @@ int drm_release(struct inode *inode, struct file *filp) > drm_property_destroy_user_blobs(dev, file_priv); > } > > + if (drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > + drm_syncobj_release(file_priv); > + > if (drm_core_check_feature(dev, DRIVER_GEM)) > drm_gem_release(dev, file_priv); > > diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h > index f37388c..44ef903 100644 > --- a/drivers/gpu/drm/drm_internal.h > +++ b/drivers/gpu/drm/drm_internal.h > @@ -142,4 +142,17 @@ static inline int drm_debugfs_crtc_crc_add(struct > drm_crtc *crtc) > { >
Re: [PATCH 3/5] drm/syncobj: add sync_file interaction.
On Fri, May 12, 2017 at 10:34:55AM +1000, Dave Airlie wrote: > From: Dave Airlie > > This interface allows importing the fence from a sync_file into > an existing drm sync object, or exporting the fence attached to > an existing drm sync object into a new sync file object. > > This should only be used to interact with sync files where necessary. > > Signed-off-by: Dave Airlie A bunch of nits around ioctl validation and stuff. lgtm otherwise, ack with those addressed. -Daniel > --- > drivers/gpu/drm/drm_syncobj.c | 56 > +++ > include/uapi/drm/drm.h| 6 +++-- > 2 files changed, 60 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c > index 9a8c690..69ef20a 100644 > --- a/drivers/gpu/drm/drm_syncobj.c > +++ b/drivers/gpu/drm/drm_syncobj.c > @@ -52,6 +52,7 @@ > #include > #include > #include > +#include > > #include "drm_internal.h" > #include > @@ -290,6 +291,48 @@ static int drm_syncobj_fd_to_handle(struct drm_file > *file_private, > return 0; > } > > +int drm_syncobj_import_sync_file_fence(struct drm_file *file_private, > +int fd, int handle) > +{ > + struct dma_fence *fence = sync_file_get_fence(fd); > + if (!fence) > + return -EINVAL; > + > + return drm_syncobj_replace_fence(file_private, handle, fence); > +} > + > +int drm_syncobj_export_sync_file(struct drm_file *file_private, > + int handle, int *p_fd) > +{ > + int ret; > + struct dma_fence *fence; > + struct sync_file *sync_file; > + int fd = get_unused_fd_flags(O_CLOEXEC); I guess the idea was to use args->fd_flags here? > + > + if (fd < 0) > + return fd; > + > + ret = drm_syncobj_fence_get(file_private, handle, &fence); > + if (ret) > + goto err_put_fd; > + > + sync_file = sync_file_create(fence); > + if (!sync_file) { > + ret = -EINVAL; > + goto err_fence_put; > + } > + > + fd_install(fd, sync_file->file); > + > + dma_fence_put(fence); > + *p_fd = fd; > + return 0; > +err_fence_put: > + dma_fence_put(fence); > +err_put_fd: > + put_unused_fd(fd); > + return ret; > +} > /** > * drm_syncobj_open - initalizes syncobj file-private structures at devnode > open time > * @dev: drm_device which is being opened by userspace > @@ -372,6 +415,12 @@ drm_syncobj_handle_to_fd_ioctl(struct drm_device *dev, > void *data, > if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > return -ENODEV; > > + if (args->flags & DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE) > + return drm_syncobj_export_sync_file(file_private, args->handle, > + &args->fd); Checks like in the wait ioctl that no other flags are set is missing in both callbacks. > + else if (args->flags) > + return -EINVAL; > + > return drm_syncobj_handle_to_fd(file_private, args->handle, > &args->fd); > } > @@ -385,6 +434,13 @@ drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, > void *data, > if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ)) > return -ENODEV; > > + if (args->flags & DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE) > + return drm_syncobj_import_sync_file_fence(file_private, > + args->fd, > + args->handle); > + else if (args->flags) > + return -EINVAL; > + > return drm_syncobj_fd_to_handle(file_private, args->fd, > &args->handle); > } > diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h > index db9e35e..d0e05f4 100644 > --- a/include/uapi/drm/drm.h > +++ b/include/uapi/drm/drm.h > @@ -707,13 +707,15 @@ struct drm_syncobj_destroy { > __u32 pad; > }; > > +#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE_FENCE (1 << 0) > +#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_FENCE_SYNC_FILE (1 << 0) > struct drm_syncobj_handle { > __u32 handle; > /** Flags.. only applicable for handle->fd */ > - __u32 flags; > + __u32 fd_flags; > > __s32 fd; > - __u32 pad; > + __u32 flags; s/pad/fd_flags/ instead of the shuffle you've done here I presume? Also I didn't spot any fd_flags validation anywhere. > }; > > /* timeout_ns is relative timeout in nanoseconds */ > -- > 2.9.3 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedeskt
Re: [PATCH 3/4] drm/amd/powerplay/smu7: add vblank check for mclk switching
Hi Alex, Comment below Den 11 maj 2017 7:59 em skrev "Alex Deucher" : Check to make sure the vblank period is long enough to support mclk switching. bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31 +--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index a74a3db..d745065 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -2655,6 +2655,28 @@ static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) return sizeof(struct smu7_power_state); } +static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, +uint32_t vblank_time_us) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t switch_limit_us = data->is_memory_gddr5 ? 450 : 150; This assignment is overwritten below. BR Nils + + switch (hwmgr->chip_id) { + case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + switch_limit_us = data->is_memory_gddr5 ? 190 : 150; + break; + default: + switch_limit_us = data->is_memory_gddr5 ? 450 : 150; + break; + } + + if (vblank_time_us < switch_limit_us) + return true; + else + return false; +} static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct pp_power_state *request_ps, @@ -2669,6 +2691,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, bool disable_mclk_switching; bool disable_mclk_switching_for_frame_lock; struct cgs_display_info info = {0}; + struct cgs_mode_info mode_info = {0}; const struct phm_clock_and_voltage_limits *max_limits; uint32_t i; struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -2677,6 +2700,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, int32_t count; int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; + info.mode_info = &mode_info; data->battery_state = (PP_StateUILabel_Battery == request_ps->classification.ui_label); @@ -2703,8 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, cgs_get_active_displays_info(hwmgr->device, &info); - /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ - minimum_clocks.engineClock = hwmgr->display_config.min_ core_set_clock; minimum_clocks.memoryClock = hwmgr->display_config.min_mem_ set_clock; @@ -2769,8 +2791,9 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, PHM_PlatformCaps_ DisableMclkSwitchingForFrameLock); - disable_mclk_switching = (1 < info.display_count) || - disable_mclk_switching_for_frame_lock; + disable_mclk_switching = ((1 < info.display_count) || + disable_mclk_switching_for_frame_lock || + smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us)); sclk = smu7_ps->performance_levels[0].engine_clock; mclk = smu7_ps->performance_levels[0].memory_clock; -- 2.5.5 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/4] drm/amdgpu/ci: disable mclk switching for high refresh rates
Hi, Alex Shouldn't the function return true when the refresh rate > 120? If so, same comment on patch 2. BR Nils Den 11 maj 2017 7:59 em skrev "Alex Deucher" : Even if the vblank period would allow it, it still seems to be problematic on some cards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 6dc1410..eb5d03b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -906,6 +906,12 @@ static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; + /* disable mclk switching if the refresh is >120Hz, even if the +* blanking period would allow it +*/ + if (amdgpu_dpm_get_vrefresh(adev) > 120) + return false; + if (vblank_time < switch_limit) return true; else -- 2.5.5 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: properly byteswap gpu_info firmware
Am 12.05.2017 um 01:10 schrieb Alex Deucher: It's stored in LE format. Signed-off-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d95d4c9..8a5bb42 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1459,19 +1459,19 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) (const struct gpu_info_firmware_v1_0 *)(fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); - adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se; - adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh; - adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se; - adev->gfx.config.max_backends_per_se = gpu_info_fw->gc_num_rb_per_se; + adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); + adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); + adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); + adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); adev->gfx.config.max_texture_channel_caches = - gpu_info_fw->gc_num_tccs; - adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs; - adev->gfx.config.max_gs_threads = gpu_info_fw->gc_num_max_gs_thds; - adev->gfx.config.gs_vgt_table_depth = gpu_info_fw->gc_gs_table_depth; - adev->gfx.config.gs_prim_buffer_depth = gpu_info_fw->gc_gsprim_buff_depth; + le32_to_cpu(gpu_info_fw->gc_num_tccs); + adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); + adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); + adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); + adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); adev->gfx.config.double_offchip_lds_buf = - gpu_info_fw->gc_double_offchip_lds_buffer; - adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size; + le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); + adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); break; } default: ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx