Re: [PATCH 2/2] drm/amdgpu: Optimize mutex usage (v2)

[Michel Dänzer]

On 16/06/17 02:03 PM, Alex Xie wrote:
> Use rw_semaphore instead of mutex for bo_lists.
> 
> In original function amdgpu_bo_list_get, the waiting
> for result->lock can be quite long while mutex
> bo_list_lock was holding. It can make other tasks
> waiting for bo_list_lock for long period too.
> Change bo_list_lock to rw_semaphore can avoid most of
> such long waiting.
> 
> Secondly, this patch allows several tasks(readers of idr)
> to proceed at the same time.
> 
> v2: use rcu and kref (Dave Airlie and Christian König)

At least the first two paragraphs above are inaccurate and confusing in
v2. Please modify the commit log to reflect what the patch actually does
now.


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Libre software enthusiast | Mesa and X developer
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[PATCH 1/2] drm/amdgpu: Optimization of AMDGPU_BO_LIST_OP_CREATE (v2)

[Alex Xie]

v2: Remove duplication of zeroing of bo list (Christian König)
Move idr_alloc function to end of ioctl (Christian König)
Call kfree bo_list when amdgpu_bo_list_set return error.
Combine the previous two patches into this patch.
Add amdgpu_bo_list_set function prototype.

Signed-off-by: Alex Xie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 53 -
 1 file changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index a664987..5af956f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -35,33 +35,45 @@
 #define AMDGPU_BO_LIST_MAX_PRIORITY32u
 #define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)
 
-static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv,
-struct amdgpu_bo_list **result,
+static int amdgpu_bo_list_set(struct amdgpu_device *adev,
+struct drm_file *filp,
+struct amdgpu_bo_list *list,
+struct drm_amdgpu_bo_list_entry *info,
+unsigned num_entries);
+
+static int amdgpu_bo_list_create(struct amdgpu_device *adev,
+struct drm_file *filp,
+struct drm_amdgpu_bo_list_entry *info,
+unsigned num_entries,
 int *id)
 {
int r;
+   struct amdgpu_fpriv *fpriv = filp->driver_priv;
+   struct amdgpu_bo_list *list;
 
-   *result = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);
-   if (!*result)
+   list = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);
+   if (!list)
return -ENOMEM;
 
+   /* initialize bo list*/
+   mutex_init(>lock);
+
+   r = amdgpu_bo_list_set(adev, filp, list, info, num_entries);
+   if (r) {
+   kfree(list);
+   return r;
+   }
+
+   /* idr alloc should be called only after initialization of bo list. */
mutex_lock(>bo_list_lock);
-   r = idr_alloc(>bo_list_handles, *result,
- 1, 0, GFP_KERNEL);
+   r = idr_alloc(>bo_list_handles, list, 1, 0, GFP_KERNEL);
+   mutex_unlock(>bo_list_lock);
if (r < 0) {
-   mutex_unlock(>bo_list_lock);
-   kfree(*result);
+   kfree(list);
return r;
}
*id = r;
 
-   mutex_init(&(*result)->lock);
-   (*result)->num_entries = 0;
-   (*result)->array = NULL;
-
-   mutex_lock(&(*result)->lock);
-   mutex_unlock(>bo_list_lock);
-
return 0;
 }
 
@@ -77,6 +89,7 @@ static void amdgpu_bo_list_destroy(struct amdgpu_fpriv 
*fpriv, int id)
mutex_unlock(>lock);
amdgpu_bo_list_free(list);
}
+
mutex_unlock(>bo_list_lock);
 }
 
@@ -273,16 +286,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void 
*data,
 
switch (args->in.operation) {
case AMDGPU_BO_LIST_OP_CREATE:
-   r = amdgpu_bo_list_create(fpriv, , );
+   r = amdgpu_bo_list_create(adev, filp, info, args->in.bo_number,
+ );
if (r)
goto error_free;
-
-   r = amdgpu_bo_list_set(adev, filp, list, info,
- args->in.bo_number);
-   amdgpu_bo_list_put(list);
-   if (r)
-   goto error_free;
-
break;
 
case AMDGPU_BO_LIST_OP_DESTROY:
-- 
2.7.4

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[PATCH 2/2] drm/amdgpu: Optimize mutex usage (v2)

[Alex Xie]

Use rw_semaphore instead of mutex for bo_lists.

In original function amdgpu_bo_list_get, the waiting
for result->lock can be quite long while mutex
bo_list_lock was holding. It can make other tasks
waiting for bo_list_lock for long period too.
Change bo_list_lock to rw_semaphore can avoid most of
such long waiting.

Secondly, this patch allows several tasks(readers of idr)
to proceed at the same time.

v2: use rcu and kref (Dave Airlie and Christian König)

Signed-off-by: Alex Xie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 40 -
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 063fc73..e9b3981 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -871,6 +871,8 @@ struct amdgpu_fpriv {
 
 struct amdgpu_bo_list {
struct mutex lock;
+   struct rcu_head rhead;
+   struct kref refcount;
struct amdgpu_bo *gds_obj;
struct amdgpu_bo *gws_obj;
struct amdgpu_bo *oa_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 5af956f..efa6903 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -41,6 +41,20 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
 struct drm_amdgpu_bo_list_entry *info,
 unsigned num_entries);
 
+static void amdgpu_bo_list_release_rcu(struct kref *ref)
+{
+   unsigned i;
+   struct amdgpu_bo_list *list = container_of(ref, struct amdgpu_bo_list,
+  refcount);
+
+   for (i = 0; i < list->num_entries; ++i)
+   amdgpu_bo_unref(>array[i].robj);
+
+   mutex_destroy(>lock);
+   drm_free_large(list->array);
+   kfree_rcu(list, rhead);
+}
+
 static int amdgpu_bo_list_create(struct amdgpu_device *adev,
 struct drm_file *filp,
 struct drm_amdgpu_bo_list_entry *info,
@@ -57,7 +71,7 @@ static int amdgpu_bo_list_create(struct amdgpu_device *adev,
 
/* initialize bo list*/
mutex_init(>lock);
-
+   kref_init(>refcount);
r = amdgpu_bo_list_set(adev, filp, list, info, num_entries);
if (r) {
kfree(list);
@@ -83,14 +97,9 @@ static void amdgpu_bo_list_destroy(struct amdgpu_fpriv 
*fpriv, int id)
 
mutex_lock(>bo_list_lock);
list = idr_remove(>bo_list_handles, id);
-   if (list) {
-   /* Another user may have a reference to this list still */
-   mutex_lock(>lock);
-   mutex_unlock(>lock);
-   amdgpu_bo_list_free(list);
-   }
-
mutex_unlock(>bo_list_lock);
+   if (list)
+   kref_put(>refcount, amdgpu_bo_list_release_rcu);
 }
 
 static int amdgpu_bo_list_set(struct amdgpu_device *adev,
@@ -185,11 +194,17 @@ amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
 {
struct amdgpu_bo_list *result;
 
-   mutex_lock(>bo_list_lock);
+   rcu_read_lock();
result = idr_find(>bo_list_handles, id);
-   if (result)
-   mutex_lock(>lock);
-   mutex_unlock(>bo_list_lock);
+
+   if (result) {
+   if (kref_get_unless_zero(>refcount))
+   mutex_lock(>lock);
+   else
+   result = NULL;
+   }
+   rcu_read_unlock();
+
return result;
 }
 
@@ -227,6 +242,7 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
 void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
 {
mutex_unlock(>lock);
+   kref_put(>refcount, amdgpu_bo_list_release_rcu);
 }
 
 void amdgpu_bo_list_free(struct amdgpu_bo_list *list)
-- 
2.7.4

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[PATCH 2/2] amdgpu: use drm sync objects for shared semaphores (v5)

[Dave Airlie]

From: Dave Airlie 

This creates a new command submission chunk for amdgpu
to add in and out sync objects around the submission.

Sync objects are managed via the drm syncobj ioctls.

The command submission interface is enhanced with two new
chunks, one for syncobj pre submission dependencies,
and one for post submission sync obj signalling,
and just takes a list of handles for each.

This is based on work originally done by David Zhou at AMD,
with input from Christian Konig on what things should look like.

In theory VkFences could be backed with sync objects and
just get passed into the cs as syncobj handles as well.

NOTE: this interface addition needs a version bump to expose
it to userspace.

TODO: update to dep_sync when rebasing onto amdgpu master.
(with this - r-b from Christian)

v1.1: keep file reference on import.
v2: move to using syncobjs
v2.1: change some APIs to just use p pointer.
v3: make more robust against CS failures, we now add the
wait sems but only remove them once the CS job has been
submitted.
v4: rewrite names of API and base on new syncobj code.
v5: move post deps earlier, rename some apis
v6: lookup post deps earlier, and just replace fences
in post deps stage (Christian)

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 88 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  2 +-
 include/uapi/drm/amdgpu_drm.h   |  6 +++
 4 files changed, 97 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0adad5..9f827ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1159,6 +1159,9 @@ struct amdgpu_cs_parser {
 
/* user fence */
struct amdgpu_bo_list_entry uf_entry;
+
+   unsigned num_post_dep_syncobjs;
+   struct drm_syncobj **post_dep_syncobjs;
 };
 
 #define AMDGPU_PREAMBLE_IB_PRESENT  (1 << 0) /* bit set means command 
submit involves a preamble IB */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 29469e6..aeee684 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
 
@@ -154,6 +155,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void 
*data)
break;
 
case AMDGPU_CHUNK_ID_DEPENDENCIES:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
break;
 
default:
@@ -682,6 +685,11 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser 
*parser, int error, bo
ttm_eu_backoff_reservation(>ticket,
   >validated);
}
+
+   for (i = 0; i < parser->num_post_dep_syncobjs; i++)
+   drm_syncobj_put(parser->post_dep_syncobjs[i]);
+   kfree(parser->post_dep_syncobjs);
+
dma_fence_put(parser->fence);
 
if (parser->ctx)
@@ -971,6 +979,64 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,
return 0;
 }
 
+static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
+uint32_t handle)
+{
+   int r;
+   struct dma_fence *fence;
+   r = drm_syncobj_fence_get(p->filp, handle, );
+   if (r)
+   return r;
+
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence);
+   dma_fence_put(fence);
+
+   return r;
+}
+
+static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
+   struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
+static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
+struct amdgpu_cs_chunk *chunk)
+{
+   unsigned num_deps;
+   int i;
+   struct drm_amdgpu_cs_chunk_sem *deps;
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+
+   p->post_dep_syncobjs = kmalloc_array(num_deps,
+sizeof(struct drm_syncobj *),
+GFP_KERNEL);
+   p->num_post_dep_syncobjs = 0;
+
+   for (i 

[PATCH 1/2] amdgpu/cs: split out fence dependency checking (v2)

[Dave Airlie]

From: Dave Airlie 

This just splits out the fence depenency checking into it's
own function to make it easier to add semaphore dependencies.

v2: rebase onto other changes.

v1-Reviewed-by: Christian König 
Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 93 +++---
 1 file changed, 51 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index a37bdf4..29469e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -923,59 +923,68 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
return 0;
 }
 
-static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- struct amdgpu_cs_parser *p)
+static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
+  struct amdgpu_cs_chunk *chunk)
 {
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-   int i, j, r;
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_dep *deps;
 
-   for (i = 0; i < p->nchunks; ++i) {
-   struct drm_amdgpu_cs_chunk_dep *deps;
-   struct amdgpu_cs_chunk *chunk;
-   unsigned num_deps;
+   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_dep);
 
-   chunk = >chunks[i];
+   for (i = 0; i < num_deps; ++i) {
+   struct amdgpu_ring *ring;
+   struct amdgpu_ctx *ctx;
+   struct dma_fence *fence;
 
-   if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
-   continue;
+   ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
+   if (ctx == NULL)
+   return -EINVAL;
 
-   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
-   num_deps = chunk->length_dw * 4 /
-   sizeof(struct drm_amdgpu_cs_chunk_dep);
+   r = amdgpu_queue_mgr_map(p->adev, >queue_mgr,
+deps[i].ip_type,
+deps[i].ip_instance,
+deps[i].ring, );
+   if (r) {
+   amdgpu_ctx_put(ctx);
+   return r;
+   }
 
-   for (j = 0; j < num_deps; ++j) {
-   struct amdgpu_ring *ring;
-   struct amdgpu_ctx *ctx;
-   struct dma_fence *fence;
+   fence = amdgpu_ctx_get_fence(ctx, ring,
+deps[i].handle);
+   if (IS_ERR(fence)) {
+   r = PTR_ERR(fence);
+   amdgpu_ctx_put(ctx);
+   return r;
+   } else if (fence) {
+   r = amdgpu_sync_fence(p->adev, >job->sync,
+ fence);
+   dma_fence_put(fence);
+   amdgpu_ctx_put(ctx);
+   if (r)
+   return r;
+   }
+   }
+   return 0;
+}
 
-   ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
-   if (ctx == NULL)
-   return -EINVAL;
+static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p)
+{
+   int i, r;
 
-   r = amdgpu_queue_mgr_map(adev, >queue_mgr,
-deps[j].ip_type,
-deps[j].ip_instance,
-deps[j].ring, );
-   if (r) {
-   amdgpu_ctx_put(ctx);
-   return r;
-   }
+   for (i = 0; i < p->nchunks; ++i) {
+   struct amdgpu_cs_chunk *chunk;
 
-   fence = amdgpu_ctx_get_fence(ctx, ring,
-deps[j].handle);
-   if (IS_ERR(fence)) {
-   r = PTR_ERR(fence);
-   amdgpu_ctx_put(ctx);
-   return r;
+   chunk = >chunks[i];
 
-   } else if (fence) {
-   r = amdgpu_sync_fence(adev, >job->sync,
- fence);
-   dma_fence_put(fence);
-   amdgpu_ctx_put(ctx);
-   if (r)
-   return r;
-   }
+   if (chunk->chunk_id == 

Re: [PATCH] drm/amdgpu: don't check the default value for vm size

[Michel Dänzer]

On 16/06/17 07:21 AM, Alex Deucher wrote:
> Avoids printing spurious messages like this:
> [3.102059] amdgpu :01:00.0: VM size (-1) must be a power of 2
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 50001bf..ff90f78 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1074,6 +1074,10 @@ static void amdgpu_check_block_size(struct 
> amdgpu_device *adev)
>  
>  static void amdgpu_check_vm_size(struct amdgpu_device *adev)
>  {
> + /* no need to check the default value */
> + if (amdgpu_vm_size == -1)
> + return;
> +
>   if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
>   dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
>amdgpu_vm_size);
> 

Reviewed-by: Michel Dänzer 


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Libre software enthusiast | Mesa and X developer
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[PATCH] drm/radeon: remove unnecessary variable in si_enable_smc_cac

[Gustavo A. R. Silva]

Remove unnecessary variable smc_result and simplify the logic related.

Variable smc_result is only being used to store the return value of function
si_send_msg_to_smc() and then compare this value against constant
PPSMC_Result_OK. In other cases this variable is not even used after
storing a value in it (lines of code 2833 and 2838). Besides,
by removing this variable the logic can be simplified and the number
of nested IF statements reduced.

Addresses-Coverity-ID: 1226969
Signed-off-by: Gustavo A. R. Silva 
---
 drivers/gpu/drm/radeon/si_dpm.c | 49 ++---
 1 file changed, 22 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index ee3e742..09ef41f 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2800,42 +2800,37 @@ static int si_enable_smc_cac(struct radeon_device *rdev,
 {
struct ni_power_info *ni_pi = ni_get_pi(rdev);
struct si_power_info *si_pi = si_get_pi(rdev);
-   PPSMC_Result smc_result;
int ret = 0;
 
if (ni_pi->enable_cac) {
-   if (enable) {
-   if (!si_should_disable_uvd_powertune(rdev, 
radeon_new_state)) {
-   if (ni_pi->support_cac_long_term_average) {
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_CACLongTermAvgEnable);
-   if (smc_result != PPSMC_Result_OK)
-   
ni_pi->support_cac_long_term_average = false;
-   }
-
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_MSG_EnableCac);
-   if (smc_result != PPSMC_Result_OK) {
-   ret = -EINVAL;
-   ni_pi->cac_enabled = false;
-   } else {
-   ni_pi->cac_enabled = true;
-   }
-
-   if (si_pi->enable_dte) {
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_MSG_EnableDTE);
-   if (smc_result != PPSMC_Result_OK)
-   ret = -EINVAL;
-   }
+   if (enable &&
+   !si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
+   if (ni_pi->support_cac_long_term_average &&
+   PPSMC_Result_OK !=
+   si_send_msg_to_smc(rdev, 
PPSMC_CACLongTermAvgEnable))
+   ni_pi->support_cac_long_term_average = false;
+
+   if (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac) !=
+   PPSMC_Result_OK) {
+   ret = -EINVAL;
+   ni_pi->cac_enabled = false;
+   } else {
+   ni_pi->cac_enabled = true;
}
-   } else if (ni_pi->cac_enabled) {
-   if (si_pi->enable_dte)
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_MSG_DisableDTE);
 
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_MSG_DisableCac);
+   if (si_pi->enable_dte &&
+   si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE) !=
+   PPSMC_Result_OK)
+   ret = -EINVAL;
+   } else if (!enable && ni_pi->cac_enabled) {
+   if (si_pi->enable_dte)
+   si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 
+   si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
ni_pi->cac_enabled = false;
 
if (ni_pi->support_cac_long_term_average)
-   smc_result = si_send_msg_to_smc(rdev, 
PPSMC_CACLongTermAvgDisable);
+   si_send_msg_to_smc(rdev, 
PPSMC_CACLongTermAvgDisable);
}
}
return ret;
-- 
2.5.0

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[PATCH] drm/amdgpu: don't check the default value for vm size

[Alex Deucher]

Avoids printing spurious messages like this:
[3.102059] amdgpu :01:00.0: VM size (-1) must be a power of 2

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 50001bf..ff90f78 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1074,6 +1074,10 @@ static void amdgpu_check_block_size(struct amdgpu_device 
*adev)
 
 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
 {
+   /* no need to check the default value */
+   if (amdgpu_vm_size == -1)
+   return;
+
if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 amdgpu_vm_size);
-- 
2.5.5

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[PATCH 1/3] drm/amdgpu: drop set_vga_render_state from display funcs (v3)

[Alex Deucher]

Not used.

v2: include DC as well
v3: handle vega10/RV

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  2 -
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|  3 --
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|  3 --
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  1 -
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |  3 --
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  7 ---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 57 ---
 11 files changed, 6 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 063fc73..831e070 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1902,7 +1902,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), 
(iv))
 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-#define amdgpu_display_set_vga_render_state(adev, r) 
(adev)->mode_info.funcs->set_vga_render_state((adev), (r))
 #define amdgpu_display_vblank_get_counter(adev, crtc) 
(adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
 #define amdgpu_display_vblank_wait(adev, crtc) 
(adev)->mode_info.funcs->vblank_wait((adev), (crtc))
 #define amdgpu_display_backlight_set_level(adev, e, l) 
(adev)->mode_info.funcs->backlight_set_level((e), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 0b211d9..e086eb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -270,8 +270,6 @@ struct amdgpu_mode_mc_save {
 };
 
 struct amdgpu_display_funcs {
-   /* vga render */
-   void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
/* get frame count */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 4550ec3..46864ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -612,8 +612,8 @@ void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 }
 
-void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render)
+static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
+  bool render)
 {
u32 tmp;
 
@@ -3736,7 +3736,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
-   .set_vga_render_state = _v10_0_set_vga_render_state,
.bandwidth_update = _v10_0_bandwidth_update,
.vblank_get_counter = _v10_0_vblank_get_counter,
.vblank_wait = _v10_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
index c29c10b1..2ced0eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h
@@ -29,9 +29,6 @@ extern const struct amdgpu_ip_block_version 
dce_v10_0_ip_block;
 extern const struct amdgpu_ip_block_version dce_v10_1_ip_block;
 
 void dce_v10_0_disable_dce(struct amdgpu_device *adev);
-
-void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render);
 void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
  struct amdgpu_mode_mc_save *save);
 void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 1ce2666..5942d3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -572,8 +572,8 @@ void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 }
 
-void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
-   bool render)
+static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
+  bool render)
 {
u32 tmp;
 
@@ -3805,7 +3805,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
-   .set_vga_render_state = _v11_0_set_vga_render_state,
.bandwidth_update = 

[PATCH 2/3] drm/amdgpu: remove *_mc_access from display funcs (v3)

[Alex Deucher]

These are no longer needed now that we use the fb_location
programmed by the vbios.

v2: update DC as well
v3: handle vega10/RV

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   6 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  10 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 130 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h|   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  75 -
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h|   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 113 ---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  77 -
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h |   5 +-
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c  |  91 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c |  18 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |  17 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c |  16 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  82 --
 15 files changed, 54 insertions(+), 599 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 831e070..dbf9207 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -615,7 +615,6 @@ struct amdgpu_mc {
struct amdgpu_irq_src   vm_fault;
uint32_tvram_type;
uint32_tsrbm_soft_reset;
-   struct amdgpu_mode_mc_save save;
boolprt_warning;
uint64_tstolen_size;
/* apertures */
@@ -1914,8 +1913,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) 
(adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
 #define amdgpu_display_add_encoder(adev, e, s, c) 
(adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) 
(adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), 
(h), (r))
-#define amdgpu_display_stop_mc_access(adev, s) 
(adev)->mode_info.funcs->stop_mc_access((adev), (s))
-#define amdgpu_display_resume_mc_access(adev, s) 
(adev)->mode_info.funcs->resume_mc_access((adev), (s))
 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) 
(adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) 
(adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
 #define amdgpu_gfx_get_gpu_clock_counter(adev) 
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c509c3f..50001bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2925,12 +2925,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
r = amdgpu_suspend(adev);
 
 retry:
-   /* Disable fb access */
-   if (adev->mode_info.num_crtc) {
-   struct amdgpu_mode_mc_save save;
-   amdgpu_display_stop_mc_access(adev, );
-   amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
-   }
if (adev->is_atom_fw)
amdgpu_atomfirmware_scratch_regs_save(adev);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index e086eb1..bba349e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -263,12 +263,6 @@ struct amdgpu_audio {
int num_pins;
 };
 
-struct amdgpu_mode_mc_save {
-   u32 vga_render_control;
-   u32 vga_hdp_control;
-   bool crtc_enabled[AMDGPU_MAX_CRTCS];
-};
-
 struct amdgpu_display_funcs {
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
@@ -304,10 +298,6 @@ struct amdgpu_display_funcs {
  uint16_t connector_object_id,
  struct amdgpu_hpd *hpd,
  struct amdgpu_router *router);
-   void (*stop_mc_access)(struct amdgpu_device *adev,
-  struct amdgpu_mode_mc_save *save);
-   void (*resume_mc_access)(struct amdgpu_device *adev,
-struct amdgpu_mode_mc_save *save);
/* it is used to enter or exit into free sync mode */
int (*notify_freesync)(struct drm_device *dev, void *data,
   struct drm_file *filp);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 46864ea..a49768f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ 

[PATCH 3/3] drm/amd/dc/dm: remove redundant display structs (v2)

[Alex Deucher]

Now that the mc_access functions are gone, we no longer
need separate structs for all the different dce families
in dm.

v2: rebase on vega10/RV

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 105 +-
 1 file changed, 4 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 621e22b..55b3464 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1454,28 +1454,7 @@ static int amdgpu_notify_freesync(struct drm_device 
*dev, void *data,
return r;
 }
 
-#ifdef CONFIG_DRM_AMDGPU_CIK
-static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   dm_crtc_get_scanoutpos,/* called unconditionally */
-   .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-   .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-   .notify_freesync = amdgpu_notify_freesync,
-};
-#endif
-
-static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = {
+static const struct amdgpu_display_funcs dm_display_funcs = {
.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
.vblank_wait = NULL,
@@ -1495,67 +1474,6 @@ static const struct amdgpu_display_funcs 
dm_dce_v10_0_display_funcs = {
 
 };
 
-static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   dm_crtc_get_scanoutpos,/* called unconditionally */
-   .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-   .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-   .notify_freesync = amdgpu_notify_freesync,
-
-};
-
-static const struct amdgpu_display_funcs dm_dce_v12_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   dm_crtc_get_scanoutpos,/* called unconditionally */
-   .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-   .add_connector = NULL, /* VBIOS parsing. DAL does it. */
-   .notify_freesync = amdgpu_notify_freesync,
-
-};
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-static const struct amdgpu_display_funcs dm_dcn_v1_0_display_funcs = {
-   .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-   .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-   .vblank_wait = NULL,
-   .backlight_set_level =
-   dm_set_backlight_level,/* called unconditionally */
-   .backlight_get_level =
-   dm_get_backlight_level,/* called unconditionally */
-   .hpd_sense = NULL,/* called unconditionally */
-   .hpd_set_polarity = NULL, /* called unconditionally */
-   .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-   .page_flip = dm_page_flip, /* called unconditionally */
-   .page_flip_get_scanoutpos =
-   

Re: [PATCH] drm/core: Fail atomic IOCTL with no CRTC state but with signaling.

[Andrey Grodzovsky]

Just a reminder.

Thanks.

On 06/09/2017 05:30 PM, Andrey Grodzovsky wrote:

Problem:
While running IGT kms_atomic_transition test suite i encountered
a hang in drmHandleEvent immidietly follwoing an atomic_commit.
After dumping the atomic state I relized that in this case there was
not even one CRTC attached to the state and only disabled
planes. This probably due to a commit which hadn't changed any property
which would require attaching crtc state. This means drmHandleEvent
will never wake up from read since without CRTC in atomic state
the event fd will not be singnaled.
This point to a bug in IGT but also DRM should gracefully
fail  such scenario so no hang on user side will happen.

Fix:
Explicitly fail by failing atomic_commit early in
drm_mode_atomic_commit where such problem can be identified.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/drm_atomic.c | 13 -
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index a567310..32eae1c 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1933,7 +1933,7 @@ static int prepare_crtc_signaling(struct drm_device *dev,
  {
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
-   int i, ret;
+   int i, c = 0, ret;
  
  	if (arg->flags & DRM_MODE_ATOMIC_TEST_ONLY)

return 0;
@@ -1994,8 +1994,17 @@ static int prepare_crtc_signaling(struct drm_device *dev,
  
  			crtc_state->event->base.fence = fence;

}
+
+   c++;
}
  
+	/*

+* Having this flag means user mode pends on event which will never
+* reach due to lack of at least one CRTC for signaling
+*/
+   if (c == 0 && (arg->flags & DRM_MODE_PAGE_FLIP_EVENT))
+   return -EINVAL;
+
return 0;
  }
  
@@ -2179,6 +2188,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,

drm_mode_object_unreference(obj);
}
  
+

+
ret = prepare_crtc_signaling(dev, state, arg, file_priv, _state,
 _fences);
if (ret)


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RE: [PATCH] drm/amdgpu: drop set_vga_render_state from display funcs

[Deucher, Alexander]

> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Thursday, June 15, 2017 2:56 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu: drop set_vga_render_state from display
> funcs
> 
> Not used.
> 
> Reviewed-by: Christian König 
> Signed-off-by: Alex Deucher 

Didn’t mean to send this out.  Ignore for now.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 --
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   | 1 -
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   | 1 -
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c| 1 -
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c| 1 -
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 7 ---
>  7 files changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index fc7e8a3..5934615 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1890,7 +1890,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring
> *ring)
>  #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs-
> >get_wptr((adev))
>  #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs-
> >decode_iv((adev), (iv))
>  #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
> -#define amdgpu_display_set_vga_render_state(adev, r) (adev)-
> >mode_info.funcs->set_vga_render_state((adev), (r))
>  #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)-
> >mode_info.funcs->vblank_get_counter((adev), (crtc))
>  #define amdgpu_display_vblank_wait(adev, crtc) (adev)-
> >mode_info.funcs->vblank_wait((adev), (crtc))
>  #define amdgpu_display_backlight_set_level(adev, e, l) (adev)-
> >mode_info.funcs->backlight_set_level((e), (l))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index 43a9d3a..35bd93c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -264,8 +264,6 @@ struct amdgpu_mode_mc_save {
>  };
> 
>  struct amdgpu_display_funcs {
> - /* vga render */
> - void (*set_vga_render_state)(struct amdgpu_device *adev, bool
> render);
>   /* display watermarks */
>   void (*bandwidth_update)(struct amdgpu_device *adev);
>   /* get frame count */
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 0cdeb6a..35906f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3734,7 +3734,6 @@ static void dce_v10_0_encoder_add(struct
> amdgpu_device *adev,
>  }
> 
>  static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
> - .set_vga_render_state = _v10_0_set_vga_render_state,
>   .bandwidth_update = _v10_0_bandwidth_update,
>   .vblank_get_counter = _v10_0_vblank_get_counter,
>   .vblank_wait = _v10_0_vblank_wait,
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 773654a..c3113e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3803,7 +3803,6 @@ static void dce_v11_0_encoder_add(struct
> amdgpu_device *adev,
>  }
> 
>  static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
> - .set_vga_render_state = _v11_0_set_vga_render_state,
>   .bandwidth_update = _v11_0_bandwidth_update,
>   .vblank_get_counter = _v11_0_vblank_get_counter,
>   .vblank_wait = _v11_0_vblank_wait,
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index fae535b..3ba29ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3522,7 +3522,6 @@ static void dce_v6_0_encoder_add(struct
> amdgpu_device *adev,
>  }
> 
>  static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
> - .set_vga_render_state = _v6_0_set_vga_render_state,
>   .bandwidth_update = _v6_0_bandwidth_update,
>   .vblank_get_counter = _v6_0_vblank_get_counter,
>   .vblank_wait = _v6_0_vblank_wait,
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 3c558c1..70ebd7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3571,7 +3571,6 @@ static void dce_v8_0_encoder_add(struct
> amdgpu_device *adev,
>  }
> 
>  static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
> - .set_vga_render_state = _v8_0_set_vga_render_state,
>   .bandwidth_update = _v8_0_bandwidth_update,
>   .vblank_get_counter = _v8_0_vblank_get_counter,
>   .vblank_wait = _v8_0_vblank_wait,
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index f1b479b..944dda0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ 

[PATCH] drm/amdgpu: drop set_vga_render_state from display funcs

[Alex Deucher]

Not used.

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 --
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   | 1 -
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   | 1 -
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c| 1 -
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c| 1 -
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 7 ---
 7 files changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fc7e8a3..5934615 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1890,7 +1890,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), 
(iv))
 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-#define amdgpu_display_set_vga_render_state(adev, r) 
(adev)->mode_info.funcs->set_vga_render_state((adev), (r))
 #define amdgpu_display_vblank_get_counter(adev, crtc) 
(adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
 #define amdgpu_display_vblank_wait(adev, crtc) 
(adev)->mode_info.funcs->vblank_wait((adev), (crtc))
 #define amdgpu_display_backlight_set_level(adev, e, l) 
(adev)->mode_info.funcs->backlight_set_level((e), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 43a9d3a..35bd93c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -264,8 +264,6 @@ struct amdgpu_mode_mc_save {
 };
 
 struct amdgpu_display_funcs {
-   /* vga render */
-   void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
/* display watermarks */
void (*bandwidth_update)(struct amdgpu_device *adev);
/* get frame count */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 0cdeb6a..35906f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3734,7 +3734,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
-   .set_vga_render_state = _v10_0_set_vga_render_state,
.bandwidth_update = _v10_0_bandwidth_update,
.vblank_get_counter = _v10_0_vblank_get_counter,
.vblank_wait = _v10_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 773654a..c3113e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3803,7 +3803,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
-   .set_vga_render_state = _v11_0_set_vga_render_state,
.bandwidth_update = _v11_0_bandwidth_update,
.vblank_get_counter = _v11_0_vblank_get_counter,
.vblank_wait = _v11_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index fae535b..3ba29ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3522,7 +3522,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
-   .set_vga_render_state = _v6_0_set_vga_render_state,
.bandwidth_update = _v6_0_bandwidth_update,
.vblank_get_counter = _v6_0_vblank_get_counter,
.vblank_wait = _v6_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 3c558c1..70ebd7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3571,7 +3571,6 @@ static void dce_v8_0_encoder_add(struct amdgpu_device 
*adev,
 }
 
 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
-   .set_vga_render_state = _v8_0_set_vga_render_state,
.bandwidth_update = _v8_0_bandwidth_update,
.vblank_get_counter = _v8_0_vblank_get_counter,
.vblank_wait = _v8_0_vblank_wait,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index f1b479b..944dda0 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -145,12 +145,6 @@ static void dce_virtual_resume_mc_access(struct 
amdgpu_device *adev,
return;
 }
 
-static void dce_virtual_set_vga_render_state(struct amdgpu_device *adev,
-   bool render)
-{
-   return;
-}
-
 /**
  * dce_virtual_bandwidth_update - program display watermarks
  *
@@ -677,7 +671,6 @@ static int dce_virtual_connector_encoder_init(struct 
amdgpu_device *adev,
 }
 
 static const struct 

RE: [PATCH umr] Add ability to read/write SMC registers directly

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Thursday, June 15, 2017 12:54 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH umr] Add ability to read/write SMC registers directly
> 
> On SI..VI platforms this allows access to SMC registers without kernel access.
> 
> Signed-off-by: Tom St Denis 
> ---
>  src/app/main.c|   4 +-
>  src/app/scan.c|   4 +-
>  src/lib/mmio.c| 112 +++-
> --
>  src/lib/read_sgpr.c   |   4 +-
>  src/lib/read_vram.c   |   6 +--
>  src/lib/wave_status.c |   8 ++--
>  src/umr.h |   4 +-
>  7 files changed, 104 insertions(+), 38 deletions(-)
> 
> diff --git a/src/app/main.c b/src/app/main.c
> index 60bf20480fd3..bcca76225727 100644
> --- a/src/app/main.c
> +++ b/src/app/main.c
> @@ -224,7 +224,7 @@ int main(int argc, char **argv)
>   if (!asic)
>   asic = get_asic();
>   if (!memcmp(argv[i+1], "0x", 2) &&
> sscanf(argv[i+1], "%"SCNx32, ) == 1 && sscanf(argv[i+2], "%"SCNx32,
> ) == 1)
> - umr_write_reg(asic, reg, val);
> + umr_write_reg(asic, reg, val,
> REG_MMIO);
>   else
>   umr_set_register(asic, argv[i+1],
> argv[i+2]);
>   i += 2;
> @@ -271,7 +271,7 @@ int main(int argc, char **argv)
>   asic = get_asic();
> 
>   if (!memcmp(argv[i+1], "0x", 2) &&
> sscanf(argv[i+1], "%"SCNx32, ) == 1) {
> - reg = umr_read_reg(asic, reg);
> + reg = umr_read_reg(asic, reg,
> REG_MMIO);
>   printf("0x%08lx\n", (unsigned
> long)reg);
>   } else {
>   str = strstr(argv[i+1], ".");
> diff --git a/src/app/scan.c b/src/app/scan.c
> index 0e1f9e3f94b5..29a3e46ba3f7 100644
> --- a/src/app/scan.c
> +++ b/src/app/scan.c
> @@ -87,10 +87,10 @@ int umr_scan_asic(struct umr_asic *asic, char
> *asicname, char *ipname, char *reg
>   r = -1;
>   goto error;
>   }
> - } else if (asic->blocks[i]-
> >regs[j].type == REG_MMIO) {
> + } else if (asic->blocks[i]-
> >regs[j].type == REG_MMIO || asic->blocks[i]->regs[j].type == REG_SMC) {
>   if (options.use_bank
> && options.no_kernel)
> 
>   umr_grbm_select_index(asic, options.se_bank, options.sh_bank,
> options.instance_bank);
> - asic->blocks[i]-
> >regs[j].value = umr_read_reg(asic, asic->blocks[i]->regs[j].addr * 4);
> + asic->blocks[i]-
> >regs[j].value = umr_read_reg(asic, asic->blocks[i]->regs[j].addr * (asic-
> >blocks[i]->regs[j].type == REG_MMIO ? 4 : 1), asic->blocks[i]->regs[j].type);
>   if (options.use_bank
> && options.no_kernel)
> 
>   umr_grbm_select_index(asic, 0x, 0x, 0x);
>   }
> diff --git a/src/lib/mmio.c b/src/lib/mmio.c
> index 22110e09a9b4..58f69fc56bd5 100644
> --- a/src/lib/mmio.c
> +++ b/src/lib/mmio.c
> @@ -24,51 +24,117 @@
>   */
>  #include "umr.h"
> 
> -uint32_t umr_read_reg(struct umr_asic *asic, uint64_t addr)
> +static uint32_t umr_smc_read(struct umr_asic *asic, uint64_t addr)
> +{
> + switch (asic->config.gfx.family) {
> + case 120: // CIK
> + case 110: // SI
> + umr_write_reg_by_name(asic,
> "mmSMC_IND_INDEX_0", addr);
> + return umr_read_reg_by_name(asic,
> "mmSMC_IND_DATA_0");
> + case 130: // VI
> + umr_write_reg_by_name(asic,
> "mmSMC_IND_INDEX_11", addr);
> + return umr_read_reg_by_name(asic,
> "mmSMC_IND_DATA_11");
> + case 135: // CZ
> + umr_write_reg_by_name(asic,
> "mmMP0PUB_IND_INDEX", addr);
> + return umr_read_reg_by_name(asic,
> "mmMP0PUB_IND_DATA");

You could use another instance of these accessors to avoid clashing with the 
driver.

Reviewed-by: Alex Deucher 

> + default:
> + fprintf(stderr, "[BUG] Unsupported family type in
> umr_smc_read()\n");
> + return 0;
> + }
> +}
> +
> +static uint32_t umr_smc_write(struct umr_asic *asic, uint64_t 

[PATCH umr] Add ability to read/write SMC registers directly

[Tom St Denis]

On SI..VI platforms this allows access to SMC registers without kernel access.

Signed-off-by: Tom St Denis 
---
 src/app/main.c|   4 +-
 src/app/scan.c|   4 +-
 src/lib/mmio.c| 112 +++---
 src/lib/read_sgpr.c   |   4 +-
 src/lib/read_vram.c   |   6 +--
 src/lib/wave_status.c |   8 ++--
 src/umr.h |   4 +-
 7 files changed, 104 insertions(+), 38 deletions(-)

diff --git a/src/app/main.c b/src/app/main.c
index 60bf20480fd3..bcca76225727 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -224,7 +224,7 @@ int main(int argc, char **argv)
if (!asic)
asic = get_asic();
if (!memcmp(argv[i+1], "0x", 2) && 
sscanf(argv[i+1], "%"SCNx32, ) == 1 && sscanf(argv[i+2], "%"SCNx32, ) 
== 1)
-   umr_write_reg(asic, reg, val);
+   umr_write_reg(asic, reg, val, REG_MMIO);
else
umr_set_register(asic, argv[i+1], 
argv[i+2]);
i += 2;
@@ -271,7 +271,7 @@ int main(int argc, char **argv)
asic = get_asic();
 
if (!memcmp(argv[i+1], "0x", 2) && 
sscanf(argv[i+1], "%"SCNx32, ) == 1) {
-   reg = umr_read_reg(asic, reg);
+   reg = umr_read_reg(asic, reg, REG_MMIO);
printf("0x%08lx\n", (unsigned long)reg);
} else {
str = strstr(argv[i+1], ".");
diff --git a/src/app/scan.c b/src/app/scan.c
index 0e1f9e3f94b5..29a3e46ba3f7 100644
--- a/src/app/scan.c
+++ b/src/app/scan.c
@@ -87,10 +87,10 @@ int umr_scan_asic(struct umr_asic *asic, char *asicname, 
char *ipname, char *reg
r = -1;
goto error;
}
-   } else if 
(asic->blocks[i]->regs[j].type == REG_MMIO) {
+   } else if 
(asic->blocks[i]->regs[j].type == REG_MMIO || asic->blocks[i]->regs[j].type == 
REG_SMC) {
if (options.use_bank && 
options.no_kernel)

umr_grbm_select_index(asic, options.se_bank, options.sh_bank, 
options.instance_bank);
-   
asic->blocks[i]->regs[j].value = umr_read_reg(asic, 
asic->blocks[i]->regs[j].addr * 4);
+   
asic->blocks[i]->regs[j].value = umr_read_reg(asic, 
asic->blocks[i]->regs[j].addr * (asic->blocks[i]->regs[j].type == REG_MMIO ? 4 
: 1), asic->blocks[i]->regs[j].type);
if (options.use_bank && 
options.no_kernel)

umr_grbm_select_index(asic, 0x, 0x, 0x);
}
diff --git a/src/lib/mmio.c b/src/lib/mmio.c
index 22110e09a9b4..58f69fc56bd5 100644
--- a/src/lib/mmio.c
+++ b/src/lib/mmio.c
@@ -24,51 +24,117 @@
  */
 #include "umr.h"
 
-uint32_t umr_read_reg(struct umr_asic *asic, uint64_t addr)
+static uint32_t umr_smc_read(struct umr_asic *asic, uint64_t addr)
+{
+   switch (asic->config.gfx.family) {
+   case 120: // CIK
+   case 110: // SI
+   umr_write_reg_by_name(asic, "mmSMC_IND_INDEX_0", addr);
+   return umr_read_reg_by_name(asic, "mmSMC_IND_DATA_0");
+   case 130: // VI
+   umr_write_reg_by_name(asic, "mmSMC_IND_INDEX_11", addr);
+   return umr_read_reg_by_name(asic, "mmSMC_IND_DATA_11");
+   case 135: // CZ
+   umr_write_reg_by_name(asic, "mmMP0PUB_IND_INDEX", addr);
+   return umr_read_reg_by_name(asic, "mmMP0PUB_IND_DATA");
+   default:
+   fprintf(stderr, "[BUG] Unsupported family type in 
umr_smc_read()\n");
+   return 0;
+   }
+}
+
+static uint32_t umr_smc_write(struct umr_asic *asic, uint64_t addr, uint32_t 
value)
+{
+   switch (asic->config.gfx.family) {
+   case 120: // CIK
+   case 110: // SI
+   umr_write_reg_by_name(asic, "mmSMC_IND_INDEX_0", addr);
+   return umr_write_reg_by_name(asic, "mmSMC_IND_DATA_0", 
value);
+   case 130: // VI
+   umr_write_reg_by_name(asic, "mmSMC_IND_INDEX_11", addr);
+   

[pull] amdgpu drm-next-4.13

[Alex Deucher]

Hi Dave,

A few more patches for 4.13.  Mostly bug fixes and code cleanup.  This is on
top of my pull request from last week.

The following changes since commit b58c11314a1706bf094c489ef5cb28f76478c704:

  drm/amdgpu: drop deprecated drm_get_pci_dev and drm_put_dev (2017-06-08 
10:54:39 -0400)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.13

for you to fetch changes up to a1924005a2e9bfcc4e217b4acd0a4f2421969040:

  drm/amdgpu: Fix compiler warnings (2017-06-15 11:50:36 -0400)


Alex Deucher (3):
  drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0
  drm/amdgpu/gfx9: fix compute ring doorbell index
  drm/amdgpu: add virtual display support for raven

Alex Xie (3):
  drm/amdgpu: remove duplicate function prototypes
  drm/amdgpu: fix a typo in comment
  drm/amdgpu: move comment to the right place

Eric Huang (3):
  drm/amd/powerplay: update vega10_ppsmc.h
  drm/amd/powerplay: add GPU power display for vega10
  drm/amd/powerplay: add avfs control for Vega10

Harish Kasiviswanathan (6):
  drm/amdgpu: Add vm context module param
  drm/amdgpu: Add amdgpu_sync_wait
  drm/amdgpu: Support page directory update via CPU
  drm/amdgpu: Support page table update via CPU
  drm/amdgpu: vm_update_ptes remove code duplication
  drm/amdgpu: Fix compiler warnings

Hawking Zhang (2):
  drm/amdgpu: add new member in gpu_info fw
  drm/amdgpu: avoid to reset wave_front_size to 0

Huang Rui (2):
  drm/amdgpu: export test ib debugfs interface
  drm/amdgpu: fix missed gpu info firmware when cache firmware during S3

Rex Zhu (1):
  drm/amd/powerplay: fix copy error in powerplay.

Tom St Denis (12):
  drm/amd/amdgpu: gfx9 tidy ups (v2)
  drm/amd/amdgpu: Rename KIQ ring to avoid spaces
  drm/amd/amdgpu: Add offset variant to SOC15 macros
  drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros
  drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns
  drm/amd/amdgpu: Port MMHUB over to new SOC15 macros
  drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros
  drm/amd/amdgpu: Port VCN over to new SOC15 macros

horchen (1):
  drm/amdgpu: add contiguous flag in ucode bo create

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  81 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   |  19 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h   |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c  |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h  |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 250 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  20 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  57 +++--
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  57 +++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  89 
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |  37 ++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c|  25 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  54 ++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  42 ++--
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c |  14 +-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  |  32 +--
 drivers/gpu/drm/amd/amdgpu/soc15.c |   2 +
 drivers/gpu/drm/amd/amdgpu/soc15_common.h  |  14 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 174 +++---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 164 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  27 ++-
 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h   |   3 +-
 27 files changed, 765 insertions(+), 422 deletions(-)
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Re: [PATCH umr] Don't read SGPR if wave isn't halted.

[Xie, AlexBin]

Reviewed-by: Alex Xie 



From: amd-gfx  on behalf of Tom St Denis 

Sent: Thursday, June 15, 2017 8:14:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH umr] Don't read SGPR if wave isn't halted.

On previous generations this was allowed but on Vega10 it will result
in the occasional system hang.

Also like others wave status reading is only reliable if

1) the waves are halted/hung (core is active)
2) or, you disable CG/PG with cg_mask=pg_mask=0

Even with this patch hangs are possible if PG/CG are still enabled on
Vega10.

Signed-off-by: Tom St Denis 
---
 src/app/print_waves.c | 40 ++--
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/src/app/print_waves.c b/src/app/print_waves.c
index e3662983d8d1..e157db9f9386 100644
--- a/src/app/print_waves.c
+++ b/src/app/print_waves.c
@@ -55,7 +55,8 @@ void umr_print_waves(struct umr_asic *asic)
 umr_get_wave_status(asic, se, sh, cu, simd, 
wave, );
 if (ws.wave_status.halt || 
ws.wave_status.valid) {
 // grab sgprs..
-   umr_read_sgprs(asic, , [0]);
+   if (ws.wave_status.halt)
+   umr_read_sgprs(asic, , 
[0]);

 if (!options.bitfields && first) {
 first = 0;
@@ -75,14 +76,15 @@ void umr_print_waves(struct umr_asic *asic)
 (unsigned long)ws.hw_id.value, (unsigned long)ws.gpr_alloc.value, (unsigned 
long)ws.lds_alloc.value, (unsigned long)ws.trapsts.value, (unsigned 
long)ws.ib_sts.value,
 (unsigned long)ws.tba_hi, (unsigned long)ws.tba_lo, (unsigned long)ws.tma_hi, 
(unsigned long)ws.tma_lo, (unsigned long)ws.ib_dbg0, (unsigned long)ws.m0
 );
-   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
-   printf(">SGPRS[%u..%u] 
= { %08lx, %08lx, %08lx, %08lx }\n",
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
-   (unsigned 
long)sgprs[x],
-   (unsigned 
long)sgprs[x+1],
-   (unsigned 
long)sgprs[x+2],
-   (unsigned 
long)sgprs[x+3]);
+   if (ws.wave_status.halt)
+   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
+   
printf(">SGPRS[%u..%u] = { %08lx, %08lx, %08lx, %08lx }\n",
+   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
+   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
+   
(unsigned long)sgprs[x],
+   
(unsigned long)sgprs[x+1],
+   
(unsigned long)sgprs[x+2],
+   
(unsigned long)sgprs[x+3]);

 pgm_addr = 
(((uint64_t)ws.pc_hi << 32) | ws.pc_lo) - (sizeof(opcodes)/2);
 umr_read_vram(asic, 
ws.hw_id.vm_id, pgm_addr, sizeof(opcodes), opcodes);
@@ -154,15 +156,17 @@ void umr_print_waves(struct umr_asic *asic)
 PP(gpr_alloc, sgpr_base);
 PP(gpr_alloc, sgpr_size);

-   printf("\n\nSGPRS:\n");
-   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
-   printf("\t[%4u..%4u] = 
{ %08lx, %08lx, %08lx, %08lx }\n",
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
-   (unsigned 
long)sgprs[x],
-

[PATCH] drm/amdgpu: adjust default display clock

[Alex Deucher]

Increase the default display clock on newer asics to
accomodate some high res modes with really high refresh
rates.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=93826
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 1cf78f4..1e8e112 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -693,6 +693,10 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device 
*adev)
DRM_INFO("Changing default dispclk from %dMhz to 
600Mhz\n",
 adev->clock.default_dispclk / 100);
adev->clock.default_dispclk = 6;
+   } else if (adev->clock.default_dispclk <= 6) {
+   DRM_INFO("Changing default dispclk from %dMhz to 
625Mhz\n",
+adev->clock.default_dispclk / 100);
+   adev->clock.default_dispclk = 62500;
}
adev->clock.dp_extclk =

le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
-- 
2.5.5

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[PATCH] drm/amdgpu/atom: fix ps allocation size for EnableDispPowerGating

[Alex Deucher]

We were using the wrong structure which lead to an overflow
on some boards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=101387
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c 
b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
index 8c9bc75..8a0818b 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
@@ -165,7 +165,7 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, 
int state)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
-   ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+   ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
 
memset(, 0, sizeof(args));
 
@@ -178,7 +178,7 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, 
int state)
 void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
 {
int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
-   ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+   ENABLE_DISP_POWER_GATING_PS_ALLOCATION args;
 
memset(, 0, sizeof(args));
 
-- 
2.5.5

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Re: [Intel-gfx] [PATCH i-g-t] tests: Rename I915_MAX_PIPES to IGT_MAX_PIPES

[Leo]

On 2017-06-13 08:55 AM, Arkadiusz Hiler wrote:

On Tue, Jun 13, 2017 at 03:41:14PM +0300, Arkadiusz Hiler wrote:

On Tue, Jun 13, 2017 at 10:35:34AM +0300, Jani Nikula wrote:

On Mon, 12 Jun 2017, Harry Wentland  wrote:

The email was sent but might be stuck in the moderation queue since Leo
(Sun peng) is fairly new on the FDO mailing lists.

Jani, Daniel, can you check if Leo's IGT emails are stuck in the
moderation queue?


Done. I've whitelisted his email address on intel-gfx, but I suggest
subscribing too.

BR,
Jani.


Thanks Jani.

I'll wait with pushing this untill we run it though CI system to make
sure nothing breaks, as suggested by Petri.


To clarify - this depends on the series that changes the number to six,
and that's the one that should use some testing.


Thanks for the patch!

--
Cheers,
Arek


Thanks Jani.

Arek, regarding CI - are there any updates on the test results?

Thanks,
Leo
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Re: amdgpu display corruption and hang on AMD A10-9620P

[Carlo Caione]

On Mon, Jun 12, 2017 at 12:24 PM, Carlo Caione  wrote:
> On Tue, May 9, 2017 at 7:03 PM, Deucher, Alexander
>  wrote:
>>> -Original Message-
>>> From: Daniel Drake [mailto:dr...@endlessm.com]
>>> Sent: Tuesday, May 09, 2017 12:55 PM
>>> To: dri-devel; amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>> Cc: Chris Chiu; Linux Upstreaming Team
>>> Subject: amdgpu display corruption and hang on AMD A10-9620P
>>>
>>> Hi,
>>>
>>> We are working with new laptops that have the AMD Bristol Ridge
>>> chipset with this SoC:
>>>
>>> AMD A10-9620P RADEON R5, 10 COMPUTE CORES 4C+6G
>>>
>>> I think this is the Bristol Ridge chipset.
>>>
>>> During boot, the display becomes unusable at the point where the
>>> amdgpu driver loads. You can see at least two horizontal lines of
>>> garbage at this point. We have reproduced on 4.8, 4.10 and linus
>>> master (early 4.12).
>>>
>>> Photo: http://pasteboard.co/qrC9mh4p.jpg
>>>
>>> Getting logs is tricky because the system appears to freeze at that point.
>>>
>>> Is this a known issue? Anything we can do to help diagnosis?
>>
>> I'm not aware of any specific issues.  Please file a bug and attach your 
>> logs (https://bugs.freedesktop.org) along with information about the system.
>
> Opened https://bugs.freedesktop.org/show_bug.cgi?id=101387 to trace
> this bug. I also have attached there the full log we get when
> modprobing amdgpu.
> Reporting here only the trace for the sake of documentation (full log
> attached to the bug opened on freedesktop)
>
> [   80.766937] ---[ end Kernel panic - not syncing: stack-protector:
> Kernel stack is corrupted in: c0c88942
> [   80.766937]
> [   80.766408] Kernel panic - not syncing: stack-protector: Kernel
> stack is corrupted in: c0c88942
> [   80.766408]
> [   80.766428] CPU: 1 PID: 1594 Comm: modprobe Not tainted 4.11.3+ #2
> [   80.766431] Hardware name: Acer Aspire A515-41G/Wartortle_BS, BIOS
> V0.09 04/19/2017
> [   80.766434] Call Trace:
> [   80.766445]  dump_stack+0x63/0x90
> [   80.766451]  panic+0xe8/0x236
> [   80.766526]  ? amdgpu_atombios_crtc_powergate_init+0x52/0x60 [amdgpu]
> [   80.766537]  __stack_chk_fail+0x1b/0x20
> [   80.766571]  amdgpu_atombios_crtc_powergate_init+0x52/0x60 [amdgpu]
> [   80.766610]  dce_v11_0_hw_init+0x3e/0x2d0 [amdgpu]
> [   80.766643]  amdgpu_device_init+0xe23/0x13c0 [amdgpu]
> [   80.766647]  ? kmalloc_order+0x18/0x40
> [   80.766650]  ? kmalloc_order_trace+0x24/0xa0
> [   80.766683]  amdgpu_driver_load_kms+0x5d/0x240 [amdgpu]
> [   80.766708]  drm_dev_register+0x148/0x1e0 [drm]
> [   80.766721]  drm_get_pci_dev+0xa0/0x160 [drm]
> [   80.766754]  amdgpu_pci_probe+0xb9/0xf0 [amdgpu]
> [   80.766759]  local_pci_probe+0x45/0xa0
> [   80.766762]  pci_device_probe+0xf4/0x150
> [   80.766768]  driver_probe_device+0x2c5/0x470
> [   80.766772]  __driver_attach+0xdf/0xf0
> [   80.766776]  ? driver_probe_device+0x470/0x470
> [   80.766780]  bus_for_each_dev+0x6c/0xc0
> [   80.766784]  driver_attach+0x1e/0x20
> [   80.766787]  bus_add_driver+0x45/0x270
> [   80.766790]  ? 0xc09a8000
> [   80.766794]  driver_register+0x60/0xe0
> [   80.766796]  ? 0xc09a8000
> [   80.766799]  __pci_register_driver+0x4c/0x50
> [   80.766811]  drm_pci_init+0xed/0x100 [drm]
> [   80.766816]  ? vga_switcheroo_register_handler+0x6c/0x90
> [   80.766819]  ? 0xc09a8000
> [   80.766850]  amdgpu_init+0x9b/0xac [amdgpu]
> [   80.766855]  do_one_initcall+0x53/0x1c0
> [   80.766860]  ? __vunmap+0x81/0xd0
> [   80.766865]  ? kmem_cache_alloc_trace+0xdb/0x1b0
> [   80.766868]  ? kfree+0x161/0x170
> [   80.766876]  do_init_module+0x60/0x202
> [   80.766881]  load_module+0x2612/0x29f0
> [   80.766885]  SYSC_finit_module+0xa6/0xf0
> [   80.766888]  ? SYSC_finit_module+0xa6/0xf0
> [   80.766892]  SyS_finit_module+0xe/0x10
> [   80.766896]  entry_SYSCALL_64_fastpath+0x1e/0xad
> [   80.766899] RIP: 0033:0x7fa525e60709
> [   80.766902] RSP: 002b:7fff2f5bbbf8 EFLAGS: 0246 ORIG_RAX:
> 0139
> [   80.766905] RAX: ffda RBX: 7fa526129760 RCX: 
> 7fa525e60709
> [   80.766908] RDX:  RSI: 55f51f1c9439 RDI: 
> 000b
> [   80.766910] RBP: 0070 R08:  R09: 
> 55f51fcd83f0
> [   80.766913] R10: 000b R11: 0246 R12: 
> 55f51fcd9ff0
> [   80.766915] R13: 0007 R14: 7fa5261297b8 R15: 
> 2710
> [   80.766931] Kernel Offset: 0x2280 from 0x8100
> (relocation range: 0x8000-0xbfff)
> [   80.766937] ---[ end Kernel panic - not syncing: stack-protector:
> Kernel stack is corrupted in: c0c88942

Trying to move this discussion here for more visibility. This is what
is happening.

In amdgpu_atombios_crtc_powergate_init() we are declaring
ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args as parameter space, this
is 32bytes wide and passed down to the atombios interpreter in
ctx->ps.

[PATCH umr] Don't read SGPR if wave isn't halted.

[Tom St Denis]

On previous generations this was allowed but on Vega10 it will result
in the occasional system hang.

Also like others wave status reading is only reliable if

1) the waves are halted/hung (core is active)
2) or, you disable CG/PG with cg_mask=pg_mask=0

Even with this patch hangs are possible if PG/CG are still enabled on
Vega10.

Signed-off-by: Tom St Denis 
---
 src/app/print_waves.c | 40 ++--
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/src/app/print_waves.c b/src/app/print_waves.c
index e3662983d8d1..e157db9f9386 100644
--- a/src/app/print_waves.c
+++ b/src/app/print_waves.c
@@ -55,7 +55,8 @@ void umr_print_waves(struct umr_asic *asic)
umr_get_wave_status(asic, se, sh, cu, simd, 
wave, );
if (ws.wave_status.halt || 
ws.wave_status.valid) {
// grab sgprs..
-   umr_read_sgprs(asic, , [0]);
+   if (ws.wave_status.halt)
+   umr_read_sgprs(asic, , 
[0]);
 
if (!options.bitfields && first) {
first = 0;
@@ -75,14 +76,15 @@ void umr_print_waves(struct umr_asic *asic)
 (unsigned long)ws.hw_id.value, (unsigned long)ws.gpr_alloc.value, (unsigned 
long)ws.lds_alloc.value, (unsigned long)ws.trapsts.value, (unsigned 
long)ws.ib_sts.value,
 (unsigned long)ws.tba_hi, (unsigned long)ws.tba_lo, (unsigned long)ws.tma_hi, 
(unsigned long)ws.tma_lo, (unsigned long)ws.ib_dbg0, (unsigned long)ws.m0
 );
-   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
-   printf(">SGPRS[%u..%u] 
= { %08lx, %08lx, %08lx, %08lx }\n",
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
-   (unsigned 
long)sgprs[x],
-   (unsigned 
long)sgprs[x+1],
-   (unsigned 
long)sgprs[x+2],
-   (unsigned 
long)sgprs[x+3]);
+   if (ws.wave_status.halt)
+   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
+   
printf(">SGPRS[%u..%u] = { %08lx, %08lx, %08lx, %08lx }\n",
+   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
+   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
+   
(unsigned long)sgprs[x],
+   
(unsigned long)sgprs[x+1],
+   
(unsigned long)sgprs[x+2],
+   
(unsigned long)sgprs[x+3]);
 
pgm_addr = (((uint64_t)ws.pc_hi 
<< 32) | ws.pc_lo) - (sizeof(opcodes)/2);
umr_read_vram(asic, 
ws.hw_id.vm_id, pgm_addr, sizeof(opcodes), opcodes);
@@ -154,15 +156,17 @@ void umr_print_waves(struct umr_asic *asic)
PP(gpr_alloc, sgpr_base);
PP(gpr_alloc, sgpr_size);
 
-   printf("\n\nSGPRS:\n");
-   for (x = 0; x < 
((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
-   printf("\t[%4u..%4u] = 
{ %08lx, %08lx, %08lx, %08lx }\n",
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
-   
(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
-   (unsigned 
long)sgprs[x],
-   (unsigned 
long)sgprs[x+1],
-   (unsigned 
long)sgprs[x+2],
-   (unsigned 
long)sgprs[x+3]);
+   if (ws.wave_status.halt) {
+   

Re: [PATCH libdrm v8] amdgpu: move asic id table to a separate file

[Michel Dänzer]

On 15/06/17 04:42 PM, Emil Velikov wrote:
> On 15 June 2017 at 04:16, Michel Dänzer  wrote:
>> On 14/06/17 08:34 PM, Emil Velikov wrote:
>>
>>> Personally I would not have bothered with the table_max_size thing
>>
>> It seemed silly to reallocate the memory in the default case where the
>> amdgpu.ids file from this repository is used. :)
>>
> Agreed. Yet the single, "reduce memory consumption" realloc seems to
> diminish amongst the ~150 [unneeded] strdup/free, in parse_one_line
> 

True.


>>> or the separate Makefile.
>>
>> You mean data/Makefile.am? What would you have done instead?
>>
> One can fold the two lines within the top makefile (see below) since
> I'm lazy to complete the "use non-recursive makefiles" [1] branch.
> 
> -Emil
> [1] https://github.com/evelikov/libdrm/commits/hello-world
> 
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -43,6 +43,9 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
>--enable-manpages \
>--enable-valgrind
> 
> +libdrmdatadir = @libdrmdatadir@
> +dist_libdrmdata_DATA = data/amdgpu.ids
> +
> pkgconfigdir = @pkgconfigdir@
> pkgconfig_DATA = libdrm.pc

Thanks. I'm afraid I don't care enough right now, but maybe somebody
else can pick up your suggestions.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH libdrm v8] amdgpu: move asic id table to a separate file

[Emil Velikov]

On 15 June 2017 at 04:16, Michel Dänzer  wrote:
> On 14/06/17 08:34 PM, Emil Velikov wrote:
>> On 13 June 2017 at 10:45, Michel Dänzer  wrote:
>>> From: Xiaojie Yuan 
>>>
>>> v2: fix an off by one error and leading white spaces
>>> v3: use thread safe strtok_r(); initialize len before calling getline();
>>> change printf() to drmMsg(); add initial amdgpu.ids
>>> v4: integrate some recent internal changes, including format changes
>>> v5: fix line number for empty/commented lines; realloc to save memory;
>>> indentation changes
>>> v6: remove a line error
>>> v7: [Michel Dänzer]
>>> * Move amdgpu.ids to new data directory
>>> * Remove placeholder entries from amdgpu.ids
>>> * Set libdrmdatadir variable in configure.ac instead of Makefile.am
>>>   [Emil Velikov]
>>> * Use isblank() instead of open-coding it [Emil Velikov]
>>> * Don't leak asic_id_table memory if realloc fails [Emil Velikov]
>>> * Check and bump table_max_size at the beginning of the while loop [Emil
>>>   Velikov]
>>> * Initialize table_max_size to the number of entries in data/amdgpu.ids
>> Thank you for addressing some of my suggestions.
>> Reviewed-by: Emil Velikov 
>
> Thanks! Pushed.
>
>
>> Personally I would not have bothered with the table_max_size thing
>
> It seemed silly to reallocate the memory in the default case where the
> amdgpu.ids file from this repository is used. :)
>
Agreed. Yet the single, "reduce memory consumption" realloc seems to
diminish amongst the ~150 [unneeded] strdup/free, in parse_one_line


>> or the separate Makefile.
>
> You mean data/Makefile.am? What would you have done instead?
>
One can fold the two lines within the top makefile (see below) since
I'm lazy to complete the "use non-recursive makefiles" [1] branch.

-Emil
[1] https://github.com/evelikov/libdrm/commits/hello-world

--- a/Makefile.am
+++ b/Makefile.am
@@ -43,6 +43,9 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
   --enable-manpages \
   --enable-valgrind

+libdrmdatadir = @libdrmdatadir@
+dist_libdrmdata_DATA = data/amdgpu.ids
+
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm.pc
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