[PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations (v2)

[Alex Deucher]

May waste a bit of memory, but simplifies the interface
significantly.

v2: convert internal accounting to use 256bit slots

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 77 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 65 +++--
 3 files changed, 20 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d492ff7..19ee2a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1131,10 +1131,6 @@ struct amdgpu_wb {
 
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb);
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fc6f8d5..62afe3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -504,7 +504,8 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
int r;
 
if (adev->wb.wb_obj == NULL) {
-   r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 
sizeof(uint32_t),
+   /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit 
slots */
+   r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 
sizeof(uint32_t) * 8,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>wb.wb_obj, 
>wb.gpu_addr,
(void **)>wb.wb);
@@ -535,47 +536,10 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 {
unsigned long offset = find_first_zero_bit(adev->wb.used, 
adev->wb.num_wb);
-   if (offset < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
 
-/**
- * amdgpu_wb_get_64bit - Allocate a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Allocate a wb slot for use by the driver (all asics).
- * Returns 0 on success or -EINVAL on failure.
- */
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
-{
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 2, 7, 0);
-   if ((offset + 1) < adev->wb.num_wb) {
+   if (offset < adev->wb.num_wb) {
__set_bit(offset, adev->wb.used);
-   __set_bit(offset + 1, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb)
-{
-   int i = 0;
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 8, 63, 0);
-   if ((offset + 7) < adev->wb.num_wb) {
-   for (i = 0; i < 8; i++)
-   __set_bit(offset + i, adev->wb.used);
-   *wb = offset;
+   *wb = offset * 8; /* convert to dw offset */
return 0;
} else {
return -EINVAL;
@@ -597,39 +561,6 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 }
 
 /**
- * amdgpu_wb_free_64bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
-{
-   if ((wb + 1) < adev->wb.num_wb) {
-   __clear_bit(wb, adev->wb.used);
-   __clear_bit(wb + 1, adev->wb.used);
-   }
-}
-
-/**
- * amdgpu_wb_free_256bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb)
-{
-   int i = 0;
-
-   if ((wb + 7) < adev->wb.num_wb)
-   for (i = 0; i < 8; i++)
-   __clear_bit(wb + i, adev->wb.used);
-}
-
-/**
  * amdgpu_vram_location - try to find VRAM location
  * @adev: amdgpu device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 3874be8..704475674 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ 

Re: [PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Andy Furniss]

Alex Deucher wrote:

On Fri, Jul 28, 2017 at 6:08 PM, Andy Furniss  wrote:

Alex Deucher wrote:


May waste a bit of memory, but simplifies the interface
significantly.



Can't boot tonga with this (testing 4.14-wip)


Should be fixed with this patch.


Yes, OK with that, thanks.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Alex Deucher]

On Fri, Jul 28, 2017 at 6:08 PM, Andy Furniss  wrote:
> Alex Deucher wrote:
>>
>> May waste a bit of memory, but simplifies the interface
>> significantly.
>
>
> Can't boot tonga with this (testing 4.14-wip)

Should be fixed with this patch.

Alex

>
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu kernel modesetting enabled.
> Jul 28 23:00:29 ph4 kernel: [drm] initializing kernel modesetting (TONGA
> 0x1002:0x6939 0x1458:0x229D 0x00).
> Jul 28 23:00:29 ph4 kernel: [drm] register mmio base: 0xFEA0
> Jul 28 23:00:29 ph4 kernel: [drm] register mmio size: 262144
> Jul 28 23:00:29 ph4 kernel: [drm] probing gen 2 caps for device 1002:5a16 =
> 31cd02/0
> Jul 28 23:00:29 ph4 kernel: [drm] probing mlw for device 1002:5a16 = 31cd02
> Jul 28 23:00:29 ph4 kernel: [drm] VCE enabled in physical mode
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: Invalid PCI ROM header
> signature: expecting 0xaa55, got 0x8b00
> Jul 28 23:00:29 ph4 kernel: ATOM BIOS: 113-xxx-Xxx
> Jul 28 23:00:29 ph4 kernel: [drm] GPU post is not needed
> Jul 28 23:00:29 ph4 kernel: [drm] Changing default dispclk from 600Mhz to
> 625Mhz
> Jul 28 23:00:29 ph4 kernel: [drm] vm size is 64 GB, block size is 13-bit
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: VRAM: 2048M
> 0x00F4 - 0x00F47FFF (2048M used)
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: GTT: 256M
> 0x - 0x0FFF
> Jul 28 23:00:29 ph4 kernel: [drm] Detected VRAM RAM=2048M, BAR=256M
> Jul 28 23:00:29 ph4 kernel: [drm] RAM width 256bits GDDR5
> Jul 28 23:00:29 ph4 kernel: [TTM] Zone  kernel: Available graphics memory:
> 4069418 kiB
> Jul 28 23:00:29 ph4 kernel: [TTM] Zone   dma32: Available graphics memory:
> 2097152 kiB
> Jul 28 23:00:29 ph4 kernel: [TTM] Initializing pool allocator
> Jul 28 23:00:29 ph4 kernel: [TTM] Initializing DMA pool allocator
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 2048M of VRAM memory ready
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 3072M of GTT memory ready.
> Jul 28 23:00:29 ph4 kernel: [drm] GART: num cpu pages 65536, num gpu pages
> 65536
> Jul 28 23:00:29 ph4 kernel: [drm] PCIE GART of 256M enabled (table at
> 0x00F40004).
> Jul 28 23:00:29 ph4 kernel: [drm] Supports vblank timestamp caching Rev 2
> (21.10.2013).
> Jul 28 23:00:29 ph4 kernel: [drm] Driver supports precise vblank timestamp
> query.
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: amdgpu: using MSI.
> Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: irq initialized.
> Jul 28 23:00:29 ph4 kernel: amdgpu: [powerplay] amdgpu: powerplay sw
> initialized
> Jul 28 23:00:29 ph4 kernel: [drm] AMDGPU Display Connectors
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 0:
> Jul 28 23:00:29 ph4 kernel: [drm]   DP-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD4
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4868 0x4868 0x4869 0x4869 0x486a
> 0x486a 0x486b 0x486b
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP1: INTERNAL_UNIPHY1
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 1:
> Jul 28 23:00:29 ph4 kernel: [drm]   HDMI-A-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD5
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4870 0x4870 0x4871 0x4871 0x4872
> 0x4872 0x4873 0x4873
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP2: INTERNAL_UNIPHY1
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 2:
> Jul 28 23:00:29 ph4 kernel: [drm]   DVI-D-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD1
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4878 0x4878 0x4879 0x4879 0x487a
> 0x487a 0x487b 0x487b
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP3: INTERNAL_UNIPHY
> Jul 28 23:00:29 ph4 kernel: [drm] Connector 3:
> Jul 28 23:00:29 ph4 kernel: [drm]   DVI-I-1
> Jul 28 23:00:29 ph4 kernel: [drm]   HPD6
> Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x487c 0x487c 0x487d 0x487d 0x487e
> 0x487e 0x487f 0x487f
> Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
> Jul 28 23:00:29 ph4 kernel: [drm] DFP4: INTERNAL_UNIPHY2
> Jul 28 23:00:29 ph4 kernel: [drm] CRT1: INTERNAL_KLDSCP_DAC1
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 0 use
> gpu addr 0x00400200, cpu addr 0x88022e059200
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 1 use
> gpu addr 0x00400600, cpu addr 0x88022e059600
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 2 use
> gpu addr 0x00400a00, cpu addr 0x88022e059a00
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 3 use
> gpu addr 0x00400e00, cpu addr 0x88022e059e00
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: (-22) ring rptr_offs wb
> alloc failed
> Jul 28 23:00:29 ph4 kernel: [drm:amdgpu_device_init [amdgpu]] *ERROR*
> sw_init of IP block  failed -22
> Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: amdgpu_init failed
> Jul 28 23:00:29 ph4 kernel: [TTM] Finalizing pool allocator
> Jul 28 

Re: [PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Andy Furniss]

Alex Deucher wrote:

May waste a bit of memory, but simplifies the interface
significantly.


Can't boot tonga with this (testing 4.14-wip)

Jul 28 23:00:29 ph4 kernel: [drm] amdgpu kernel modesetting enabled.
Jul 28 23:00:29 ph4 kernel: [drm] initializing kernel modesetting (TONGA 
0x1002:0x6939 0x1458:0x229D 0x00).

Jul 28 23:00:29 ph4 kernel: [drm] register mmio base: 0xFEA0
Jul 28 23:00:29 ph4 kernel: [drm] register mmio size: 262144
Jul 28 23:00:29 ph4 kernel: [drm] probing gen 2 caps for device 
1002:5a16 = 31cd02/0

Jul 28 23:00:29 ph4 kernel: [drm] probing mlw for device 1002:5a16 = 31cd02
Jul 28 23:00:29 ph4 kernel: [drm] VCE enabled in physical mode
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: Invalid PCI ROM header 
signature: expecting 0xaa55, got 0x8b00

Jul 28 23:00:29 ph4 kernel: ATOM BIOS: 113-xxx-Xxx
Jul 28 23:00:29 ph4 kernel: [drm] GPU post is not needed
Jul 28 23:00:29 ph4 kernel: [drm] Changing default dispclk from 600Mhz 
to 625Mhz

Jul 28 23:00:29 ph4 kernel: [drm] vm size is 64 GB, block size is 13-bit
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: VRAM: 2048M 
0x00F4 - 0x00F47FFF (2048M used)
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: GTT: 256M 
0x - 0x0FFF

Jul 28 23:00:29 ph4 kernel: [drm] Detected VRAM RAM=2048M, BAR=256M
Jul 28 23:00:29 ph4 kernel: [drm] RAM width 256bits GDDR5
Jul 28 23:00:29 ph4 kernel: [TTM] Zone  kernel: Available graphics 
memory: 4069418 kiB
Jul 28 23:00:29 ph4 kernel: [TTM] Zone   dma32: Available graphics 
memory: 2097152 kiB

Jul 28 23:00:29 ph4 kernel: [TTM] Initializing pool allocator
Jul 28 23:00:29 ph4 kernel: [TTM] Initializing DMA pool allocator
Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 2048M of VRAM memory ready
Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: 3072M of GTT memory ready.
Jul 28 23:00:29 ph4 kernel: [drm] GART: num cpu pages 65536, num gpu 
pages 65536
Jul 28 23:00:29 ph4 kernel: [drm] PCIE GART of 256M enabled (table at 
0x00F40004).
Jul 28 23:00:29 ph4 kernel: [drm] Supports vblank timestamp caching Rev 
2 (21.10.2013).
Jul 28 23:00:29 ph4 kernel: [drm] Driver supports precise vblank 
timestamp query.

Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: amdgpu: using MSI.
Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: irq initialized.
Jul 28 23:00:29 ph4 kernel: amdgpu: [powerplay] amdgpu: powerplay sw 
initialized

Jul 28 23:00:29 ph4 kernel: [drm] AMDGPU Display Connectors
Jul 28 23:00:29 ph4 kernel: [drm] Connector 0:
Jul 28 23:00:29 ph4 kernel: [drm]   DP-1
Jul 28 23:00:29 ph4 kernel: [drm]   HPD4
Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4868 0x4868 0x4869 0x4869 
0x486a 0x486a 0x486b 0x486b

Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
Jul 28 23:00:29 ph4 kernel: [drm] DFP1: INTERNAL_UNIPHY1
Jul 28 23:00:29 ph4 kernel: [drm] Connector 1:
Jul 28 23:00:29 ph4 kernel: [drm]   HDMI-A-1
Jul 28 23:00:29 ph4 kernel: [drm]   HPD5
Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4870 0x4870 0x4871 0x4871 
0x4872 0x4872 0x4873 0x4873

Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
Jul 28 23:00:29 ph4 kernel: [drm] DFP2: INTERNAL_UNIPHY1
Jul 28 23:00:29 ph4 kernel: [drm] Connector 2:
Jul 28 23:00:29 ph4 kernel: [drm]   DVI-D-1
Jul 28 23:00:29 ph4 kernel: [drm]   HPD1
Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x4878 0x4878 0x4879 0x4879 
0x487a 0x487a 0x487b 0x487b

Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
Jul 28 23:00:29 ph4 kernel: [drm] DFP3: INTERNAL_UNIPHY
Jul 28 23:00:29 ph4 kernel: [drm] Connector 3:
Jul 28 23:00:29 ph4 kernel: [drm]   DVI-I-1
Jul 28 23:00:29 ph4 kernel: [drm]   HPD6
Jul 28 23:00:29 ph4 kernel: [drm]   DDC: 0x487c 0x487c 0x487d 0x487d 
0x487e 0x487e 0x487f 0x487f

Jul 28 23:00:29 ph4 kernel: [drm]   Encoders:
Jul 28 23:00:29 ph4 kernel: [drm] DFP4: INTERNAL_UNIPHY2
Jul 28 23:00:29 ph4 kernel: [drm] CRT1: INTERNAL_KLDSCP_DAC1
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 0 
use gpu addr 0x00400200, cpu addr 0x88022e059200
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 1 
use gpu addr 0x00400600, cpu addr 0x88022e059600
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 2 
use gpu addr 0x00400a00, cpu addr 0x88022e059a00
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: fence driver on ring 3 
use gpu addr 0x00400e00, cpu addr 0x88022e059e00
Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: (-22) ring rptr_offs wb 
alloc failed
Jul 28 23:00:29 ph4 kernel: [drm:amdgpu_device_init [amdgpu]] *ERROR* 
sw_init of IP block  failed -22

Jul 28 23:00:29 ph4 kernel: amdgpu :01:00.0: amdgpu_init failed
Jul 28 23:00:29 ph4 kernel: [TTM] Finalizing pool allocator
Jul 28 23:00:29 ph4 kernel: [TTM] Finalizing DMA pool allocator
Jul 28 23:00:29 ph4 kernel: [TTM] Zone  kernel: Used memory at exit: 73 kiB
Jul 28 23:00:29 ph4 kernel: [TTM] Zone   dma32: Used memory at exit: 25 kiB
Jul 28 23:00:29 ph4 kernel: [drm] amdgpu: ttm finalized
Jul 

[PATCH 1/1] drm/amdgpu: Fix KFD initialization for multi-GPU systems

[Felix Kuehling]

kfd2kgd is device-specific, so it should not be a global variable.
Merge amdgpu_amdkfd_load_interface and amdgpu_amdkfd_device_probe
so that it's only needed as a local variable in one function.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 37 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  2 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  1 -
 3 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 2292c77..471f9d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -27,7 +27,6 @@
 #include "amdgpu_gfx.h"
 #include 
 
-const struct kfd2kgd_calls *kfd2kgd;
 const struct kgd2kfd_calls *kgd2kfd;
 bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
 
@@ -61,8 +60,21 @@ int amdgpu_amdkfd_init(void)
return ret;
 }
 
-bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev)
+void amdgpu_amdkfd_fini(void)
+{
+   if (kgd2kfd) {
+   kgd2kfd->exit();
+   symbol_put(kgd2kfd_init);
+   }
+}
+
+void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
 {
+   const struct kfd2kgd_calls *kfd2kgd;
+
+   if (!kgd2kfd)
+   return;
+
switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_KAVERI:
@@ -73,25 +85,12 @@ bool amdgpu_amdkfd_load_interface(struct amdgpu_device 
*adev)
kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
break;
default:
-   return false;
+   dev_info(adev->dev, "kfd not supported on this ASIC\n");
+   return;
}
 
-   return true;
-}
-
-void amdgpu_amdkfd_fini(void)
-{
-   if (kgd2kfd) {
-   kgd2kfd->exit();
-   symbol_put(kgd2kfd_init);
-   }
-}
-
-void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
-{
-   if (kgd2kfd)
-   adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
-   adev->pdev, kfd2kgd);
+   adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
+  adev->pdev, kfd2kgd);
 }
 
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 73f83a1..b8802a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -39,8 +39,6 @@ struct kgd_mem {
 int amdgpu_amdkfd_init(void);
 void amdgpu_amdkfd_fini(void);
 
-bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev);
-
 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev);
 int amdgpu_amdkfd_resume(struct amdgpu_device *adev);
 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 9182def..33b5fe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -157,7 +157,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned 
long flags)
"Error during ACPI methods call\n");
}
 
-   amdgpu_amdkfd_load_interface(adev);
amdgpu_amdkfd_device_probe(adev);
amdgpu_amdkfd_device_init(adev);
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] drm/amdgpu/sdma4: drop hdp flush from wptr shadow update

[Alex Deucher]

The wb buffer is in system memory, not vram so the flush
is useless.

Cc: Frank Min 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 660704d..c76727b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -313,7 +313,6 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
offset = 
adev->sdma.instance[i].poll_mem_offs;
atomic64_set((atomic64_t 
*)>wb.wb[offset],
 (ring->wptr << 2));
-   nbio_v6_1_hdp_flush(adev);
}
}
}
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/4] drm/amdgpu/sdma4: move wptr polling setup

[Alex Deucher]

Move it up before ring enablement with all of the other
engine setup and explicitly disable it for bare metal.

Cc: Frank Min 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 85b8561..79a9e44 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -662,6 +662,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), 
temp);
}
 
+   /* setup the wptr shadow polling */
+   wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+  lower_32_bits(wptr_gpu_addr));
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+  upper_32_bits(wptr_gpu_addr));
+   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+   if (amdgpu_sriov_vf(adev))
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+   else
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
1);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
@@ -690,17 +703,6 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
if (adev->mman.buffer_funcs_ring == ring)
amdgpu_ttm_set_active_vram_size(adev, 
adev->mc.real_vram_size);
 
-   if (amdgpu_sriov_vf(adev)) {
-   wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 
4);
-   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
-   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
-
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
-  lower_32_bits(wptr_gpu_addr));
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
-  upper_32_bits(wptr_gpu_addr));
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
-   }
}
 
return 0;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/9 v2] ASoC: AMD: disabling memory gating in stoney platform

[Alex Deucher]

From: Vijendar Mukunda 

For Stoney platform, Memory gating is disabled.i.e SRAM Banks
won't be turned off. By Default, SRAM Bank state set to ON.
Added condition checks to skip SRAM Bank state set logic for
Stoney platform.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2: Added comments in code and removed locally defined macros
for STONEY and Carrizo.

sound/soc/amd/acp-pcm-dma.c | 79 +++--
 1 file changed, 55 insertions(+), 24 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index dcbf997..f00b6b9 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -20,7 +20,7 @@
 #include 
 
 #include 
-
+#include 
 #include "acp.h"
 
 #define PLAYBACK_MIN_NUM_PERIODS2
@@ -419,7 +419,7 @@ static void acp_set_sram_bank_state(void __iomem *acp_mmio, 
u16 bank,
 }
 
 /* Initialize and bring ACP hardware to default state. */
-static int acp_init(void __iomem *acp_mmio)
+static int acp_init(void __iomem *acp_mmio, u32 asic_type)
 {
u16 bank;
u32 val, count, sram_pte_offset;
@@ -493,9 +493,14 @@ static int acp_init(void __iomem *acp_mmio)
/* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
* Now, turn off all of them. This can't be done in 'poweron' of
* ACP pm domain, as this requires ACP to be initialized.
+   * For Stoney, Memory gating is disabled,i.e SRAM Banks
+   * won't be turned off. The default state for SRAM banks is ON.
+   * Setting SRAM bank state code skipped for STONEY platform.
*/
-   for (bank = 1; bank < 48; bank++)
-   acp_set_sram_bank_state(acp_mmio, bank, false);
+   if (asic_type != CHIP_STONEY) {
+   for (bank = 1; bank < 48; bank++)
+   acp_set_sram_bank_state(acp_mmio, bank, false);
+   }
 
return 0;
 }
@@ -646,14 +651,22 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
intr_data->play_stream = substream;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+*/
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
} else {
intr_data->capture_stream = substream;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(intr_data->acp_mmio, bank,
-   true);
+   if (intr_data->asic_type != CHIP_STONEY) {
+   for (bank = 5; bank <= 8; bank++)
+   acp_set_sram_bank_state(intr_data->acp_mmio,
+   bank, true);
+   }
}
 
return 0;
@@ -869,14 +882,23 @@ static int acp_dma_close(struct snd_pcm_substream 
*substream)
 
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
adata->play_stream = NULL;
-   for (bank = 1; bank <= 4; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
-   } else {
+   /* For Stoney, Memory gating is disabled,i.e SRAM Banks
+* won't be turned off. The default state for SRAM banks is ON.
+* Setting SRAM bank state code skipped for STONEY platform.
+* added condition checks for Carrizo platform only
+*/
+   if (adata->asic_type != CHIP_STONEY) {
+   for (bank = 1; bank <= 4; bank++)
+   acp_set_sram_bank_state(adata->acp_mmio, bank,
+   false);
+   }
+   } else  {
adata->capture_stream = NULL;
-   for (bank = 5; bank <= 8; bank++)
-   acp_set_sram_bank_state(adata->acp_mmio, bank,
-   false);
+   if (adata->asic_type != CHIP_STONEY) {
+   for (bank = 5; bank <= 8; bank++)
+   acp_set_sram_bank_state(adata->acp_mmio, bank,
+false);
+   }
}
 
/* Disable ACP irq, when the current stream is being 

[PATCH 6/9 v2] ASoC: AMD: DMA driver changes for Stoney Platform

[Alex Deucher]

From: Vijendar Mukunda 

Added DMA driver changes for Stoney platform.
Below are the key differences between Stoney and CZ

In Stoney, Memory Gating is disabled.SRAM Banks won't
be turned off.No Of SRAM Banks reduced to 6.
DAGB Garlic Interface used and 16 bit resolution is supported.
SRAM bank 1 & SRAM bank 2 will be used for playback scenario.
SRAM Bank 3 & SRAM Bank 4 will be used for Capture scenario.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2: Added switch cases for asic type.

sound/soc/amd/acp-pcm-dma.c | 87 +
 sound/soc/amd/acp.h |  2 ++
 2 files changed, 67 insertions(+), 22 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f00b6b9..f16e0b8 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -137,8 +137,8 @@ static void config_dma_descriptor_in_sram(void __iomem 
*acp_mmio,
  * system memory <-> ACP SRAM
  */
 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
-  u32 size, int direction,
-  u32 pte_offset)
+   u32 size, int direction,
+   u32 pte_offset, u32 asic_type)
 {
u16 i;
u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
@@ -152,20 +152,42 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
(size / 2) - (i * (size/2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size/2));
-   dmadscr[i].xfer_val |=
-   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM  
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].xfer_val |=
+   (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM  << 
16) |
+   (size / 2);
+   }
} else {
dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
-   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
-   (i * (size/2));
-   dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
-   + (pte_offset * SZ_4K) +
-   (i * (size/2));
-   dmadscr[i].xfer_val |=
-   BIT(22) |
-   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
-   (size / 2);
+   switch (asic_type) {
+   case CHIP_STONEY:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC 
<< 16) |
+   (size / 2);
+   break;
+   default:
+   dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
+   (i * (size/2));
+   dmadscr[i].dest =
+   ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+   (pte_offset * SZ_4K) + (i * (size/2));
+   dmadscr[i].xfer_val |=
+   BIT(22) |
+   (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 
16) |
+   (size / 2);
+   }
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
[i]);
@@ -186,7 +208,8 @@ static void set_acp_sysmem_dma_descriptors(void __iomem 
*acp_mmio,
  * ACP SRAM <-> I2S
  */
 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
-  u32 size, int direction)
+   u32 size, int direction,
+   u32 asic_type)
 {
 
u16 i;
@@ -207,8 +230,17 @@ static void 

[PATCH 1/9] ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver

[Alex Deucher]

From: Vijendar Mukunda 

Added quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to Designware
driver. This quirk will set idx value to 1.

By setting this quirk, it will override supported format
as 16 bit resolution and bus width as 2 Bytes.

Reviewed-by: Alex Deucher 
Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

This patch is already applied to the audio tree, I'm just
including it here for completeness since it's not yet in
the drm tree.

include/sound/designware_i2s.h | 1 +
 sound/soc/dwc/dwc-i2s.c| 6 ++
 2 files changed, 7 insertions(+)

diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h
index 5681855..830f5ca 100644
--- a/include/sound/designware_i2s.h
+++ b/include/sound/designware_i2s.h
@@ -47,6 +47,7 @@ struct i2s_platform_data {
 
#define DW_I2S_QUIRK_COMP_REG_OFFSET(1 << 0)
#define DW_I2S_QUIRK_COMP_PARAM1(1 << 1)
+   #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
unsigned int quirks;
unsigned int i2s_reg_comp1;
unsigned int i2s_reg_comp2;
diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c
index 9c46e41..9160676 100644
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -496,6 +496,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
idx = COMP1_TX_WORDSIZE_0(comp1);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->playback.channels_max =
1 << (COMP1_TX_CHANNELS(comp1) + 1);
@@ -508,6 +510,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
idx = COMP2_RX_WORDSIZE_0(comp2);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->capture.channels_max =
1 << (COMP1_RX_CHANNELS(comp1) + 1);
@@ -543,6 +547,8 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
if (ret < 0)
return ret;
 
+   if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+   idx = 1;
/* Set DMA slaves info */
dev->play_dma_data.pd.data = pdata->play_dma_data;
dev->capture_dma_data.pd.data = pdata->capture_dma_data;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 7/9 v2] ASoC: AMD: Audio buffer related changes for Stoney

[Alex Deucher]

From: Vijendar Mukunda 

Stoney uses 16kb SRAM memory for playback and 16Kb
for capture.Modified Max buffer size to have the
correct mapping between System Memory and SRAM.

Added snd_pcm_hardware structures for playback
and capture for Stoney.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2: Added switch cases for asic type.

sound/soc/amd/acp-pcm-dma.c | 73 +
 1 file changed, 68 insertions(+), 5 deletions(-)

diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index f16e0b8..a6def3b 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -35,6 +35,10 @@
 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 #define MIN_BUFFER MAX_BUFFER
 
+#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
+#define ST_CAPTURE_MAX_PERIOD_SIZE  8192
+#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define ST_MIN_BUFFER ST_MAX_BUFFER
 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
@@ -73,6 +77,44 @@ static const struct snd_pcm_hardware 
acp_pcm_hardware_capture = {
.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
+static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 8,
+   .rates = SNDRV_PCM_RATE_8000_96000,
+   .rate_min = 8000,
+   .rate_max = 96000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
+   .periods_min = PLAYBACK_MIN_NUM_PERIODS,
+   .periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
+   .info = SNDRV_PCM_INFO_INTERLEAVED |
+   SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
+   SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
+   SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+   .formats = SNDRV_PCM_FMTBIT_S16_LE |
+   SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
+   .channels_min = 1,
+   .channels_max = 2,
+   .rates = SNDRV_PCM_RATE_8000_48000,
+   .rate_min = 8000,
+   .rate_max = 48000,
+   .buffer_bytes_max = ST_MAX_BUFFER,
+   .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+   .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
+   .periods_min = CAPTURE_MIN_NUM_PERIODS,
+   .periods_max = CAPTURE_MAX_NUM_PERIODS,
+};
+
 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 {
return readl(acp_mmio + (reg * 4));
@@ -664,10 +706,23 @@ static int acp_dma_open(struct snd_pcm_substream 
*substream)
if (adata == NULL)
return -ENOMEM;
 
-   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-   runtime->hw = acp_pcm_hardware_playback;
-   else
-   runtime->hw = acp_pcm_hardware_capture;
+   if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_playback;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_playback;
+   }
+   } else {
+   switch (intr_data->asic_type) {
+   case CHIP_STONEY:
+   runtime->hw = acp_st_pcm_hardware_capture;
+   break;
+   default:
+   runtime->hw = acp_pcm_hardware_capture;
+   }
+   }
 
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
@@ -905,7 +960,15 @@ static int acp_dma_trigger(struct snd_pcm_substream 
*substream, int cmd)
 
 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
 {
-   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+   struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev);
+
+   if (adata->asic_type == CHIP_STONEY)
+   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+   SNDRV_DMA_TYPE_DEV,
+   NULL, ST_MIN_BUFFER,
+   ST_MAX_BUFFER);
+   else
+   return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,

[PATCH 8/9 v2] drm/amd/amdgpu: Disabling Power Gating for Stoney platform

[Alex Deucher]

From: Vijendar Mukunda 

Power Gating is disabled in Stoney platform.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2: added missing changes required for power gating and
removed local variable.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 51 ++---
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 9c0bd6c..ebca223 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -285,19 +285,20 @@ static int acp_hw_init(void *handle)
return 0;
else if (r)
return r;
+   if (adev->asic_type != CHIP_STONEY) {
+   adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), 
GFP_KERNEL);
+   if (adev->acp.acp_genpd == NULL)
+   return -ENOMEM;
 
-   adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
-   if (adev->acp.acp_genpd == NULL)
-   return -ENOMEM;
-
-   adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
-   adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
-   adev->acp.acp_genpd->gpd.power_on = acp_poweron;
+   adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
+   adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
+   adev->acp.acp_genpd->gpd.power_on = acp_poweron;
 
 
-   adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
+   adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
 
-   pm_genpd_init(>acp.acp_genpd->gpd, NULL, false);
+   pm_genpd_init(>acp.acp_genpd->gpd, NULL, false);
+   }
 
adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
GFP_KERNEL);
@@ -390,12 +391,14 @@ static int acp_hw_init(void *handle)
if (r)
return r;
 
-   for (i = 0; i < ACP_DEVS ; i++) {
-   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-   r = pm_genpd_add_device(>acp.acp_genpd->gpd, dev);
-   if (r) {
-   dev_err(dev, "Failed to add dev to genpd\n");
-   return r;
+   if (adev->asic_type != CHIP_STONEY) {
+   for (i = 0; i < ACP_DEVS ; i++) {
+   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+   r = pm_genpd_add_device(>acp.acp_genpd->gpd, dev);
+   if (r) {
+   dev_err(dev, "Failed to add dev to genpd\n");
+   return r;
+   }
}
}
 
@@ -415,20 +418,22 @@ static int acp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
/* return early if no ACP */
-   if (!adev->acp.acp_genpd)
+   if (!adev->acp.acp_cell)
return 0;
 
-   for (i = 0; i < ACP_DEVS ; i++) {
-   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
-   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, dev);
-   /* If removal fails, dont giveup and try rest */
-   if (ret)
-   dev_err(dev, "remove dev from genpd failed\n");
+   if (adev->acp.acp_genpd) {
+   for (i = 0; i < ACP_DEVS ; i++) {
+   dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+   ret = pm_genpd_remove_device(>acp.acp_genpd->gpd, 
dev);
+   /* If removal fails, dont giveup and try rest */
+   if (ret)
+   dev_err(dev, "remove dev from genpd failed\n");
+   }
+   kfree(adev->acp.acp_genpd);
}
 
mfd_remove_devices(adev->acp.parent);
kfree(adev->acp.acp_res);
-   kfree(adev->acp.acp_genpd);
kfree(adev->acp.acp_cell);
 
return 0;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/9] drm/amdgpu Moving amdgpu asic types to a separate file

[Alex Deucher]

From: Akshu Agrawal 

Amdgpu asic types will be required for other drivers too.
Hence, its better to keep it in a separate include file.

Signed-off-by: Akshu Agrawal 
Signed-off-by: Alex Deucher 
---

New patch to share asic_type definitions between GPU and audio driver.

drivers/gpu/drm/amd/include/amd_shared.h | 29 ++
 include/drm/amd_asic_type.h  | 52 
 2 files changed, 54 insertions(+), 27 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 70e8c20..3a49fbd 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -23,34 +23,9 @@
 #ifndef __AMD_SHARED_H__
 #define __AMD_SHARED_H__
 
-#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
+#include 
 
-/*
- * Supported ASIC types
- */
-enum amd_asic_type {
-   CHIP_TAHITI = 0,
-   CHIP_PITCAIRN,
-   CHIP_VERDE,
-   CHIP_OLAND,
-   CHIP_HAINAN,
-   CHIP_BONAIRE,
-   CHIP_KAVERI,
-   CHIP_KABINI,
-   CHIP_HAWAII,
-   CHIP_MULLINS,
-   CHIP_TOPAZ,
-   CHIP_TONGA,
-   CHIP_FIJI,
-   CHIP_CARRIZO,
-   CHIP_STONEY,
-   CHIP_POLARIS10,
-   CHIP_POLARIS11,
-   CHIP_POLARIS12,
-   CHIP_VEGA10,
-   CHIP_RAVEN,
-   CHIP_LAST,
-};
+#define AMD_MAX_USEC_TIMEOUT   20  /* 200 ms */
 
 /*
  * Chip flags
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
new file mode 100644
index 000..599028f
--- /dev/null
+++ b/include/drm/amd_asic_type.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_ASIC_TYPE_H__
+#define __AMD_ASIC_TYPE_H__
+/*
+ * Supported ASIC types
+ */
+enum amd_asic_type {
+   CHIP_TAHITI = 0,
+   CHIP_PITCAIRN,
+   CHIP_VERDE,
+   CHIP_OLAND,
+   CHIP_HAINAN,
+   CHIP_BONAIRE,
+   CHIP_KAVERI,
+   CHIP_KABINI,
+   CHIP_HAWAII,
+   CHIP_MULLINS,
+   CHIP_TOPAZ,
+   CHIP_TONGA,
+   CHIP_FIJI,
+   CHIP_CARRIZO,
+   CHIP_STONEY,
+   CHIP_POLARIS10,
+   CHIP_POLARIS11,
+   CHIP_POLARIS12,
+   CHIP_VEGA10,
+   CHIP_RAVEN,
+   CHIP_LAST,
+};
+
+#endif /*__AMD_ASIC_TYPE_H__ */
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/9 v2] drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data

[Alex Deucher]

From: Vijendar Mukunda 

asic_type information is passed to ACP DMA Driver as platform data.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2:Removed asic_type local variable and directly passing asic_type
instance to ACP DMA driver as platform data.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 ++
 sound/soc/amd/acp-pcm-dma.c | 8 ++--
 sound/soc/amd/acp.h | 7 +++
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 06879d1..0fa8122 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -355,6 +355,8 @@ static int acp_hw_init(void *handle)
adev->acp.acp_cell[0].name = "acp_audio_dma";
adev->acp.acp_cell[0].num_resources = 4;
adev->acp.acp_cell[0].resources = >acp.acp_res[0];
+   adev->acp.acp_cell[0].platform_data = >asic_type;
+   adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
 
adev->acp.acp_cell[1].name = "designware-i2s";
adev->acp.acp_cell[1].num_resources = 1;
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 08b1399..dcbf997 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -73,12 +73,6 @@ static const struct snd_pcm_hardware 
acp_pcm_hardware_capture = {
.periods_max = CAPTURE_MAX_NUM_PERIODS,
 };
 
-struct audio_drv_data {
-   struct snd_pcm_substream *play_stream;
-   struct snd_pcm_substream *capture_stream;
-   void __iomem *acp_mmio;
-};
-
 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 {
return readl(acp_mmio + (reg * 4));
@@ -916,6 +910,7 @@ static int acp_audio_probe(struct platform_device *pdev)
int status;
struct audio_drv_data *audio_drv_data;
struct resource *res;
+   const u32 *pdata = pdev->dev.platform_data;
 
audio_drv_data = devm_kzalloc(>dev, sizeof(struct audio_drv_data),
GFP_KERNEL);
@@ -932,6 +927,7 @@ static int acp_audio_probe(struct platform_device *pdev)
 
audio_drv_data->play_stream = NULL;
audio_drv_data->capture_stream = NULL;
+   audio_drv_data->asic_type =  *pdata;
 
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h
index 330832e..28cf914 100644
--- a/sound/soc/amd/acp.h
+++ b/sound/soc/amd/acp.h
@@ -84,6 +84,13 @@ struct audio_substream_data {
void __iomem *acp_mmio;
 };
 
+struct audio_drv_data {
+   struct snd_pcm_substream *play_stream;
+   struct snd_pcm_substream *capture_stream;
+   void __iomem *acp_mmio;
+   u32 asic_type;
+};
+
 enum {
ACP_TILE_P1 = 0,
ACP_TILE_P2,
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/9 v2] drm/amd/amdgpu: Added a quirk for Stoney platform

[Alex Deucher]

From: Vijendar Mukunda 

Added DW_I2S_QUIRK_16BIT_IDX_OVERRIDE quirk for Stoney.

Supported format and bus width for I2S controller read
from I2S Component Parameter registers.
These are ready only registers.

For Stoney, I2S Component Parameter registers are programmed
to support 32 bit format and 4 bytes bus width only.

By setting this quirk,It will override 32 bit format with
16 bit format and 2 bytes as bus width for Stoney.

Signed-off-by: Vijendar Mukunda 
Signed-off-by: Alex Deucher 
---

v2: added switch cases for handling asic types.

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 0fa8122..9c0bd6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -319,14 +319,29 @@ static int acp_hw_init(void *handle)
return -ENOMEM;
}
 
-   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+   switch (adev->asic_type) {
+   case CHIP_STONEY:
+   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+   break;
+   default:
+   i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
+   }
i2s_pdata[0].cap = DWC_I2S_PLAY;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
+   switch (adev->asic_type) {
+   case CHIP_STONEY:
+   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_COMP_PARAM1 |
+   DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+   break;
+   default:
+   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+   DW_I2S_QUIRK_COMP_PARAM1;
+   }
 
-   i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-   DW_I2S_QUIRK_COMP_PARAM1;
i2s_pdata[1].cap = DWC_I2S_RECORD;
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/9 v2] Add ASoC support for AMD Stoney APUs

[Alex Deucher]

This patch set updates the AMD GPU and Audio CoProcessor (ACP)
audio drivers and the designware i2s driver for Stoney (ST).
ST is an APU similar to Carrizo (CZ) which already has ACP audio
support.  The i2s controller and ACP audio DMA engine are part of
the GPU and both need updating so I would like to upstream the
whole patch set via one tree if possible.

The current code is based on drm-next, but I'm happy to rebase on
whatever tree this ends up going through if there are any problems
applying.  The entire patch set can be viewed here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=stoney_acp

Thanks!

Alex

v2:
- Patch 1 is already applied to the audio tree, just including it for
  completeness since it's required for this patch set and it's not yet
  in the drm tree.
- New patch to share asic types between gpu and audio drivers
- ACPI ID changed for rt5650 machine driver
- Integrate feedback on other patches

Akshu Agrawal (2):
  drm/amdgpu Moving amdgpu asic types to a separate file
  ASoC: AMD: Add machine driver for cz rt5650

Vijendar Mukunda (7):
  ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver
  drm/amd/amdgpu: Added asic_type as ACP DMA driver platform data
  drm/amd/amdgpu: Added a quirk for Stoney platform
  ASoC: AMD: disabling memory gating in stoney platform
  ASoC: AMD: DMA driver changes for Stoney Platform
  ASoC: AMD: Audio buffer related changes for Stoney
  drm/amd/amdgpu: Disabling Power Gating for Stoney platform

 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c  |  74 ++
 drivers/gpu/drm/amd/include/amd_shared.h |  29 +---
 include/drm/amd_asic_type.h  |  52 +++
 include/sound/designware_i2s.h   |   1 +
 sound/soc/amd/Kconfig|   7 +
 sound/soc/amd/Makefile   |   2 +
 sound/soc/amd/acp-pcm-dma.c  | 243 ---
 sound/soc/amd/acp-rt5645.c   | 210 ++
 sound/soc/amd/acp.h  |   9 ++
 sound/soc/dwc/dwc-i2s.c  |   6 +
 10 files changed, 525 insertions(+), 108 deletions(-)
 create mode 100644 include/drm/amd_asic_type.h
 create mode 100644 sound/soc/amd/acp-rt5645.c

-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Christian König]

Am 28.07.2017 um 18:15 schrieb Alex Deucher:

May waste a bit of memory, but simplifies the interface
significantly.

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 65 --
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  8 ++--
  4 files changed, 20 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ed1b688..c880851 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1190,10 +1190,6 @@ struct amdgpu_wb {
  
  int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);

  void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb);
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
  
  void amdgpu_get_pcie_info(struct amdgpu_device *adev);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index c2ddeb1..d422277 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -570,41 +570,6 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
   */
  int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
  {
-   unsigned long offset = find_first_zero_bit(adev->wb.used, 
adev->wb.num_wb);
-   if (offset < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-/**
- * amdgpu_wb_get_64bit - Allocate a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Allocate a wb slot for use by the driver (all asics).
- * Returns 0 on success or -EINVAL on failure.
- */
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
-{
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 2, 7, 0);
-   if ((offset + 1) < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   __set_bit(offset + 1, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb)
-{
int i = 0;
unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
adev->wb.num_wb, 0, 8, 63, 0);


Could be simplified to find_first_zero_bit() as well and then just 
multiply the resulting offset by 16.


Either way the patch looks good to me and is Reviewed-by: Christian 
König .


Regards,
Christian.


@@ -628,36 +593,6 @@ int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 
*wb)
   */
  void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
  {
-   if (wb < adev->wb.num_wb)
-   __clear_bit(wb, adev->wb.used);
-}
-
-/**
- * amdgpu_wb_free_64bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
-{
-   if ((wb + 1) < adev->wb.num_wb) {
-   __clear_bit(wb, adev->wb.used);
-   __clear_bit(wb + 1, adev->wb.used);
-   }
-}
-
-/**
- * amdgpu_wb_free_256bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb)
-{
int i = 0;
  
  	if ((wb + 7) < adev->wb.num_wb)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 3874be8..704475674 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -184,47 +184,22 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
return r;
}
  
-	if (ring->funcs->support_64bit_ptrs) {

-   r = amdgpu_wb_get_64bit(adev, >rptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring rptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
-   r = amdgpu_wb_get_64bit(adev, >wptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring wptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
-   } else {
-   r = amdgpu_wb_get(adev, >rptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring rptr_offs wb alloc 
failed\n", r);

[PATCH umr] Improve and fix VM decoding

[Tom St Denis]

We now filter the output nicely to not repeat PDE entries
unncessarily.  The VA mask was also fixed for AI platforms.

Signed-off-by: Tom St Denis 
---
 src/app/main.c  |   6 +--
 src/lib/read_vram.c | 128 +++-
 2 files changed, 77 insertions(+), 57 deletions(-)

diff --git a/src/app/main.c b/src/app/main.c
index 006727ba7981..920f6815e220 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -374,11 +374,7 @@ int main(int argc, char **argv)
if (options.hub_name[0])
vmid |= UMR_USER_HUB;
 
-   while (size--) {
-   if (umr_read_vram(asic, vmid, address, 
0, NULL))
-   break;
-   address += 0x1000;
-   }
+   umr_read_vram(asic, vmid, address, 0x1000UL * 
size, NULL);
i += 2;
 
asic->options.verbose = overbose;
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index 91d4e7659704..685617424e53 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -91,7 +91,7 @@ static int umr_read_vram_vi(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
frag_size,
pte_base_addr,
valid;
-   } pde_fields;
+   } pde_fields, pde_copy;
struct {
uint64_t
page_base_addr,
@@ -110,6 +110,7 @@ static int umr_read_vram_vi(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
unsigned char *pdst = dst;
 
memset(, 0, sizeof registers);
+   memset(_copy, 0, sizeof pde_copy);
 
/*
 * PTE format on VI:
@@ -186,12 +187,13 @@ static int umr_read_vram_vi(struct umr_asic *asic, 
uint32_t vmid, uint64_t addre
pde_fields.frag_size = (pde_entry >> 59) & 0x1F;
pde_fields.pte_base_addr = pde_entry & 0xFFF000ULL;
pde_fields.valid = pde_entry & 1;
-   if (asic->options.verbose)
+   if (memcmp(_copy, _fields, sizeof pde_fields) 
&& asic->options.verbose)
fprintf(stderr, "[VERBOSE]: PDE=0x%016llx, 
VA=0x%010llx, PBA==0x%010llx, V=%d\n",
(unsigned long long)pde_entry,
(unsigned long long)address & 
pde_mask,
(unsigned long 
long)pde_fields.pte_base_addr,
(int)pde_fields.valid);
+   memcpy(_copy, _fields, sizeof pde_fields);
 
if (!pde_fields.valid)
return -1;
@@ -206,7 +208,7 @@ static int umr_read_vram_vi(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
pte_fields.system = (pte_entry >> 1) & 1;
pte_fields.valid  = pte_entry & 1;
if (asic->options.verbose)
-   fprintf(stderr, "[VERBOSE]: PTE=0x%016llx, 
VA=0x%010llx, PBA==0x%010llx, V=%d, S=%d\n",
+   fprintf(stderr, "[VERBOSE]: \\-> PTE=0x%016llx, 
VA=0x%010llx, PBA==0x%010llx, V=%d, S=%d\n",
(unsigned long long)pte_entry,
(unsigned long long)address & pte_mask,
(unsigned long 
long)pte_fields.page_base_addr,
@@ -252,19 +254,23 @@ static int umr_read_vram_vi(struct umr_asic *asic, 
uint32_t vmid, uint64_t addre
chunk_size = size;
}
DEBUG("Computed address we will read from: %s:%llx (reading: 
%lu bytes)\n", pte_fields.system ? "sys" : "vram", (unsigned long 
long)start_addr, (unsigned long)chunk_size);
-   if (pte_fields.system) {
-   if (umr_read_sram(start_addr, chunk_size, pdst) < 0) {
-   fprintf(stderr, "[ERROR]: Cannot read system 
ram, perhaps CONFIG_STRICT_DEVMEM is set in your kernel config?\n");
-   fprintf(stderr, "[ERROR]: Alternatively 
download and install /dev/fmem\n");
-   return -1;
-   }
-   } else {
-   if (umr_read_vram(asic, UMR_LINEAR_HUB, start_addr, 
chunk_size, pdst) < 0) {
-   fprintf(stderr, "[ERROR]: Cannot read from 
VRAM\n");
-   return -1;
+
+   // allow destination to be NULL to simply use decoder
+   if (pdst) {
+   if (pte_fields.system) {
+   if 

Re: [PATCH] drm/amd/powerplay: rv: Use designated initializers

[Kees Cook]

On Thu, Jul 27, 2017 at 6:43 PM, Alex Deucher  wrote:
> On Tue, Jul 25, 2017 at 5:47 PM, Kees Cook  wrote:
>> As done for vega10 in commit 3ddd396f6b57 ("drm/amd/powerplay: Use
>> designated initializers") mark other tableFunction entries with designated
>> initializers. The randstruct plugin requires designated initializers for
>> structures that are entirely function pointers.
>>
>> Cc: Rex Zhu 
>> Cc: Hawking Zhang 
>> Cc: Alex Deucher 
>> Signed-off-by: Kees Cook 
>> ---
>> If I can get an Ack for this, I'll carry it in the gcc-plugins tree, unless
>> you think this is worth landing for v4.13, in which case, please take it
>> now. :)
>>
>
> Acked-by: Alex Deucher 
>
> I'm happy to take this through my tree if that is ok with you.

Since the randstruct patch depends on this fix, it's likely best to go
through my tree unless you can get this into v4.13. (Since then when
the randstruct patch lands in v4.14, it'll already be there.) I'm fine
either way.

Thanks!

-Kees

-- 
Kees Cook
Pixel Security
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: rv: Use designated initializers

[Kees Cook]

On Fri, Jul 28, 2017 at 2:13 AM, Christian König
 wrote:
> Am 28.07.2017 um 03:43 schrieb Alex Deucher:
>>
>> On Tue, Jul 25, 2017 at 5:47 PM, Kees Cook  wrote:
>>>
>>> As done for vega10 in commit 3ddd396f6b57 ("drm/amd/powerplay: Use
>>> designated initializers") mark other tableFunction entries with
>>> designated
>>> initializers. The randstruct plugin requires designated initializers for
>>> structures that are entirely function pointers.
>>>
>>> Cc: Rex Zhu 
>>> Cc: Hawking Zhang 
>>> Cc: Alex Deucher 
>>> Signed-off-by: Kees Cook 
>>> ---
>>> If I can get an Ack for this, I'll carry it in the gcc-plugins tree,
>>> unless
>>> you think this is worth landing for v4.13, in which case, please take it
>>> now. :)
>>>
>> Acked-by: Alex Deucher 
>>
>> I'm happy to take this through my tree if that is ok with you.
>
>
> I'm wondering a bit how the plugin detects that it can randomize a structure
> layout?
>
> We have a couple of structs where this would be fatal.

Automatic randomization only happen on struct that are entirely
function pointers.

See:
https://git.kernel.org/linus/313dd1b629219db50cad532dba6a3b3b22ffe622

And:
https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git/commit/?id=914e2dfc61195a95868ae5c750690a7f1c87bc66

If you have any structures that are shared externally from the kernel,
I can mark them with __no_randomize_layout.

-Kees

-- 
Kees Cook
Pixel Security
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/powerplay: rv: Use designated initializers

[Deucher, Alexander]

> -Original Message-
> From: keesc...@google.com [mailto:keesc...@google.com] On Behalf Of
> Kees Cook
> Sent: Friday, July 28, 2017 1:16 PM
> To: Alex Deucher
> Cc: LKML; David Airlie; amd-gfx list; Maling list - DRI developers; Deucher,
> Alexander; Zhu, Rex; Koenig, Christian; Zhang, Hawking
> Subject: Re: [PATCH] drm/amd/powerplay: rv: Use designated initializers
> 
> On Thu, Jul 27, 2017 at 6:43 PM, Alex Deucher 
> wrote:
> > On Tue, Jul 25, 2017 at 5:47 PM, Kees Cook 
> wrote:
> >> As done for vega10 in commit 3ddd396f6b57 ("drm/amd/powerplay: Use
> >> designated initializers") mark other tableFunction entries with designated
> >> initializers. The randstruct plugin requires designated initializers for
> >> structures that are entirely function pointers.
> >>
> >> Cc: Rex Zhu 
> >> Cc: Hawking Zhang 
> >> Cc: Alex Deucher 
> >> Signed-off-by: Kees Cook 
> >> ---
> >> If I can get an Ack for this, I'll carry it in the gcc-plugins tree, unless
> >> you think this is worth landing for v4.13, in which case, please take it
> >> now. :)
> >>
> >
> > Acked-by: Alex Deucher 
> >
> > I'm happy to take this through my tree if that is ok with you.
> 
> Since the randstruct patch depends on this fix, it's likely best to go
> through my tree unless you can get this into v4.13. (Since then when
> the randstruct patch lands in v4.14, it'll already be there.) I'm fine
> either way.

Go ahead and take it through your tree.  Thanks!

Alex

> 
> Thanks!
> 
> -Kees
> 
> --
> Kees Cook
> Pixel Security
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amd/powerplay: update didt configs

[Alex Deucher]

On Fri, Jul 28, 2017 at 5:59 AM, Huang Rui  wrote:
> On Fri, Jul 28, 2017 at 04:01:01PM +0800, Evan Quan wrote:
>> Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
>> Signed-off-by: Evan Quan 
>
> Reviewed-by: Huang Rui 

Reviewed-by: Alex Deucher 

>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> index fbafc84..e7fa670 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> @@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
>> SEEDCCtrlForceStallConfig_Vega10[] =
>>   * 
>> -
>>   */
>>   /* SQ */
>> - {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
>> 0x0001 },
>> + {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
>> 0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
>> DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
>> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
>> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
>> @@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
>> SEEDCCtrlForceStallConfig_Vega10[] =
>>   {   ixDIDT_SQ_EDC_CTRL,
>> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
>> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
>>
>>   /* TD */
>> - {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
>> 0x0001 },
>> + {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,  
>>  DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
>> 0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
>> DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
>> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>>   {   ixDIDT_TD_EDC_CTRL,
>> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
>> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
>> @@ -1208,7 +1208,7 @@ static int 
>> vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
>>   if (0 != result)
>>   return result;
>>
>> - vega10_didt_set_mask(hwmgr, true);
>> + vega10_didt_set_mask(hwmgr, false);
>>
>>   cgs_enter_safe_mode(hwmgr->device, false);
>>
>> --
>> 2.7.4
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control

[Alex Deucher]

On Fri, Jul 28, 2017 at 4:47 AM, Quan, Evan  wrote:
> Oops, the changes were made by a remote windows editor which added the 
> executable bit wrongly.
> Thanks for the remind. Will pay attention to it.

With the mode fixed, the patch is:
Reviewed-by: Alex Deucher 

>
> Regards,
> Evan
>>-Original Message-
>>From: Michel Dänzer [mailto:mic...@daenzer.net]
>>Sent: Friday, July 28, 2017 4:38 PM
>>To: Quan, Evan 
>>Cc: amd-gfx@lists.freedesktop.org
>>Subject: Re: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control
>>
>>On 28/07/17 05:00 PM, Evan Quan wrote:
>>> Change-Id: Ifbeb1f0c8e195cc9cb1e9cff975284d96d49b193
>>> Signed-off-by: Evan Quan 
>>> ---
>>>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +-
>>>  1 file changed, 1 insertion(+), 5 deletions(-)
>>>  mode change 100644 => 100755
>>drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>>
>>Please fix your setup not to set executable bits for source code files.
>>
>>
>>--
>>Earthling Michel Dänzer   |   http://www.amd.com
>>Libre software enthusiast | Mesa and X developer
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: add vclk/dclkSoftMin support for raven

[Alex Deucher]

On Fri, Jul 28, 2017 at 5:28 AM, Junwei Zhang  wrote:
> Signed-off-by: Junwei Zhang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 9 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 2 ++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
>  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h   | 7 ++-
>  4 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index f61da66..14e0321 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -279,6 +279,15 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, 
> void *input,
> }
> } */
>
> +   if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != 
> rv_data->vclk_soft_min) ||
> +   ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != 
> rv_data->dclk_soft_min)) {
> +   rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 
> 100;
> +   rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 
> 100;
> +   smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> +   PPSMC_MSG_SetSoftMinVcn,
> +   (rv_data->vclk_soft_min << 16) | 
> rv_data->vclk_soft_min);
> +   }
> +
> if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
> ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != 
> rv_data->soc_actual_hard_min_freq)) {
> smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> index afb8522..2472b50 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> @@ -280,6 +280,8 @@ struct rv_hwmgr {
>
> uint32_tf_actual_hard_min_freq;
> uint32_tfabric_actual_soft_min_freq;
> +   uint32_tvclk_soft_min;
> +   uint32_tdclk_soft_min;
> uint32_tgfx_actual_soft_min_freq;
>
> bool   vcn_power_gated;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 3a0e6b1..f539d55 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -128,6 +128,8 @@ struct phm_uvd_arbiter {
> uint32_t dclk;
> uint32_t vclk_ceiling;
> uint32_t dclk_ceiling;
> +   uint32_t vclk_soft_min;
> +   uint32_t dclk_soft_min;
>  };
>
>  struct phm_vce_arbiter {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h 
> b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index e0e106f..901c960c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -66,7 +66,12 @@
>  #define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
>  #define PPSMC_MSG_SetMinVideoFclkFreq   0x23
>  #define PPSMC_MSG_SetMinDeepSleepDcefclk0x24
> -#define PPSMC_Message_Count 0x25
> +#define PPSMC_MSG_ForcePowerDownGfx 0x25
> +#define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
> +#define PPSMC_MSG_SetDppclkVoltageByFreq0x27
> +#define PPSMC_MSG_SetSoftMinVcn 0x28
> +#define PPSMC_Message_Count 0x29
> +
>
>  typedef uint16_t PPSMC_Result;
>  typedef int  PPSMC_Msg;
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: use 256 bit buffers for all wb allocations

[Alex Deucher]

May waste a bit of memory, but simplifies the interface
significantly.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 65 --
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  8 ++--
 4 files changed, 20 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ed1b688..c880851 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1190,10 +1190,6 @@ struct amdgpu_wb {
 
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb);
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c2ddeb1..d422277 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -570,41 +570,6 @@ static int amdgpu_wb_init(struct amdgpu_device *adev)
  */
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 {
-   unsigned long offset = find_first_zero_bit(adev->wb.used, 
adev->wb.num_wb);
-   if (offset < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-/**
- * amdgpu_wb_get_64bit - Allocate a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Allocate a wb slot for use by the driver (all asics).
- * Returns 0 on success or -EINVAL on failure.
- */
-int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
-{
-   unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
-   adev->wb.num_wb, 0, 2, 7, 0);
-   if ((offset + 1) < adev->wb.num_wb) {
-   __set_bit(offset, adev->wb.used);
-   __set_bit(offset + 1, adev->wb.used);
-   *wb = offset;
-   return 0;
-   } else {
-   return -EINVAL;
-   }
-}
-
-int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb)
-{
int i = 0;
unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
adev->wb.num_wb, 0, 8, 63, 0);
@@ -628,36 +593,6 @@ int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 
*wb)
  */
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 {
-   if (wb < adev->wb.num_wb)
-   __clear_bit(wb, adev->wb.used);
-}
-
-/**
- * amdgpu_wb_free_64bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
-{
-   if ((wb + 1) < adev->wb.num_wb) {
-   __clear_bit(wb, adev->wb.used);
-   __clear_bit(wb + 1, adev->wb.used);
-   }
-}
-
-/**
- * amdgpu_wb_free_256bit - Free a wb entry
- *
- * @adev: amdgpu_device pointer
- * @wb: wb index
- *
- * Free a wb slot allocated for use by the driver (all asics)
- */
-void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb)
-{
int i = 0;
 
if ((wb + 7) < adev->wb.num_wb)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 3874be8..704475674 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -184,47 +184,22 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
return r;
}
 
-   if (ring->funcs->support_64bit_ptrs) {
-   r = amdgpu_wb_get_64bit(adev, >rptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring rptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
-   r = amdgpu_wb_get_64bit(adev, >wptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring wptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
-   } else {
-   r = amdgpu_wb_get(adev, >rptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring rptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
-   r = amdgpu_wb_get(adev, >wptr_offs);
-   if (r) {
-   dev_err(adev->dev, "(%d) ring wptr_offs wb alloc 
failed\n", r);
-   return r;
-   }
-
+   r = 

Re: [PATCH 1/2] drm/amdgpu: Add a parameter to amdgpu_bo_create()

[Yong Zhao]

Got it.


On 2017-07-28 05:01 AM, Christian König wrote:

Am 27.07.2017 um 21:48 schrieb Yong Zhao:

The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.

Change-Id: I9ef3b9dd3ca9b98cc25dd2eaff68fbe1129c3e3c
Signed-off-by: Yong Zhao 


I'm about to push a cleanup which removes a bunch of references to 
amdgpu_bo_create(), so don't be surprised when you need to rebase your 
patch once more before pushing.


The patch is Reviewed-by: Christian König  
and that rebase should only require you to remove changes, so feel 
free to push it after the rebase.


Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 12 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_test.c  |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  4 ++--
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  4 ++--
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 10 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  6 +++---
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  4 ++--
  20 files changed, 43 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

index 2292c77..6d2bd80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -185,7 +185,8 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
  return -ENOMEM;
r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, 
AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 
&(*mem)->bo);

+ AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0,
+ &(*mem)->bo);
  if (r) {
  dev_err(adev->dev,
  "failed to allocate BO for amdkfd (%d)\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c

index 2fb299a..63ec1e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -81,7 +81,7 @@ static void amdgpu_benchmark_move(struct 
amdgpu_device *adev, unsigned size,

n = AMDGPU_BENCHMARK_ITERATIONS;
  r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, 
NULL,

- NULL, );
+ NULL, 0, );
  if (r) {
  goto out_cleanup;
  }
@@ -94,7 +94,7 @@ static void amdgpu_benchmark_move(struct 
amdgpu_device *adev, unsigned size,

  goto out_cleanup;
  }
  r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, 
NULL,

- NULL, );
+ NULL, 0, );
  if (r) {
  goto out_cleanup;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

index 3d41cd4..343cdf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -124,7 +124,7 @@ static int amdgpu_cgs_alloc_gpu_mem(struct 
cgs_device *cgs_device,

  ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
true, domain, flags,
NULL, , NULL,
-  );
+  0, );
  if (ret) {
  DRM_ERROR("(%d) bo create failed\n", ret);
  return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index fe6783e..cf81f9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -344,7 +344,7 @@ static int amdgpu_vram_scratch_init(struct 
amdgpu_device *adev)

   PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
- NULL, NULL, >vram_scratch.robj);
+ NULL, NULL, 0, >vram_scratch.robj);
  if (r) {
  return r;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

index 124b237..8cd79dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -141,7 +141,7 @@ int 

[PATCH umr] Support user named VM hubs

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/app/main.c  | 18 ++
 src/lib/read_vram.c | 22 +-
 src/umr.h   |  7 +--
 3 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/src/app/main.c b/src/app/main.c
index 0b46643400ba..006727ba7981 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -341,6 +341,14 @@ int main(int argc, char **argv)
} else if (!strcmp(argv[i], "--enumerate") || !strcmp(argv[i], 
"-e")) {
umr_enumerate_devices();
return 0;
+   } else if (!strcmp(argv[i], "-mm")) {
+   if (i + 1 < argc) {
+   strcpy(options.hub_name, argv[i+1]);
+   ++i;
+   } else {
+   printf("-mm requires on parameter");
+   return EXIT_FAILURE;
+   }
} else if (!strcmp(argv[i], "--vm-decode") || !strcmp(argv[i], 
"-vm")) {
if (i + 2 < argc) {
uint64_t address;
@@ -361,6 +369,11 @@ int main(int argc, char **argv)
exit(EXIT_FAILURE);
}
sscanf(argv[i+2], "%"SCNx32, );
+
+   // imply user hub if hub name specified
+   if (options.hub_name[0])
+   vmid |= UMR_USER_HUB;
+
while (size--) {
if (umr_read_vram(asic, vmid, address, 
0, NULL))
break;
@@ -389,6 +402,11 @@ int main(int argc, char **argv)
sscanf(argv[i+1], "%"SCNx64, 
);
vmid = UMR_LINEAR_HUB;
}
+
+   // imply user hub if hub name specified
+   if (options.hub_name[0])
+   vmid |= UMR_USER_HUB;
+
sscanf(argv[i+2], "%"SCNx32, );
do {
n = size > sizeof(buf) ? sizeof(buf) : 
size;
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index b58400f1f4ca..91d4e7659704 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -309,6 +309,7 @@ static int umr_read_vram_ai(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
char buf[64];
unsigned char *pdst = dst;
char *hub;
+   unsigned hubid;
 
memset(, 0, sizeof registers);
 
@@ -333,13 +334,24 @@ static int umr_read_vram_ai(struct umr_asic *asic, 
uint32_t vmid, uint64_t addre
 * 0 valid
 */
 
-   if ((vmid & 0xFF00) == UMR_MM_HUB)
-   hub = "mmhub";
-   else
-   hub = "gfx";
-
+   hubid = vmid & 0xFF00;
vmid &= 0xFF;
 
+   switch (hubid) {
+   case UMR_MM_HUB:
+   hub = "mmhub";
+   break;
+   case UMR_GFX_HUB:
+   hub = "gfx";
+   break;
+   case UMR_USER_HUB:
+   hub = asic->options.hub_name;
+   break;
+   default:
+   fprintf(stderr, "[ERROR]: Invalid hub specified in 
umr_read_vram_ai()\n");
+   return -1;
+   }
+
// read vm registers
sprintf(buf, "mmVM_CONTEXT%d_PAGE_TABLE_START_ADDR_LO32", (int)vmid);
registers.mmVM_CONTEXTx_PAGE_TABLE_START_ADDR_LO32 = 
umr_read_reg_by_name_by_ip(asic, hub, buf);
diff --git a/src/umr.h b/src/umr.h
index dd7f80c38f0c..3cc7994fc8ad 100644
--- a/src/umr.h
+++ b/src/umr.h
@@ -44,6 +44,7 @@ enum umr_hub_space {
UMR_GFX_HUB = 0 << 8,// default on everything before AI
UMR_MM_HUB = 1 << 8, // available on AI and later
 
+   UMR_USER_HUB = 0xFE << 8,// for user supplied HUB names (npi 
work...)
UMR_LINEAR_HUB = 0xFF << 8,  // this is for linear access to vram
 };
 
@@ -196,8 +197,10 @@ struct umr_options {
se_bank,
sh_bank;
long forcedid;
-   char *scanblock;
-   char dev_name[32];
+   char
+   *scanblock,
+   dev_name[32],
+   hub_name[32];
struct {
int domain,
bus,
-- 
2.12.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amd/powerplay: update didt configs

[Huang Rui]

On Fri, Jul 28, 2017 at 04:01:01PM +0800, Evan Quan wrote:
> Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
> Signed-off-by: Evan Quan 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> index fbafc84..e7fa670 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> @@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
> SEEDCCtrlForceStallConfig_Vega10[] =
>   * 
> -
>   */
>   /* SQ */
> - {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
> 0x0001 },
> + {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
> 0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
> DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
> DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
> DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
> @@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
> SEEDCCtrlForceStallConfig_Vega10[] =
>   {   ixDIDT_SQ_EDC_CTRL,
> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
> DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
>  
>   /* TD */
> - {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
> DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
> 0x0001 },
> + {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
> DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
> 0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
> DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
> DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
>   {   ixDIDT_TD_EDC_CTRL,
> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
> DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
> @@ -1208,7 +1208,7 @@ static int 
> vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
>   if (0 != result)
>   return result;
>  
> - vega10_didt_set_mask(hwmgr, true);
> + vega10_didt_set_mask(hwmgr, false);
>  
>   cgs_enter_safe_mode(hwmgr->device, false);
>  
> -- 
> 2.7.4
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amd/powerplay: update didt configs

[Evan Quan]

Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index fbafc84..e7fa670 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
  * 
-
  */
/* SQ */
-   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
 
/* TD */
-   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -1208,7 +1208,7 @@ static int vega10_enable_se_edc_force_stall_config(struct 
pp_hwmgr *hwmgr)
if (0 != result)
return result;
 
-   vega10_didt_set_mask(hwmgr, true);
+   vega10_didt_set_mask(hwmgr, false);
 
cgs_enter_safe_mode(hwmgr->device, false);
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/powerplay: add vclk/dclkSoftMin support for raven

[Junwei Zhang]

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 9 +
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 2 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 2 ++
 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h   | 7 ++-
 4 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index f61da66..14e0321 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -279,6 +279,15 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, 
void *input,
}
} */
 
+   if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != 
rv_data->vclk_soft_min) ||
+   ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != 
rv_data->dclk_soft_min)) {
+   rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
+   rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
+   smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+   PPSMC_MSG_SetSoftMinVcn,
+   (rv_data->vclk_soft_min << 16) | 
rv_data->vclk_soft_min);
+   }
+
if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
((hwmgr->gfx_arbiter.sclk_hard_min / 100) != 
rv_data->soc_actual_hard_min_freq)) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index afb8522..2472b50 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -280,6 +280,8 @@ struct rv_hwmgr {
 
uint32_tf_actual_hard_min_freq;
uint32_tfabric_actual_soft_min_freq;
+   uint32_tvclk_soft_min;
+   uint32_tdclk_soft_min;
uint32_tgfx_actual_soft_min_freq;
 
bool   vcn_power_gated;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 3a0e6b1..f539d55 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -128,6 +128,8 @@ struct phm_uvd_arbiter {
uint32_t dclk;
uint32_t vclk_ceiling;
uint32_t dclk_ceiling;
+   uint32_t vclk_soft_min;
+   uint32_t dclk_soft_min;
 };
 
 struct phm_vce_arbiter {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index e0e106f..901c960c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -66,7 +66,12 @@
 #define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
 #define PPSMC_MSG_SetMinVideoFclkFreq   0x23
 #define PPSMC_MSG_SetMinDeepSleepDcefclk0x24
-#define PPSMC_Message_Count 0x25
+#define PPSMC_MSG_ForcePowerDownGfx 0x25
+#define PPSMC_MSG_SetPhyclkVoltageByFreq0x26
+#define PPSMC_MSG_SetDppclkVoltageByFreq0x27
+#define PPSMC_MSG_SetSoftMinVcn 0x28
+#define PPSMC_Message_Count 0x29
+
 
 typedef uint16_t PPSMC_Result;
 typedef int  PPSMC_Msg;
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/3] drm/amdgpu: add psp bootloader command list

[Junwei Zhang]

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ++
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   |  4 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 538fa9d..3776186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -53,6 +53,16 @@ struct psp_ring
uint32_tring_size;
 };
 
+enum psp_bootloader_command_list
+{
+   PSP_BL__LOAD_SYSDRV = 0x1,
+   PSP_BL__LOAD_SOSDRV = 0x2,
+   PSP_BL__NO_ECC  = 0x3,
+   PSP_BL__PARTIAL_ECC = 0x30001,
+   PSP_BL__FULL_ECC= 0x30002,
+   PSP_BL__DEFAULT_ECC = 0x30003,
+};
+
 struct psp_context
 {
struct amdgpu_device*adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 2718e86..f93a66e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -190,7 +190,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
/* Provide the sys driver to bootrom */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
-   psp_gfxdrv_command_reg = 1 << 16;
+   psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
   psp_gfxdrv_command_reg);
 
@@ -231,7 +231,7 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
/* Provide the PSP secure OS to bootrom */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
-   psp_gfxdrv_command_reg = 2 << 16;
+   psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
   psp_gfxdrv_command_reg);
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amdgpu: add psp ecc support for vega10

[Junwei Zhang]

Disable ecc by default

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  3 ++
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 60 +
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h   |  2 ++
 3 files changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index b04cc80..ec433b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -52,6 +52,8 @@ static int psp_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_VEGA10:
psp->init_microcode = psp_v3_1_init_microcode;
+   psp->bootloader_is_sos_running = 
psp_v3_1_bootloader_is_sos_running;
+   psp->bootloader_set_ecc_mode = psp_v3_1_bootloader_set_ecc_mode;
psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
@@ -61,6 +63,7 @@ static int psp_sw_init(void *handle)
psp->cmd_submit = psp_v3_1_cmd_submit;
psp->compare_sram_data = psp_v3_1_compare_sram_data;
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+   psp->config.ecc_mode = PSP_ECC_MODE__NONE;
break;
case CHIP_RAVEN:
 #if 0
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f93a66e..0a51dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -162,6 +162,66 @@ int psp_v3_1_init_microcode(struct psp_context *psp)
return err;
 }
 
+bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+
+   if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81) != 0)
+   return true;
+   else
+   return false;
+}
+
+int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp)
+{
+   int ret = 0;
+   uint32_t sol_reg;
+   struct amdgpu_device *adev = psp->adev;
+   uint32_t psp_gfxdrv_command_reg = 0;
+
+   /* Workaround: check bootloader version and skip old one */
+   sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+   if (sol_reg < 0xB0C00)
+   return ret;
+
+   switch (psp->config.ecc_mode)
+   {
+   case PSP_ECC_MODE__NONE:
+   break;
+   case PSP_ECC_MODE__OFF:
+   psp_gfxdrv_command_reg = PSP_BL__NO_ECC;
+   break;
+   case PSP_ECC_MODE__ON:
+   psp_gfxdrv_command_reg = PSP_BL__FULL_ECC;
+   break;
+   case PSP_ECC_MODE__PARTIALON:
+   psp_gfxdrv_command_reg = PSP_BL__PARTIAL_ECC;
+   break;
+   default:
+   break;
+   }
+
+   if (psp_gfxdrv_command_reg == 0)
+   return ret;
+
+   /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
+   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+  0x8000, 0x8000, false);
+   if (ret)
+   return ret;
+
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg);
+
+   /* There might be handshake issue with hardware which needs delay */
+   mdelay(20);
+
+   /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
+   ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+  0x8000, 0x8000, false);
+
+   return ret;
+}
+
 int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
 {
int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
index 9dcd0b2..3e52b5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
@@ -34,6 +34,8 @@
 
 extern int psp_v3_1_init_microcode(struct psp_context *psp);
 extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
+extern bool psp_v3_1_bootloader_is_sos_running(struct psp_context *psp);
+extern int psp_v3_1_bootloader_set_ecc_mode(struct psp_context *psp);
 extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
 extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
 struct psp_gfx_cmd_resp *cmd);
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: drop old ip definitions for gfxhub and mmhub

[Christian König]

Am 28.07.2017 um 05:41 schrieb Alex Deucher:

The gfxhub and mmhub code are now helpers for gmc rather
than standalone IPs.  When that changes these were left
over.  Remove them.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 --
  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  | 3 ---
  2 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
index d2dbb08..206e29c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
@@ -30,7 +30,5 @@ void gfxhub_v1_0_set_fault_enable_default(struct 
amdgpu_device *adev,
  bool value);
  void gfxhub_v1_0_init(struct amdgpu_device *adev);
  u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);
-extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;
-extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;
  
  #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
index 57bb940..5d38229 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
@@ -36,7 +36,4 @@ void mmhub_v1_0_initialize_power_gating(struct amdgpu_device 
*adev);
  void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
  bool enable);
  
-extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;

-extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
-
  #endif



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: rv: Use designated initializers

[Christian König]

Am 28.07.2017 um 03:43 schrieb Alex Deucher:

On Tue, Jul 25, 2017 at 5:47 PM, Kees Cook  wrote:

As done for vega10 in commit 3ddd396f6b57 ("drm/amd/powerplay: Use
designated initializers") mark other tableFunction entries with designated
initializers. The randstruct plugin requires designated initializers for
structures that are entirely function pointers.

Cc: Rex Zhu 
Cc: Hawking Zhang 
Cc: Alex Deucher 
Signed-off-by: Kees Cook 
---
If I can get an Ack for this, I'll carry it in the gcc-plugins tree, unless
you think this is worth landing for v4.13, in which case, please take it
now. :)


Acked-by: Alex Deucher 

I'm happy to take this through my tree if that is ok with you.


I'm wondering a bit how the plugin detects that it can randomize a 
structure layout?


We have a couple of structs where this would be fatal.

Christian.



Alex


Thanks!
---
  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 4c7f430b36eb..8e6cfd89c7e0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -308,8 +308,8 @@ static int rv_tf_set_num_active_display(struct pp_hwmgr 
*hwmgr, void *input,
  }

  static const struct phm_master_table_item rv_set_power_state_list[] = {
-   { NULL, rv_tf_set_clock_limit },
-   { NULL, rv_tf_set_num_active_display },
+   { .tableFunction = rv_tf_set_clock_limit },
+   { .tableFunction = rv_tf_set_num_active_display },
 { }
  };

@@ -382,7 +382,7 @@ static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
  }

  static const struct phm_master_table_item rv_disable_dpm_list[] = {
-   {NULL, rv_tf_disable_gfx_off},
+   { .tableFunction = rv_tf_disable_gfx_off },
 { },
  };

@@ -407,7 +407,7 @@ static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
  }

  static const struct phm_master_table_item rv_enable_dpm_list[] = {
-   {NULL, rv_tf_enable_gfx_off},
+   { .tableFunction = rv_tf_enable_gfx_off },
 { },
  };

--
2.7.4


--
Kees Cook
Pixel Security
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amd/powerplay: update didt configs

[Evan Quan]

Change-Id: I1506f4c6e9320a1e90a89be55368328cbaab7844
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index fbafc84..e7fa670 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
  * 
-
  */
/* SQ */
-   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_SQ_EDC_CTRL,DIDT_SQ_EDC_CTRL__EDC_EN_MASK,   
DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg 
SEEDCCtrlForceStallConfig_Vega10[] =
{   ixDIDT_SQ_EDC_CTRL,
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, 
DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,  0x0001 },
 
/* TD */
-   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x0001 },
+   {   ixDIDT_TD_EDC_CTRL,DIDT_TD_EDC_CTRL__EDC_EN_MASK,   
DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,
0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,   
DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,  
DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,   0x },
{   ixDIDT_TD_EDC_CTRL,
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,  
DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,   0x0001 },
@@ -1208,7 +1208,7 @@ static int vega10_enable_se_edc_force_stall_config(struct 
pp_hwmgr *hwmgr)
if (0 != result)
return result;
 
-   vega10_didt_set_mask(hwmgr, true);
+   vega10_didt_set_mask(hwmgr, false);
 
cgs_enter_safe_mode(hwmgr->device, false);
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/3] *** Add PSP ECC support for Vega10 ***

[Junwei Zhang]

Junwei Zhang (3):
  drm/amdgpu: add psp bootloader command list
  drm/amdgpu: add psp ecc support
  drm/amdgpu: add psp ecc support for vega10

 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 20 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 32 +
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 64 +++--
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h   |  2 ++
 4 files changed, 113 insertions(+), 5 deletions(-)

-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amdgpu: add psp ecc support

[Junwei Zhang]

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++
 2 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 1aa41af..b04cc80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -256,6 +256,10 @@ static int psp_hw_start(struct psp_context *psp)
 {
int ret;
 
+   ret = psp_bootloader_set_ecc_mode(psp);
+   if (ret)
+   return ret;
+
ret = psp_bootloader_load_sysdrv(psp);
if (ret)
return ret;
@@ -365,9 +369,16 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (ret)
goto failed_mem;
 
-   ret = psp_hw_start(psp);
-   if (ret)
-   goto failed_mem;
+   if (psp_bootloader_is_sos_running(psp) &&
+   psp->config.ecc_mode != PSP_ECC_MODE__NONE) {
+   if (psp_ring_create(psp, PSP_RING_TYPE__KM))
+   goto failed_mem;
+   if (psp_tmr_load(psp))
+   goto failed_mem;
+   } else {
+   if (psp_hw_start(psp))
+   goto failed_mem;
+   }
 
ret = psp_np_fw_load(psp);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 3776186..8ec9194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -63,6 +63,19 @@ enum psp_bootloader_command_list
PSP_BL__DEFAULT_ECC = 0x30003,
 };
 
+enum psp_ecc_mode
+{
+   PSP_ECC_MODE__NONE = 0,
+   PSP_ECC_MODE__OFF = 1,
+   PSP_ECC_MODE__ON = 2,
+   PSP_ECC_MODE__PARTIALON = 3,
+};
+
+struct psp_config
+{
+   enum psp_ecc_mode   ecc_mode;
+};
+
 struct psp_context
 {
struct amdgpu_device*adev;
@@ -70,6 +83,8 @@ struct psp_context
struct psp_gfx_cmd_resp *cmd;
 
int (*init_microcode)(struct psp_context *psp);
+   int (*bootloader_set_ecc_mode)(struct psp_context *psp);
+   bool (*bootloader_is_sos_running)(struct psp_context *psp);
int (*bootloader_load_sysdrv)(struct psp_context *psp);
int (*bootloader_load_sos)(struct psp_context *psp);
int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
@@ -123,6 +138,9 @@ struct psp_context
struct amdgpu_bo*cmd_buf_bo;
uint64_tcmd_buf_mc_addr;
struct psp_gfx_cmd_resp *cmd_buf_mem;
+
+   /* psp config */
+   struct psp_config   config;
 };
 
 struct amdgpu_psp_funcs {
@@ -140,6 +158,10 @@ struct amdgpu_psp_funcs {
(psp)->compare_sram_data((psp), (ucode), (type))
 #define psp_init_microcode(psp) \
((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
+#define psp_bootloader_set_ecc_mode(psp) \
+   ((psp)->bootloader_set_ecc_mode ? 
(psp)->bootloader_set_ecc_mode((psp)) : 0)
+#define psp_bootloader_is_sos_running(psp) \
+   ((psp)->bootloader_is_sos_running ? 
(psp)->bootloader_is_sos_running((psp)) : 0)
 #define psp_bootloader_load_sysdrv(psp) \
((psp)->bootloader_load_sysdrv ? 
(psp)->bootloader_load_sysdrv((psp)) : 0)
 #define psp_bootloader_load_sos(psp) \
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: make wb 256bit function names consistent

[Christian König]

Am 27.07.2017 um 22:43 schrieb Alex Deucher:

Use a lower case b to be consistent with the other wb functions.

Signed-off-by: Alex Deucher 


I still suggest to get rid of all those variants and always allocate 
256bits, but anyway the patch is Reviewed-by: Christian König 
.



---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 2 +-
  3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f364900..5f8d2e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1192,7 +1192,7 @@ struct amdgpu_wb {
  int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
  void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
  int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
-int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb);
+int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb);
  void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
  void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 06c214f..41f6af3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -602,7 +602,7 @@ int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
}
  }
  
-int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb)

+int amdgpu_wb_get_256bit(struct amdgpu_device *adev, u32 *wb)
  {
int i = 0;
unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 15b7149..3874be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -213,7 +213,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ring *ring,
}
  
  	if (amdgpu_sriov_vf(adev) && ring->funcs->type == AMDGPU_RING_TYPE_GFX) {

-   r = amdgpu_wb_get_256Bit(adev, >fence_offs);
+   r = amdgpu_wb_get_256bit(adev, >fence_offs);
if (r) {
dev_err(adev->dev, "(%d) ring fence_offs wb alloc 
failed\n", r);
return r;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] drm/amdgpu: Support IOMMU on Raven

[Christian König]

Am 27.07.2017 um 21:48 schrieb Yong Zhao:

We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for
PDEs and setting S bit to 1 for PTEs when the corresponding addresses
are not occupied by gpu driver allocated buffers.

Change-Id: I52e41b6e93243dbbd08d97781da1c9a60ce1f9a4
Signed-off-by: Yong Zhao 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  3 +++
  2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9325f39..d152724 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -288,6 +288,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
unsigned pt_idx, from, to;
int r;
u64 flags;
+   uint64_t init_value = 0;
  
  	if (!parent->entries) {

unsigned num_entries = amdgpu_vm_num_entries(adev, level);
@@ -320,6 +321,12 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
AMDGPU_GEM_CREATE_SHADOW);
  
+	if (vm->pte_support_ats) {

+   init_value = AMDGPU_PTE_SYSTEM;
+   if (level != adev->vm_manager.num_level - 1)
+   init_value |= AMDGPU_PDE_PTE;
+   }
+
/* walk over the address space and allocate the page tables */
for (pt_idx = from; pt_idx <= to; ++pt_idx) {
struct reservation_object *resv = vm->root.bo->tbo.resv;
@@ -332,7 +339,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
 AMDGPU_GPU_PAGE_SIZE, true,
 AMDGPU_GEM_DOMAIN_VRAM,
 flags,
-NULL, resv, 0, );
+NULL, resv, init_value, );
if (r)
return r;
  
@@ -1994,15 +2001,19 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,

struct amdgpu_bo_va_mapping *mapping;
struct dma_fence *f = NULL;
int r;
+   uint64_t init_pte_value = 0;
  
  	while (!list_empty(>freed)) {

mapping = list_first_entry(>freed,
struct amdgpu_bo_va_mapping, list);
list_del(>list);
  
+		if (vm->pte_support_ats)

+   init_pte_value = AMDGPU_PTE_SYSTEM;
+
r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
mapping->start, mapping->last,
-   0, 0, );
+   init_pte_value, 0, );
amdgpu_vm_free_mapping(adev, vm, mapping, f);
if (r) {
dma_fence_put(f);
@@ -2493,6 +2504,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
struct amd_sched_rq *rq;
int r, i;
u64 flags;
+   uint64_t init_pde_value = 0;
  
  	vm->va = RB_ROOT;

vm->client_id = atomic64_inc_return(>vm_manager.client_counter);
@@ -2514,10 +2526,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
if (r)
return r;
  
-	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)

+   vm->pte_support_ats = false;
+
+   if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE);
-   else
+
+   if (adev->asic_type == CHIP_RAVEN) {
+   vm->pte_support_ats = true;
+   init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
+   }
+   } else
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_GFX);
DRM_DEBUG_DRIVER("VM update mode is %s\n",
@@ -2537,7 +2556,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
 AMDGPU_GEM_DOMAIN_VRAM,
 flags,
-NULL, NULL, 0, >root.bo);
+NULL, NULL, init_pde_value, >root.bo);
if (r)
goto error_free_sched_entity;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

index 34d9174..217ecba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -146,6 +146,9 @@ struct amdgpu_vm {
  
  	/* Flag to indicate if VM tables are updated by CPU 

Re: [PATCH 1/2] drm/amdgpu: Add a parameter to amdgpu_bo_create()

[Christian König]

Am 27.07.2017 um 21:48 schrieb Yong Zhao:

The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.

Change-Id: I9ef3b9dd3ca9b98cc25dd2eaff68fbe1129c3e3c
Signed-off-by: Yong Zhao 


I'm about to push a cleanup which removes a bunch of references to 
amdgpu_bo_create(), so don't be surprised when you need to rebase your 
patch once more before pushing.


The patch is Reviewed-by: Christian König  and 
that rebase should only require you to remove changes, so feel free to 
push it after the rebase.


Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 12 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_test.c  |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  4 ++--
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  4 ++--
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 10 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  6 +++---
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  4 ++--
  20 files changed, 43 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 2292c77..6d2bd80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -185,7 +185,8 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
return -ENOMEM;
  
  	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,

-AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 
&(*mem)->bo);
+AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0,
+&(*mem)->bo);
if (r) {
dev_err(adev->dev,
"failed to allocate BO for amdkfd (%d)\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 2fb299a..63ec1e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -81,7 +81,7 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, 
unsigned size,
  
  	n = AMDGPU_BENCHMARK_ITERATIONS;

r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, NULL,
-NULL, );
+NULL, 0, );
if (r) {
goto out_cleanup;
}
@@ -94,7 +94,7 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, 
unsigned size,
goto out_cleanup;
}
r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, NULL,
-NULL, );
+NULL, 0, );
if (r) {
goto out_cleanup;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 3d41cd4..343cdf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -124,7 +124,7 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device 
*cgs_device,
ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
  true, domain, flags,
  NULL, , NULL,
- );
+ 0, );
if (ret) {
DRM_ERROR("(%d) bo create failed\n", ret);
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fe6783e..cf81f9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -344,7 +344,7 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device 
*adev)
 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
-NULL, NULL, >vram_scratch.robj);
+NULL, NULL, 0, >vram_scratch.robj);
if (r) {
return r;
}
diff 

Re: [PATCH 1/5] drm/amdgpu/sdma4: drop unused register header

[Christian König]

Am 27.07.2017 um 21:46 schrieb Alex Deucher:

nbio registers are not used in this file.

Cc: Frank Min 
Signed-off-by: Alex Deucher 


Patches #1 and #3-#5 are Reviewed-by: Christian König 
.


I agree with Felix that #2 looks a bit ugly, but using writeq doesn't 
sounds like the correct answer either.


If WRITE_ONCE() does the job then I would use that one.

Christian.


---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 5c24708..7cb5320 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,7 +35,6 @@
  #include "vega10/MMHUB/mmhub_1_0_offset.h"
  #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  #include "vega10/HDP/hdp_4_0_offset.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
  #include "raven1/SDMA0/sdma0_4_1_default.h"
  
  #include "soc15_common.h"



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/5] drm/amdgpu/sdma4: set wptr shadow atomically

[Christian König]

Am 27.07.2017 um 22:50 schrieb Alex Deucher:

On Thu, Jul 27, 2017 at 4:39 PM, Felix Kuehling  wrote:

On 17-07-27 03:46 PM, Alex Deucher wrote:

No functional change until wptr polling uses this
location (future patch).

Cc: Frank Min 
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7cb5320..9392799 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -301,8 +301,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
   lower_32_bits(ring->wptr << 2),
   upper_32_bits(ring->wptr << 2));
   /* XXX check if swapping is necessary on BE */
- adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
- adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
+ atomic64_set((atomic64_t *)>wb.wb[ring->wptr_offs],
+  (ring->wptr << 2));

This looks a bit awkward. Would "writeq" do the job? That's what we use
for updating kernel queue doorbells in KFD.

Probably.  We just want to make sure the whole 64 bit value is updated
before the GPU polls the value.


writeq is for iomem and does endian conversion IIRC.

How about WRITE_ONCE()?

Christian.



Alex


The generic implementation of atomic64_set uses a spinlock. But that
doesn't do anything for protecting against concurrent access by the GPU
hardware.

Regards,
   Felix


   DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
   ring->doorbell_index, ring->wptr << 2);


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control

[Quan, Evan]

Oops, the changes were made by a remote windows editor which added the 
executable bit wrongly.
Thanks for the remind. Will pay attention to it.

Regards,
Evan
>-Original Message-
>From: Michel Dänzer [mailto:mic...@daenzer.net]
>Sent: Friday, July 28, 2017 4:38 PM
>To: Quan, Evan 
>Cc: amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control
>
>On 28/07/17 05:00 PM, Evan Quan wrote:
>> Change-Id: Ifbeb1f0c8e195cc9cb1e9cff975284d96d49b193
>> Signed-off-by: Evan Quan 
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +-
>>  1 file changed, 1 insertion(+), 5 deletions(-)
>>  mode change 100644 => 100755
>drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>
>Please fix your setup not to set executable bits for source code files.
>
>
>--
>Earthling Michel Dänzer   |   http://www.amd.com
>Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control

[Huang Rui]

On Fri, Jul 28, 2017 at 04:00:45PM +0800, Evan Quan wrote:
> Change-Id: Ifbeb1f0c8e195cc9cb1e9cff975284d96d49b193
> Signed-off-by: Evan Quan 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +-
>  1 file changed, 1 insertion(+), 5 deletions(-)
>  mode change 100644 => 100755 
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> old mode 100644
> new mode 100755
> index 7bb4e46..ace1aca
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> @@ -321,10 +321,7 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct 
> pp_hwmgr *hwmgr)
>  
>   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_MicrocodeFanControl)) {
> - result = vega10_fan_ctrl_set_static_mode(hwmgr,
> - FDO_PWM_MODE_STATIC);
> - if (!result)
> - result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
> + result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
>   } else
>   result = vega10_fan_ctrl_set_default_mode(hwmgr);
>  
> @@ -633,7 +630,6 @@ int tf_vega10_thermal_start_smc_fan_control(struct 
> pp_hwmgr *hwmgr,
>   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_MicrocodeFanControl)) {
>   vega10_fan_ctrl_start_smc_fan_control(hwmgr);
> - vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
>   }
>  
>   return 0;
> -- 
> 2.7.4
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/3] drm/amd/powerplay: updated vega10 fan control

[Michel Dänzer]

On 28/07/17 05:00 PM, Evan Quan wrote:
> Change-Id: Ifbeb1f0c8e195cc9cb1e9cff975284d96d49b193
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +-
>  1 file changed, 1 insertion(+), 5 deletions(-)
>  mode change 100644 => 100755 
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

Please fix your setup not to set executable bits for source code files.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amd/powerplay: updated vega10 fan control

[Evan Quan]

Change-Id: Ifbeb1f0c8e195cc9cb1e9cff975284d96d49b193
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)
 mode change 100644 => 100755 
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
old mode 100644
new mode 100755
index 7bb4e46..ace1aca
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -321,10 +321,7 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct 
pp_hwmgr *hwmgr)
 
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl)) {
-   result = vega10_fan_ctrl_set_static_mode(hwmgr,
-   FDO_PWM_MODE_STATIC);
-   if (!result)
-   result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
+   result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
} else
result = vega10_fan_ctrl_set_default_mode(hwmgr);
 
@@ -633,7 +630,6 @@ int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr 
*hwmgr,
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl)) {
vega10_fan_ctrl_start_smc_fan_control(hwmgr);
-   vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
 
return 0;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/3] drm/amdgpu: update vega10 golden setting

[Evan Quan]

Change-Id: I44c22b126824ccb022bf5cefa1d73639ac1a53c7
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 49de169..85fead0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -116,7 +116,9 @@ static const u32 golden_settings_gc_9_0[] =
SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x0800, 0x0880,
SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x0800, 
0x0880,
SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x0800, 0x0880,
+   SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x1000, 0x1000,
SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x000f, 0x01000107,
+   SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x0300, 0x020a2000,
SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfeef, 0x010b,
SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0x, 0x4a2c0e68,
SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0x, 0xb5d3f197,
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx