[PATCH 2/2] amdgpu/dc: inline a bunch of the fixed 31_32 helpers.

[Dave Airlie]

From: Dave Airlie 

This decreases code size by a few hundred bytes.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 122 ---
 drivers/gpu/drm/amd/display/include/fixed31_32.h   | 132 +++--
 2 files changed, 93 insertions(+), 161 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 546ed67..578691c 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -132,79 +132,6 @@ struct fixed31_32 dal_fixed31_32_from_int(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_neg(
-   struct fixed31_32 arg)
-{
-   struct fixed31_32 res;
-
-   res.value = -arg.value;
-
-   return res;
-}
-
-struct fixed31_32 dal_fixed31_32_abs(
-   struct fixed31_32 arg)
-{
-   if (arg.value < 0)
-   return dal_fixed31_32_neg(arg);
-   else
-   return arg;
-}
-
-bool dal_fixed31_32_lt(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   return arg1.value < arg2.value;
-}
-
-bool dal_fixed31_32_le(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   return arg1.value <= arg2.value;
-}
-
-bool dal_fixed31_32_eq(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   return arg1.value == arg2.value;
-}
-
-struct fixed31_32 dal_fixed31_32_min(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   if (arg1.value <= arg2.value)
-   return arg1;
-   else
-   return arg2;
-}
-
-struct fixed31_32 dal_fixed31_32_max(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   if (arg1.value <= arg2.value)
-   return arg2;
-   else
-   return arg1;
-}
-
-struct fixed31_32 dal_fixed31_32_clamp(
-   struct fixed31_32 arg,
-   struct fixed31_32 min_value,
-   struct fixed31_32 max_value)
-{
-   if (dal_fixed31_32_le(arg, min_value))
-   return min_value;
-   else if (dal_fixed31_32_le(max_value, arg))
-   return max_value;
-   else
-   return arg;
-}
-
 struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
uint8_t shift)
@@ -219,19 +146,6 @@ struct fixed31_32 dal_fixed31_32_shl(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_shr(
-   struct fixed31_32 arg,
-   uint8_t shift)
-{
-   struct fixed31_32 res;
-
-   ASSERT(shift < 64);
-
-   res.value = arg.value >> shift;
-
-   return res;
-}
-
 struct fixed31_32 dal_fixed31_32_add(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
@@ -246,24 +160,6 @@ struct fixed31_32 dal_fixed31_32_add(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_add_int(
-   struct fixed31_32 arg1,
-   int32_t arg2)
-{
-   return dal_fixed31_32_add(
-   arg1,
-   dal_fixed31_32_from_int(arg2));
-}
-
-struct fixed31_32 dal_fixed31_32_sub_int(
-   struct fixed31_32 arg1,
-   int32_t arg2)
-{
-   return dal_fixed31_32_sub(
-   arg1,
-   dal_fixed31_32_from_int(arg2));
-}
-
 struct fixed31_32 dal_fixed31_32_sub(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
@@ -278,15 +174,6 @@ struct fixed31_32 dal_fixed31_32_sub(
return res;
 }
 
-struct fixed31_32 dal_fixed31_32_mul_int(
-   struct fixed31_32 arg1,
-   int32_t arg2)
-{
-   return dal_fixed31_32_mul(
-   arg1,
-   dal_fixed31_32_from_int(arg2));
-}
-
 struct fixed31_32 dal_fixed31_32_mul(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
@@ -390,15 +277,6 @@ struct fixed31_32 dal_fixed31_32_div_int(
dal_fixed31_32_from_int(arg2).value);
 }
 
-struct fixed31_32 dal_fixed31_32_div(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   return dal_fixed31_32_from_fraction(
-   arg1.value,
-   arg2.value);
-}
-
 struct fixed31_32 dal_fixed31_32_recip(
struct fixed31_32 arg)
 {
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 5a4364d..f0bc3c4 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -90,15 +90,26 @@ struct fixed31_32 dal_fixed31_32_from_int(
  * @brief
  * result = -arg
  */
-struct fixed31_32 dal_fixed31_32_neg(
-   struct fixed31_32 arg);
+static inline struct fixed31_32 dal_fixed31_32_neg(struct fixed31_32 arg)
+{
+   struct fixed31_32 res;
+
+   res.value = -arg.value;
+
+   return res;
+}
 
 /*
  * @brief
  * result = abs(arg) := (arg >= 0) ? arg : -arg
  */
-struct fixed31_32 dal_fixed31_32_abs(
-   struct fixed31_32 arg);
+static inline struct fixed31_32 dal_fixed31_32_abs(struct 

[PATCH 1/2] amdgpu/dc: inline some of the fixed 32_32 fns

[Dave Airlie]

From: Dave Airlie 

This drops ~400 bytes here.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c | 60 -
 drivers/gpu/drm/amd/display/include/fixed32_32.h   | 76 +-
 2 files changed, 61 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c
index 911e90b..4d3aaa8 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c
@@ -57,14 +57,6 @@ struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, 
uint32_t d)
return fx;
 }
 
-struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
-{
-   struct fixed32_32 fx;
-
-   fx.value = (uint64_t)value<<32;
-   return fx;
-}
-
 struct fixed32_32 dal_fixed32_32_add(
struct fixed32_32 lhs,
struct fixed32_32 rhs)
@@ -155,67 +147,15 @@ struct fixed32_32 dal_fixed32_32_div_int(struct 
fixed32_32 lhs, uint32_t rhs)
return fx;
 }
 
-struct fixed32_32 dal_fixed32_32_min(
-   struct fixed32_32 lhs,
-   struct fixed32_32 rhs)
-{
-   return (lhs.value < rhs.value) ? lhs : rhs;
-}
-
-struct fixed32_32 dal_fixed32_32_max(
-   struct fixed32_32 lhs,
-   struct fixed32_32 rhs)
-{
-   return (lhs.value > rhs.value) ? lhs : rhs;
-}
-
-bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-   return lhs.value > rhs.value;
-}
-bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-   return lhs.value > ((uint64_t)rhs<<32);
-}
-
-bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-   return lhs.value < rhs.value;
-}
-
-bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-   return lhs.value <= rhs.value;
-}
-
-bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-   return lhs.value < ((uint64_t)rhs<<32);
-}
-
-bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-   return lhs.value <= ((uint64_t)rhs<<32);
-}
-
 uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
 {
ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
 }
 
-uint32_t dal_fixed32_32_floor(struct fixed32_32 v)
-{
-   return v.value>>32;
-}
-
 uint32_t dal_fixed32_32_round(struct fixed32_32 v)
 {
ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
return (v.value + (1ULL<<31))>>32;
 }
 
-bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-   return lhs.value == rhs.value;
-}
diff --git a/drivers/gpu/drm/amd/display/include/fixed32_32.h 
b/drivers/gpu/drm/amd/display/include/fixed32_32.h
index c7ddd0e..9c70341 100644
--- a/drivers/gpu/drm/amd/display/include/fixed32_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed32_32.h
@@ -38,7 +38,14 @@ static const struct fixed32_32 dal_fixed32_32_one = { 
0x1LL };
 static const struct fixed32_32 dal_fixed32_32_half = { 0x8000LL };
 
 struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d);
-struct fixed32_32 dal_fixed32_32_from_int(uint32_t value);
+static inline struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
+{
+   struct fixed32_32 fx;
+
+   fx.value = (uint64_t)value<<32;
+   return fx;
+}
+
 struct fixed32_32 dal_fixed32_32_add(
struct fixed32_32 lhs,
struct fixed32_32 rhs);
@@ -63,21 +70,60 @@ struct fixed32_32 dal_fixed32_32_div(
 struct fixed32_32 dal_fixed32_32_div_int(
struct fixed32_32 lhs,
uint32_t rhs);
-struct fixed32_32 dal_fixed32_32_min(
-   struct fixed32_32 lhs,
-   struct fixed32_32 rhs);
-struct fixed32_32 dal_fixed32_32_max(
-   struct fixed32_32 lhs,
-   struct fixed32_32 rhs);
-bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs);
-bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs);
-bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs);
-bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs);
-bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs);
-bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs);
-bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs);
+
+static inline struct fixed32_32 dal_fixed32_32_min(struct fixed32_32 lhs,
+  struct fixed32_32 rhs)
+{
+   return (lhs.value < rhs.value) ? lhs : rhs;
+}
+
+static inline struct fixed32_32 dal_fixed32_32_max(struct fixed32_32 lhs,
+  struct fixed32_32 rhs)
+{
+   return (lhs.value > rhs.value) ? lhs : rhs;
+}
+
+static inline bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 
rhs)
+{
+   return lhs.value > rhs.value;
+}
+
+static inline bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
+{
+   return lhs.value > 

[PATCH] amdgpu/dc: remove pointless returns in the i2caux constructor paths. (v2)

[Dave Airlie]

From: Dave Airlie 

There was lots of return true, and error checking that was never used
in these paths.

Just remove it all.

v2: I missed one return true.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c |  6 ++--
 drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h |  2 +-
 .../amd/display/dc/i2caux/dce100/i2caux_dce100.c   | 21 +-
 .../display/dc/i2caux/dce110/aux_engine_dce110.c   | 20 +++---
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c| 24 ++--
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.h|  4 ---
 .../dc/i2caux/dce110/i2c_sw_engine_dce110.c| 20 +++---
 .../amd/display/dc/i2caux/dce110/i2caux_dce110.c   | 30 ++--
 .../amd/display/dc/i2caux/dce110/i2caux_dce110.h   |  2 +-
 .../amd/display/dc/i2caux/dce112/i2caux_dce112.c   | 30 ++--
 .../amd/display/dc/i2caux/dce120/i2caux_dce120.c   | 21 +-
 .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c  | 32 --
 .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c  | 19 +++--
 .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 19 +++--
 .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 21 +-
 .../display/dc/i2caux/diagnostics/i2caux_diag.c| 20 +++---
 drivers/gpu/drm/amd/display/dc/i2caux/engine.h |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/engine_base.c|  3 +-
 drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c |  7 ++---
 drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h |  2 +-
 .../amd/display/dc/i2caux/i2c_generic_hw_engine.c  |  6 ++--
 .../amd/display/dc/i2caux/i2c_generic_hw_engine.h  |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c  |  6 ++--
 .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h  |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c  | 17 +++-
 .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h  |  2 +-
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c |  4 +--
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h |  2 +-
 28 files changed, 100 insertions(+), 246 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
index 3c9608c..fc7a7d4 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
@@ -555,15 +555,13 @@ bool dal_aux_engine_submit_request(
return result;
 }
 
-bool dal_aux_engine_construct(
+void dal_aux_engine_construct(
struct aux_engine *engine,
struct dc_context *ctx)
 {
-   if (!dal_i2caux_construct_engine(>base, ctx))
-   return false;
+   dal_i2caux_construct_engine(>base, ctx);
engine->delay = 0;
engine->max_defer_write_retry = 0;
-   return true;
 }
 
 void dal_aux_engine_destruct(
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
index 40b2028..8e71324 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
@@ -100,7 +100,7 @@ struct aux_engine {
bool acquire_reset;
 };
 
-bool dal_aux_engine_construct(
+void dal_aux_engine_construct(
struct aux_engine *engine,
struct dc_context *ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
index c45a2ee..e8d3781 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
@@ -95,18 +95,11 @@ struct i2caux *dal_i2caux_dce100_create(
return NULL;
}
 
-   if (dal_i2caux_dce110_construct(
-   i2caux_dce110,
-   ctx,
-   dce100_aux_regs,
-   dce100_hw_engine_regs,
-   _shift,
-   _mask))
-   return _dce110->base;
-
-   ASSERT_CRITICAL(false);
-
-   kfree(i2caux_dce110);
-
-   return NULL;
+   dal_i2caux_dce110_construct(i2caux_dce110,
+   ctx,
+   dce100_aux_regs,
+   dce100_hw_engine_regs,
+   _shift,
+   _mask);
+   return _dce110->base;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
index 4b673b4..0c4bbc1 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
@@ -426,22 +426,16 @@ static const struct engine_funcs engine_funcs = {
.acquire = dal_aux_engine_acquire,
 };
 
-static bool construct(
+static void construct(
struct 

[PATCH 9/9] amdgpu/dc: fix construct return values on irq service.

[Dave Airlie]

From: Dave Airlie 

This just removes more unused return/errors paths.

Signed-off-by: Dave Airlie 
---
 .../gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 14 --
 .../gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 14 --
 .../gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c   | 14 --
 .../gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c   | 14 --
 drivers/gpu/drm/amd/display/dc/irq/irq_service.c   |  9 +
 drivers/gpu/drm/amd/display/dc/irq/irq_service.h   |  2 +-
 6 files changed, 22 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 5c55896..f7e40b2 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -406,17 +406,14 @@ static const struct irq_service_funcs 
irq_service_funcs_dce110 = {
.to_dal_irq_source = to_dal_irq_source_dce110
 };
 
-static bool construct(
+static void construct(
struct irq_service *irq_service,
struct irq_service_init_data *init_data)
 {
-   if (!dal_irq_service_construct(irq_service, init_data))
-   return false;
+   dal_irq_service_construct(irq_service, init_data);
 
irq_service->info = irq_source_info_dce110;
irq_service->funcs = _service_funcs_dce110;
-
-   return true;
 }
 
 struct irq_service *dal_irq_service_dce110_create(
@@ -428,9 +425,6 @@ struct irq_service *dal_irq_service_dce110_create(
if (!irq_service)
return NULL;
 
-   if (construct(irq_service, init_data))
-   return irq_service;
-
-   kfree(irq_service);
-   return NULL;
+   construct(irq_service, init_data);
+   return irq_service;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index 61d7c28..2ad56b1 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -265,17 +265,14 @@ static const struct irq_service_funcs 
irq_service_funcs_dce120 = {
.to_dal_irq_source = to_dal_irq_source_dce110
 };
 
-static bool construct(
+static void construct(
struct irq_service *irq_service,
struct irq_service_init_data *init_data)
 {
-   if (!dal_irq_service_construct(irq_service, init_data))
-   return false;
+   dal_irq_service_construct(irq_service, init_data);
 
irq_service->info = irq_source_info_dce120;
irq_service->funcs = _service_funcs_dce120;
-
-   return true;
 }
 
 struct irq_service *dal_irq_service_dce120_create(
@@ -287,9 +284,6 @@ struct irq_service *dal_irq_service_dce120_create(
if (!irq_service)
return NULL;
 
-   if (construct(irq_service, init_data))
-   return irq_service;
-
-   kfree(irq_service);
-   return NULL;
+   construct(irq_service, init_data);
+   return irq_service;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
index d6e1fb6..8a2066c 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
@@ -277,17 +277,14 @@ static const struct irq_service_funcs 
irq_service_funcs_dce80 = {
.to_dal_irq_source = to_dal_irq_source_dce110
 };
 
-static bool construct(
+static void construct(
struct irq_service *irq_service,
struct irq_service_init_data *init_data)
 {
-   if (!dal_irq_service_construct(irq_service, init_data))
-   return false;
+   dal_irq_service_construct(irq_service, init_data);
 
irq_service->info = irq_source_info_dce80;
irq_service->funcs = _service_funcs_dce80;
-
-   return true;
 }
 
 struct irq_service *dal_irq_service_dce80_create(
@@ -299,11 +296,8 @@ struct irq_service *dal_irq_service_dce80_create(
if (!irq_service)
return NULL;
 
-   if (construct(irq_service, init_data))
-   return irq_service;
-
-   kfree(irq_service);
-   return NULL;
+   construct(irq_service, init_data);
+   return irq_service;
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
index f6e8611..74ad247 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
@@ -332,17 +332,14 @@ static const struct irq_service_funcs 
irq_service_funcs_dcn10 = {
.to_dal_irq_source = to_dal_irq_source_dcn10
 };
 
-static bool construct(
+static void 

[PATCH 5/9] amdgpu/dc: cleanup construct returns in gpio.

[Dave Airlie]

From: Dave Airlie 

This is similiar to previous patches, don't return when we don't
need to, also do error checking before allocating memory, makes
it simpler to cleanup after.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c  | 33 +++
 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c |  4 +--
 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h |  2 +-
 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c  | 47 ++-
 4 files changed, 30 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 
b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
index 7b6efa4..310f489 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
@@ -199,25 +199,14 @@ static const struct hw_gpio_pin_funcs funcs = {
.close = dal_hw_gpio_close,
 };
 
-static bool construct(
+static void construct(
struct hw_ddc *ddc,
enum gpio_id id,
uint32_t en,
struct dc_context *ctx)
 {
-   if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
-   ASSERT_CRITICAL(false);
-   return false;
-   }
-
-   if (!dal_hw_gpio_construct(>base, id, en, ctx)) {
-   ASSERT_CRITICAL(false);
-   return false;
-   }
-
+   dal_hw_gpio_construct(>base, id, en, ctx);
ddc->base.base.funcs = 
-
-   return true;
 }
 
 struct hw_gpio_pin *dal_hw_ddc_create(
@@ -225,19 +214,19 @@ struct hw_gpio_pin *dal_hw_ddc_create(
enum gpio_id id,
uint32_t en)
 {
-   struct hw_ddc *pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
+   struct hw_ddc *pin;
 
-   if (!pin) {
+   if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
ASSERT_CRITICAL(false);
return NULL;
}
 
-   if (construct(pin, id, en, ctx))
-   return >base.base;
-
-   ASSERT_CRITICAL(false);
-
-   kfree(pin);
+   pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
+   if (!pin) {
+   ASSERT_CRITICAL(false);
+   return NULL;
+   }
 
-   return NULL;
+   construct(pin, id, en, ctx);
+   return >base.base;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 
b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
index 4cdcdfb..6605108 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
@@ -176,7 +176,7 @@ enum gpio_result dal_hw_gpio_config_mode(
}
 }
 
-bool dal_hw_gpio_construct(
+void dal_hw_gpio_construct(
struct hw_gpio *pin,
enum gpio_id id,
uint32_t en,
@@ -194,8 +194,6 @@ bool dal_hw_gpio_construct(
pin->store.mux = 0;
 
pin->mux_supported = false;
-
-   return true;
 }
 
 void dal_hw_gpio_destruct(
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h 
b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
index fb41ee2..bca0cef 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
@@ -109,7 +109,7 @@ struct hw_gpio {
 #define HW_GPIO_FROM_BASE(hw_gpio_pin) \
container_of((hw_gpio_pin), struct hw_gpio, base)
 
-bool dal_hw_gpio_construct(
+void dal_hw_gpio_construct(
struct hw_gpio *pin,
enum gpio_id id,
uint32_t en,
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c 
b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
index 0c255c0..784fecc 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
@@ -41,15 +41,13 @@
 #define REG(reg)\
(hpd->regs->reg)
 
-static bool dal_hw_hpd_construct(
+static void dal_hw_hpd_construct(
struct hw_hpd *pin,
enum gpio_id id,
uint32_t en,
struct dc_context *ctx)
 {
-   if (!dal_hw_gpio_construct(>base, id, en, ctx))
-   return false;
-   return true;
+   dal_hw_gpio_construct(>base, id, en, ctx);
 }
 
 static void dal_hw_hpd_destruct(
@@ -126,30 +124,14 @@ static const struct hw_gpio_pin_funcs funcs = {
.close = dal_hw_gpio_close,
 };
 
-static bool construct(
+static void construct(
struct hw_hpd *hpd,
enum gpio_id id,
uint32_t en,
struct dc_context *ctx)
 {
-   if (id != GPIO_ID_HPD) {
-   ASSERT_CRITICAL(false);
-   return false;
-   }
-
-   if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
-   ASSERT_CRITICAL(false);
-   return false;
-   }
-
-   if (!dal_hw_hpd_construct(hpd, id, en, ctx)) {
-   ASSERT_CRITICAL(false);
-   return false;
-   }
-
+   dal_hw_hpd_construct(hpd, id, en, ctx);
hpd->base.base.funcs = 
-
-   return true;
 }
 
 struct hw_gpio_pin *dal_hw_hpd_create(
@@ -157,19 +139,24 @@ struct hw_gpio_pin *dal_hw_hpd_create(
enum gpio_id id,

[PATCH 8/9] amdgpu: fixup construct to void paths on some more dc objects.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +++---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c   | 18 +-
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c  | 15 +++
 3 files changed, 11 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 226512c..315160d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -245,7 +245,7 @@ void dal_ddc_aux_payloads_add(
}
 }
 
-static bool construct(
+static void construct(
struct ddc_service *ddc_service,
struct ddc_service_init_data *init_data)
 {
@@ -282,7 +282,6 @@ static bool construct(
connector_id == CONNECTOR_ID_LVDS;
 
ddc_service->wa.raw = 0;
-   return true;
 }
 
 struct ddc_service *dal_ddc_service_create(
@@ -295,11 +294,8 @@ struct ddc_service *dal_ddc_service_create(
if (!ddc_service)
return NULL;
 
-   if (construct(ddc_service, init_data))
-   return ddc_service;
-
-   kfree(ddc_service);
-   return NULL;
+   construct(ddc_service, init_data);
+   return ddc_service;
 }
 
 static void destruct(struct ddc_service *ddc)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index d5da847..a9919641 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -56,7 +56,7 @@ static void update_stream_signal(struct dc_stream_state 
*stream)
}
 }
 
-static bool construct(struct dc_stream_state *stream,
+static void construct(struct dc_stream_state *stream,
struct dc_sink *dc_sink_data)
 {
uint32_t i = 0;
@@ -104,7 +104,6 @@ static bool construct(struct dc_stream_state *stream,
stream->status.link = stream->sink->link;
 
update_stream_signal(stream);
-   return true;
 }
 
 static void destruct(struct dc_stream_state *stream)
@@ -142,25 +141,18 @@ struct dc_stream_state *dc_create_stream_for_sink(
struct dc_stream_state *stream;
 
if (sink == NULL)
-   goto alloc_fail;
+   return NULL;
 
stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
+   if (stream == NULL)
+   return NULL;
 
-   if (NULL == stream)
-   goto alloc_fail;
-
-   if (false == construct(stream, sink))
-   goto construct_fail;
+   construct(stream, sink);
 
atomic_inc(>ref_count);
 
return stream;
 
-construct_fail:
-   kfree(stream);
-
-alloc_fail:
-   return NULL;
 }
 
 struct dc_stream_status *dc_stream_get_status(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 511ada9..f170ae9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -34,12 +34,11 @@
 
/***
  * Private functions
  
**/
-static bool construct(struct dc_context *ctx, struct dc_plane_state 
*plane_state)
+static void construct(struct dc_context *ctx, struct dc_plane_state 
*plane_state)
 {
plane_state->ctx = ctx;
memset(_state->hdr_static_ctx,
0, sizeof(struct dc_hdr_static_metadata));
-   return true;
 }
 
 static void destruct(struct dc_plane_state *plane_state)
@@ -72,20 +71,12 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
 GFP_KERNEL);
 
if (NULL == plane_state)
-   goto alloc_fail;
-
-   if (false == construct(core_dc->ctx, plane_state))
-   goto construct_fail;
+   return NULL;
 
+   construct(core_dc->ctx, plane_state);
atomic_inc(_state->ref_count);
 
return plane_state;
-
-construct_fail:
-   kfree(plane_state);
-
-alloc_fail:
-   return NULL;
 }
 
 const struct dc_plane_status *dc_plane_get_status(
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 7/9] amdgpu/dc: remove pointless return from build_pipe_hw_param

[Dave Airlie]

From: Dave Airlie 

This never returned anything else.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c |  6 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 10 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h |  2 +-
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c |  6 +-
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   |  6 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 11 ++-
 6 files changed, 8 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 0db987d..b1cf591 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -631,16 +631,12 @@ static enum dc_status build_mapped_resource(
struct dc_state *context,
struct dc_stream_state *stream)
 {
-   enum dc_status status = DC_OK;
struct pipe_ctx *pipe_ctx = 
resource_get_head_pipe_for_stream(>res_ctx, stream);
 
if (!pipe_ctx)
return DC_ERROR_UNEXPECTED;
 
-   status = dce110_resource_build_pipe_hw_param(pipe_ctx);
-
-   if (status != DC_OK)
-   return status;
+   dce110_resource_build_pipe_hw_param(pipe_ctx);
 
resource_build_info_frame(pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 017a1fd..89036af 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -724,7 +724,7 @@ static void get_pixel_clock_parameters(
}
 }
 
-enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 {
get_pixel_clock_parameters(pipe_ctx, 
_ctx->stream_res.pix_clk_params);
pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
@@ -734,8 +734,6 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct 
pipe_ctx *pipe_ctx)
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
_ctx->stream->bit_depth_params);
pipe_ctx->stream->clamping.pixel_encoding = 
pipe_ctx->stream->timing.pixel_encoding;
-
-   return DC_OK;
 }
 
 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, 
unsigned int underlay_idx)
@@ -754,7 +752,6 @@ static enum dc_status build_mapped_resource(
struct dc_state *context,
struct dc_stream_state *stream)
 {
-   enum dc_status status = DC_OK;
struct pipe_ctx *pipe_ctx = 
resource_get_head_pipe_for_stream(>res_ctx, stream);
 
if (!pipe_ctx)
@@ -764,10 +761,7 @@ static enum dc_status build_mapped_resource(
dc->res_pool->underlay_pipe_index))
return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
 
-   status = dce110_resource_build_pipe_hw_param(pipe_ctx);
-
-   if (status != DC_OK)
-   return status;
+   dce110_resource_build_pipe_hw_param(pipe_ctx);
 
/* TODO: validate audio ASIC caps, encoder */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
index 5bb692d..e5f168c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
@@ -38,7 +38,7 @@ struct dce110_resource_pool {
struct resource_pool base;
 };
 
-enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
+void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
 
 struct resource_pool *dce110_create_resource_pool(
uint8_t num_virtual_links,
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 11902a2..663e0a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -704,16 +704,12 @@ static enum dc_status build_mapped_resource(
struct dc_state *context,
struct dc_stream_state *stream)
 {
-   enum dc_status status = DC_OK;
struct pipe_ctx *pipe_ctx = 
resource_get_head_pipe_for_stream(>res_ctx, stream);
 
if (!pipe_ctx)
return DC_ERROR_UNEXPECTED;
 
-   status = dce110_resource_build_pipe_hw_param(pipe_ctx);
-
-   if (status != DC_OK)
-   return status;
+   dce110_resource_build_pipe_hw_param(pipe_ctx);
 
resource_build_info_frame(pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index c6571a9..9c18efd 100644
--- 

[PATCH 4/9] amdgpu/dc: remove pointless returns in the i2caux constructor paths.

[Dave Airlie]

From: Dave Airlie 

There was lots of return true, and error checking that was never used
in these paths.

Just remove it all.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c |  6 ++--
 drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h |  2 +-
 .../amd/display/dc/i2caux/dce100/i2caux_dce100.c   | 21 +-
 .../display/dc/i2caux/dce110/aux_engine_dce110.c   | 20 +++---
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.c| 24 ++--
 .../dc/i2caux/dce110/i2c_hw_engine_dce110.h|  4 ---
 .../dc/i2caux/dce110/i2c_sw_engine_dce110.c| 20 +++---
 .../amd/display/dc/i2caux/dce110/i2caux_dce110.c   | 30 ++--
 .../amd/display/dc/i2caux/dce110/i2caux_dce110.h   |  2 +-
 .../amd/display/dc/i2caux/dce112/i2caux_dce112.c   | 30 ++--
 .../amd/display/dc/i2caux/dce120/i2caux_dce120.c   | 21 +-
 .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c  | 32 --
 .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c  | 17 +++-
 .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 19 +++--
 .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 21 +-
 .../display/dc/i2caux/diagnostics/i2caux_diag.c| 20 +++---
 drivers/gpu/drm/amd/display/dc/i2caux/engine.h |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/engine_base.c|  3 +-
 drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c |  7 ++---
 drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h |  2 +-
 .../amd/display/dc/i2caux/i2c_generic_hw_engine.c  |  6 ++--
 .../amd/display/dc/i2caux/i2c_generic_hw_engine.h  |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c  |  6 ++--
 .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h  |  2 +-
 .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c  | 17 +++-
 .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h  |  2 +-
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c |  4 +--
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h |  2 +-
 28 files changed, 100 insertions(+), 244 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
index 3c9608c..fc7a7d4 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
@@ -555,15 +555,13 @@ bool dal_aux_engine_submit_request(
return result;
 }
 
-bool dal_aux_engine_construct(
+void dal_aux_engine_construct(
struct aux_engine *engine,
struct dc_context *ctx)
 {
-   if (!dal_i2caux_construct_engine(>base, ctx))
-   return false;
+   dal_i2caux_construct_engine(>base, ctx);
engine->delay = 0;
engine->max_defer_write_retry = 0;
-   return true;
 }
 
 void dal_aux_engine_destruct(
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
index 40b2028..8e71324 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
@@ -100,7 +100,7 @@ struct aux_engine {
bool acquire_reset;
 };
 
-bool dal_aux_engine_construct(
+void dal_aux_engine_construct(
struct aux_engine *engine,
struct dc_context *ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
index c45a2ee..e8d3781 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
@@ -95,18 +95,11 @@ struct i2caux *dal_i2caux_dce100_create(
return NULL;
}
 
-   if (dal_i2caux_dce110_construct(
-   i2caux_dce110,
-   ctx,
-   dce100_aux_regs,
-   dce100_hw_engine_regs,
-   _shift,
-   _mask))
-   return _dce110->base;
-
-   ASSERT_CRITICAL(false);
-
-   kfree(i2caux_dce110);
-
-   return NULL;
+   dal_i2caux_dce110_construct(i2caux_dce110,
+   ctx,
+   dce100_aux_regs,
+   dce100_hw_engine_regs,
+   _shift,
+   _mask);
+   return _dce110->base;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
index 4b673b4..0c4bbc1 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
@@ -426,22 +426,16 @@ static const struct engine_funcs engine_funcs = {
.acquire = dal_aux_engine_acquire,
 };
 
-static bool construct(
+static void construct(
struct aux_engine_dce110 *engine,
const struct 

[PATCH 3/9] amdgpu/dc: make some audio functions return void

[Dave Airlie]

From: Dave Airlie 

There is no need to check for these pointers being valid
at this level. Check earlier if required.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 198f453..6e94028 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -703,14 +703,11 @@ void dce_aud_az_configure(
 */
 
 /* search pixel clock value for Azalia HDMI Audio */
-static bool get_azalia_clock_info_hdmi(
+static void get_azalia_clock_info_hdmi(
uint32_t crtc_pixel_clock_in_khz,
uint32_t actual_pixel_clock_in_khz,
struct azalia_clock_info *azalia_clock_info)
 {
-   if (azalia_clock_info == NULL)
-   return false;
-
/* audio_dto_phase= 24 * 10,000;
 *   24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase =
@@ -720,18 +717,13 @@ static bool get_azalia_clock_info_hdmi(
 *  [khz] -> [100Hz] */
azalia_clock_info->audio_dto_module =
actual_pixel_clock_in_khz * 10;
-
-   return true;
 }
 
-static bool get_azalia_clock_info_dp(
+static void get_azalia_clock_info_dp(
uint32_t requested_pixel_clock_in_khz,
const struct audio_pll_info *pll_info,
struct azalia_clock_info *azalia_clock_info)
 {
-   if (pll_info == NULL || azalia_clock_info == NULL)
-   return false;
-
/* Reported dpDtoSourceClockInkhz value for
 * DCE8 already adjusted for SS, do not need any
 * adjustment here anymore
@@ -745,8 +737,6 @@ static bool get_azalia_clock_info_dp(
 *  [khz] ->[100Hz] */
azalia_clock_info->audio_dto_module =
pll_info->dp_dto_source_clock_in_khz * 10;
-
-   return true;
 }
 
 void dce_aud_wall_dto_setup(
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/9] amdgpu/dc: make program_regamma_pwl return void

[Dave Airlie]

From: Dave Airlie 

The return value was unused.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c   | 4 +---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h   | 2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 4 +---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +---
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h| 2 +-
 6 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index c40d2e9..ae32af3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1375,7 +1375,7 @@ static void regamma_config_regions_and_segments(
 
 
 
-bool dce110_opp_program_regamma_pwl(
+void dce110_opp_program_regamma_pwl(
struct transform *xfm,
const struct pwl_params *params)
 {
@@ -1386,8 +1386,6 @@ bool dce110_opp_program_regamma_pwl(
 
/* Program PWL */
program_pwl(xfm_dce, params);
-
-   return true;
 }
 
 void dce110_opp_power_on_regamma_lut(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
index e1f1e51..bfc94b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
@@ -506,7 +506,7 @@ void dce110_opp_power_on_regamma_lut(
struct transform *xfm,
bool power_on);
 
-bool dce110_opp_program_regamma_pwl(
+void dce110_opp_program_regamma_pwl(
struct transform *xfm,
const struct pwl_params *params);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index c86105b..e98ed30 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -490,7 +490,7 @@ static void program_pwl(struct dce_transform *xfm_dce,
}
 }
 
-bool dce110_opp_program_regamma_pwl_v(
+void dce110_opp_program_regamma_pwl_v(
struct transform *xfm,
const struct pwl_params *params)
 {
@@ -512,8 +512,6 @@ bool dce110_opp_program_regamma_pwl_v(
 
/* Power return to auto back */
power_on_lut(xfm, false, false, true);
-
-   return true;
 }
 
 void dce110_opp_power_on_regamma_lut_v(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
index eeed3b9..b707802 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
@@ -43,7 +43,7 @@ void dce110_opp_v_set_csc_adjustment(
const struct out_csc_color_matrix *tbl_entry);
 
 
-bool dce110_opp_program_regamma_pwl_v(
+void dce110_opp_program_regamma_pwl_v(
struct transform *xfm,
const struct pwl_params *params);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index ac03b04..8607ab2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -183,7 +183,7 @@ void dpp_reset(struct transform *xfm_base)
 
 
 
-static bool dcn10_dpp_cm_set_regamma_pwl(
+static void dcn10_dpp_cm_set_regamma_pwl(
struct transform *xfm_base, const struct pwl_params *params)
 {
struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
@@ -198,8 +198,6 @@ static bool dcn10_dpp_cm_set_regamma_pwl(
 
dcn10_dpp_cm_program_regamma_lut(
xfm_base, params->rgb_resulted, params->hw_points_num);
-
-   return true;
 }
 
 static void dcn10_dpp_cm_set_regamma_mode(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 9d4a3a0..785d397 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -213,7 +213,7 @@ struct transform_funcs {
struct transform *xfm,
const struct pwl_params *params);
 
-   bool (*opp_program_regamma_pwl)(
+   void (*opp_program_regamma_pwl)(
struct transform *xfm, const struct pwl_params *params);
 
void (*opp_set_regamma_mode)(
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/9] amdgpu/dc: make get_audio_clock_info return void.

[Dave Airlie]

From: Dave Airlie 

This function never returned false under any sane circumstances.

Signed-off-by: Dave Airlie 
---
 .../drm/amd/display/dc/dce/dce_stream_encoder.c| 75 ++
 1 file changed, 34 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index b2add58..a09727f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -1238,7 +1238,7 @@ uint32_t calc_max_audio_packets_per_line(
return max_packets_per_line;
 }
 
-bool get_audio_clock_info(
+void get_audio_clock_info(
enum dc_color_depth color_depth,
uint32_t crtc_pixel_clock_in_khz,
uint32_t actual_pixel_clock_in_khz,
@@ -1249,9 +1249,6 @@ bool get_audio_clock_info(
uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
uint32_t audio_array_size;
 
-   if (audio_clock_info == NULL)
-   return false; /* should not happen */
-
switch (color_depth) {
case COLOR_DEPTH_161616:
clock_info = audio_clock_info_table_48bpc;
@@ -1280,7 +1277,7 @@ bool get_audio_clock_info(
crtc_pixel_clock_in_10khz) {
/* match found */
*audio_clock_info = clock_info[index];
-   return true;
+   return;
}
}
}
@@ -1300,8 +1297,6 @@ bool get_audio_clock_info(
audio_clock_info->n_32khz = 4096;
audio_clock_info->n_44khz = 6272;
audio_clock_info->n_48khz = 6144;
-
-   return true;
 }
 
 static void dce110_se_audio_setup(
@@ -1362,40 +1357,38 @@ static void dce110_se_setup_hdmi_audio(
HDMI_ACR_AUDIO_PRIORITY, 0);
 
/* Program audio clock sample/regeneration parameters */
-   if (get_audio_clock_info(
-   crtc_info->color_depth,
-   crtc_info->requested_pixel_clock,
-   crtc_info->calculated_pixel_clock,
-   _clock_info)) {
-   dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
-   "\n%s:Input::requested_pixel_clock = %d"\
-   "calculated_pixel_clock = %d \n", __func__,\
-   crtc_info->requested_pixel_clock,\
-   crtc_info->calculated_pixel_clock);
-
-   /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-   REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, 
audio_clock_info.cts_32khz);
-
-   /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-   REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, 
audio_clock_info.n_32khz);
-
-   /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-   REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, 
audio_clock_info.cts_44khz);
-
-   /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-   REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, 
audio_clock_info.n_44khz);
-
-   /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-   REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, 
audio_clock_info.cts_48khz);
-
-   /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-   REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, 
audio_clock_info.n_48khz);
-
-   /* Video driver cannot know in advance which sample rate will
-   be used by HD Audio driver
-   HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-   programmed below in interruppt callback */
-   } /* if */
+   get_audio_clock_info(crtc_info->color_depth,
+crtc_info->requested_pixel_clock,
+crtc_info->calculated_pixel_clock,
+_clock_info);
+   dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
+   "\n%s:Input::requested_pixel_clock = %d"\
+   "calculated_pixel_clock = %d \n", __func__, \
+   crtc_info->requested_pixel_clock,   \
+   crtc_info->calculated_pixel_clock);
+
+   /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
+   REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
+
+   /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
+   REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
+
+   /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
+   REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
+
+   /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
+   REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
+
+   /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
+   REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
+
+   /* 

Re: global data in display/dc/dce/dce_abm.c

[Cyr, Aric]

Hi Dave,

Agreed, those should probably be per adapter. We'll take a look and fix them 
up. Thanks for pointing them out.

Regards,
Aric

From: Wentland, Harry
Sent: Thursday, September 28, 2017 8:29:58 PM
To: Dave Airlie; amd-gfx mailing list; Cyr, Aric; Koo, Anthony
Subject: Re: global data in display/dc/dce/dce_abm.c

On 2017-09-28 08:24 PM, Dave Airlie wrote:
> On 29 September 2017 at 10:18, Dave Airlie  wrote:
>> Hi Harry,
>>
>> stored_backlight_registers is a global static struct in bss segment,
>> it should probably be per device.
>
> There is also cached_wait_loop_number in
> amd/display/dc/dce/dce_dmcu.c
>

Thanks for spotting these. We probably want to fix them up.

I think both are used for embedded panels only which is why we haven't
noticed this being a problem.

Aric, Anthony, thoughts? Can you provide a patch to fix these?

Harry

> Dave.
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 6/6] amdgpu/dc: make dce80 timing generator construct return void.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 ++--
 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c | 7 +--
 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h | 2 +-
 3 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index db8afb6..5e00ca6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -404,12 +404,8 @@ static struct timing_generator 
*dce80_timing_generator_create(
if (!tg110)
return NULL;
 
-   if (dce80_timing_generator_construct(tg110, ctx, instance, offsets))
-   return >base;
-
-   BREAK_TO_DEBUGGER();
-   kfree(tg110);
-   return NULL;
+   dce80_timing_generator_construct(tg110, ctx, instance, offsets);
+   return >base;
 }
 
 static struct output_pixel_processor *dce80_opp_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 179a6d6..2658948 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -152,15 +152,12 @@ static const struct timing_generator_funcs dce80_tg_funcs 
= {
dce80_timing_generator_enable_advanced_request,
 };
 
-bool dce80_timing_generator_construct(
+void dce80_timing_generator_construct(
struct dce110_timing_generator *tg110,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
 {
-   if (!tg110)
-   return false;
-
tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->base.inst = instance;
tg110->offsets = *offsets;
@@ -177,8 +174,6 @@ bool dce80_timing_generator_construct(
tg110->min_h_blank = 56;
tg110->min_h_front_porch = 4;
tg110->min_h_back_porch = 4;
-
-   return true;
 }
 
 void dce80_timing_generator_enable_advanced_request(
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
index 6e4722a..9cebb24 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h
@@ -30,7 +30,7 @@
 #include "../include/grph_object_id.h"
 
 /* DCE8.0 implementation inherits from DCE11.0 */
-bool dce80_timing_generator_construct(
+void dce80_timing_generator_construct(
struct dce110_timing_generator *tg,
struct dc_context *ctx,
uint32_t instance,
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/6] amdgpu/dc: make timing generator constructor return void.

[Dave Airlie]

From: Dave Airlie 

This can't fail as is.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 9 ++---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 8 ++--
 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 7 +--
 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h | 2 +-
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 8 ++--
 5 files changed, 8 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 9a75bde..6765162 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -375,13 +375,8 @@ static struct timing_generator 
*dce100_timing_generator_create(
if (!tg110)
return NULL;
 
-   if (dce110_timing_generator_construct(tg110, ctx, instance,
-   offsets))
-   return >base;
-
-   BREAK_TO_DEBUGGER();
-   kfree(tg110);
-   return NULL;
+   dce110_timing_generator_construct(tg110, ctx, instance, offsets);
+   return >base;
 }
 
 static struct stream_encoder *dce100_stream_encoder_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 787e20e..3d91f2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -410,12 +410,8 @@ static struct timing_generator 
*dce110_timing_generator_create(
if (!tg110)
return NULL;
 
-   if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
-   return >base;
-
-   BREAK_TO_DEBUGGER();
-   kfree(tg110);
-   return NULL;
+   dce110_timing_generator_construct(tg110, ctx, instance, offsets);
+   return >base;
 }
 
 static struct stream_encoder *dce110_stream_encoder_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 7f93d6d..bcd544d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1941,15 +1941,12 @@ static const struct timing_generator_funcs 
dce110_tg_funcs = {
.arm_vert_intr = dce110_arm_vert_intr,
 };
 
-bool dce110_timing_generator_construct(
+void dce110_timing_generator_construct(
struct dce110_timing_generator *tg110,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
 {
-   if (!tg110)
-   return false;
-
tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->base.inst = instance;
 
@@ -1966,6 +1963,4 @@ bool dce110_timing_generator_construct(
tg110->min_h_blank = 56;
tg110->min_h_front_porch = 4;
tg110->min_h_back_porch = 4;
-
-   return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index a5d63c6..bd8d0ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -118,7 +118,7 @@ struct dce110_timing_generator {
 #define DCE110TG_FROM_TG(tg)\
container_of(tg, struct dce110_timing_generator, base)
 
-bool dce110_timing_generator_construct(
+void dce110_timing_generator_construct(
struct dce110_timing_generator *tg,
struct dc_context *ctx,
uint32_t instance,
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 4e2ed34..a06a685 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -415,12 +415,8 @@ static struct timing_generator 
*dce112_timing_generator_create(
if (!tg110)
return NULL;
 
-   if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
-   return >base;
-
-   BREAK_TO_DEBUGGER();
-   kfree(tg110);
-   return NULL;
+   dce110_timing_generator_construct(tg110, ctx, instance, offsets);
+   return >base;
 }
 
 static struct stream_encoder *dce112_stream_encoder_create(
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/6] amdgpu/dc: make link encoder construct void.

[Dave Airlie]

From: Dave Airlie 

This only ever returned true.

Signed-off-by: Dave Airlie 
---
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c   |  4 +---
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h   |  2 +-
 .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 21 +++--
 .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 21 +++--
 .../gpu/drm/amd/display/dc/dce112/dce112_resource.c | 21 +++--
 .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 20 +++-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 21 +++--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 20 +++-
 8 files changed, 44 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 2ce730d..37aeddf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -914,7 +914,7 @@ bool dce110_link_encoder_validate_dp_output(
return false;
 }
 
-bool dce110_link_encoder_construct(
+void dce110_link_encoder_construct(
struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data,
const struct encoder_feature_support *enc_features,
@@ -1013,8 +1013,6 @@ bool dce110_link_encoder_construct(
bp_cap_info.DP_HBR3_EN;
enc110->base.features.flags.bits.HDMI_6GB_EN = 
bp_cap_info.HDMI_6GB_EN;
}
-
-   return true;
 }
 
 bool dce110_link_encoder_validate_output_with_stream(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 5960fb9..be0a45b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -168,7 +168,7 @@ struct dce110_link_encoder {
 };
 
 
-bool dce110_link_encoder_construct(
+void dce110_link_encoder_construct(
struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data,
const struct encoder_feature_support *enc_features,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 7596133..0084645 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -528,20 +528,13 @@ struct link_encoder *dce100_link_encoder_create(
if (!enc110)
return NULL;
 
-   if (dce110_link_encoder_construct(
-   enc110,
-   enc_init_data,
-   _enc_feature,
-   _enc_regs[enc_init_data->transmitter],
-   _enc_aux_regs[enc_init_data->channel - 1],
-   _enc_hpd_regs[enc_init_data->hpd_source])) {
-
-   return >base;
-   }
-
-   BREAK_TO_DEBUGGER();
-   kfree(enc110);
-   return NULL;
+   dce110_link_encoder_construct(enc110,
+ enc_init_data,
+ _enc_feature,
+ 
_enc_regs[enc_init_data->transmitter],
+ _enc_aux_regs[enc_init_data->channel 
- 1],
+ 
_enc_hpd_regs[enc_init_data->hpd_source]);
+   return >base;
 }
 
 struct output_pixel_processor *dce100_opp_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 9faf2fe..2c24f2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -567,20 +567,13 @@ static struct link_encoder *dce110_link_encoder_create(
if (!enc110)
return NULL;
 
-   if (dce110_link_encoder_construct(
-   enc110,
-   enc_init_data,
-   _enc_feature,
-   _enc_regs[enc_init_data->transmitter],
-   _enc_aux_regs[enc_init_data->channel - 1],
-   _enc_hpd_regs[enc_init_data->hpd_source])) {
-
-   return >base;
-   }
-
-   BREAK_TO_DEBUGGER();
-   kfree(enc110);
-   return NULL;
+   dce110_link_encoder_construct(enc110,
+ enc_init_data,
+ _enc_feature,
+ 
_enc_regs[enc_init_data->transmitter],
+ _enc_aux_regs[enc_init_data->channel 
- 1],
+ 
_enc_hpd_regs[enc_init_data->hpd_source]);
+   return >base;
 }
 
 static struct output_pixel_processor *dce110_opp_create(
diff --git 

RE: some more powerplay/pwr virus size reduction patches

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Dave Airlie
> Sent: Thursday, September 28, 2017 10:44 PM
> To: amd-gfx mailing list; Alex Deucher
> Subject: some more powerplay/pwr virus size reduction patches
> 
> I don't think these patches will land on the list due to size.
> 
> https://cgit.freedesktop.org/~airlied/linux/log/?h=amdgpu-non-dc-cleanups
> 
> The top 3 patches on that branch.
> 
> These reduce the size of the driver by about 60k, by redesigning the
> pwrvirus upload code to use less space. I did notice the fiji and
> polaris 10 across the 6 data blocks uploaded, there is only a single
> bit different. So it might be possible to further merge these.
> 
> I'd really like someone from the powermangement side to take a look if
> possible, it might be the one bit doesn't matter, and we could merge
> these for fiji and polaris and save another 40k.

Rex, can you take a look?

Thanks,

Alex

> 
> Dave.
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create

[Chunming Zhou]

On 2017年09月13日 04:42, Marek Olšák wrote:

From: Marek Olšák 

For amdgpu.

drm_syncobj_create is renamed to drm_syncobj_create_as_handle, and new
helpers drm_syncobj_create and drm_syncobj_get_handle are added.

Signed-off-by: Marek Olšák 
---
  drivers/gpu/drm/drm_syncobj.c | 49 +++
  include/drm/drm_syncobj.h |  4 
  2 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 0422b8c..0bb1741 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
  }
  EXPORT_SYMBOL(drm_syncobj_free);
  
-static int drm_syncobj_create(struct drm_file *file_private,

- u32 *handle, uint32_t flags)
You can add a new parameter for passing dma fence, then in patch3, you 
can directly use it for AMDGPU_FENCE_TO HANDLE_GET_SYNCOBJ.


otherwise the set looks good to me.

Regards,
David Zhou


+/**
+ * drm_syncobj_create - create a new syncobj
+ * @out_syncobj: returned syncobj
+ * @flags: DRM_SYNCOBJ_* flags
+ * @fence: if non-NULL, the syncobj will represent this fence
+ */
+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
+  struct dma_fence *fence)
  {
int ret;
struct drm_syncobj *syncobj;
@@ -284,6 +290,25 @@ static int drm_syncobj_create(struct drm_file 
*file_private,
}
}
  
+	if (fence)

+   drm_syncobj_replace_fence(syncobj, fence);
+
+   *out_syncobj = syncobj;
+   return 0;
+}
+EXPORT_SYMBOL(drm_syncobj_create);
+
+/**
+ * drm_syncobj_get_handle - get a handle from a syncobj
+ */
+int drm_syncobj_get_handle(struct drm_file *file_private,
+  struct drm_syncobj *syncobj, u32 *handle)
+{
+   int ret;
+
+   /* take a reference to put in the idr */
+   drm_syncobj_get(syncobj);
+
idr_preload(GFP_KERNEL);
spin_lock(_private->syncobj_table_lock);
ret = idr_alloc(_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT);
@@ -299,6 +324,22 @@ static int drm_syncobj_create(struct drm_file 
*file_private,
*handle = ret;
return 0;
  }
+EXPORT_SYMBOL(drm_syncobj_get_handle);
+
+static int drm_syncobj_create_as_handle(struct drm_file *file_private,
+   u32 *handle, uint32_t flags)
+{
+   int ret;
+   struct drm_syncobj *syncobj;
+
+   ret = drm_syncobj_create(, flags, NULL);
+   if (ret)
+   return ret;
+
+   ret = drm_syncobj_get_handle(file_private, syncobj, handle);
+   drm_syncobj_put(syncobj);
+   return ret;
+}
  
  static int drm_syncobj_destroy(struct drm_file *file_private,

   u32 handle)
@@ -522,8 +563,8 @@ drm_syncobj_create_ioctl(struct drm_device *dev, void *data,
if (args->flags & ~DRM_SYNCOBJ_CREATE_SIGNALED)
return -EINVAL;
  
-	return drm_syncobj_create(file_private,

- >handle, args->flags);
+   return drm_syncobj_create_as_handle(file_private,
+   >handle, args->flags);
  }
  
  int

diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index c00fee5..e7f0035 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -136,5 +136,9 @@ int drm_syncobj_find_fence(struct drm_file *file_private,
   u32 handle,
   struct dma_fence **fence);
  void drm_syncobj_free(struct kref *kref);
+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
+  struct dma_fence *fence);
+int drm_syncobj_get_handle(struct drm_file *file_private,
+  struct drm_syncobj *syncobj, u32 *handle);
  
  #endif


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

some more powerplay/pwr virus size reduction patches

[Dave Airlie]

I don't think these patches will land on the list due to size.

https://cgit.freedesktop.org/~airlied/linux/log/?h=amdgpu-non-dc-cleanups

The top 3 patches on that branch.

These reduce the size of the driver by about 60k, by redesigning the
pwrvirus upload code to use less space. I did notice the fiji and
polaris 10 across the 6 data blocks uploaded, there is only a single
bit different. So it might be possible to further merge these.

I'd really like someone from the powermangement side to take a look if
possible, it might be the one bit doesn't matter, and we could merge
these for fiji and polaris and save another 40k.

Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/3] amdgpu/pp: use array_size to size the pwrvirus tables.

[Dave Airlie]

From: Dave Airlie 

This avoids fragile hardcoding of array size.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h   | 3 +--
 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h  | 5 +
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c  | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +-
 4 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h 
b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
index 243de29..e202e56 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h
@@ -35,8 +35,7 @@ struct PWR_Command_Table
 };
 typedef struct PWR_Command_Table PWR_Command_Table;
 
-#define PWR_VIRUS_TABLE_SIZE  10243
-static const PWR_Command_Table PwrVirusTable[PWR_VIRUS_TABLE_SIZE] =
+static const PWR_Command_Table PwrVirusTable[] =
 {
 { 0x100100b6, mmPCIE_INDEX   },
 { 0x, mmPCIE_DATA},
diff --git a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h 
b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
index 7603986..8edd3e7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
@@ -36,10 +36,7 @@ struct PWR_Command_Table {
 
 typedef struct PWR_Command_Table PWR_Command_Table;
 
-
-#define PWR_VIRUS_TABLE_SIZE  10031
-
-static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
+static const PWR_Command_Table pwr_virus_table[] = {
{ 0x, mmRLC_CNTL },
{ 0x0002, mmRLC_SRM_CNTL },
{ 0x1500, mmCP_ME_CNTL   },
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 3820fe8..289006b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -167,7 +167,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 
const PWR_Command_Table *pvirus = PwrVirusTable;
 
-   for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
+   for (i = 0; i < ARRAY_SIZE(PwrVirusTable); i++) {
reg  = pvirus->reg;
data = pvirus->data;
if (reg != 0x)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index b73b2b4..f039320 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -68,7 +68,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
 
const PWR_Command_Table *pvirus = pwr_virus_table;
 
-   for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
+   for (i = 0; i < ARRAY_SIZE(pwr_virus_table); i++) {
reg  = pvirus->reg;
data = pvirus->data;
if (reg != 0x) {
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amd/sched: signal and free remaining fences in amd_sched_entity_fini

[Chunming Zhou]

On 2017年09月28日 22:55, Nicolai Hähnle wrote:

From: Nicolai Hähnle 

Highly concurrent Piglit runs can trigger a race condition where a pending
SDMA job on a buffer object is never executed because the corresponding
process is killed (perhaps due to a crash). Since the job's fences were
never signaled, the buffer object was effectively leaked. Worse, the
buffer was stuck wherever it happened to be at the time, possibly in VRAM.

Indeed good catch.

Cheers,
David Zhou


The symptom was user space processes stuck in interruptible waits with
kernel stacks like:

 [] dma_fence_default_wait+0x112/0x250
 [] dma_fence_wait_timeout+0x39/0xf0
 [] reservation_object_wait_timeout_rcu+0x1c2/0x300
 [] ttm_bo_cleanup_refs_and_unlock+0xff/0x1a0 [ttm]
 [] ttm_mem_evict_first+0xba/0x1a0 [ttm]
 [] ttm_bo_mem_space+0x341/0x4c0 [ttm]
 [] ttm_bo_validate+0xd4/0x150 [ttm]
 [] ttm_bo_init_reserved+0x2ed/0x420 [ttm]
 [] amdgpu_bo_create_restricted+0x1f3/0x470 [amdgpu]
 [] amdgpu_bo_create+0xda/0x220 [amdgpu]
 [] amdgpu_gem_object_create+0xaa/0x140 [amdgpu]
 [] amdgpu_gem_create_ioctl+0x97/0x120 [amdgpu]
 [] drm_ioctl+0x1fa/0x480 [drm]
 [] amdgpu_drm_ioctl+0x4f/0x90 [amdgpu]
 [] do_vfs_ioctl+0xa3/0x5f0
 [] SyS_ioctl+0x79/0x90
 [] entry_SYSCALL_64_fastpath+0x1e/0xad
 [] 0x

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 54eb77cffd9b..32a99e980d78 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -220,22 +220,27 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler 
*sched,
amd_sched_entity_is_idle(entity));
amd_sched_rq_remove_entity(rq, entity);
if (r) {
struct amd_sched_job *job;
  
  		/* Park the kernel for a moment to make sure it isn't processing

 * our enity.
 */
kthread_park(sched->thread);
kthread_unpark(sched->thread);
-   while (kfifo_out(>job_queue, , sizeof(job)))
+   while (kfifo_out(>job_queue, , sizeof(job))) {
+   struct amd_sched_fence *s_fence = job->s_fence;
+   amd_sched_fence_scheduled(s_fence);
+   amd_sched_fence_finished(s_fence);
+   dma_fence_put(_fence->finished);
sched->ops->free_job(job);
+   }
  
  	}

kfifo_free(>job_queue);
  }
  
  static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb)

  {
struct amd_sched_entity *entity =
container_of(cb, struct amd_sched_entity, cb);
entity->dependency = NULL;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper

[Chunming Zhou]

On 2017年09月29日 06:10, Marek Olšák wrote:

From: Marek Olšák 

---
  include/drm/drm.h | 24 
  xf86drm.c | 22 ++
  xf86drm.h |  3 +++
  3 files changed, 49 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4da1667 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -687,38 +687,57 @@ struct drm_prime_handle {
  
  	/** Flags.. only applicable for handle->fd */

__u32 flags;
  
  	/** Returned dmabuf file descriptor */

__s32 fd;
  };
  
  struct drm_syncobj_create {

__u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
  };
  
  struct drm_syncobj_destroy {

__u32 handle;
__u32 pad;
  };
  
  #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)

  #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)

Typo for '(1 << 1)' ?

With that fixes, the set is Reviewed-by: Chunming Zhou 


  struct drm_syncobj_handle {
__u32 handle;
__u32 flags;
  
  	__s32 fd;

__u32 pad;
  };
  
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)

+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+   __u64 handles;
+   /* absolute timeout */
+   __s64 timeout_nsec;
+   __u32 count_handles;
+   __u32 flags;
+   __u32 first_signaled; /* only valid when not waiting all */
+   __u32 pad;
+};
+
+struct drm_syncobj_array {
+   __u64 handles;
+   __u32 count_handles;
+   __u32 pad;
+};
+
  #if defined(__cplusplus)
  }
  #endif
  
  #include "drm_mode.h"
  
  #if defined(__cplusplus)

  extern "C" {
  #endif
  
@@ -827,20 +846,23 @@ extern "C" {

  #define DRM_IOCTL_MODE_OBJ_SETPROPERTYDRM_IOWR(0xBA, struct 
drm_mode_obj_set_property)
  #define DRM_IOCTL_MODE_CURSOR2DRM_IOWR(0xBB, struct 
drm_mode_cursor2)
  #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
  #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct 
drm_mode_create_blob)
  #define DRM_IOCTL_MODE_DESTROYPROPBLOBDRM_IOWR(0xBE, struct 
drm_mode_destroy_blob)
  
  #define DRM_IOCTL_SYNCOBJ_CREATE	DRM_IOWR(0xBF, struct drm_syncobj_create)

  #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct 
drm_syncobj_destroy)
  #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FDDRM_IOWR(0xC1, struct 
drm_syncobj_handle)
  #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLEDRM_IOWR(0xC2, struct 
drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESETDRM_IOWR(0xC4, struct 
drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL   DRM_IOWR(0xC5, struct drm_syncobj_array)
  
  /**

   * Device specific ioctls should only be in their respective headers
   * The device specific ioctl range is from 0x40 to 0x9f.
   * Generic IOCTLS restart at 0xA0.
   *
   * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
   * drmCommandReadWrite().
   */
  #define DRM_COMMAND_BASE0x40
@@ -869,20 +891,21 @@ struct drm_event {
  struct drm_event_vblank {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 sequence;
__u32 crtc_id; /* 0 on older kernels that do not support this */
  };
  
  /* typedef area */

+#ifndef __KERNEL__
  typedef struct drm_clip_rect drm_clip_rect_t;
  typedef struct drm_drawable_info drm_drawable_info_t;
  typedef struct drm_tex_region drm_tex_region_t;
  typedef struct drm_hw_lock drm_hw_lock_t;
  typedef struct drm_version drm_version_t;
  typedef struct drm_unique drm_unique_t;
  typedef struct drm_list drm_list_t;
  typedef struct drm_block drm_block_t;
  typedef struct drm_control drm_control_t;
  typedef enum drm_map_type drm_map_type_t;
@@ -910,16 +933,17 @@ typedef struct drm_draw drm_draw_t;
  typedef struct drm_update_draw drm_update_draw_t;
  typedef struct drm_auth drm_auth_t;
  typedef struct drm_irq_busid drm_irq_busid_t;
  typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
  
  typedef struct drm_agp_buffer drm_agp_buffer_t;

  typedef struct drm_agp_binding drm_agp_binding_t;
  typedef struct drm_agp_info drm_agp_info_t;
  typedef struct drm_scatter_gather drm_scatter_gather_t;
  typedef struct drm_set_version drm_set_version_t;
+#endif
  
  #if defined(__cplusplus)

  }
  #endif
  
  #endif

diff --git a/xf86drm.c b/xf86drm.c
index 6ea0112..8a32717 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4218,10 +4218,32 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, 
int *sync_file_fd)
  memclear(args);
  args.fd = -1;
  args.handle = handle;
  args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE;
  ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
  if (ret)
return ret;
  *sync_file_fd = args.fd;
  return 0;
  }
+
+int drmSyncobjWait(int fd, 

Re: [PATCH] amdgpu/dc: drop dc_ver char

[Harry Wentland]

On 2017-09-28 08:20 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This isn't referenced anywhere, and if it was it should be const.
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 7fd42fc..008f137 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -49,8 +49,6 @@
>  #include "mem_input.h"
>  
>  
> -char dc_ver[] = DC_VER;
> -
>  
> /***
>   * Private functions
>   
> **/
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] amdgpu/dm: constify rgb formats.

[Harry Wentland]

On 2017-09-28 08:32 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index ef93852..61ccddd 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3062,7 +3062,7 @@ static const struct drm_plane_helper_funcs 
> dm_plane_helper_funcs = {
>   * plane capabilities, or initialize this array to all formats, so internal 
> drm
>   * check will succeed, and let DC to implement proper check
>   */
> -static uint32_t rgb_formats[] = {
> +static const uint32_t rgb_formats[] = {
>   DRM_FORMAT_RGB888,
>   DRM_FORMAT_XRGB,
>   DRM_FORMAT_ARGB,
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] amdgpu/dm: constify plane type.

[Harry Wentland]

On 2017-09-28 08:32 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  | 2 +-
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index b541ade..59e2e5d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -361,7 +361,7 @@ struct amdgpu_mode_info {
>   int num_dig; /* number of dig blocks */
>   int disp_priority;
>   const struct amdgpu_display_funcs *funcs;
> - enum drm_plane_type *plane_type;
> + const enum drm_plane_type *plane_type;
>  };
>  
>  #define AMDGPU_MAX_BL_LEVEL 0xFF
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 89442cc..ef93852 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -71,7 +71,7 @@
>  #include "i2caux_interface.h"
>  
>  
> -static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
> +static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_PRIMARY,
> @@ -80,14 +80,14 @@ static enum drm_plane_type 
> dm_plane_type_default[AMDGPU_MAX_PLANES] = {
>   DRM_PLANE_TYPE_PRIMARY,
>  };
>  
> -static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
> +static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
>  };
>  
> -static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
> +static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_PRIMARY,
>   DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu/nbio: use constant nbio_hdp_flush_reg structs.

[Dave Airlie]

From: Dave Airlie 

This removes the init path as well, since the init path
just did some constant init of some structs.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 38 +++---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 38 +++---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c | 15 --
 7 files changed, 38 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 508efc8..99a5b3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3583,7 +3583,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring 
*ring)
 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
u32 ref_and_mask, reg_mem_engine;
-   struct nbio_hdp_flush_reg *nbio_hf_reg;
+   const struct nbio_hdp_flush_reg *nbio_hf_reg;
 
if (ring->adev->flags & AMD_IS_APU)
nbio_hf_reg = _v7_0_hdp_flush_reg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 7723d7b..904a1ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -215,32 +215,28 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device 
*adev, u32 *flags)
*flags |= AMD_CG_SUPPORT_BIF_LS;
 }
 
-struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
+const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
+   .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
+   .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
+   .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+   .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+   .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+   .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
+   .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
+   .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
+   .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
+   .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
+   .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
+   .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
+   .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+   .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
+};
+
 const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
 };
 
-int nbio_v6_1_init(struct amdgpu_device *adev)
-{
-   nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 
0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
-   nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 
0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
-   nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
-
-   return 0;
-}
-
 void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
 {
uint32_t reg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index c5ca1e4..14ca8d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -26,7 +26,7 @@
 
 #include "soc15_common.h"
 
-extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
+extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
 extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
 int nbio_v6_1_init(struct amdgpu_device *adev);
 

Re: [PATCH] amdgpu/dm: constify yuv_formats.

[Harry Wentland]

On 2017-09-28 08:27 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index dba54c0..89442cc 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3073,7 +3073,7 @@ static uint32_t rgb_formats[] = {
>   DRM_FORMAT_ABGR2101010,
>  };
>  
> -static uint32_t yuv_formats[] = {
> +static const uint32_t yuv_formats[] = {
>   DRM_FORMAT_NV12,
>   DRM_FORMAT_NV21,
>  };
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/dc: static constify update_surface_trace_level

[Harry Wentland]

On 2017-09-28 08:23 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 008f137..c8235b0 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1172,7 +1172,7 @@ static struct dc_stream_status *stream_get_status(
>   return NULL;
>  }
>  
> -enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
> +static const enum surface_update_type update_surface_trace_level = 
> UPDATE_TYPE_FULL;
>  
>  void dc_update_planes_and_stream(struct dc *dc,
>   struct dc_surface_update *srf_updates, int surface_count,
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/2] amdgpu/dc: constify a bunch of dc structs.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 8 
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c| 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c   | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 3e9ff2f5..9031d22 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -51,7 +51,7 @@
clk_dce->base.ctx
 
 /* Max clock values for each state indexed by "enum clocks_state": */
-static struct state_dependent_clocks dce80_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
 /* ClocksStateInvalid - should not be used */
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
@@ -63,7 +63,7 @@ static struct state_dependent_clocks 
dce80_max_clks_by_state[] = {
 /* ClocksStatePerformance */
 { .display_clk_khz = 60, .pixel_clk_khz = 40 } };
 
-static struct state_dependent_clocks dce110_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
@@ -75,7 +75,7 @@ static struct state_dependent_clocks 
dce110_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 643000, .pixel_clk_khz = 40 } };
 
-static struct state_dependent_clocks dce112_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
@@ -87,7 +87,7 @@ static struct state_dependent_clocks 
dce112_max_clks_by_state[] = {
 /*ClocksStatePerformance*/
 { .display_clk_khz = 1132000, .pixel_clk_khz = 60 } };
 
-static struct state_dependent_clocks dce120_max_clks_by_state[] = {
+static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
 /*ClocksStateInvalid - should not be used*/
 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 6b5d594..a6f93a42 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -302,7 +302,7 @@ static const struct dce_opp_mask opp_mask = {
AUD_COMMON_REG_LIST(id)\
 }
 
-static struct dce_audio_registers audio_regs[] = {
+static const struct dce_audio_registers audio_regs[] = {
audio_regs(0),
audio_regs(1),
audio_regs(2),
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 58a070d..791c9b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1109,7 +1109,7 @@ static bool dce120_arm_vert_intr(
return true;
 }
 
-static struct timing_generator_funcs dce120_tg_funcs = {
+static const struct timing_generator_funcs dce120_tg_funcs = {
.validate_timing = dce120_tg_validate_timing,
.program_timing = dce120_tg_program_timing,
.enable_crtc = dce120_timing_generator_enable_crtc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 4876941..ac03b04 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -373,7 +373,7 @@ void ippn10_cnv_setup (
}
 }
 
-static struct transform_funcs dcn10_dpp_funcs = {
+static const struct transform_funcs dcn10_dpp_funcs = {
.transform_reset = dpp_reset,
.transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale,
.transform_get_optimal_number_of_taps = 
dpp_get_optimal_number_of_taps,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 2d3dd9a..7cd10cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1146,7 +1146,7 @@ void tgn10_read_otg_state(struct dcn10_timing_generator 
*tgn10,
 }
 
 
-static struct 

[PATCH 2/2] amdgpu/pp: constify soft_dummy_pp_table.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 485f7eb..afae32e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -790,7 +790,7 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
return pstate;
 }
 
-static unsigned char soft_dummy_pp_table[] = {
+static const unsigned char soft_dummy_pp_table[] = {
0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 
0x00, 0x6c, 0x00, 0x00,
0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 
0x80, 0x00, 0x00, 0x00,
0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 
0x9e, 0x00, 0x00, 0x00,
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/2] amdgpu/dm: constify plane type.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index b541ade..59e2e5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -361,7 +361,7 @@ struct amdgpu_mode_info {
int num_dig; /* number of dig blocks */
int disp_priority;
const struct amdgpu_display_funcs *funcs;
-   enum drm_plane_type *plane_type;
+   const enum drm_plane_type *plane_type;
 };
 
 #define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 89442cc..ef93852 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -71,7 +71,7 @@
 #include "i2caux_interface.h"
 
 
-static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
+static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
@@ -80,14 +80,14 @@ static enum drm_plane_type 
dm_plane_type_default[AMDGPU_MAX_PLANES] = {
DRM_PLANE_TYPE_PRIMARY,
 };
 
-static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
+static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 };
 
-static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
+static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] amdgpu/dm: constify rgb formats.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ef93852..61ccddd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3062,7 +3062,7 @@ static const struct drm_plane_helper_funcs 
dm_plane_helper_funcs = {
  * plane capabilities, or initialize this array to all formats, so internal drm
  * check will succeed, and let DC to implement proper check
  */
-static uint32_t rgb_formats[] = {
+static const uint32_t rgb_formats[] = {
DRM_FORMAT_RGB888,
DRM_FORMAT_XRGB,
DRM_FORMAT_ARGB,
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: global data in display/dc/dce/dce_abm.c

[Harry Wentland]

On 2017-09-28 08:24 PM, Dave Airlie wrote:
> On 29 September 2017 at 10:18, Dave Airlie  wrote:
>> Hi Harry,
>>
>> stored_backlight_registers is a global static struct in bss segment,
>> it should probably be per device.
> 
> There is also cached_wait_loop_number in
> amd/display/dc/dce/dce_dmcu.c
> 

Thanks for spotting these. We probably want to fix them up.

I think both are used for embedded panels only which is why we haven't
noticed this being a problem.

Aric, Anthony, thoughts? Can you provide a patch to fix these?

Harry

> Dave.
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu/dm: constify yuv_formats.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index dba54c0..89442cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3073,7 +3073,7 @@ static uint32_t rgb_formats[] = {
DRM_FORMAT_ABGR2101010,
 };
 
-static uint32_t yuv_formats[] = {
+static const uint32_t yuv_formats[] = {
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
 };
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: global data in display/dc/dce/dce_abm.c

[Dave Airlie]

On 29 September 2017 at 10:18, Dave Airlie  wrote:
> Hi Harry,
>
> stored_backlight_registers is a global static struct in bss segment,
> it should probably be per device.

There is also cached_wait_loop_number in
amd/display/dc/dce/dce_dmcu.c

Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu/dc: static constify update_surface_trace_level

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 008f137..c8235b0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1172,7 +1172,7 @@ static struct dc_stream_status *stream_get_status(
return NULL;
 }
 
-enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
+static const enum surface_update_type update_surface_trace_level = 
UPDATE_TYPE_FULL;
 
 void dc_update_planes_and_stream(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu/dc: drop dc_ver char

[Dave Airlie]

From: Dave Airlie 

This isn't referenced anywhere, and if it was it should be const.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7fd42fc..008f137 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -49,8 +49,6 @@
 #include "mem_input.h"
 
 
-char dc_ver[] = DC_VER;
-
 
/***
  * Private functions
  
**/
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

global data in display/dc/dce/dce_abm.c

[Dave Airlie]

Hi Harry,

stored_backlight_registers is a global static struct in bss segment,
it should probably be per device.

Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] [rfc] amdgfx/gfx: don't use static objects for de meta.

[Dave Airlie]

From: Dave Airlie 

This isn't safe if we have multiple GPUs plugged in, since
there is only one copy of this struct in the bss, just allocate
on stack, it's 108 bytes which should be safe.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index dfc10b1..57ac558 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7105,7 +7105,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring 
*ring)
 {
uint64_t de_payload_addr, gds_addr, csa_addr;
int cnt_de;
-   static union {
+   union {
struct vi_de_ib_state regular;
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index deeaee14..6373e00 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3825,7 +3825,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring 
*ring)
 
 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
 {
-   static struct v9_de_ib_state de_payload = {0};
+   struct v9_de_ib_state de_payload = {0};
uint64_t csa_addr, gds_addr;
int cnt;
 
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] amdgpu/soc15: make the pcie index/data registers constant.

[Dave Airlie]

From: Dave Airlie 

These don't seem to change at runtime, and the initialisers
are constant data. This could be improved by not selecting
the apu/non-apu path on each pcie read/write access.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 8 
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 8 
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 045988b..7723d7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -216,7 +216,10 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device 
*adev, u32 *flags)
 }
 
 struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
+const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
+   .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
+   .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
+};
 
 int nbio_v6_1_init(struct amdgpu_device *adev)
 {
@@ -235,9 +238,6 @@ int nbio_v6_1_init(struct amdgpu_device *adev)
nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = 
BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 
-   nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmPCIE_INDEX);
-   nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmPCIE_DATA);
-
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index 686e4b4..c5ca1e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -27,7 +27,7 @@
 #include "soc15_common.h"
 
 extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
+extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
 int nbio_v6_1_init(struct amdgpu_device *adev);
 u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
 uint32_t idx);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 11b70d6..b932b78 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -186,7 +186,10 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
 }
 
 struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = {
+   .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2),
+   .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)
+};
 
 int nbio_v7_0_init(struct amdgpu_device *adev)
 {
@@ -205,8 +208,5 @@ int nbio_v7_0_init(struct amdgpu_device *adev)
nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = 
GPU_HDP_FLUSH_DONE__SDMA0_MASK;
nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = 
GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 
-   nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmPCIE_INDEX2);
-   nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmPCIE_DATA2);
-
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
index 054ff49..21bad00 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -27,7 +27,7 @@
 #include "soc15_common.h"
 
 extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
 int nbio_v7_0_init(struct amdgpu_device *adev);
 u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
 uint32_t idx);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c2611ec..28294f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -101,7 +101,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 
reg)
 {
unsigned long flags, address, data;
u32 r;
-   struct nbio_pcie_index_data *nbio_pcie_id;
+   const struct nbio_pcie_index_data *nbio_pcie_id;
 
if (adev->flags & AMD_IS_APU)
nbio_pcie_id = _v7_0_pcie_index_data;
@@ -122,7 +122,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 
reg)
 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
unsigned long flags, address, data;
-   struct nbio_pcie_index_data *nbio_pcie_id;
+   const struct nbio_pcie_index_data *nbio_pcie_id;
 
if (adev->flags & AMD_IS_APU)
nbio_pcie_id = 

[PATCH] [rfc] amdgfx/gfx: don't use static objects for ce/de meta. (v2)

[Dave Airlie]

From: Dave Airlie 

This isn't safe if we have multiple GPUs plugged in, since
there is only one copy of this struct in the bss, just allocate
on stack, it's 40/108 bytes which should be safe.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index dfc10b1..5887f29 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7076,7 +7076,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring 
*ring)
 {
uint64_t ce_payload_addr;
int cnt_ce;
-   static union {
+   union {
struct vi_ce_ib_state regular;
struct vi_ce_ib_state_chained_ib chained;
} ce_payload = {};
@@ -7105,7 +7105,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring 
*ring)
 {
uint64_t de_payload_addr, gds_addr, csa_addr;
int cnt_de;
-   static union {
+   union {
struct vi_de_ib_state regular;
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index deeaee14..508efc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3806,7 +3806,7 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
 
 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
 {
-   static struct v9_ce_ib_state ce_payload = {0};
+   struct v9_ce_ib_state ce_payload = {0};
uint64_t csa_addr;
int cnt;
 
@@ -3825,7 +3825,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring 
*ring)
 
 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
 {
-   static struct v9_de_ib_state de_payload = {0};
+   struct v9_de_ib_state de_payload = {0};
uint64_t csa_addr, gds_addr;
int cnt;
 
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file

[Dave Airlie]

On 29 September 2017 at 06:41, Marek Olšák  wrote:
> Can I get Rb for this series?
>

For the series,

Reviewed-by: Dave Airlie 

Alex, please merge the two drm core precursor with patch 3.

Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 2/4] drm: add drmSyncobjWait wrapper

[Marek Olšák]

From: Marek Olšák 

---
 include/drm/drm.h | 24 
 xf86drm.c | 22 ++
 xf86drm.h |  3 +++
 3 files changed, 49 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4da1667 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -687,38 +687,57 @@ struct drm_prime_handle {
 
/** Flags.. only applicable for handle->fd */
__u32 flags;
 
/** Returned dmabuf file descriptor */
__s32 fd;
 };
 
 struct drm_syncobj_create {
__u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
 };
 
 struct drm_syncobj_destroy {
__u32 handle;
__u32 pad;
 };
 
 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
 struct drm_syncobj_handle {
__u32 handle;
__u32 flags;
 
__s32 fd;
__u32 pad;
 };
 
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+   __u64 handles;
+   /* absolute timeout */
+   __s64 timeout_nsec;
+   __u32 count_handles;
+   __u32 flags;
+   __u32 first_signaled; /* only valid when not waiting all */
+   __u32 pad;
+};
+
+struct drm_syncobj_array {
+   __u64 handles;
+   __u32 count_handles;
+   __u32 pad;
+};
+
 #if defined(__cplusplus)
 }
 #endif
 
 #include "drm_mode.h"
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
@@ -827,20 +846,23 @@ extern "C" {
 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct 
drm_mode_obj_set_property)
 #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
 #define DRM_IOCTL_MODE_ATOMIC  DRM_IOWR(0xBC, struct drm_mode_atomic)
 #define DRM_IOCTL_MODE_CREATEPROPBLOB  DRM_IOWR(0xBD, struct 
drm_mode_create_blob)
 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct 
drm_mode_destroy_blob)
 
 #define DRM_IOCTL_SYNCOBJ_CREATE   DRM_IOWR(0xBF, struct 
drm_syncobj_create)
 #define DRM_IOCTL_SYNCOBJ_DESTROY  DRM_IOWR(0xC0, struct 
drm_syncobj_destroy)
 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct 
drm_syncobj_handle)
 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct 
drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESETDRM_IOWR(0xC4, struct 
drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL   DRM_IOWR(0xC5, struct drm_syncobj_array)
 
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
  * Generic IOCTLS restart at 0xA0.
  *
  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
  * drmCommandReadWrite().
  */
 #define DRM_COMMAND_BASE0x40
@@ -869,20 +891,21 @@ struct drm_event {
 struct drm_event_vblank {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 sequence;
__u32 crtc_id; /* 0 on older kernels that do not support this */
 };
 
 /* typedef area */
+#ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_drawable_info drm_drawable_info_t;
 typedef struct drm_tex_region drm_tex_region_t;
 typedef struct drm_hw_lock drm_hw_lock_t;
 typedef struct drm_version drm_version_t;
 typedef struct drm_unique drm_unique_t;
 typedef struct drm_list drm_list_t;
 typedef struct drm_block drm_block_t;
 typedef struct drm_control drm_control_t;
 typedef enum drm_map_type drm_map_type_t;
@@ -910,16 +933,17 @@ typedef struct drm_draw drm_draw_t;
 typedef struct drm_update_draw drm_update_draw_t;
 typedef struct drm_auth drm_auth_t;
 typedef struct drm_irq_busid drm_irq_busid_t;
 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
 
 typedef struct drm_agp_buffer drm_agp_buffer_t;
 typedef struct drm_agp_binding drm_agp_binding_t;
 typedef struct drm_agp_info drm_agp_info_t;
 typedef struct drm_scatter_gather drm_scatter_gather_t;
 typedef struct drm_set_version drm_set_version_t;
+#endif
 
 #if defined(__cplusplus)
 }
 #endif
 
 #endif
diff --git a/xf86drm.c b/xf86drm.c
index 6ea0112..8a32717 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4218,10 +4218,32 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle, 
int *sync_file_fd)
 memclear(args);
 args.fd = -1;
 args.handle = handle;
 args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE;
 ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, );
 if (ret)
return ret;
 *sync_file_fd = args.fd;
 return 0;
 }
+
+int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+  int64_t timeout_nsec, unsigned flags,
+  uint32_t *first_signaled)
+{
+   struct drm_syncobj_wait args;
+   int ret;
+
+   memclear(args);
+   args.handles = 

[PATCH libdrm 3/4] amdgpu: add amdgpu_cs_syncobj_wait

[Marek Olšák]

From: Marek Olšák 

v2: update amdgpu-symbol-check
---
 amdgpu/amdgpu-symbol-check |  1 +
 amdgpu/amdgpu.h| 20 
 amdgpu/amdgpu_cs.c | 12 
 3 files changed, 33 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index bc9ed3f..7ecfc98 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -35,20 +35,21 @@ amdgpu_cs_destroy_semaphore
 amdgpu_cs_destroy_syncobj
 amdgpu_cs_export_syncobj
 amdgpu_cs_import_syncobj
 amdgpu_cs_query_fence_status
 amdgpu_cs_query_reset_state
 amdgpu_cs_signal_semaphore
 amdgpu_cs_submit
 amdgpu_cs_submit_raw
 amdgpu_cs_syncobj_export_sync_file
 amdgpu_cs_syncobj_import_sync_file
+amdgpu_cs_syncobj_wait
 amdgpu_cs_wait_fences
 amdgpu_cs_wait_semaphore
 amdgpu_device_deinitialize
 amdgpu_device_initialize
 amdgpu_get_marketing_name
 amdgpu_query_buffer_size_alignment
 amdgpu_query_crtc_from_id
 amdgpu_query_firmware_version
 amdgpu_query_gds_info
 amdgpu_query_gpu_info
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b44b9b6..979acfc 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1347,20 +1347,40 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
  * \param   syncobj - \c [in] sync object handle
  *
  * \return   0 on success\n
  *  <0 - Negative POSIX Error code
  *
 */
 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
  uint32_t syncobj);
 
 /**
+ *  Wait for one or all sync objects to signal.
+ *
+ * \param   dev- \c [in] self-explanatory
+ * \param   handles - \c [in] array of sync object handles
+ * \param   num_handles - \c [in] self-explanatory
+ * \param   timeout_nsec - \c [in] self-explanatory
+ * \param   flags   - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param   first_signaled - \c [in] self-explanatory
+ *
+ * \return   0 on success\n
+ *  -ETIME - Timeout
+ *  <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+  uint32_t *handles, unsigned num_handles,
+  int64_t timeout_nsec, unsigned flags,
+  uint32_t *first_signaled);
+
+/**
  *  Export kernel sync object to shareable fd.
  *
  * \param   dev   - \c [in] device handle
  * \param   syncobj- \c [in] sync object handle
  * \param   shared_fd  - \c [out] shared file descriptor.
  *
  * \return   0 on success\n
  *  <0 - Negative POSIX Error code
  *
 */
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 4a05536..2cde7bf 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -608,20 +608,32 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
 
 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
  uint32_t handle)
 {
if (NULL == dev)
return -EINVAL;
 
return drmSyncobjDestroy(dev->fd, handle);
 }
 
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+  uint32_t *handles, unsigned num_handles,
+  int64_t timeout_nsec, unsigned flags,
+  uint32_t *first_signaled)
+{
+   if (NULL == dev)
+   return -EINVAL;
+
+   return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec,
+ flags, first_signaled);
+}
+
 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
 uint32_t handle,
 int *shared_fd)
 {
if (NULL == dev)
return -EINVAL;
 
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
 }
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 4/4] amdgpu: add amdgpu_cs_fence_to_handle

[Marek Olšák]

From: Marek Olšák 

v2: update amdgpu-symbol-check
---
 amdgpu/amdgpu-symbol-check |  1 +
 amdgpu/amdgpu.h| 14 ++
 amdgpu/amdgpu_cs.c | 22 ++
 include/drm/amdgpu_drm.h   | 21 +
 4 files changed, 58 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 7ecfc98..d9f89ef 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -27,20 +27,21 @@ amdgpu_bo_wait_for_idle
 amdgpu_create_bo_from_user_mem
 amdgpu_cs_chunk_fence_info_to_data
 amdgpu_cs_chunk_fence_to_dep
 amdgpu_cs_create_semaphore
 amdgpu_cs_create_syncobj
 amdgpu_cs_ctx_create
 amdgpu_cs_ctx_free
 amdgpu_cs_destroy_semaphore
 amdgpu_cs_destroy_syncobj
 amdgpu_cs_export_syncobj
+amdgpu_cs_fence_to_handle
 amdgpu_cs_import_syncobj
 amdgpu_cs_query_fence_status
 amdgpu_cs_query_reset_state
 amdgpu_cs_signal_semaphore
 amdgpu_cs_submit
 amdgpu_cs_submit_raw
 amdgpu_cs_syncobj_export_sync_file
 amdgpu_cs_syncobj_import_sync_file
 amdgpu_cs_syncobj_wait
 amdgpu_cs_wait_fences
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 979acfc..23cde10 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1426,20 +1426,34 @@ int 
amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
  *
  * \return   0 on success\n
  *  <0 - Negative POSIX Error code
  *
  */
 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
   uint32_t syncobj,
   int sync_file_fd);
 
 /**
+ * Export an amdgpu fence as a handle (syncobj or fd).
+ *
+ * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
+ * \param out_handle   returned handle
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ */
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle);
+
+/**
  *  Submit raw command submission to kernel
  *
  * \param   dev   - \c [in] device handle
  * \param   context- \c [in] context handle for context id
  * \param   bo_list_handle - \c [in] request bo list handle (0 for none)
  * \param   num_chunks - \c [in] number of CS chunks to submit
  * \param   chunks - \c [in] array of CS chunks
  * \param   seq_no - \c [out] output sequence number for submission.
  *
  * \return   0 on success\n
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 2cde7bf..9577d5c 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -706,10 +706,32 @@ void amdgpu_cs_chunk_fence_info_to_data(struct 
amdgpu_cs_fence_info *fence_info,
 
 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
  struct drm_amdgpu_cs_chunk_dep *dep)
 {
dep->ip_type = fence->ip_type;
dep->ip_instance = fence->ip_instance;
dep->ring = fence->ring;
dep->ctx_id = fence->context->id;
dep->handle = fence->fence;
 }
+
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
+{
+   union drm_amdgpu_fence_to_handle fth = {0};
+   int r;
+
+   fth.in.fence.ctx_id = fence->context->id;
+   fth.in.fence.ip_type = fence->ip_type;
+   fth.in.fence.ip_instance = fence->ip_instance;
+   fth.in.fence.ring = fence->ring;
+   fth.in.fence.seq_no = fence->fence;
+   fth.in.what = what;
+
+   r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
+   , sizeof(fth));
+   if (r == 0)
+   *out_handle = fth.out.handle;
+   return r;
+}
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a3..00f1b81 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -45,55 +45,59 @@ extern "C" {
 #define DRM_AMDGPU_CS  0x04
 #define DRM_AMDGPU_INFO0x05
 #define DRM_AMDGPU_GEM_METADATA0x06
 #define DRM_AMDGPU_GEM_WAIT_IDLE   0x07
 #define DRM_AMDGPU_GEM_VA  0x08
 #define DRM_AMDGPU_WAIT_CS 0x09
 #define DRM_AMDGPU_GEM_OP  0x10
 #define DRM_AMDGPU_GEM_USERPTR 0x11
 #define DRM_AMDGPU_WAIT_FENCES 0x12
 #define DRM_AMDGPU_VM  0x13
+#define DRM_AMDGPU_FENCE_TO_HANDLE 0x15
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
 #define DRM_IOCTL_AMDGPU_CTX   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
 #define DRM_IOCTL_AMDGPU_BO_LIST   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_AMDGPU_BO_LIST, union 

[PATCH libdrm 1/4] amdgpu: add sync_file import and export functions

[Marek Olšák]

From: Marek Olšák 

v2: update amdgpu-symbol-check
---
 amdgpu/amdgpu-symbol-check |  2 ++
 amdgpu/amdgpu.h| 30 ++
 amdgpu/amdgpu_cs.c | 20 
 3 files changed, 52 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index c5b85b5..bc9ed3f 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -33,20 +33,22 @@ amdgpu_cs_ctx_create
 amdgpu_cs_ctx_free
 amdgpu_cs_destroy_semaphore
 amdgpu_cs_destroy_syncobj
 amdgpu_cs_export_syncobj
 amdgpu_cs_import_syncobj
 amdgpu_cs_query_fence_status
 amdgpu_cs_query_reset_state
 amdgpu_cs_signal_semaphore
 amdgpu_cs_submit
 amdgpu_cs_submit_raw
+amdgpu_cs_syncobj_export_sync_file
+amdgpu_cs_syncobj_import_sync_file
 amdgpu_cs_wait_fences
 amdgpu_cs_wait_semaphore
 amdgpu_device_deinitialize
 amdgpu_device_initialize
 amdgpu_get_marketing_name
 amdgpu_query_buffer_size_alignment
 amdgpu_query_crtc_from_id
 amdgpu_query_firmware_version
 amdgpu_query_gds_info
 amdgpu_query_gpu_info
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 238b1aa..b44b9b6 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1376,20 +1376,50 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
  *
  * \return   0 on success\n
  *  <0 - Negative POSIX Error code
  *
 */
 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
 int shared_fd,
 uint32_t *syncobj);
 
 /**
+ *  Export kernel sync object to a sync_file.
+ *
+ * \param   dev   - \c [in] device handle
+ * \param   syncobj- \c [in] sync object handle
+ * \param   sync_file_fd - \c [out] sync_file file descriptor.
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+  uint32_t syncobj,
+  int *sync_file_fd);
+
+/**
+ *  Import kernel sync object from a sync_file.
+ *
+ * \param   dev   - \c [in] device handle
+ * \param   syncobj- \c [in] sync object handle
+ * \param   sync_file_fd - \c [in] sync_file file descriptor.
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+  uint32_t syncobj,
+  int sync_file_fd);
+
+/**
  *  Submit raw command submission to kernel
  *
  * \param   dev   - \c [in] device handle
  * \param   context- \c [in] context handle for context id
  * \param   bo_list_handle - \c [in] request bo list handle (0 for none)
  * \param   num_chunks - \c [in] number of CS chunks to submit
  * \param   chunks - \c [in] array of CS chunks
  * \param   seq_no - \c [out] output sequence number for submission.
  *
  * \return   0 on success\n
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index dfba875..4a05536 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -628,20 +628,40 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
 int shared_fd,
 uint32_t *handle)
 {
if (NULL == dev)
return -EINVAL;
 
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
 }
 
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+  uint32_t syncobj,
+  int *sync_file_fd)
+{
+   if (NULL == dev)
+   return -EINVAL;
+
+   return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+  uint32_t syncobj,
+  int sync_file_fd)
+{
+   if (NULL == dev)
+   return -EINVAL;
+
+   return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
 int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
 amdgpu_context_handle context,
 amdgpu_bo_list_handle bo_list_handle,
 int num_chunks,
 struct drm_amdgpu_cs_chunk *chunks,
 uint64_t *seq_no)
 {
union drm_amdgpu_cs cs = {0};
uint64_t *chunk_array;
int i, r;
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/3] drm/syncobj: extract two helpers from drm_syncobj_create

[Marek Olšák]

On Thu, Sep 14, 2017 at 10:01 AM, Emil Velikov  wrote:
> On 14 September 2017 at 08:56, Emil Velikov  wrote:
>> Hi Marek,
>>
>> On 12 September 2017 at 21:42, Marek Olšák  wrote:
>>
>>>  include/drm/drm_syncobj.h |  4 
>> Please sync the header as described in
>> https://cgit.freedesktop.org/mesa/drm/tree/include/drm/README#n72
>>
>> Tl;DR: cd .../linux; make headers_install; cp ... .../drm/include/drm;
>> cd .../drm; git commit -sm " $branch $sha1..."
>>
> Seems like I've replied to the wrong patch - silly me.
> This was meant for the libdrm ones - suggestion still applies though.

I actually did that, but I'm on amd-staging-drm-next.

Marek
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amdgpu: add FENCE_TO_HANDLE ioctl that returns syncobj or sync_file

[Marek Olšák]

Can I get Rb for this series?

Thanks,
Marek

On Tue, Sep 12, 2017 at 10:42 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> for being able to convert an amdgpu fence into one of the handles.
> Mesa will use this.
>
> Signed-off-by: Marek Olšák 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 61 
> +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  1 +
>  include/uapi/drm/amdgpu_drm.h   | 16 +
>  5 files changed, 82 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index b5c8b90..c15fa93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1308,6 +1308,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
> *data,
>  int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp);
>  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *filp);
> +int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
> +   struct drm_file *filp);
>  int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *filp);
>  int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 7cb8a59..6dd719c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -25,6 +25,7 @@
>   *Jerome Glisse 
>   */
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1311,6 +1312,66 @@ static struct dma_fence *amdgpu_cs_get_fence(struct 
> amdgpu_device *adev,
> return fence;
>  }
>
> +int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
> +   struct drm_file *filp)
> +{
> +   struct amdgpu_device *adev = dev->dev_private;
> +   struct amdgpu_fpriv *fpriv = filp->driver_priv;
> +   union drm_amdgpu_fence_to_handle *info = data;
> +   struct dma_fence *fence;
> +   struct drm_syncobj *syncobj;
> +   struct sync_file *sync_file;
> +   int fd, r;
> +
> +   if (amdgpu_kms_vram_lost(adev, fpriv))
> +   return -ENODEV;
> +
> +   fence = amdgpu_cs_get_fence(adev, filp, >in.fence);
> +   if (IS_ERR(fence))
> +   return PTR_ERR(fence);
> +
> +   switch (info->in.what) {
> +   case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
> +   r = drm_syncobj_create(, 0, fence);
> +   dma_fence_put(fence);
> +   if (r)
> +   return r;
> +   r = drm_syncobj_get_handle(filp, syncobj, >out.handle);
> +   drm_syncobj_put(syncobj);
> +   return r;
> +
> +   case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
> +   r = drm_syncobj_create(, 0, fence);
> +   dma_fence_put(fence);
> +   if (r)
> +   return r;
> +   r = drm_syncobj_get_fd(syncobj, (int*)>out.handle);
> +   drm_syncobj_put(syncobj);
> +   return r;
> +
> +   case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
> +   fd = get_unused_fd_flags(O_CLOEXEC);
> +   if (fd < 0) {
> +   dma_fence_put(fence);
> +   return fd;
> +   }
> +
> +   sync_file = sync_file_create(fence);
> +   dma_fence_put(fence);
> +   if (!sync_file) {
> +   put_unused_fd(fd);
> +   return -ENOMEM;
> +   }
> +
> +   fd_install(fd, sync_file->file);
> +   info->out.handle = fd;
> +   return 0;
> +
> +   default:
> +   return -EINVAL;
> +   }
> +}
> +
>  /**
>   * amdgpu_cs_wait_all_fence - wait on all fences to signal
>   *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d01aca6..1e38411 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -70,9 +70,10 @@
>   * - 3.18.0 - Export gpu always on cu bitmap
>   * - 3.19.0 - Add support for UVD MJPEG decode
>   * - 3.20.0 - Add support for local BOs
> + * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
>   */
>  #define KMS_DRIVER_MAJOR   3
> -#define KMS_DRIVER_MINOR   20
> +#define KMS_DRIVER_MINOR   21
>  #define KMS_DRIVER_PATCHLEVEL  0
>
>  int amdgpu_vram_limit = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index d31777b..b09d315 100644
> --- 

RE: [PATCH] drm/amd/display: Remove DWB

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Harry Wentland
> Sent: Thursday, September 28, 2017 3:42 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Cheng, Tony; airl...@gmail.com; dri-
> de...@lists.freedesktop.org; Wentland, Harry
> Subject: [PATCH] drm/amd/display: Remove DWB
> 
> It's not in a good shape and currently completely unused.
> 
> Signed-off-by: Harry Wentland 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c   |   9 -
>  drivers/gpu/drm/amd/display/dc/dcn10/Makefile  |   2 +-
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c   | 365 --
> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h   | 277 
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  57 
>  drivers/gpu/drm/amd/display/dc/inc/core_types.h|   3 -
>  drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h| 193 ---
>  7 files changed, 1 insertion(+), 905 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
>  delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
>  delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d86d9796e4cc..7fd42fc8bdfa 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1525,15 +1525,6 @@ struct dc_link *dc_get_link_at_index(struct dc
> *dc, uint32_t link_index)
>   return dc->links[link_index];
>  }
> 
> -struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe)
> -{
> - if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) {
> - return dc->res_pool->dwbc[(int)pipe];
> - } else {
> - return NULL;
> - }
> -}
> -
>  const struct graphics_object_id dc_get_link_id_at_index(
>   struct dc *dc, uint32_t link_index)
>  {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> index e92ac2997a1a..2d6d3a371858 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> @@ -3,7 +3,7 @@
> 
>  DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
>   dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
> - dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \
> + dcn10_mem_input.o dcn10_mpc.o \
>   dcn10_dpp_dscl.o dcn10_dpp_cm.o
> dcn10_dpp_cm_helper.o
> 
>  AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
> deleted file mode 100644
> index 4ec5554f0f5b..
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
> +++ /dev/null
> @@ -1,365 +0,0 @@
> -/*
> - * Copyright 2012-17 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> -
> -#include "reg_helper.h"
> -#include "resource.h"
> -#include "dwb.h"
> -#include "dcn10_dwb.h"
> -
> -
> -#define REG(reg)\
> - dwbc10->dwbc_regs->reg
> -
> -#define CTX \
> - dwbc10->base.ctx
> -
> -#undef FN
> -#define FN(reg_name, field_name) \
> - dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask-
> >field_name
> -
> -#define TO_DCN10_DWBC(dwbc_base) \
> - container_of(dwbc_base, struct dcn10_dwbc, base)
> -
> -static bool get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
> -{
> - if (caps) {
> - caps->adapter_id = 0;   /* we only support 1 adapter
> currently */
> - caps->hw_version = DCN_VERSION_1_0;
> - caps->num_pipes = 2;
> - 

Re: [PATCH] amdgpu/pp: move amdgpu_fuses_default into static const.

[Alex Deucher]

On Wed, Sep 27, 2017 at 7:37 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> There is no reason that this gets passed back into the function
> from outside the file, just reference the table directly.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c | 4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h | 2 --
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c  | 2 +-
>  3 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
> index 34fdf1a..2b08371 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c
> @@ -1,7 +1,7 @@
>  #include "pp_overdriver.h"
>  #include 
>
> -const struct phm_fuses_default vega10_fuses_default[] = {
> +static const struct phm_fuses_default vega10_fuses_default[] = {
> 
> {"00110010101010010100110011100100100101100100",0x3C96,0xE226,0x0656,0x2203,0xF201,0x03FF,0x2203,0xF201,0x03FF},
> 
> {"001100101010100101001100101110001100",0x3CC5,0xE23A,0x064E,0x2258,0xF1F7,0x03FC,0x2258,0xF1F7,0x03FC},
> 
> {"00110010101010010100110011100011000110100100",0x3CAF,0xE36E,0x0602,0x1E98,0xF569,0x0357,0x1E98,0xF569,0x0357},
> @@ -1240,9 +1240,9 @@ const struct phm_fuses_default vega10_fuses_default[] = 
> {
>  };
>
>  int pp_override_get_default_fuse_value(uint64_t key,
> -   const struct phm_fuses_default list[],
> struct phm_fuses_default *result)
>  {
> +   const struct phm_fuses_default *list = vega10_fuses_default;
> uint32_t i;
> uint64_t temp_serial_numer;
> uint32_t bit;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
> index 133745f..22e2dd0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h
> @@ -40,9 +40,7 @@ struct phm_fuses_default {
> uint32_t VFT0_b;
>  };
>
> -extern const struct phm_fuses_default vega10_fuses_default[];
>  extern int pp_override_get_default_fuse_value(uint64_t key,
> -   const struct phm_fuses_default list[],
> struct phm_fuses_default *result);
>
>  #endif
> \ No newline at end of file
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 71b9424..6a85954 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2393,7 +2393,7 @@ static int 
> vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
>
> serial_number = ((uint64_t)bottom32 << 32) | top32;
>
> -   if (pp_override_get_default_fuse_value(serial_number, 
> vega10_fuses_default, ) == 0) {
> +   if (pp_override_get_default_fuse_value(serial_number, ) == 0) {
> avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
> avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
> avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
> --
> 2.9.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH][drm-next] drm/amd/powerplay: fix spelling mistake: "dividable" -> "divisible"

[Alex Deucher]

On Thu, Sep 28, 2017 at 6:35 AM, Colin King  wrote:
> From: Colin Ian King 
>
> Trivial fix to spelling mistakes in pr_err error message and ASSERT
> messages.
>
> Signed-off-by: Colin Ian King 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c| 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> index fcf88b8fc738..9d1086894d2b 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> @@ -2332,7 +2332,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
> PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
> AUTO_INCREMENT_IND_0, 0);
>
> if (0 != byte_count) {
> -   pr_err("SMC size must be dividable by 4\n");
> +   pr_err("SMC size must be divisible by 4\n");
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index 78aa1122eacc..a778e174ba01 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -108,7 +108,7 @@ static int iceland_upload_smc_firmware_data(struct 
> pp_hwmgr *hwmgr,
>
> PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
> AUTO_INCREMENT_IND_0, 0);
>
> -   PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 
> 4.", return -EINVAL);
> +   PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 
> 4.", return -EINVAL);
>
> return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 2ae05bbdb974..c997117f2461 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -513,7 +513,7 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr 
> *hwmgr, uint32_t length
>
> PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, 
> AUTO_INCREMENT_IND_11, 0);
>
> -   PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 
> 4.", return -EINVAL);
> +   PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 
> 4.", return -EINVAL);
>
> return 0;
>  }
> --
> 2.14.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/display: Remove DWB

[Harry Wentland]

It's not in a good shape and currently completely unused.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |   9 -
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile  |   2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c   | 365 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h   | 277 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  57 
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   3 -
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h| 193 ---
 7 files changed, 1 insertion(+), 905 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
 delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d86d9796e4cc..7fd42fc8bdfa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1525,15 +1525,6 @@ struct dc_link *dc_get_link_at_index(struct dc *dc, 
uint32_t link_index)
return dc->links[link_index];
 }
 
-struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe)
-{
-   if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) {
-   return dc->res_pool->dwbc[(int)pipe];
-   } else {
-   return NULL;
-   }
-}
-
 const struct graphics_object_id dc_get_link_id_at_index(
struct dc *dc, uint32_t link_index)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index e92ac2997a1a..2d6d3a371858 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -3,7 +3,7 @@
 
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
-   dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \
+   dcn10_mem_input.o dcn10_mpc.o \
dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_dpp_cm_helper.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
deleted file mode 100644
index 4ec5554f0f5b..
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * Copyright 2012-17 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-
-#include "reg_helper.h"
-#include "resource.h"
-#include "dwb.h"
-#include "dcn10_dwb.h"
-
-
-#define REG(reg)\
-   dwbc10->dwbc_regs->reg
-
-#define CTX \
-   dwbc10->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
-   dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
-
-#define TO_DCN10_DWBC(dwbc_base) \
-   container_of(dwbc_base, struct dcn10_dwbc, base)
-
-static bool get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
-{
-   if (caps) {
-   caps->adapter_id = 0;   /* we only support 1 adapter currently 
*/
-   caps->hw_version = DCN_VERSION_1_0;
-   caps->num_pipes = 2;
-   memset(>reserved, 0, sizeof(caps->reserved));
-   memset(>reserved2, 0, sizeof(caps->reserved2));
-   caps->sw_version = dwb_ver_1_0;
-   caps->caps.support_dwb = true;
-   caps->caps.support_ogam = false;
-   caps->caps.support_wbscl = true;
-   caps->caps.support_ocsc = false;
-   return true;
-   } else {
-   return false;
-   }
-}
-
-static bool enable(struct dwbc *dwbc)
-{
-   struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
-
-   /* disable first. */
-   dwbc->funcs->disable(dwbc);
-
-   /* disable 

Re: [PATCH 4/5] drm/amd/sched: NULL out the s_fence field after run_job

[Nicolai Hähnle]

On 28.09.2017 20:39, Andres Rodriguez wrote:



On 2017-09-28 10:55 AM, Nicolai Hähnle wrote:

From: Nicolai Hähnle 

amd_sched_process_job drops the fence reference, so NULL out the s_fence
field before adding it as a callback to guard against accidentally using
s_fence after it may have be freed.

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c

index e793312e351c..54eb77cffd9b 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -604,20 +604,23 @@ static int amd_sched_main(void *param)
  if (!sched_job)
  continue;
  s_fence = sched_job->s_fence;
  atomic_inc(>hw_rq_count);
  amd_sched_job_begin(sched_job);
  fence = sched->ops->run_job(sched_job);
  amd_sched_fence_scheduled(s_fence);
+
+    sched_job->s_fence = NULL;


Minor optional nitpick here. Could this be moved somewhere closer to 
where the fence reference is actually dropped? Alternatively, could a 
comment be added to specify which function call results in the reference 
ownership transfer?


Sure, I can add a comment. (It's amd_sched_process_job, which is called 
directly or indirectly in all the branches of the following if-statement.)




Whether a change is made or not, this series is
Reviewed-by: Andres Rodriguez 


Thanks.


Currently running piglit to check if this fixes the occasional soft 
hangs I was getting where all tests complete except one.


You may be running into this Mesa issue:

https://patchwork.freedesktop.org/patch/179535/

Cheers,
Nicolai





+
  if (fence) {
  s_fence->parent = dma_fence_get(fence);
  r = dma_fence_add_callback(fence, _fence->cb,
 amd_sched_process_job);
  if (r == -ENOENT)
  amd_sched_process_job(fence, _fence->cb);
  else if (r)
  DRM_ERROR("fence add callback failed (%d)\n",
    r);
  dma_fence_put(fence);



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: amdgpu_vf_errors

[Wan, Gavin]

Hi Dave,

This feature is used on Virtualization environment to send errors of amdgpu 
initialization fail from Guest side to Host side via mailbox (function 
xgpu_ai_mailbox_trans_msg in file mxgpu_ai.c).

In Virtualization environment, it should not use multi GPUs. So I just created 
a global array not to impacts amdgpu structure. The array size is 16, operated 
as ring buffer. It is bigger enough to save the errors of amdgpu initialization 
fail.

You are right, I should move struct amdgpu_vf_error_buffer to struct 
amdgpu_device OR struct amdgpu_virt. Which one is better?

Yes, there are a lot typoes adm->amd and I will fix them.

Thanks your very much.

Best Regards,
Gavin

-Original Message-
From: Dave Airlie [mailto:airl...@gmail.com] 
Sent: Wednesday, September 27, 2017 7:17 PM
To: amd-gfx mailing list ; Wan, Gavin 

Subject: Re: amdgpu_vf_errors

On 28 September 2017 at 09:14, Dave Airlie  wrote:
> I've no idea what this is used for, virtual function errors?
>
> but why does it have no locking, and why is there a global array, (not per 
> gpu?)
>
> Alex, you reviewed it, please rewrite/remove as necessary.

Oh it also typoes adm->amd in lots of places.

Dave.

>
> Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [alsa-devel] [PATCH 0/6 v4] Add ASoC support for AMD Stoney APUs

[Deucher, Alexander]

> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Thursday, September 28, 2017 3:00 PM
> To: Alex Deucher
> Cc: alsa-de...@alsa-project.org; Takashi Iwai; Liam Girdwood; Maling list -
> DRI developers; rajeev kumar; amd-gfx list; Mukunda, Vijendar; Deucher,
> Alexander; Dave Airlie
> Subject: Re: [alsa-devel] [PATCH 0/6 v4] Add ASoC support for AMD Stoney
> APUs
> 
> On Thu, Sep 14, 2017 at 10:42:28AM -0700, Mark Brown wrote:
> > On Wed, Sep 13, 2017 at 02:49:08PM -0400, Alex Deucher wrote:
> 
> > > I'm not quite sure what you mean by the cross merge.  There are no
> > > dependencies outside this patch set.  The only patches that touch drm
> > > are patches 1 and 2.  Patch 1 touches both audio and drm, patch 2 just
> > > touches drm.  Do you want me to send you a pull request for patches 1
> 
> > I can't see any reason for patch 1 to be a single patch, just have a DRM
> > patch that adds the property and then a separate audio patch that uses
> > it.  Send me a pull request for that and patch 2 then I can handle the
> > audio stuff.
> 
> Any updates with the pull requests?

Sorry travelling last week and swamped this week.  I'm going to try and get it 
done tomorrow, otherwise, probably the week after.

Alex

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: map compute rings by least recently used pipe

[Alex Deucher]

On Tue, Sep 26, 2017 at 5:43 PM, Andres Rodriguez  wrote:
> This patch provides a guarantee that the first n queues allocated by
> an application will be on different pipes. Where n is the number of
> pipes available from the hardware.
>
> This helps avoid ring aliasing which can result in work executing in
> time-sliced mode instead of truly parallel mode.
>
> Signed-off-by: Andres Rodriguez 

Reviewed-by: Alex Deucher 
And applied.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c |  8 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c  | 25 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h  |  5 +++--
>  3 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
> index befc09b..190e28c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
> @@ -121,7 +121,7 @@ static enum amdgpu_ring_type 
> amdgpu_hw_ip_to_ring_type(int hw_ip)
>
>  static int amdgpu_lru_map(struct amdgpu_device *adev,
>   struct amdgpu_queue_mapper *mapper,
> - int user_ring,
> + int user_ring, bool lru_pipe_order,
>   struct amdgpu_ring **out_ring)
>  {
> int r, i, j;
> @@ -139,7 +139,7 @@ static int amdgpu_lru_map(struct amdgpu_device *adev,
> }
>
> r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
> -   j, out_ring);
> +   j, lru_pipe_order, out_ring);
> if (r)
> return r;
>
> @@ -284,8 +284,10 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
> r = amdgpu_identity_map(adev, mapper, ring, out_ring);
> break;
> case AMDGPU_HW_IP_DMA:
> +   r = amdgpu_lru_map(adev, mapper, ring, false, out_ring);
> +   break;
> case AMDGPU_HW_IP_COMPUTE:
> -   r = amdgpu_lru_map(adev, mapper, ring, out_ring);
> +   r = amdgpu_lru_map(adev, mapper, ring, true, out_ring);
> break;
> default:
> *out_ring = NULL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 5ce6528..019932a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -315,14 +315,16 @@ static bool amdgpu_ring_is_blacklisted(struct 
> amdgpu_ring *ring,
>   * @type: amdgpu_ring_type enum
>   * @blacklist: blacklisted ring ids array
>   * @num_blacklist: number of entries in @blacklist
> + * @lru_pipe_order: find a ring from the least recently used pipe
>   * @ring: output ring
>   *
>   * Retrieve the amdgpu_ring structure for the least recently used ring of
>   * a specific IP block (all asics).
>   * Returns 0 on success, error on failure.
>   */
> -int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
> -   int num_blacklist, struct amdgpu_ring **ring)
> +int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
> +   int *blacklist, int num_blacklist,
> +   bool lru_pipe_order, struct amdgpu_ring **ring)
>  {
> struct amdgpu_ring *entry;
>
> @@ -337,10 +339,23 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int 
> type, int *blacklist,
> if (amdgpu_ring_is_blacklisted(entry, blacklist, 
> num_blacklist))
> continue;
>
> -   *ring = entry;
> -   amdgpu_ring_lru_touch_locked(adev, *ring);
> -   break;
> +   if (!*ring) {
> +   *ring = entry;
> +
> +   /* We are done for ring LRU */
> +   if (!lru_pipe_order)
> +   break;
> +   }
> +
> +   /* Move all rings on the same pipe to the end of the list */
> +   if (entry->pipe == (*ring)->pipe)
> +   amdgpu_ring_lru_touch_locked(adev, entry);
> }
> +
> +   /* Move the ring we found to the end of the list */
> +   if (*ring)
> +   amdgpu_ring_lru_touch_locked(adev, *ring);
> +
> spin_unlock(>ring_lru_list_lock);
>
> if (!*ring) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 322d2529..491bd55 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -201,8 +201,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct 
> amdgpu_ring *ring,
>  unsigned ring_size, struct amdgpu_irq_src *irq_src,
>  unsigned irq_type);
>  void amdgpu_ring_fini(struct amdgpu_ring *ring);
> -int 

Re: [alsa-devel] [PATCH 0/6 v4] Add ASoC support for AMD Stoney APUs

[Mark Brown]

On Thu, Sep 14, 2017 at 10:42:28AM -0700, Mark Brown wrote:
> On Wed, Sep 13, 2017 at 02:49:08PM -0400, Alex Deucher wrote:

> > I'm not quite sure what you mean by the cross merge.  There are no
> > dependencies outside this patch set.  The only patches that touch drm
> > are patches 1 and 2.  Patch 1 touches both audio and drm, patch 2 just
> > touches drm.  Do you want me to send you a pull request for patches 1

> I can't see any reason for patch 1 to be a single patch, just have a DRM
> patch that adds the property and then a separate audio patch that uses
> it.  Send me a pull request for that and patch 2 then I can handle the
> audio stuff.

Any updates with the pull requests?


signature.asc
Description: PGP signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 0/2] Selectively spread compute rings across pipes

[Alex Deucher]

On Tue, Sep 26, 2017 at 2:15 PM, Felix Kuehling  wrote:
> The series is Acked-by: Felix Kuehling 
>
> Regards,
>   Felix
>
>
> On 2017-09-26 12:22 PM, Andres Rodriguez wrote:
>> This was disabled due to an OCL perf regression as discussed on amd-gfx.
>>
>> This series re-enables the feature for ASICs that are not affected, and also
>> introduces a boot parameter to force the policy on or off. This should help
>> future effort of comparing performance with the feature enabled/disabled.

Applied.  thanks!

Alex

>>
>>
>>
>> Andres Rodriguez (2):
>>   drm/amdgpu: use multipipe compute policy on non PL11 asics
>>   drm/amdgpu: add option for force enable multipipe policy for compute
>>
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  4 
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20 ++--
>>  3 files changed, 23 insertions(+), 2 deletions(-)
>>
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/pp/vega10: mark vega10_pp_tables_initialize as static.

[Alex Deucher]

On Thu, Sep 28, 2017 at 3:17 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This isn't used outside this file.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> index e343df1..22c4d5b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> @@ -1131,7 +1131,7 @@ static int init_dpm_2_parameters(
> return result;
>  }
>
> -int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
> +static int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
>  {
> int result = 0;
> const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
> --
> 2.9.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: use designated initialiser for thermal_irq_src.

[Alex Deucher]

On Thu, Sep 28, 2017 at 2:13 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This fixes the 0-day build warning.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 73969f3..35e80c9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -124,9 +124,9 @@ static int phm_ctf_irq(void *private_data,
>  }
>
>  static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
> -   {NULL, phm_thermal_l2h_irq},
> -   {NULL, phm_thermal_h2l_irq},
> -   {NULL, phm_ctf_irq}
> +   { .handler = phm_thermal_l2h_irq },
> +   { .handler = phm_thermal_h2l_irq },
> +   { .handler = phm_ctf_irq }
>  };
>
>  int hwmgr_early_init(struct pp_instance *handle)
> --
> 2.9.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/pp: move PhwVega10_Magic to static const.

[Alex Deucher]

On Wed, Sep 27, 2017 at 7:33 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This isn't used outside this file.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 80e41be..71b9424 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -81,7 +81,7 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 
> 0, 16, 2};
>  static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
> enum pp_clock_type type, uint32_t mask);
>
> -const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
> +static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
>
>  struct vega10_power_state *cast_phw_vega10_power_state(
>   struct pp_hw_power_state *hw_ps)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 676cd77..b4b461c3 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -31,7 +31,6 @@
>  #include "vega10_ppsmc.h"
>  #include "vega10_powertune.h"
>
> -extern const uint32_t PhwVega10_Magic;
>  #define VEGA10_MAX_HARDWARE_POWERLEVELS 2
>
>  #define WaterMarksExist  1
> --
> 2.9.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/pp: remove ci_smc/smumgr split.

[Alex Deucher]

On Wed, Sep 27, 2017 at 7:04 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This split serves no purpose, and we can make a bunch of functions
> static now.
>
> There are lots of cases of this sort of split in the powerplay code,
> please start cleaning them up. Ideally the function table is in the
> same file as all the implementations used in it.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/Makefile|  2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c| 85 ++-
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h| 52 --
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 86 
> 
>  4 files changed, 71 insertions(+), 154 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.h
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile 
> b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
> index a423c0a..4e29888 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
> @@ -4,7 +4,7 @@
>
>  SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
>   polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
> - smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o ci_smc.o 
> ci_smumgr.o
> + smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o ci_smc.o
>
>  AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> index 9ee1431..8fb0aa0 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> @@ -28,7 +28,6 @@
>
>  #include "smumgr.h"
>  #include "pp_debug.h"
> -#include "ci_smc.h"
>  #include "ci_smumgr.h"
>  #include "ppsmc.h"
>  #include "smu7_hwmgr.h"
> @@ -208,7 +207,7 @@ static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, 
> uint32_t smc_addr,
> return 0;
>  }
>
> -int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
> +static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
>  {
> int ret;
>
> @@ -227,7 +226,7 @@ int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t 
> msg)
> return 0;
>  }
>
> -int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
> +static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
> uint16_t msg, uint32_t parameter)
>  {
> cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
> @@ -476,7 +475,7 @@ static int ci_populate_single_graphic_level(struct 
> pp_hwmgr *hwmgr,
> return result;
>  }
>
> -int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
> +static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
>  {
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
> @@ -1297,7 +1296,7 @@ static int ci_populate_single_memory_level(
> return result;
>  }
>
> -int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
> +static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
>  {
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
> @@ -1944,7 +1943,7 @@ static int ci_start_smc(struct pp_hwmgr *hwmgr)
> return 0;
>  }
>
> -int ci_init_smc_table(struct pp_hwmgr *hwmgr)
> +static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
>  {
> int result;
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> @@ -2125,7 +2124,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
> return 0;
>  }
>
> -int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
> +static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
>  {
> struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
> SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
> @@ -2211,7 +2210,7 @@ static int ci_program_mem_timing_parameters(struct 
> pp_hwmgr *hwmgr)
> return 0;
>  }
>
> -int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
> +static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
>  {
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
> @@ -2252,7 +2251,7 @@ int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
> return result;
>  }
>
> -uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
> +static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
>  {
> switch (type) {
> case SMU_SoftRegisters:
> @@ -2278,7 +2277,7 @@ 

RE: [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Thursday, September 28, 2017 5:41 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID
> 
> don't need to check pp_valid, all pp
> export functions are moved to ip_funcs
> and pp_funcs. so just need to check the
> function point.
> 
> Change-Id: Ib75cebece8fb9ebc7307f5d3cf084a813b5493db
> Signed-off-by: Rex Zhu 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c   | 3 +--
>  drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 3 ---
>  2 files changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index a0f08ec..94f85db 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -35,7 +35,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum
> amd_pp_task task_id,
> 
>  static inline int pp_check(struct pp_instance *handle)
>  {
> - if (handle == NULL || handle->pp_valid != PP_VALID)
> + if (handle == NULL)
>   return -EINVAL;
> 
>   if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs ==
> NULL ||
> @@ -60,7 +60,6 @@ static int amd_powerplay_create(struct amd_pp_init
> *pp_init,
>   if (instance == NULL)
>   return -ENOMEM;
> 
> - instance->pp_valid = PP_VALID;
>   instance->chip_family = pp_init->chip_family;
>   instance->chip_id = pp_init->chip_id;
>   instance->pm_en = pp_init->pm_en;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> index 25fb146..7d1eec5 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> @@ -25,10 +25,7 @@
> 
>  #include "hwmgr.h"
> 
> -#define PP_VALID  0x1F1F1F1F
> -
>  struct pp_instance {
> - uint32_t pp_valid;
>   uint32_t chip_family;
>   uint32_t chip_id;
>   bool pm_en;
> --
> 1.9.1
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH v2] drm/amd/powerplay: refine code in amd_powerplay.c

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Thursday, September 28, 2017 1:06 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH v2] drm/amd/powerplay: refine code in amd_powerplay.c
> 
> v2: not set global module option amdgpu_dpm in
> cgs interface and not set dpm_enabled in
> function amdgpu_pp_hw_init.
> 
> delete flag of PP_DPM_DISABLED
> pp_en in pp_handle is enough
> 
> Signed-off-by: Rex Zhu 

Split this into two patches, one to remove PP_DPM_DISABLED and one to clean up 
the ret checks,  e.g.,
> - if (ret != 0) {
> + if (ret) {
With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  12 --
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 153 ++---
> -
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |   2 -
>  3 files changed, 70 insertions(+), 97 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> index 1649b1e..3b42f40 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
> @@ -98,10 +98,6 @@ static int amdgpu_pp_early_init(void *handle)
>   amd_pp->cgs_device ? amd_pp-
> >cgs_device :
>   amd_pp->pp_handle);
> 
> - if (ret == PP_DPM_DISABLED) {
> - adev->pm.dpm_enabled = false;
> - return 0;
> - }
>   return ret;
>  }
> 
> @@ -154,14 +150,6 @@ static int amdgpu_pp_hw_init(void *handle)
>   ret = adev->powerplay.ip_funcs->hw_init(
>   adev->powerplay.pp_handle);
> 
> - if (ret == PP_DPM_DISABLED) {
> - adev->pm.dpm_enabled = false;
> - return 0;
> - }
> -
> - if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
> - adev->pm.dpm_enabled = true;
> -
>   return ret;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 488347a..8c725d2 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -41,11 +41,8 @@ static inline int pp_check(struct pp_instance *handle)
>   if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs ==
> NULL)
>   return -EINVAL;
> 
> - if (handle->pm_en == 0)
> - return PP_DPM_DISABLED;
> -
>   if (handle->hwmgr->hwmgr_func == NULL)
> - return PP_DPM_DISABLED;
> + handle->pm_en = 0;
> 
>   return 0;
>  }
> @@ -96,14 +93,8 @@ static int pp_early_init(void *handle)
>   return -EINVAL;
> 
>   ret = hwmgr_early_init(pp_handle);
> - if (ret)
> - return -EINVAL;
> 
> - if ((pp_handle->pm_en == 0)
> - || cgs_is_virtualization_enabled(pp_handle->device))
> - return PP_DPM_DISABLED;
> -
> - return 0;
> + return ret;
>  }
> 
>  static int pp_sw_init(void *handle)
> @@ -114,7 +105,7 @@ static int pp_sw_init(void *handle)
> 
>   ret = pp_check(pp_handle);
> 
> - if (ret == 0 || ret == PP_DPM_DISABLED) {
> + if (!ret) {
>   hwmgr = pp_handle->hwmgr;
> 
>   if (hwmgr->smumgr_funcs->smu_init == NULL)
> @@ -134,7 +125,7 @@ static int pp_sw_fini(void *handle)
>   struct pp_instance *pp_handle = (struct pp_instance *)handle;
> 
>   ret = pp_check(pp_handle);
> - if (ret == 0 || ret == PP_DPM_DISABLED) {
> + if (!ret) {
>   hwmgr = pp_handle->hwmgr;
> 
>   if (hwmgr->smumgr_funcs->smu_fini == NULL)
> @@ -153,7 +144,7 @@ static int pp_hw_init(void *handle)
> 
>   ret = pp_check(pp_handle);
> 
> - if (ret == 0 || ret == PP_DPM_DISABLED) {
> + if (!ret) {
>   hwmgr = pp_handle->hwmgr;
> 
>   if (hwmgr->smumgr_funcs->start_smu == NULL)
> @@ -164,17 +155,16 @@ static int pp_hw_init(void *handle)
>   hwmgr->smumgr_funcs->smu_fini(pp_handle-
> >hwmgr);
>   return -EINVAL;;
>   }
> - if (ret == PP_DPM_DISABLED)
> - return PP_DPM_DISABLED;
>   }
> 
> - ret = hwmgr_hw_init(pp_handle);
> - if (ret)
> - goto err;
> + if (pp_handle->pm_en) {
> + ret = hwmgr_hw_init(pp_handle);
> + if (ret) {
> + pp_handle->pm_en = 0;
> + cgs_notify_dpm_enabled(hwmgr->device, false);
> + }
> + }
>   return 0;
> -err:
> - pp_handle->pm_en = 0;
> - return PP_DPM_DISABLED;
>  }
> 
>  static int pp_hw_fini(void *handle)
> @@ -183,7 +173,7 @@ static int pp_hw_fini(void *handle)
>   int ret = 0;
> 
>   ret = pp_check(pp_handle);
> - if (ret == 0)
> + if (!ret && 

Re: [PATCH 4/5] drm/amd/sched: NULL out the s_fence field after run_job

[Andres Rodriguez]

On 2017-09-28 10:55 AM, Nicolai Hähnle wrote:

From: Nicolai Hähnle 

amd_sched_process_job drops the fence reference, so NULL out the s_fence
field before adding it as a callback to guard against accidentally using
s_fence after it may have be freed.

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index e793312e351c..54eb77cffd9b 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -604,20 +604,23 @@ static int amd_sched_main(void *param)
if (!sched_job)
continue;
  
  		s_fence = sched_job->s_fence;
  
  		atomic_inc(>hw_rq_count);

amd_sched_job_begin(sched_job);
  
  		fence = sched->ops->run_job(sched_job);

amd_sched_fence_scheduled(s_fence);
+
+   sched_job->s_fence = NULL;


Minor optional nitpick here. Could this be moved somewhere closer to 
where the fence reference is actually dropped? Alternatively, could a 
comment be added to specify which function call results in the reference 
ownership transfer?


Whether a change is made or not, this series is
Reviewed-by: Andres Rodriguez 

Currently running piglit to check if this fixes the occasional soft 
hangs I was getting where all tests complete except one.



+
if (fence) {
s_fence->parent = dma_fence_get(fence);
r = dma_fence_add_callback(fence, _fence->cb,
   amd_sched_process_job);
if (r == -ENOENT)
amd_sched_process_job(fence, _fence->cb);
else if (r)
DRM_ERROR("fence add callback failed (%d)\n",
  r);
dma_fence_put(fence);


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amd/sched: signal and free remaining fences in amd_sched_entity_fini

[Marek Olšák]

Thanks for this series. I can finally finish piglit on VI.

Marek

On Thu, Sep 28, 2017 at 4:55 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Highly concurrent Piglit runs can trigger a race condition where a pending
> SDMA job on a buffer object is never executed because the corresponding
> process is killed (perhaps due to a crash). Since the job's fences were
> never signaled, the buffer object was effectively leaked. Worse, the
> buffer was stuck wherever it happened to be at the time, possibly in VRAM.
>
> The symptom was user space processes stuck in interruptible waits with
> kernel stacks like:
>
> [] dma_fence_default_wait+0x112/0x250
> [] dma_fence_wait_timeout+0x39/0xf0
> [] reservation_object_wait_timeout_rcu+0x1c2/0x300
> [] ttm_bo_cleanup_refs_and_unlock+0xff/0x1a0 [ttm]
> [] ttm_mem_evict_first+0xba/0x1a0 [ttm]
> [] ttm_bo_mem_space+0x341/0x4c0 [ttm]
> [] ttm_bo_validate+0xd4/0x150 [ttm]
> [] ttm_bo_init_reserved+0x2ed/0x420 [ttm]
> [] amdgpu_bo_create_restricted+0x1f3/0x470 [amdgpu]
> [] amdgpu_bo_create+0xda/0x220 [amdgpu]
> [] amdgpu_gem_object_create+0xaa/0x140 [amdgpu]
> [] amdgpu_gem_create_ioctl+0x97/0x120 [amdgpu]
> [] drm_ioctl+0x1fa/0x480 [drm]
> [] amdgpu_drm_ioctl+0x4f/0x90 [amdgpu]
> [] do_vfs_ioctl+0xa3/0x5f0
> [] SyS_ioctl+0x79/0x90
> [] entry_SYSCALL_64_fastpath+0x1e/0xad
> [] 0x
>
> Signed-off-by: Nicolai Hähnle 
> Acked-by: Christian König 
> ---
>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
> b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
> index 54eb77cffd9b..32a99e980d78 100644
> --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
> +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
> @@ -220,22 +220,27 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler 
> *sched,
> amd_sched_entity_is_idle(entity));
> amd_sched_rq_remove_entity(rq, entity);
> if (r) {
> struct amd_sched_job *job;
>
> /* Park the kernel for a moment to make sure it isn't 
> processing
>  * our enity.
>  */
> kthread_park(sched->thread);
> kthread_unpark(sched->thread);
> -   while (kfifo_out(>job_queue, , sizeof(job)))
> +   while (kfifo_out(>job_queue, , sizeof(job))) {
> +   struct amd_sched_fence *s_fence = job->s_fence;
> +   amd_sched_fence_scheduled(s_fence);
> +   amd_sched_fence_finished(s_fence);
> +   dma_fence_put(_fence->finished);
> sched->ops->free_job(job);
> +   }
>
> }
> kfifo_free(>job_queue);
>  }
>
>  static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb 
> *cb)
>  {
> struct amd_sched_entity *entity =
> container_of(cb, struct amd_sched_entity, cb);
> entity->dependency = NULL;
> --
> 2.11.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH v2] drm/amd/display: DC I2C review

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Harry Wentland
> Sent: Thursday, September 28, 2017 10:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: daniel.vet...@ffwll.ch; dri-de...@lists.freedesktop.org;
> seanp...@chromium.org; Deucher, Alexander; daniel.vet...@intel.com;
> Wentland, Harry
> Subject: [PATCH v2] drm/amd/display: DC I2C review
> 
> While reviewing I2C in DC identified a few places. Added a couple to the
> TODO list.
> 
> 1) Connector info read
> 
> See get_ext_display_connection_info
> 
> On some boards the connector information has to be read through a
> special I2C channel. This line is only used for this purpose and only on
> driver init.
> 
> 2) SCDC stuff
> 
> This should all be reworked to go through DRM's SCDC code. When this is
> done some unnecessary I2C code can be retired as well.
> 
> 3) Max TMDS clock read
> 
> See dal_ddc_service_i2c_query_dp_dual_mode_adaptor
> 
> This should happen in DRM as well. I haven't checked if there's
> currently functionality in DRM. If not we can propose something.
> 
> 4) HDMI retimer programming
> 
> Some boards have an HDMI retimer that we need to program to pass PHY
> compliance.
> 
> 1 & 3 might be a good exercise if someone is looking for things to do.
> 
> v2: Merge dp_dual_mode_adaptor TODO
> 
> Signed-off-by: Harry Wentland 
> Acked-by: Daniel Vetter 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/TODO | 25 ++---
>  1 file changed, 10 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/TODO
> b/drivers/gpu/drm/amd/display/TODO
> index eea645b102a1..46464678f2b3 100644
> --- a/drivers/gpu/drm/amd/display/TODO
> +++ b/drivers/gpu/drm/amd/display/TODO
> @@ -62,20 +62,10 @@ TODOs
>  ~ Daniel Vetter
> 
> 
> -11. Remove existing i2c implementation from DC
> -
> -"Similar story for i2c, it uses the kernel's i2c code now, but there's
> -still a full i2c implementation hidden beneath that in
> -display/dc/i2caux. Kinda not cool, but imo ok if you fix that
> -post-merging (perhaps by not including any of this in the linux DC
> -code in the upstream kernel, but as an aux module in your internal
> -codebase since there you probably need that, same applies to the edid
> -parsing DC still does. For both cases I assume that the minimal shim
> -you need on linux (bit banging and edid parsing isn't rocket since) is
> -a lot less than the glue code to interface with the dc-provided
> -abstraction."
> -~ Daniel Vetter
> -
> +11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically
> an
> +overy complicated HW programming function for sendind and receiving
> i2c/aux
> +commands. We can greatly simplify that and move it into dc/dceXYZ like
> other
> +HW blocks.
> 
>  12. drm_modeset_lock in MST should no longer be needed in recent kernels
>  * Adopt appropriate locking scheme
> @@ -89,7 +79,8 @@ moving all your driver state printing into the various
> atomic_print_state
>  callbacks. There's also plans to expose this stuff in a standard way across 
> all
>  drivers, to make debugging userspace compositors easier across different
> hw.
> 
> -15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c.
> +15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c.
> See
> +dal_ddc_service_i2c_query_dp_dual_mode_adaptor.
> 
>  16. Move to core SCDC helpers (I think those are new since initial DC 
> review).
> 
> @@ -110,3 +101,7 @@ guilty.
>  stuff just isn't up to the challenges either. We need to figure out something
>  that integrates better with DRM and linux debug printing, while not being
>  useless with filtering output. dynamic debug printing might be an option.
> +
> +20. Use kernel i2c device to program HDMI retimer. Some boards have an
> HDMI
> +retimer that we need to program to pass PHY compliance. Currently that's
> +bypassing the i2c device and goes directly to HW. This should be changed.
> --
> 2.11.0
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/dc: drop dml_util_is_420

[Harry Wentland]

On 2017-09-27 08:55 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This is unused code.
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  .../gpu/drm/amd/display/dc/dml/dml_common_defs.c   | 33 
> --
>  .../gpu/drm/amd/display/dc/dml/dml_common_defs.h   |  1 -
>  2 files changed, 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> index c242b8d..7c0eb52 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> @@ -59,36 +59,3 @@ unsigned int dml_round_to_multiple(
>   else
>   return (num - remainder);
>  }
> -
> -bool dml_util_is_420(enum source_format_class sorce_format)
> -{
> - bool val = false;
> -
> - switch (sorce_format) {
> - case dm_444_16:
> - val = false;
> - break;
> - case dm_444_32:
> - val = false;
> - break;
> - case dm_444_64:
> - val = false;
> - break;
> - case dm_420_8:
> - val = true;
> - break;
> - case dm_420_10:
> - val = true;
> - break;
> - case dm_422_8:
> - val = false;
> - break;
> - case dm_422_10:
> - val = false;
> - break;
> - default:
> - BREAK_TO_DEBUGGER();
> - }
> -
> - return val;
> -}
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h 
> b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> index c621f83..a2da3da 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> @@ -32,7 +32,6 @@
>  
>  #define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, 
> ##__VA_ARGS__);
>  
> -bool dml_util_is_420(enum source_format_class sorce_format);
>  double dml_round(double a);
>  unsigned int dml_round_to_multiple(
>   unsigned int num, unsigned int multiple, bool up);
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/dc: don't check for 0 on register read/writes always.

[Harry Wentland]

On 2017-09-27 10:42 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This adds ~50k to the driver text segment, and 10k to data segment.
> 
>text  data bss dec hex filename
> 2385556 396811045 2426282  2505aa 
> drivers/gpu/drm/amd/amdgpu/amdgpu.o
>   text   data bss dec hex filename
> 2336593 288571045 2366495  241c1f 
> drivers/gpu/drm/amd/amdgpu/amdgpu.o
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

> ---
>  drivers/gpu/drm/amd/display/dc/dm_services.h | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
> b/drivers/gpu/drm/amd/display/dc/dm_services.h
> index 8ab0af6..c976e2a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
> @@ -96,6 +96,9 @@ irq_handler_idx dm_register_interrupt(
>   *
>   */
>  
> +/* enable for debugging new code, this adds 50k to the driver size. */
> +/* #define DM_CHECK_ADDR_0 */
> +

I like this approach. It allows us to also set it on internal builds for
dev teams.

Harry

>  #define dm_read_reg(ctx, address)\
>   dm_read_reg_func(ctx, address, __func__)
>  
> @@ -105,12 +108,12 @@ static inline uint32_t dm_read_reg_func(
>   const char *func_name)
>  {
>   uint32_t value;
> -
> +#ifdef DM_CHECK_ADDR_0
>   if (address == 0) {
>   DC_ERR("invalid register read; address = 0\n");
>   return 0;
>   }
> -
> +#endif
>   value = cgs_read_register(ctx->cgs_device, address);
>  
>   return value;
> @@ -125,10 +128,12 @@ static inline void dm_write_reg_func(
>   uint32_t value,
>   const char *func_name)
>  {
> +#ifdef DM_CHECK_ADDR_0
>   if (address == 0) {
>   DC_ERR("invalid register write. address = 0");
>   return;
>   }
> +#endif
>   cgs_write_register(ctx->cgs_device, address, value);
>  }
>  
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amd/sched: signal and free remaining fences in amd_sched_entity_fini

[Christian König]

Am 28.09.2017 um 16:55 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

Highly concurrent Piglit runs can trigger a race condition where a pending
SDMA job on a buffer object is never executed because the corresponding
process is killed (perhaps due to a crash). Since the job's fences were
never signaled, the buffer object was effectively leaked. Worse, the
buffer was stuck wherever it happened to be at the time, possibly in VRAM.

The symptom was user space processes stuck in interruptible waits with
kernel stacks like:

 [] dma_fence_default_wait+0x112/0x250
 [] dma_fence_wait_timeout+0x39/0xf0
 [] reservation_object_wait_timeout_rcu+0x1c2/0x300
 [] ttm_bo_cleanup_refs_and_unlock+0xff/0x1a0 [ttm]
 [] ttm_mem_evict_first+0xba/0x1a0 [ttm]
 [] ttm_bo_mem_space+0x341/0x4c0 [ttm]
 [] ttm_bo_validate+0xd4/0x150 [ttm]
 [] ttm_bo_init_reserved+0x2ed/0x420 [ttm]
 [] amdgpu_bo_create_restricted+0x1f3/0x470 [amdgpu]
 [] amdgpu_bo_create+0xda/0x220 [amdgpu]
 [] amdgpu_gem_object_create+0xaa/0x140 [amdgpu]
 [] amdgpu_gem_create_ioctl+0x97/0x120 [amdgpu]
 [] drm_ioctl+0x1fa/0x480 [drm]
 [] amdgpu_drm_ioctl+0x4f/0x90 [amdgpu]
 [] do_vfs_ioctl+0xa3/0x5f0
 [] SyS_ioctl+0x79/0x90
 [] entry_SYSCALL_64_fastpath+0x1e/0xad
 [] 0x

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 54eb77cffd9b..32a99e980d78 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -220,22 +220,27 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler 
*sched,
amd_sched_entity_is_idle(entity));
amd_sched_rq_remove_entity(rq, entity);
if (r) {
struct amd_sched_job *job;
  
  		/* Park the kernel for a moment to make sure it isn't processing

 * our enity.
 */
kthread_park(sched->thread);
kthread_unpark(sched->thread);
-   while (kfifo_out(>job_queue, , sizeof(job)))
+   while (kfifo_out(>job_queue, , sizeof(job))) {
+   struct amd_sched_fence *s_fence = job->s_fence;
+   amd_sched_fence_scheduled(s_fence);


It would be really nice to have an error code set on s_fence->finished 
before it is signaled, use dma_fence_set_error() for this.


Additional to that it would be nice to note in the subject line that 
this is a rather important bug fix.


With that fixed the whole series is Reviewed-by: Christian König 
.


Regards,
Christian.


+   amd_sched_fence_finished(s_fence);
+   dma_fence_put(_fence->finished);
sched->ops->free_job(job);
+   }
  
  	}

kfifo_free(>job_queue);
  }
  
  static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb)

  {
struct amd_sched_entity *entity =
container_of(cb, struct amd_sched_entity, cb);
entity->dependency = NULL;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/amd/sched: fix an outdated comment

[Nicolai Hähnle]

From: Nicolai Hähnle 

Signed-off-by: Nicolai Hähnle 
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 742d724cd720..6e899c593b7e 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -347,22 +347,21 @@ static bool amd_sched_entity_in(struct amd_sched_job 
*sched_job)
 
/* first job wakes up scheduler */
if (first) {
/* Add the entity to the run queue */
amd_sched_rq_add_entity(entity->rq, entity);
amd_sched_wakeup(sched);
}
return added;
 }
 
-/* job_finish is called after hw fence signaled, and
- * the job had already been deleted from ring_mirror_list
+/* job_finish is called after hw fence signaled
  */
 static void amd_sched_job_finish(struct work_struct *work)
 {
struct amd_sched_job *s_job = container_of(work, struct amd_sched_job,
   finish_work);
struct amd_gpu_scheduler *sched = s_job->sched;
 
/* remove job from ring_mirror_list */
spin_lock(>job_list_lock);
list_del_init(_job->node);
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/amd/sched: move adding finish callback to amd_sched_job_begin

[Nicolai Hähnle]

From: Nicolai Hähnle 

The finish callback is responsible for removing the job from the ring
mirror list, among other things. It makes sense to add it as callback
in the place where the job is added to the ring mirror list.

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 6e899c593b7e..e793312e351c 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -388,20 +388,23 @@ static void amd_sched_job_finish_cb(struct dma_fence *f,
 {
struct amd_sched_job *job = container_of(cb, struct amd_sched_job,
 finish_cb);
schedule_work(>finish_work);
 }
 
 static void amd_sched_job_begin(struct amd_sched_job *s_job)
 {
struct amd_gpu_scheduler *sched = s_job->sched;
 
+   dma_fence_add_callback(_job->s_fence->finished, _job->finish_cb,
+  amd_sched_job_finish_cb);
+
spin_lock(>job_list_lock);
list_add_tail(_job->node, >ring_mirror_list);
if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
list_first_entry_or_null(>ring_mirror_list,
 struct amd_sched_job, node) == s_job)
schedule_delayed_work(_job->work_tdr, sched->timeout);
spin_unlock(>job_list_lock);
 }
 
 static void amd_sched_job_timedout(struct work_struct *work)
@@ -480,22 +483,20 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler 
*sched)
  *
  * @sched_job  The pointer to job required to submit
  *
  * Returns 0 for success, negative error code otherwise.
  */
 void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
 {
struct amd_sched_entity *entity = sched_job->s_entity;
 
trace_amd_sched_job(sched_job);
-   dma_fence_add_callback(_job->s_fence->finished, 
_job->finish_cb,
-  amd_sched_job_finish_cb);
wait_event(entity->sched->job_scheduled,
   amd_sched_entity_in(sched_job));
 }
 
 /* init a sched_job with basic field */
 int amd_sched_job_init(struct amd_sched_job *job,
   struct amd_gpu_scheduler *sched,
   struct amd_sched_entity *entity,
   void *owner)
 {
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/5] drm/amd/sched: rename amd_sched_entity_pop_job

[Nicolai Hähnle]

From: Nicolai Hähnle 

The function does not actually remove the job from the FIFO, so "peek"
describes it better.

Signed-off-by: Nicolai Hähnle 
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 97c94f9683fa..742d724cd720 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -301,21 +301,21 @@ static bool amd_sched_entity_add_dependency_cb(struct 
amd_sched_entity *entity)
 
if (!dma_fence_add_callback(entity->dependency, >cb,
amd_sched_entity_wakeup))
return true;
 
dma_fence_put(entity->dependency);
return false;
 }
 
 static struct amd_sched_job *
-amd_sched_entity_pop_job(struct amd_sched_entity *entity)
+amd_sched_entity_peek_job(struct amd_sched_entity *entity)
 {
struct amd_gpu_scheduler *sched = entity->sched;
struct amd_sched_job *sched_job;
 
if (!kfifo_out_peek(>job_queue, _job, sizeof(sched_job)))
return NULL;
 
while ((entity->dependency = sched->ops->dependency(sched_job)))
if (amd_sched_entity_add_dependency_cb(entity))
return NULL;
@@ -593,21 +593,21 @@ static int amd_sched_main(void *param)
struct dma_fence *fence;
 
wait_event_interruptible(sched->wake_up_worker,
 (!amd_sched_blocked(sched) &&
  (entity = 
amd_sched_select_entity(sched))) ||
 kthread_should_stop());
 
if (!entity)
continue;
 
-   sched_job = amd_sched_entity_pop_job(entity);
+   sched_job = amd_sched_entity_peek_job(entity);
if (!sched_job)
continue;
 
s_fence = sched_job->s_fence;
 
atomic_inc(>hw_rq_count);
amd_sched_job_begin(sched_job);
 
fence = sched->ops->run_job(sched_job);
amd_sched_fence_scheduled(s_fence);
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amd/sched: NULL out the s_fence field after run_job

[Nicolai Hähnle]

From: Nicolai Hähnle 

amd_sched_process_job drops the fence reference, so NULL out the s_fence
field before adding it as a callback to guard against accidentally using
s_fence after it may have be freed.

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index e793312e351c..54eb77cffd9b 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -604,20 +604,23 @@ static int amd_sched_main(void *param)
if (!sched_job)
continue;
 
s_fence = sched_job->s_fence;
 
atomic_inc(>hw_rq_count);
amd_sched_job_begin(sched_job);
 
fence = sched->ops->run_job(sched_job);
amd_sched_fence_scheduled(s_fence);
+
+   sched_job->s_fence = NULL;
+
if (fence) {
s_fence->parent = dma_fence_get(fence);
r = dma_fence_add_callback(fence, _fence->cb,
   amd_sched_process_job);
if (r == -ENOENT)
amd_sched_process_job(fence, _fence->cb);
else if (r)
DRM_ERROR("fence add callback failed (%d)\n",
  r);
dma_fence_put(fence);
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/5] drm/amd/sched: signal and free remaining fences in amd_sched_entity_fini

[Nicolai Hähnle]

From: Nicolai Hähnle 

Highly concurrent Piglit runs can trigger a race condition where a pending
SDMA job on a buffer object is never executed because the corresponding
process is killed (perhaps due to a crash). Since the job's fences were
never signaled, the buffer object was effectively leaked. Worse, the
buffer was stuck wherever it happened to be at the time, possibly in VRAM.

The symptom was user space processes stuck in interruptible waits with
kernel stacks like:

[] dma_fence_default_wait+0x112/0x250
[] dma_fence_wait_timeout+0x39/0xf0
[] reservation_object_wait_timeout_rcu+0x1c2/0x300
[] ttm_bo_cleanup_refs_and_unlock+0xff/0x1a0 [ttm]
[] ttm_mem_evict_first+0xba/0x1a0 [ttm]
[] ttm_bo_mem_space+0x341/0x4c0 [ttm]
[] ttm_bo_validate+0xd4/0x150 [ttm]
[] ttm_bo_init_reserved+0x2ed/0x420 [ttm]
[] amdgpu_bo_create_restricted+0x1f3/0x470 [amdgpu]
[] amdgpu_bo_create+0xda/0x220 [amdgpu]
[] amdgpu_gem_object_create+0xaa/0x140 [amdgpu]
[] amdgpu_gem_create_ioctl+0x97/0x120 [amdgpu]
[] drm_ioctl+0x1fa/0x480 [drm]
[] amdgpu_drm_ioctl+0x4f/0x90 [amdgpu]
[] do_vfs_ioctl+0xa3/0x5f0
[] SyS_ioctl+0x79/0x90
[] entry_SYSCALL_64_fastpath+0x1e/0xad
[] 0x

Signed-off-by: Nicolai Hähnle 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index 54eb77cffd9b..32a99e980d78 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -220,22 +220,27 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler 
*sched,
amd_sched_entity_is_idle(entity));
amd_sched_rq_remove_entity(rq, entity);
if (r) {
struct amd_sched_job *job;
 
/* Park the kernel for a moment to make sure it isn't processing
 * our enity.
 */
kthread_park(sched->thread);
kthread_unpark(sched->thread);
-   while (kfifo_out(>job_queue, , sizeof(job)))
+   while (kfifo_out(>job_queue, , sizeof(job))) {
+   struct amd_sched_fence *s_fence = job->s_fence;
+   amd_sched_fence_scheduled(s_fence);
+   amd_sched_fence_finished(s_fence);
+   dma_fence_put(_fence->finished);
sched->ops->free_job(job);
+   }
 
}
kfifo_free(>job_queue);
 }
 
 static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb 
*cb)
 {
struct amd_sched_entity *entity =
container_of(cb, struct amd_sched_entity, cb);
entity->dependency = NULL;
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH][drm-next] drm/radeon: make functions alloc_pasid and free_pasid static

[Colin King]

From: Colin Ian King 

The functions alloc_pasid  and free_pasid are local to the
source and do not need to be in global scope, so make them static.

Cleans up sparse warnings:
warning: symbol 'alloc_pasid' was not declared. Should it be static?
warning: symbol 'free_pasid' was not declared. Should it be static?

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/radeon/radeon_kfd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c 
b/drivers/gpu/drm/radeon/radeon_kfd.c
index a2ac8ac0930d..385b4d76956d 100644
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -352,7 +352,7 @@ static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev 
*kgd)
  */
 static DEFINE_IDA(pasid_ida);
 
-int alloc_pasid(unsigned int bits)
+static int alloc_pasid(unsigned int bits)
 {
int pasid = -EINVAL;
 
@@ -367,7 +367,7 @@ int alloc_pasid(unsigned int bits)
return pasid;
 }
 
-void free_pasid(unsigned int pasid)
+static void free_pasid(unsigned int pasid)
 {
ida_simple_remove(_ida, pasid);
 }
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/dc: add static to construct function

[Harry Wentland]

On 2017-09-27 07:21 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> There was a global construct symbol in the module symbols, kill it.
> 

Good catch. I should really watch out for global namespace pollution
which is really not cool in the kernel tree.

> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> index 7cce284..c627694 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
> @@ -406,7 +406,7 @@ static const struct irq_service_funcs 
> irq_service_funcs_dce110 = {
>   .to_dal_irq_source = to_dal_irq_source_dce110
>  };
>  
> -bool construct(
> +static bool construct(
>   struct irq_service *irq_service,
>   struct irq_service_init_data *init_data)
>  {
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] amdgpu/dc: move filter taps to being static const data (v2)

[Harry Wentland]

On 2017-09-27 08:22 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This just adds two accessor methods, and moves all the data
> to static const.
> 
> v2: fix dcn build.
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  .../gpu/drm/amd/display/dc/dce/dce_scl_filters.c   | 78 
> --
>  drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |  2 +-
>  .../drm/amd/display/dc/dce110/dce110_transform_v.c |  2 +-
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  2 +-
>  drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |  4 +-
>  5 files changed, 49 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
> index 2cfdb83..6243450 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
> @@ -25,7 +25,7 @@
>  
>  #include "transform.h"
>  
> -const uint16_t filter_2tap_16p[18] = {
> +static const uint16_t filter_2tap_16p[18] = {
>   4096, 0,
>   3840, 256,
>   3584, 512,
> @@ -37,7 +37,7 @@ const uint16_t filter_2tap_16p[18] = {
>   2048, 2048
>  };
>  
> -const uint16_t filter_3tap_16p_upscale[27] = {
> +static const uint16_t filter_3tap_16p_upscale[27] = {
>   2048, 2048, 0,
>   1708, 2424, 16348,
>   1372, 2796, 16308,
> @@ -49,7 +49,7 @@ const uint16_t filter_3tap_16p_upscale[27] = {
>   0, 4096, 0
>  };
>  
> -const uint16_t filter_3tap_16p_117[27] = {
> +static const uint16_t filter_3tap_16p_117[27] = {
>   2048, 2048, 0,
>   1824, 2276, 16376,
>   1600, 2496, 16380,
> @@ -61,7 +61,7 @@ const uint16_t filter_3tap_16p_117[27] = {
>   428, 3236, 428
>  };
>  
> -const uint16_t filter_3tap_16p_150[27] = {
> +static const uint16_t filter_3tap_16p_150[27] = {
>   2048, 2048, 0,
>   1872, 2184, 36,
>   1692, 2308, 88,
> @@ -73,7 +73,7 @@ const uint16_t filter_3tap_16p_150[27] = {
>   696, 2696, 696
>  };
>  
> -const uint16_t filter_3tap_16p_183[27] = {
> +static const uint16_t filter_3tap_16p_183[27] = {
>   2048, 2048, 0,
>   1892, 2104, 92,
>   1744, 2152, 196,
> @@ -85,7 +85,7 @@ const uint16_t filter_3tap_16p_183[27] = {
>   900, 2292, 900
>  };
>  
> -const uint16_t filter_4tap_16p_upscale[36] = {
> +static const uint16_t filter_4tap_16p_upscale[36] = {
>   0, 4096, 0, 0,
>   16240, 4056, 180, 16380,
>   16136, 3952, 404, 16364,
> @@ -97,7 +97,7 @@ const uint16_t filter_4tap_16p_upscale[36] = {
>   16128, 2304, 2304, 16128
>  };
>  
> -const uint16_t filter_4tap_16p_117[36] = {
> +static const uint16_t filter_4tap_16p_117[36] = {
>   428, 3236, 428, 0,
>   276, 3232, 604, 16364,
>   148, 3184, 800, 16340,
> @@ -109,7 +109,7 @@ const uint16_t filter_4tap_16p_117[36] = {
>   16212, 2216, 2216, 16212
>  };
>  
> -const uint16_t filter_4tap_16p_150[36] = {
> +static const uint16_t filter_4tap_16p_150[36] = {
>   696, 2700, 696, 0,
>   560, 2700, 848, 16364,
>   436, 2676, 1008, 16348,
> @@ -121,7 +121,7 @@ const uint16_t filter_4tap_16p_150[36] = {
>   16376, 2052, 2052, 16376
>  };
>  
> -const uint16_t filter_4tap_16p_183[36] = {
> +static const uint16_t filter_4tap_16p_183[36] = {
>   940, 2208, 940, 0,
>   832, 2200, 1052, 4,
>   728, 2180, 1164, 16,
> @@ -133,7 +133,7 @@ const uint16_t filter_4tap_16p_183[36] = {
>   232, 1812, 1812, 232
>  };
>  
> -const uint16_t filter_2tap_64p[66] = {
> +static const uint16_t filter_2tap_64p[66] = {
>   4096, 0,
>   4032, 64,
>   3968, 128,
> @@ -168,7 +168,7 @@ const uint16_t filter_2tap_64p[66] = {
>   2112, 1984,
>   2048, 2048 };
>  
> -const uint16_t filter_3tap_64p_upscale[99] = {
> +static const uint16_t filter_3tap_64p_upscale[99] = {
>   2048, 2048, 0,
>   1960, 2140, 16376,
>   1876, 2236, 16364,
> @@ -204,7 +204,7 @@ const uint16_t filter_3tap_64p_upscale[99] = {
>   0, 4096, 0
>  };
>  
> -const uint16_t filter_3tap_64p_117[99] = {
> +static const uint16_t filter_3tap_64p_117[99] = {
>   2048, 2048, 0,
>   1992, 2104, 16380,
>   1936, 2160, 16380,
> @@ -240,7 +240,7 @@ const uint16_t filter_3tap_64p_117[99] = {
>   428, 3236, 428
>  };
>  
> -const uint16_t filter_3tap_64p_150[99] = {
> +static const uint16_t filter_3tap_64p_150[99] = {
>   2048, 2048, 0,
>   2004, 2080, 8,
>   1960, 2116, 16,
> @@ -276,7 +276,7 @@ const uint16_t filter_3tap_64p_150[99] = {
>   696, 2696, 696
>  };
>  
> -const uint16_t filter_3tap_64p_183[99] = {
> +static const uint16_t filter_3tap_64p_183[99] = {
>   2048, 2048, 0,
>   2008, 2060, 20,
>   1968, 2076, 44,
> @@ -312,7 +312,7 @@ const uint16_t filter_3tap_64p_183[99] = {
>   900, 2292, 900
>  };
>  
> -const uint16_t filter_4tap_64p_upscale[132] = {
> +static const uint16_t filter_4tap_64p_upscale[132] = {
>

Re: [PATCH] amdgpu/dc: separate out some common code from bios parsers.

[Harry Wentland]

On 2017-09-27 09:24 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This extracts the bios parser object id handling into a common file.
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/bios/Makefile   |   2 +-
>  drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  | 274 +---
>  drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 284 +---
>  .../drm/amd/display/dc/bios/bios_parser_common.c   | 288 
> +
>  .../drm/amd/display/dc/bios/bios_parser_common.h   |  33 +++
>  5 files changed, 324 insertions(+), 557 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
> b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> index a26cc60..6ec815d 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> @@ -2,7 +2,7 @@
>  # Makefile for the 'bios' sub-component of DAL.
>  # It provides the parsing and executing controls for atom bios image.
>  
> -BIOS = bios_parser.o bios_parser_interface.o  bios_parser_helper.o 
> command_table.o command_table_helper.o
> +BIOS = bios_parser.o bios_parser_interface.o  bios_parser_helper.o 
> command_table.o command_table_helper.o bios_parser_common.o
>  
>  BIOS += command_table2.o command_table_helper2.o bios_parser2.o
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 
> b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> index 2c41144..c742720 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> @@ -41,6 +41,7 @@
>  #include "bios_parser_types_internal.h"
>  #include "bios_parser_interface.h"
>  
> +#include "bios_parser_common.h"
>  /* TODO remove - only needed for default i2c speed */
>  #include "dc.h"
>  
> @@ -57,18 +58,6 @@ static const uint8_t 
> ext_display_connection_guid[NUMBER_OF_UCHAR_FOR_GUID] = {
>  
>  #define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)
>  
> -static enum object_type object_type_from_bios_object_id(
> - uint32_t bios_object_id);
> -static struct graphics_object_id object_id_from_bios_object_id(
> - uint32_t bios_object_id);
> -static enum object_enum_id enum_id_from_bios_object_id(uint32_t 
> bios_object_id);
> -static enum encoder_id encoder_id_from_bios_object_id(uint32_t 
> bios_object_id);
> -static enum connector_id connector_id_from_bios_object_id(
> - uint32_t bios_object_id);
> -static uint32_t id_from_bios_object_id(enum object_type type,
> - uint32_t bios_object_id);
> -static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id);
> -static enum generic_id generic_id_from_bios_object_id(uint32_t 
> bios_object_id);
>  static void get_atom_data_table_revision(
>   ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
>   struct atom_data_revision *tbl_revision);
> @@ -2403,267 +2392,6 @@ static uint32_t get_dst_number_from_object(struct 
> bios_parser *bp,
>   return *number;
>  }
>  
> -
> -static struct graphics_object_id object_id_from_bios_object_id(
> - uint32_t bios_object_id)
> -{
> - enum object_type type;
> - enum object_enum_id enum_id;
> - struct graphics_object_id go_id = { 0 };
> -
> - type = object_type_from_bios_object_id(bios_object_id);
> -
> - if (OBJECT_TYPE_UNKNOWN == type)
> - return go_id;
> -
> - enum_id = enum_id_from_bios_object_id(bios_object_id);
> -
> - if (ENUM_ID_UNKNOWN == enum_id)
> - return go_id;
> -
> - go_id = dal_graphics_object_id_init(
> - id_from_bios_object_id(type, bios_object_id), enum_id, 
> type);
> -
> - return go_id;
> -}
> -
> -static enum object_type object_type_from_bios_object_id(uint32_t 
> bios_object_id)
> -{
> - uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
> - >> OBJECT_TYPE_SHIFT;
> - enum object_type object_type;
> -
> - switch (bios_object_type) {
> - case GRAPH_OBJECT_TYPE_GPU:
> - object_type = OBJECT_TYPE_GPU;
> - break;
> - case GRAPH_OBJECT_TYPE_ENCODER:
> - object_type = OBJECT_TYPE_ENCODER;
> - break;
> - case GRAPH_OBJECT_TYPE_CONNECTOR:
> - object_type = OBJECT_TYPE_CONNECTOR;
> - break;
> - case GRAPH_OBJECT_TYPE_ROUTER:
> - object_type = OBJECT_TYPE_ROUTER;
> - break;
> - case GRAPH_OBJECT_TYPE_GENERIC:
> - object_type = OBJECT_TYPE_GENERIC;
> - break;
> - default:
> - object_type = OBJECT_TYPE_UNKNOWN;
> - break;
> - }
> -
> - return object_type;
> -}
> -
> -static enum object_enum_id 

Re: [PATCH] amdgpu/dc: drop dml display_mode_support.c (v2)

[Harry Wentland]

On 2017-09-27 10:29 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This code isn't used, and this function is huge, reimport later if
> going to be used.
> 
> Signed-off-by: Dave Airlie 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dml/Makefile|4 +-
>  .../drm/amd/display/dc/dml/display_mode_support.c  | 2327 
> 
>  .../drm/amd/display/dc/dml/display_mode_support.h  |5 -
>  3 files changed, 1 insertion(+), 2335 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index a6bf364..ec712d7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -10,12 +10,10 @@ CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse 
> -mpreferred-stack-boundary
>  CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4
>  CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
>  CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -CFLAGS_display_mode_support.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> -
>  
>  DML = display_mode_lib.o display_rq_dlg_calc.o \
> display_rq_dlg_helpers.o display_watermark.o \
> -   soc_bounding_box.o dml_common_defs.o display_mode_support.o
> +   soc_bounding_box.o dml_common_defs.o
>  
>  AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c 
> b/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
> deleted file mode 100644
> index ac57356..000
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
> +++ /dev/null
> @@ -1,2327 +0,0 @@
> -/*
> - * Copyright 2017 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -#include "display_mode_support.h"
> -#include "display_mode_lib.h"
> -
> -#include "dml_inline_defs.h"
> -int dml_ms_check(
> - struct display_mode_lib *mode_lib,
> - struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
> - int num_pipes)
> -{
> - struct _vcs_dpi_ip_params_st *ip;
> - struct _vcs_dpi_soc_bounding_box_st *soc;
> - struct _vcs_dpi_mode_evaluation_st *me;
> - struct dml_ms_internal_vars *v;
> - int num_planes, i, j, ij, k, ijk;
> -
> - ip = &(mode_lib->ip);
> - soc = &(mode_lib->soc);
> - me = &(mode_lib->me);
> - v = &(mode_lib->vars);
> - num_planes = dml_wm_e2e_to_wm(mode_lib, e2e, num_pipes, v->planes);
> -
> - //instantiating variables to zero
> - v->MacroTileBlockWidthC = 0;
> - v->SwathWidthGranularityC = 0;
> -
> - v->DCFCLKPerState[5] = 0;
> - v->DCFCLKPerState[4] = 0;
> - v->DCFCLKPerState[3] = 0;
> - v->DCFCLKPerState[2] = 0;
> - v->DCFCLKPerState[1] = 0;
> - v->DCFCLKPerState[0] = 0;
> -
> - if (soc->vmin.dcfclk_mhz > 0) {
> - v->DCFCLKPerState[5] = soc->vmin.dcfclk_mhz;
> - v->DCFCLKPerState[4] = soc->vmin.dcfclk_mhz;
> - v->DCFCLKPerState[3] = soc->vmin.dcfclk_mhz;
> - v->DCFCLKPerState[2] = soc->vmin.dcfclk_mhz;
> - v->DCFCLKPerState[1] = soc->vmin.dcfclk_mhz;
> - v->DCFCLKPerState[0] = soc->vmin.dcfclk_mhz;
> - }
> -
> - if (soc->vmid.dcfclk_mhz > 0) {
> - v->DCFCLKPerState[5] = soc->vmid.dcfclk_mhz;
> - v->DCFCLKPerState[4] = soc->vmid.dcfclk_mhz;
> - v->DCFCLKPerState[3] = soc->vmid.dcfclk_mhz;
> - v->DCFCLKPerState[2] = soc->vmid.dcfclk_mhz;
> - v->DCFCLKPerState[1] = soc->vmid.dcfclk_mhz;
> - }
> -
> - if (soc->vnom.dcfclk_mhz > 

Re: [PATCH] amdgpu/dc: remove wait_reg/wait_reg_func interfaces.

[Harry Wentland]

On 2017-09-27 11:29 PM, Dave Airlie wrote:
> From: Dave Airlie 
> 
> These aren't used in the tree anywhere, and there is a TODO.
> 
> Signed-off-by: Dave Airlie 
Reviewed-by: Harry Wentland 

> ---
>  drivers/gpu/drm/amd/display/dc/dm_services.h | 46 
> 
>  1 file changed, 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
> b/drivers/gpu/drm/amd/display/dc/dm_services.h
> index c976e2a..8166027 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
> @@ -236,52 +236,6 @@ unsigned int generic_reg_wait(const struct dc_context 
> *ctx,
>   block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
>   block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
>  
> -/* TODO get rid of this pos*/
> -static inline bool wait_reg_func(
> - const struct dc_context *ctx,
> - uint32_t addr,
> - uint32_t mask,
> - uint8_t shift,
> - uint32_t condition_value,
> - unsigned int interval_us,
> - unsigned int timeout_us)
> -{
> - uint32_t field_value;
> - uint32_t reg_val;
> - unsigned int count = 0;
> -
> - if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
> - timeout_us *= 655;  /* 6553 give about 30 second before time 
> out */
> -
> - do {
> - /* try once without sleeping */
> - if (count > 0) {
> - if (interval_us >= 1000)
> - msleep(interval_us/1000);
> - else
> - udelay(interval_us);
> - }
> - reg_val = dm_read_reg(ctx, addr);
> - field_value = get_reg_field_value_ex(reg_val, mask, shift);
> - count += interval_us;
> -
> - } while (field_value != condition_value && count <= timeout_us);
> -
> - ASSERT(count <= timeout_us);
> -
> - return count <= timeout_us;
> -}
> -
> -#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\
> - wait_reg_func(\
> - ctx,\
> - mm##reg_name + inst_offset + 
> DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\
> - reg_name ## __ ## reg_field ## _MASK,\
> - reg_name ## __ ## reg_field ## __SHIFT,\
> - condition_value,\
> - 2,\
> - 20)
> -
>  /**
>   * Power Play (PP) interfaces
>   **/
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2] drm/amd/display: DC I2C review

[Harry Wentland]

While reviewing I2C in DC identified a few places. Added a couple to the
TODO list.

1) Connector info read

See get_ext_display_connection_info

On some boards the connector information has to be read through a
special I2C channel. This line is only used for this purpose and only on
driver init.

2) SCDC stuff

This should all be reworked to go through DRM's SCDC code. When this is
done some unnecessary I2C code can be retired as well.

3) Max TMDS clock read

See dal_ddc_service_i2c_query_dp_dual_mode_adaptor

This should happen in DRM as well. I haven't checked if there's
currently functionality in DRM. If not we can propose something.

4) HDMI retimer programming

Some boards have an HDMI retimer that we need to program to pass PHY
compliance.

1 & 3 might be a good exercise if someone is looking for things to do.

v2: Merge dp_dual_mode_adaptor TODO

Signed-off-by: Harry Wentland 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/amd/display/TODO | 25 ++---
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/TODO b/drivers/gpu/drm/amd/display/TODO
index eea645b102a1..46464678f2b3 100644
--- a/drivers/gpu/drm/amd/display/TODO
+++ b/drivers/gpu/drm/amd/display/TODO
@@ -62,20 +62,10 @@ TODOs
 ~ Daniel Vetter
 
 
-11. Remove existing i2c implementation from DC
-
-"Similar story for i2c, it uses the kernel's i2c code now, but there's
-still a full i2c implementation hidden beneath that in
-display/dc/i2caux. Kinda not cool, but imo ok if you fix that
-post-merging (perhaps by not including any of this in the linux DC
-code in the upstream kernel, but as an aux module in your internal
-codebase since there you probably need that, same applies to the edid
-parsing DC still does. For both cases I assume that the minimal shim
-you need on linux (bit banging and edid parsing isn't rocket since) is
-a lot less than the glue code to interface with the dc-provided
-abstraction."
-~ Daniel Vetter
-
+11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically an
+overy complicated HW programming function for sendind and receiving i2c/aux
+commands. We can greatly simplify that and move it into dc/dceXYZ like other
+HW blocks.
 
 12. drm_modeset_lock in MST should no longer be needed in recent kernels
 * Adopt appropriate locking scheme
@@ -89,7 +79,8 @@ moving all your driver state printing into the various 
atomic_print_state
 callbacks. There's also plans to expose this stuff in a standard way across all
 drivers, to make debugging userspace compositors easier across different hw.
 
-15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c.
+15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c. See
+dal_ddc_service_i2c_query_dp_dual_mode_adaptor.
 
 16. Move to core SCDC helpers (I think those are new since initial DC review).
 
@@ -110,3 +101,7 @@ guilty.
 stuff just isn't up to the challenges either. We need to figure out something
 that integrates better with DRM and linux debug printing, while not being
 useless with filtering output. dynamic debug printing might be an option.
+
+20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
+retimer that we need to program to pass PHY compliance. Currently that's
+bypassing the i2c device and goes directly to HW. This should be changed.
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] drm/amdgpu: add functions to create bo at the specified position

[Christian König]

NAK, please use the existing functionality for that.

Using amdgpu_bo_do_create() with domain=0 will just create the amdgpu_bo 
structure without allocating any backing memory.


This BO can then pinned to the desired VRAM location using amdgpu_bo_pin().

Regards,
Christian.

Am 28.09.2017 um 10:36 schrieb Horace Chen:

Add two function to create and free bo at the specified position
on the VRAM.

Add a new parameter to amdgpu_bo_do_create to tell the start
address of the special bo. If the start address is located in
the GPU MC address space, the placement will be set to the exact
place according to the size and start address. Otherwise the start
address will be ingored.

Signed-off-by: Horace Chen 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 129 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |   6 ++
  2 files changed, 133 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6982bae..0695160 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -284,6 +284,7 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 
*gpu_addr,
  }
  
  static int amdgpu_bo_do_create(struct amdgpu_device *adev,

+  u64 start_addr,
   unsigned long size, int byte_align,
   bool kernel, u32 domain, u64 flags,
   struct sg_table *sg,
@@ -297,9 +298,12 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
u64 initial_bytes_moved, bytes_moved;
size_t acc_size;
int r;
+   int i;
+   bool vram_restricted = false;
  
  	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;

size = ALIGN(size, PAGE_SIZE);
+   start_addr = ALIGN(start_addr, PAGE_SIZE);
  
  	if (kernel) {

type = ttm_bo_type_kernel;
@@ -366,6 +370,32 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
bo->tbo.bdev = >mman.bdev;
amdgpu_ttm_placement_from_domain(bo, domain);
  
+	/*

+* if domain is VRAM && start_addr in vram address space,
+* set the place to the specified place
+*/
+   if ((domain == AMDGPU_GEM_DOMAIN_VRAM) &&
+   start_addr >= adev->mc.vram_start &&
+   (start_addr + size) < adev->mc.vram_end) {
+   start_addr -= adev->mc.vram_start;
+   vram_restricted = true;
+   } else if ((domain == AMDGPU_GEM_DOMAIN_GTT) &&
+   start_addr >= adev->mc.gart_start &&
+   (start_addr + size) < adev->mc.gart_end) {
+   /* if in gart address space */
+   start_addr -= adev->mc.gart_start;
+   vram_restricted = true;
+   }
+
+   if (vram_restricted) {
+   for (i = 0; i < bo->placement.num_placement; ++i) {
+   bo->placements[i].fpfn =
+   start_addr >> PAGE_SHIFT;
+   bo->placements[i].lpfn =
+   (start_addr + size) >> PAGE_SHIFT;
+   }
+   }
+
initial_bytes_moved = atomic64_read(>num_bytes_moved);
/* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, type,
@@ -418,6 +448,101 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
return r;
  }
  
+/**

+ * amdgpu_bo_create_vram_restricted_kernel -
+ *create BO at the specified place on the VRAM.
+ *
+ * @adev: amdgpu device object
+ * @offset: start offset of the new BO
+ * @size: size for the new BO
+ * @byte_align: alignment for the new BO
+ * @flags: addition flags for the BO
+ * @bo_ptr: resulting BO
+ * @gpu_addr: GPU addr of the pinned BO
+ * @cpu_addr: optional CPU address mapping
+ *
+ * Allocates and pins a BO at the specified place on the VRAM.
+ *
+ * Returns 0 on success, negative error code otherwise.
+ */
+int amdgpu_bo_create_vram_restricted_kernel(struct amdgpu_device *adev,
+u64 offset, unsigned long size, int byte_align,
+u64 flags, struct amdgpu_bo **bo_ptr,
+u64 *gpu_addr, void **cpu_addr)
+{
+   int r;
+   u64 start_addr = offset + adev->mc.vram_start;
+   /* specified memory must be in contiguous*/
+   flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+
+   r = amdgpu_bo_do_create(adev, start_addr, size, byte_align, true,
+   AMDGPU_GEM_DOMAIN_VRAM, flags, NULL, NULL, 0, bo_ptr);
+   if (r)
+   return r;
+
+   r = amdgpu_bo_reserve(*bo_ptr, false);
+   if (r)
+   goto error_reserve;
+   r = amdgpu_bo_pin_restricted(*bo_ptr,
+   AMDGPU_GEM_DOMAIN_VRAM, offset, (offset + size),
+   gpu_addr);
+   if (r)
+   goto error_pin;
+   if (cpu_addr) {
+   r = amdgpu_bo_kmap(*bo_ptr,
+

[PATCH] drm/amdgpu: fix vf error handling

[Alex Deucher]

The error handling for virtual functions assumed a single
vf per VM and didn't properly account for bare metal.  Make
the error arrays per device and add locking.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   | 23 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c | 54 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h |  5 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 13 +++
 4 files changed, 54 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3e84ddf..fc0c1cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2040,6 +2040,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>srbm_mutex);
mutex_init(>grbm_idx_mutex);
mutex_init(>mn_lock);
+   mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
 
amdgpu_check_arguments(adev);
@@ -2125,7 +2126,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atombios_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atombios_init failed\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 
0, 0);
goto failed;
}
 
@@ -2136,7 +2137,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (amdgpu_vpost_needed(adev)) {
if (!adev->bios) {
dev_err(adev->dev, "no vBIOS found\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 
0);
r = -EINVAL;
goto failed;
}
@@ -2144,7 +2145,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
if (r) {
dev_err(adev->dev, "gpu post error!\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 
0);
+   amdgpu_vf_error_put(adev, 
AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
goto failed;
}
} else {
@@ -2156,7 +2157,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atomfirmware_get_clock_info(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info 
failed\n");
-   
amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
+   amdgpu_vf_error_put(adev, 
AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
goto failed;
}
} else {
@@ -2164,7 +2165,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_atombios_get_clock_info(adev);
if (r) {
dev_err(adev->dev, "amdgpu_atombios_get_clock_info 
failed\n");
-   
amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
+   amdgpu_vf_error_put(adev, 
AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
goto failed;
}
/* init i2c buses */
@@ -2175,7 +2176,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_fence_driver_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 
0);
goto failed;
}
 
@@ -2185,7 +2186,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_init failed\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 
0);
amdgpu_fini(adev);
goto failed;
}
@@ -2205,7 +2206,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
goto failed;
}
 
@@ -2254,7 +2255,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_late_init(adev);
if (r) {
dev_err(adev->dev, "amdgpu_late_init failed\n");
-   amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, 
r);
+   amdgpu_vf_error_put(adev, 

[PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID

[Rex Zhu]

don't need to check pp_valid, all pp
export functions are moved to ip_funcs
and pp_funcs. so just need to check the
function point.

Change-Id: Ib75cebece8fb9ebc7307f5d3cf084a813b5493db
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c   | 3 +--
 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 3 ---
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index a0f08ec..94f85db 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -35,7 +35,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum 
amd_pp_task task_id,
 
 static inline int pp_check(struct pp_instance *handle)
 {
-   if (handle == NULL || handle->pp_valid != PP_VALID)
+   if (handle == NULL)
return -EINVAL;
 
if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL ||
@@ -60,7 +60,6 @@ static int amd_powerplay_create(struct amd_pp_init *pp_init,
if (instance == NULL)
return -ENOMEM;
 
-   instance->pp_valid = PP_VALID;
instance->chip_family = pp_init->chip_family;
instance->chip_id = pp_init->chip_id;
instance->pm_en = pp_init->pm_en;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h 
b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
index 25fb146..7d1eec5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
@@ -25,10 +25,7 @@
 
 #include "hwmgr.h"
 
-#define PP_VALID  0x1F1F1F1F
-
 struct pp_instance {
-   uint32_t pp_valid;
uint32_t chip_family;
uint32_t chip_id;
bool pm_en;
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amd/powerplay: move functions to amd_pm_funcs table

[Rex Zhu]

those functions are exported to DC

Change-Id: I67637337ee40a6da6ecdd15fd78af0335f4c8414
Signed-off-by: Rex Zhu 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c |  29 +++--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 140 +++--
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  32 -
 3 files changed, 93 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index aefd9eb..56bc7cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -185,11 +185,12 @@ bool dm_pp_apply_display_requirements(
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
 
/* TODO: complete implementation of
-* amd_powerplay_display_configuration_change().
+* pp_display_configuration_change().
 * Follow example of:
 * PHM_StoreDALConfigurationData - 
powerplay\hwmgr\hardwaremanager.c
 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c 
*/
-   amd_powerplay_display_configuration_change(
+   if (adev->powerplay.pp_funcs->display_configuration_change)
+   adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
>pm.pm_display_cfg);
 
@@ -318,22 +319,26 @@ bool dm_pp_get_clock_levels_by_type(
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
 
-   if (amd_powerplay_get_clock_by_type(pp_handle,
+   if (adev->powerplay.pp_funcs->get_clock_by_type) {
+   if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), _clks)) {
/* Error in pplib. Provide default values. */
-   get_default_clock_levels(clk_type, dc_clks);
-   return true;
+   get_default_clock_levels(clk_type, dc_clks);
+   return true;
+   }
}
 
pp_to_dc_clock_levels(_clks, dc_clks, clk_type);
 
-   if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
-   _clks)) {
-   /* Error in pplib. Provide default values. */
-   DRM_INFO("DM_PPLIB: Warning: using default validation 
clocks!\n");
-   validation_clks.engine_max_clock = 72000;
-   validation_clks.memory_max_clock = 8;
-   validation_clks.level = 0;
+   if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
+   if 
(adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
+   pp_handle, _clks)) {
+   /* Error in pplib. Provide default values. */
+   DRM_INFO("DM_PPLIB: Warning: using default validation 
clocks!\n");
+   validation_clks.engine_max_clock = 72000;
+   validation_clks.memory_max_clock = 8;
+   validation_clks.level = 0;
+   }
}
 
DRM_INFO("DM_PPLIB: Validation clocks:\n");
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 03999a6..a0f08ec 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -781,6 +781,29 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
return size;
 }
 
+static int amd_powerplay_reset(void *handle)
+{
+   struct pp_instance *instance = (struct pp_instance *)handle;
+   int ret;
+
+   if (!instance->pm_en)
+   return 0;
+
+   ret = pp_check(instance);
+   if (ret)
+   return ret;
+
+   ret = pp_hw_fini(instance);
+   if (ret)
+   return ret;
+
+   ret = hwmgr_hw_init(instance);
+   if (ret)
+   return ret;
+
+   return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, 
NULL);
+}
+
 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 {
struct pp_hwmgr *hwmgr;
@@ -1136,64 +1159,9 @@ static int pp_dpm_switch_power_profile(void *handle,
return 0;
 }
 
-const struct amd_pm_funcs pp_dpm_funcs = {
-   .get_temperature = pp_dpm_get_temperature,
-   .load_firmware = pp_dpm_load_fw,
-   .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
-   .force_performance_level = pp_dpm_force_performance_level,
-   .get_performance_level = pp_dpm_get_performance_level,
-   .get_current_power_state = pp_dpm_get_current_power_state,
-   .get_sclk = pp_dpm_get_sclk,
-   .get_mclk = pp_dpm_get_mclk,
-   .powergate_vce = pp_dpm_powergate_vce,
-   .powergate_uvd = pp_dpm_powergate_uvd,

[PATCH 1/2] drm/amdgpu: add functions to create bo at the specified position

[Horace Chen]

Add two function to create and free bo at the specified position
on the VRAM.

Add a new parameter to amdgpu_bo_do_create to tell the start
address of the special bo. If the start address is located in
the GPU MC address space, the placement will be set to the exact
place according to the size and start address. Otherwise the start
address will be ingored.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 129 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |   6 ++
 2 files changed, 133 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6982bae..0695160 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -284,6 +284,7 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 
*gpu_addr,
 }
 
 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+  u64 start_addr,
   unsigned long size, int byte_align,
   bool kernel, u32 domain, u64 flags,
   struct sg_table *sg,
@@ -297,9 +298,12 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
u64 initial_bytes_moved, bytes_moved;
size_t acc_size;
int r;
+   int i;
+   bool vram_restricted = false;
 
page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
size = ALIGN(size, PAGE_SIZE);
+   start_addr = ALIGN(start_addr, PAGE_SIZE);
 
if (kernel) {
type = ttm_bo_type_kernel;
@@ -366,6 +370,32 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
bo->tbo.bdev = >mman.bdev;
amdgpu_ttm_placement_from_domain(bo, domain);
 
+   /*
+* if domain is VRAM && start_addr in vram address space,
+* set the place to the specified place
+*/
+   if ((domain == AMDGPU_GEM_DOMAIN_VRAM) &&
+   start_addr >= adev->mc.vram_start &&
+   (start_addr + size) < adev->mc.vram_end) {
+   start_addr -= adev->mc.vram_start;
+   vram_restricted = true;
+   } else if ((domain == AMDGPU_GEM_DOMAIN_GTT) &&
+   start_addr >= adev->mc.gart_start &&
+   (start_addr + size) < adev->mc.gart_end) {
+   /* if in gart address space */
+   start_addr -= adev->mc.gart_start;
+   vram_restricted = true;
+   }
+
+   if (vram_restricted) {
+   for (i = 0; i < bo->placement.num_placement; ++i) {
+   bo->placements[i].fpfn =
+   start_addr >> PAGE_SHIFT;
+   bo->placements[i].lpfn =
+   (start_addr + size) >> PAGE_SHIFT;
+   }
+   }
+
initial_bytes_moved = atomic64_read(>num_bytes_moved);
/* Kernel allocation are uninterruptible */
r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, type,
@@ -418,6 +448,101 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
return r;
 }
 
+/**
+ * amdgpu_bo_create_vram_restricted_kernel -
+ *create BO at the specified place on the VRAM.
+ *
+ * @adev: amdgpu device object
+ * @offset: start offset of the new BO
+ * @size: size for the new BO
+ * @byte_align: alignment for the new BO
+ * @flags: addition flags for the BO
+ * @bo_ptr: resulting BO
+ * @gpu_addr: GPU addr of the pinned BO
+ * @cpu_addr: optional CPU address mapping
+ *
+ * Allocates and pins a BO at the specified place on the VRAM.
+ *
+ * Returns 0 on success, negative error code otherwise.
+ */
+int amdgpu_bo_create_vram_restricted_kernel(struct amdgpu_device *adev,
+u64 offset, unsigned long size, int byte_align,
+u64 flags, struct amdgpu_bo **bo_ptr,
+u64 *gpu_addr, void **cpu_addr)
+{
+   int r;
+   u64 start_addr = offset + adev->mc.vram_start;
+   /* specified memory must be in contiguous*/
+   flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+
+   r = amdgpu_bo_do_create(adev, start_addr, size, byte_align, true,
+   AMDGPU_GEM_DOMAIN_VRAM, flags, NULL, NULL, 0, bo_ptr);
+   if (r)
+   return r;
+
+   r = amdgpu_bo_reserve(*bo_ptr, false);
+   if (r)
+   goto error_reserve;
+   r = amdgpu_bo_pin_restricted(*bo_ptr,
+   AMDGPU_GEM_DOMAIN_VRAM, offset, (offset + size),
+   gpu_addr);
+   if (r)
+   goto error_pin;
+   if (cpu_addr) {
+   r = amdgpu_bo_kmap(*bo_ptr,
+   cpu_addr);
+   if (r)
+   goto error_kmap;
+   }
+
+   amdgpu_bo_unreserve(*bo_ptr);
+
+   return r;
+error_kmap:
+   amdgpu_bo_unpin(*bo_ptr);
+error_pin:
+   amdgpu_bo_unreserve(*bo_ptr);
+error_reserve:
+   amdgpu_bo_unref(bo_ptr);
+

[PATCH] amdgpu/pp/vega10: mark vega10_pp_tables_initialize as static.

[Dave Airlie]

From: Dave Airlie 

This isn't used outside this file.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index e343df1..22c4d5b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -1131,7 +1131,7 @@ static int init_dpm_2_parameters(
return result;
 }
 
-int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
+static int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
 {
int result = 0;
const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amd/display: DC I2C review

[Daniel Vetter]

On Wed, Sep 27, 2017 at 9:46 PM, Harry Wentland  wrote:
> While reviewing I2C in DC identified a few places. Added a couple to the
> TODO list.
>
> 1) Connector info read
>
> See get_ext_display_connection_info
>
> On some boards the connector information has to be read through a
> special I2C channel. This line is only used for this purpose and only on
> driver init.
>
> 2) SCDC stuff
>
> This should all be reworked to go through DRM's SCDC code. When this is
> done some unnecessary I2C code can be retired as well.
>
> 3) Max TMDS clock read
>
> See dal_ddc_service_i2c_query_dp_dual_mode_adaptor
>
> This should happen in DRM as well. I haven't checked if there's
> currently functionality in DRM. If not we can propose something.
>
> 4) HDMI retimer programming
>
> Some boards have an HDMI retimer that we need to program to pass PHY
> compliance.
>
> 1 & 3 might be a good exercise if someone is looking for things to do.
>
> Signed-off-by: Harry Wentland 
> ---
>  drivers/gpu/drm/amd/display/TODO | 26 --
>  1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/TODO 
> b/drivers/gpu/drm/amd/display/TODO
> index eea645b102a1..981352bc95f0 100644
> --- a/drivers/gpu/drm/amd/display/TODO
> +++ b/drivers/gpu/drm/amd/display/TODO
> @@ -62,20 +62,10 @@ TODOs
>  ~ Daniel Vetter
>
>
> -11. Remove existing i2c implementation from DC
> -
> -"Similar story for i2c, it uses the kernel's i2c code now, but there's
> -still a full i2c implementation hidden beneath that in
> -display/dc/i2caux. Kinda not cool, but imo ok if you fix that
> -post-merging (perhaps by not including any of this in the linux DC
> -code in the upstream kernel, but as an aux module in your internal
> -codebase since there you probably need that, same applies to the edid
> -parsing DC still does. For both cases I assume that the minimal shim
> -you need on linux (bit banging and edid parsing isn't rocket since) is
> -a lot less than the glue code to interface with the dc-provided
> -abstraction."
> -~ Daniel Vetter
> -
> +11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically 
> an
> +overy complicated HW programming function for sendind and receiving i2c/aux
> +commands. We can greatly simplify that and move it into dc/dceXYZ like other
> +HW blocks.

Best case I think would be if you directly implement the i2c_adapter
in there. It's a tiny abstraction/api, so should be trivial to
reimplement for the windows side. Or at least align really closely.
Even more so for the gpio bit-banging case, that should use the linux
implementation I think. Might be good to clarify.

Anyway, ack on this.

>  12. drm_modeset_lock in MST should no longer be needed in recent kernels
>  * Adopt appropriate locking scheme
> @@ -110,3 +100,11 @@ guilty.
>  stuff just isn't up to the challenges either. We need to figure out something
>  that integrates better with DRM and linux debug printing, while not being
>  useless with filtering output. dynamic debug printing might be an option.
> +
> +20. Move Max TMDS clock read to DRM. See
> +dal_ddc_service_i2c_query_dp_dual_mode_adaptor. I haven't checked if there's
> +currently functionality in DRM. If not we can propose something.

We already have dual_mode helpers. It's one of the todo's I've added,
merged this with point 15?

> +21. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
> +retimer that we need to program to pass PHY compliance. Currently that's
> +bypassing the i2c device and goes directly to HW. This should be changed.

I thought it eventually goes through the i2c stuff, after a few layers
at least. Maybe I got derailed. Anyway, makes sense.

With 20 merged into 15, ack on the patch from me.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: use designated initialiser for thermal_irq_src.

[Dave Airlie]

From: Dave Airlie 

This fixes the 0-day build warning.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 73969f3..35e80c9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -124,9 +124,9 @@ static int phm_ctf_irq(void *private_data,
 }
 
 static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
-   {NULL, phm_thermal_l2h_irq},
-   {NULL, phm_thermal_h2l_irq},
-   {NULL, phm_ctf_irq}
+   { .handler = phm_thermal_l2h_irq },
+   { .handler = phm_thermal_h2l_irq },
+   { .handler = phm_ctf_irq }
 };
 
 int hwmgr_early_init(struct pp_instance *handle)
-- 
2.9.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx