RE: [PATCH 0/7] *** GPU recover V3 ***

[Liu, Monk]

Please share the dmesg log, and what’s the chip are you using ?

From: Julien Isorce [mailto:julien.iso...@gmail.com]
Sent: 2017年11月9日 17:35
To: Liu, Monk 
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 0/7] *** GPU recover V3 ***

Hi Monk.

I am interested on this. Currently when a "ring X stalled for more than N sec" 
happens it usually goes into the gpu reset routine.
Does it always cause the vram to be lost ? Could you explain what happens if 
the vram remains lost ?

I am asking this because I experienced some recurrent gpu reset that are marked 
succeeded from the log but fail in the "resume" step.
I would not be interested in this if it would always leave a chance to the user 
to cleanly reboot the machine.

The issue is that it can require a hard reboot without kernel panic and without 
keeping the keyboard responding to magic keys.
Are those patches trying to address this issue ?

Note that here "issue" is not referring to the root cause of a ring X stalled 
and it is also not referring to why "resume" step fails.

Thx a lot
Julien


On 30 October 2017 at 04:15, Monk Liu 
> wrote:
*** job skipping logic in scheduler part is re-implemented  ***

Monk Liu (7):
  amd/scheduler:imple job skip feature(v3)
  drm/amdgpu:implement new GPU recover(v3)
  drm/amdgpu:cleanup in_sriov_reset and lock_reset
  drm/amdgpu:cleanup ucode_init_bo
  drm/amdgpu:block kms open during gpu_reset
  drm/amdgpu/sriov:fix memory leak in psp_load_fw
  drm/amdgpu:fix random missing of FLR NOTIFY

 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   9 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 311 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  22 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |   2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |   2 -
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |   6 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   6 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  16 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c |   2 +-
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  39 ++--
 15 files changed, 220 insertions(+), 232 deletions(-)

--
2.7.4

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FW: [PATCH] drm/amd/display: fix static checker warning

[S, Shirish]

On 11/7/2017 2:06 PM, Michel Dänzer wrote:
> On 07/11/17 04:29 AM, S, Shirish wrote:
>> From: Shirish S 
>>
>> This patch fixes static checker warning of
>> "warn: cast after binop" introduced by
>> 4d3e00dad80a: "drm/amd/display : add high part address calculation for 
>> underlay"
>>
>> Signed-off-by: Shirish S 
>> ---
>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index a87e5ac..e1bdf5e 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -1827,7 +1827,7 @@ static int fill_plane_attributes_from_fb(struct 
>> amdgpu_device *adev,
>>  = lower_32_bits(fb_location);
>>  plane_state->address.video_progressive.luma_addr.high_part
>>  = upper_32_bits(fb_location);
>> -chroma_addr = fb_location + (u64)(awidth * fb->height);
>> +chroma_addr = fb_location + (u64)awidth * fb->height;
>>  plane_state->address.video_progressive.chroma_addr.low_part
>>  = lower_32_bits(chroma_addr);
>>  plane_state->address.video_progressive.chroma_addr.high_part
>> @@ -2959,7 +2959,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane 
>> *plane,
>>  = 
>> lower_32_bits(afb->address);
>>  
>> plane_state->address.video_progressive.luma_addr.high_part
>>  = 
>> upper_32_bits(afb->address);
>> -chroma_addr = afb->address + (u64)(awidth * 
>> new_state->fb->height);
>> +chroma_addr = afb->address + (u64)awidth * 
>> new_state->fb->height;
>>  
>> plane_state->address.video_progressive.chroma_addr.low_part
>>  = 
>> lower_32_bits(chroma_addr);
>>  
>> plane_state->address.video_progressive.chroma_addr.high_part
>>
> This code should really be removed, since fb_location is always 0 now 
> in this function, so the values derived from it cannot be used for 
> anything anyway.
I remember Andrey had some concerns with it, if he is ok with it i can move it 
as a separate patch, for future bisect-ability.

Regards,
Shirish S
>
>

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[PATCH libdrm 3/4] amdgpu: Move memory alloc tests in bo suite.

[Andrey Grodzovsky]

Signed-off-by: Andrey Grodzovsky 
---
 tests/amdgpu/basic_tests.c | 49 --
 tests/amdgpu/bo_tests.c| 49 ++
 2 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 18bcf91..e7f48e3 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -44,7 +44,6 @@ static  uint32_t  minor_version;
 static  uint32_t  family_id;
 
 static void amdgpu_query_info_test(void);
-static void amdgpu_memory_alloc(void);
 static void amdgpu_command_submission_gfx(void);
 static void amdgpu_command_submission_compute(void);
 static void amdgpu_command_submission_multi_fence(void);
@@ -58,7 +57,6 @@ static void 
amdgpu_command_submission_copy_linear_helper(unsigned ip_type);
 
 CU_TestInfo basic_tests[] = {
{ "Query Info Test",  amdgpu_query_info_test },
-   { "Memory alloc Test",  amdgpu_memory_alloc },
{ "Userptr Test",  amdgpu_userptr_test },
{ "Command submission Test (GFX)",  amdgpu_command_submission_gfx },
{ "Command submission Test (Compute)", 
amdgpu_command_submission_compute },
@@ -277,53 +275,6 @@ static void amdgpu_query_info_test(void)
CU_ASSERT_EQUAL(r, 0);
 }
 
-static void amdgpu_memory_alloc(void)
-{
-   amdgpu_bo_handle bo;
-   amdgpu_va_handle va_handle;
-   uint64_t bo_mc;
-   int r;
-
-   /* Test visible VRAM */
-   bo = gpu_mem_alloc(device_handle,
-   4096, 4096,
-   AMDGPU_GEM_DOMAIN_VRAM,
-   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-   _mc, _handle);
-
-   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-   CU_ASSERT_EQUAL(r, 0);
-
-   /* Test invisible VRAM */
-   bo = gpu_mem_alloc(device_handle,
-   4096, 4096,
-   AMDGPU_GEM_DOMAIN_VRAM,
-   AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
-   _mc, _handle);
-
-   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-   CU_ASSERT_EQUAL(r, 0);
-
-   /* Test GART Cacheable */
-   bo = gpu_mem_alloc(device_handle,
-   4096, 4096,
-   AMDGPU_GEM_DOMAIN_GTT,
-   0, _mc, _handle);
-
-   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-   CU_ASSERT_EQUAL(r, 0);
-
-   /* Test GART USWC */
-   bo = gpu_mem_alloc(device_handle,
-   4096, 4096,
-   AMDGPU_GEM_DOMAIN_GTT,
-   AMDGPU_GEM_CREATE_CPU_GTT_USWC,
-   _mc, _handle);
-
-   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-   CU_ASSERT_EQUAL(r, 0);
-}
-
 static void amdgpu_command_submission_gfx_separate_ibs(void)
 {
amdgpu_context_handle context_handle;
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 74b5e77..4545196 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -46,6 +46,7 @@ static amdgpu_va_handle va_handle;
 static void amdgpu_bo_export_import(void);
 static void amdgpu_bo_metadata(void);
 static void amdgpu_bo_map_unmap(void);
+static void amdgpu_memory_alloc(void);
 
 CU_TestInfo bo_tests[] = {
{ "Export/Import",  amdgpu_bo_export_import },
@@ -53,6 +54,7 @@ CU_TestInfo bo_tests[] = {
{ "Metadata",  amdgpu_bo_metadata },
 #endif
{ "CPU map/unmap",  amdgpu_bo_map_unmap },
+   { "Memory alloc Test",  amdgpu_memory_alloc },
CU_TEST_INFO_NULL,
 };
 
@@ -195,3 +197,50 @@ static void amdgpu_bo_map_unmap(void)
r = amdgpu_bo_cpu_unmap(buffer_handle);
CU_ASSERT_EQUAL(r, 0);
 }
+
+static void amdgpu_memory_alloc(void)
+{
+   amdgpu_bo_handle bo;
+   amdgpu_va_handle va_handle;
+   uint64_t bo_mc;
+   int r;
+
+   /* Test visible VRAM */
+   bo = gpu_mem_alloc(device_handle,
+   4096, 4096,
+   AMDGPU_GEM_DOMAIN_VRAM,
+   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+   _mc, _handle);
+
+   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+   CU_ASSERT_EQUAL(r, 0);
+
+   /* Test invisible VRAM */
+   bo = gpu_mem_alloc(device_handle,
+   4096, 4096,
+   AMDGPU_GEM_DOMAIN_VRAM,
+   AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+   _mc, _handle);
+
+   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+   CU_ASSERT_EQUAL(r, 0);
+
+   /* Test GART Cacheable */
+   bo = gpu_mem_alloc(device_handle,
+   4096, 4096,
+   AMDGPU_GEM_DOMAIN_GTT,
+   0, _mc, _handle);
+
+   r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
+   CU_ASSERT_EQUAL(r, 0);
+
+   /* Test GART USWC */
+   bo = gpu_mem_alloc(device_handle,
+   4096, 4096,
+ 

[PATCH libdrm 2/4] amdgpu: Use new suite/test disabling functionality.

[Andrey Grodzovsky]

Switch from disabling tests during run to using the new disable
API.

Signed-off-by: Andrey Grodzovsky 
---
 tests/amdgpu/amdgpu_test.c| 14 ++--
 tests/amdgpu/amdgpu_test.h| 15 
 tests/amdgpu/deadlock_tests.c |  8 +
 tests/amdgpu/uvd_enc_tests.c  | 81 +--
 tests/amdgpu/vce_tests.c  | 65 +-
 tests/amdgpu/vcn_tests.c  | 74 +--
 6 files changed, 123 insertions(+), 134 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 68ec5d3..91010dc 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -150,15 +150,15 @@ static Suites_Active_Status suites_active_stat[] = {
},
{
.pName = VCE_TESTS_STR,
-   .pActive = always_active,
+   .pActive = suite_vce_tests_enable,
},
{
.pName = VCN_TESTS_STR,
-   .pActive = always_active,
+   .pActive = suite_vcn_tests_enable,
},
{
.pName = UVD_ENC_TESTS_STR,
-   .pActive = always_active,
+   .pActive = suite_uvd_enc_tests_enable,
},
{
.pName = DEADLOCK_TESTS_STR,
@@ -409,6 +409,14 @@ static void amdgpu_disable_suits()
if (amdgpu_set_suite_active(suites_active_stat[i].pName,
suites_active_stat[i].pActive()))
fprintf(stderr, "suit deactivation failed - %s\n", 
CU_get_error_msg());
+
+   /* Explicitly disable specific tests due to known bugs or preferences */
+   /*
+   * BUG: Compute ring stalls and never recovers when the address is
+   * written after the command already submitted
+   */
+   if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block 
test", CU_FALSE))
+   fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
 }
 
 /* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 9ccc1ff..dd236ed 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -100,6 +100,11 @@ int suite_vce_tests_init();
 int suite_vce_tests_clean();
 
 /**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_vce_tests_enable(void);
+
+/**
  * Tests in vce test suite
  */
 extern CU_TestInfo vce_tests[];
@@ -115,6 +120,11 @@ int suite_vcn_tests_init();
 int suite_vcn_tests_clean();
 
 /**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_vcn_tests_enable(void);
+
+/**
 + * Tests in vcn test suite
 + */
 extern CU_TestInfo vcn_tests[];
@@ -130,6 +140,11 @@ int suite_uvd_enc_tests_init();
 int suite_uvd_enc_tests_clean();
 
 /**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_uvd_enc_tests_enable(void);
+
+/**
  * Tests in uvd enc test suite
  */
 extern CU_TestInfo uvd_enc_tests[];
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index e23d903..f5c4552 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -119,13 +119,7 @@ int suite_deadlock_tests_clean(void)
 
 CU_TestInfo deadlock_tests[] = {
{ "gfx ring block test",  amdgpu_deadlock_gfx },
-
-   /*
-   * BUG: Compute ring stalls and never recovers when the address is
-   * written after the command already submitted
-   */
-   /* { "compute ring block test",  amdgpu_deadlock_compute }, */
-
+   { "compute ring block test",  amdgpu_deadlock_compute },
CU_TEST_INFO_NULL,
 };
 
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index bbda131..bed8494 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -79,7 +79,6 @@ static void amdgpu_cs_uvd_enc_session_init(void);
 static void amdgpu_cs_uvd_enc_encode(void);
 static void amdgpu_cs_uvd_enc_destroy(void);
 
-static bool uvd_enc_support(void);
 
 CU_TestInfo uvd_enc_tests[] = {
{ "UVD ENC create",  amdgpu_cs_uvd_enc_create },
@@ -89,6 +88,27 @@ CU_TestInfo uvd_enc_tests[] = {
CU_TEST_INFO_NULL,
 };
 
+CU_BOOL suite_uvd_enc_tests_enable(void)
+{
+   int r;
+   struct drm_amdgpu_info_hw_ip info;
+
+   if (amdgpu_device_initialize(drm_amdgpu[0], _version,
+_version, _handle))
+   return CU_FALSE;
+
+   r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, 
);
+
+   if (amdgpu_device_deinitialize(device_handle))
+   return CU_FALSE;
+
+   if (!info.available_rings)
+   printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n");
+
+   return (r == 0 && 

[PATCH libdrm 0/4] Dynamicly disable suites and tets.

[Andrey Grodzovsky]

THe following  patch series intoroduce  dynamic tests dusabling/enabling
in amdgpu  tester using Cunit API. Today test suits that
don't apply to specific HW just return success w/o executing while
single tests that can't be executed properly are commented out.

Suits are diasbled based on hooks they provide (e.g incompatible 
ASIC or missing blocks) while single tests are diasbled explicitly since this 
is 
usually due to some bug preventing from the tester  or the system  to handle
the test w/o crashing or killing the tester.

Inside this series also a minor cleanup and new test for memory over allocation.

Andrey Grodzovsky (4):
  amdgpu: Add functions to disable suites and tests.
  amdgpu: Use new suite/test disabling functionality.
  amdgpu: Move memory alloc tests in bo suite.
  amdgpu: Add memory over allocation test.

 tests/amdgpu/amdgpu_test.c| 169 +-
 tests/amdgpu/amdgpu_test.h|  46 
 tests/amdgpu/basic_tests.c|  49 
 tests/amdgpu/bo_tests.c   |  69 +
 tests/amdgpu/deadlock_tests.c |   8 +-
 tests/amdgpu/uvd_enc_tests.c  |  81 
 tests/amdgpu/vce_tests.c  |  65 
 tests/amdgpu/vcn_tests.c  |  74 --
 8 files changed, 363 insertions(+), 198 deletions(-)

-- 
2.7.4

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[PATCH libdrm 1/4] amdgpu: Add functions to disable suites and tests.

[Andrey Grodzovsky]

Suits are diasbled based on hooks they provide (e.g incompatible
ASIC or missing blocks). Single tests are diasbled explicitly.
Suit or test can be forced to execute even if disabled by adding -f 
flag after specifying suit [test] ids.

Signed-off-by: Andrey Grodzovsky 
---
 tests/amdgpu/amdgpu_test.c | 157 +++--
 tests/amdgpu/amdgpu_test.h |  31 +
 2 files changed, 170 insertions(+), 18 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index a82d9ab..68ec5d3 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -50,6 +50,16 @@
 
 #include "amdgpu_test.h"
 
+/* Test suit names */
+#define BASIC_TESTS_STR "Basic Tests"
+#define BO_TESTS_STR "BO Tests"
+#define CS_TESTS_STR "CS Tests"
+#define VCE_TESTS_STR "VCE Tests"
+#define VCN_TESTS_STR "VCN Tests"
+#define UVD_ENC_TESTS_STR "UVD ENC Tests"
+#define DEADLOCK_TESTS_STR "Deadlock Tests"
+#define VM_TESTS_STR "VM Tests"
+
 /**
  *  Open handles for amdgpu devices
  *
@@ -62,49 +72,49 @@ int open_render_node = 0;   /* By default run most tests on 
primary node */
 /** The table of all known test suites to run */
 static CU_SuiteInfo suites[] = {
{
-   .pName = "Basic Tests",
+   .pName = BASIC_TESTS_STR,
.pInitFunc = suite_basic_tests_init,
.pCleanupFunc = suite_basic_tests_clean,
.pTests = basic_tests,
},
{
-   .pName = "BO Tests",
+   .pName = BO_TESTS_STR,
.pInitFunc = suite_bo_tests_init,
.pCleanupFunc = suite_bo_tests_clean,
.pTests = bo_tests,
},
{
-   .pName = "CS Tests",
+   .pName = CS_TESTS_STR,
.pInitFunc = suite_cs_tests_init,
.pCleanupFunc = suite_cs_tests_clean,
.pTests = cs_tests,
},
{
-   .pName = "VCE Tests",
+   .pName = VCE_TESTS_STR,
.pInitFunc = suite_vce_tests_init,
.pCleanupFunc = suite_vce_tests_clean,
.pTests = vce_tests,
},
{
-   .pName = "VCN Tests",
+   .pName = VCN_TESTS_STR,
.pInitFunc = suite_vcn_tests_init,
.pCleanupFunc = suite_vcn_tests_clean,
.pTests = vcn_tests,
},
{
-   .pName = "UVD ENC Tests",
+   .pName = UVD_ENC_TESTS_STR,
.pInitFunc = suite_uvd_enc_tests_init,
.pCleanupFunc = suite_uvd_enc_tests_clean,
.pTests = uvd_enc_tests,
},
{
-   .pName = "Deadlock Tests",
+   .pName = DEADLOCK_TESTS_STR,
.pInitFunc = suite_deadlock_tests_init,
.pCleanupFunc = suite_deadlock_tests_clean,
.pTests = deadlock_tests,
},
{
-   .pName = "VM Tests",
+   .pName = VM_TESTS_STR,
.pInitFunc = suite_vm_tests_init,
.pCleanupFunc = suite_vm_tests_clean,
.pTests = vm_tests,
@@ -113,23 +123,99 @@ static CU_SuiteInfo suites[] = {
CU_SUITE_INFO_NULL,
 };
 
+typedef CU_BOOL (*active__stat_func)(void);
+
+typedef struct Suites_Active_Status {
+   char* pName;
+   active__stat_func pActive;
+}Suites_Active_Status;
+
+static CU_BOOL always_active()
+{
+   return CU_TRUE;
+}
+
+static Suites_Active_Status suites_active_stat[] = {
+   {
+   .pName = BASIC_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = BO_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = CS_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = VCE_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = VCN_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = UVD_ENC_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = DEADLOCK_TESTS_STR,
+   .pActive = always_active,
+   },
+   {
+   .pName = VM_TESTS_STR,
+   .pActive = always_active,
+   },
+};
+
 
-/** Display information about all  suites and their tests */
+/*
+ * Display information about all  suites and their tests
+ *
+ * NOTE: Must be run after registry is initialized and suites registered.
+ */
 static void display_test_suites(void)
 {
int iSuite;
int iTest;
+   CU_pSuite 

Re: [PATCH 1/1] drm/amdkfd: CWSR and trap handler support

[Kuehling, Felix]

The file contains the assembly code as a reference (inside #if 0) and an array 
with the pre-compiled code. It gets #included in kfd_device.c.

The trap handler binary gets compiled/linked into the kernel. To be 
GPL-compliant the source code needs to be included. Otherwise we'd have to load 
the trap handler as firmware to get around licensing issues.

Regards,
  Felix


From: Oded Gabbay 
Sent: Thursday, November 9, 2017 2:02:18 AM
To: Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdkfd: CWSR and trap handler support

Yes, that would be helpful to review.
I assume the asm file provided is just a reference code and doesn't
need to be in the kernel tree for this to work, correct ?


On Thu, Nov 9, 2017 at 4:46 AM, Felix Kuehling  wrote:
> I'll probably need a v2 of this patch. #include  should
> not be needed. That's a leftover from some late cleanup.
>
> This change also ended up a bit big after squashing about 12 changes and
> fixes, and adding more cleanups on top of that. Let me know you want me
> to split it. I'm thinking this may make sense:
>
>  1. Add trap handler .asm file
>  2. Implement CWSR support
>  3. Implement user mode trap handler support
>
> I also pushed an updated kfd_ioctl.h to the Thunk github WIP branch.
>
> Regards,
>   Felix
>
>
> On 2017-11-08 09:29 PM, Felix Kuehling wrote:
>> From: shaoyunl 
>>
>> CWSR = compute wave save restore
>>
>> This hardware feature allows the GPU to preempt shader execution in
>> the middle of a compute wave, save the state and restore it later
>> to resume execution.
>>
>> This feature requires help from a trap handler, which is like an
>> interrupt handler running on the compute unit. The trap handler is
>> written mostly by the hardware team. It's provided as pre-compiled
>> shader code with the SP3 assembly source code as reference.
>>
>> Memory for saving the state is allocated per queue in user mode and
>> the address and size passed to the create_queue ioctl. The size
>> depends on the number of waves that can be in flight simultaneously
>> on a given ASIC.
>>
>> A second-level user mode trap handler can be installed. The CWSR trap
>> handler jumps to the secondary trap handler conditionally for any
>> conditions not handled by it. This can be used e.g. for debugging or
>> catching math exceptions.
>>
>> Signed-off-by: Shaoyun.liu 
>> Signed-off-by: Jay Cornwall 
>> Signed-off-by: Yong Zhao 
>> Signed-off-by: Felix Kuehling 
>> ---
>>  .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm  | 1384 
>> 
>>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c   |   44 +-
>>  drivers/gpu/drm/amd/amdkfd/kfd_device.c|   24 +-
>>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |   28 +
>>  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  |5 +
>>  drivers/gpu/drm/amd/amdkfd/kfd_module.c|4 +
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c|   27 +
>>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |   31 +-
>>  drivers/gpu/drm/amd/amdkfd/kfd_process.c   |   89 +-
>>  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |4 +-
>>  include/uapi/linux/kfd_ioctl.h |   15 +-
>>  11 files changed, 1644 insertions(+), 11 deletions(-)
>>  create mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm 
>> b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
>> new file mode 100644
>> index 000..751cc2e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
>> @@ -0,0 +1,1384 @@
>> +/*
>> + * Copyright 2015-2017 Advanced Micro Devices, Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the 
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included 
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 

[PATCH 50/73] drm/amd/display: Report pitch_alignment for DCN

[Harry Wentland]

From: Andrew Jiang 

Change-Id: I2825b787ae02b7317bf1602eb2d45aeca8ba1041
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h   | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f2647b40f3cb..459a1c55b5cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -58,6 +58,7 @@ struct dc_caps {
uint32_t i2c_speed_in_khz;
unsigned int max_cursor_size;
unsigned int max_video_width;
+   int pitch_alignment;
bool dcc_const_color;
bool dynamic_audio;
bool is_apu;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 2e6122c4670a..c350fe2fec20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1267,7 +1267,7 @@ static bool construct(
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 256;
-
+   dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */
dc->caps.max_slave_planes = 1;
dc->caps.is_apu = true;
 
-- 
2.14.1

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[PATCH 56/73] drm/amd/display: Remove dangling planes on dc commit state

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

When disabling pipe splitting, we need to make sure we disable both
planes used.

This should be done for Linux as well.

Change-Id: I79f5416a55bd26c19ca3cfb346a943d69872a8ce
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 39 
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 56df1304e49c..d70dbc102123 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -629,6 +629,39 @@ static bool construct(struct dc *dc,
return false;
 }
 
+static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+{
+   int i, j;
+   struct dc_state *dangling_context = dc_create_state();
+   struct dc_state *current_ctx;
+
+   if (dangling_context == NULL)
+   return;
+
+   dc_resource_state_copy_construct(dc->current_state, dangling_context);
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct dc_stream_state *old_stream =
+   dc->current_state->res_ctx.pipe_ctx[i].stream;
+   bool should_disable = true;
+
+   for (j = 0; j < context->stream_count; j++) {
+   if (old_stream == context->streams[j]) {
+   should_disable = false;
+   break;
+   }
+   }
+   if (should_disable && old_stream) {
+   dc_rem_all_planes_for_stream(dc, old_stream, 
dangling_context);
+   dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, 
dangling_context);
+   }
+   }
+
+   current_ctx = dc->current_state;
+   dc->current_state = dangling_context;
+   dc_release_state(current_ctx);
+}
+
 
/***
  * Public functions
  
**/
@@ -833,14 +866,14 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
+   disable_dangling_plane(dc, context);
+
for (i = 0; i < context->stream_count; i++)
dc_streams[i] =  context->streams[i];
 
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc);
 
-
-
for (i = 0; i < context->stream_count; i++) {
const struct dc_sink *sink = context->streams[i]->sink;
 
@@ -864,8 +897,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
}
}
 
-
-
CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
context->streams[i]->timing.h_addressable,
context->streams[i]->timing.v_addressable,
-- 
2.14.1

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[PATCH 65/73] drm/amd/display: Fix unused variable warning

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

'struct mpc *mpc' is not used.

Change-Id: Icc20385798c76e41e29f44ccb26d32b044829821
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0bc1cb889992..d0f46e13efca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -431,7 +431,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
struct dc *dc)
 {
struct dc_stream_state *stream = pipe_ctx->stream;
-   struct mpc *mpc = dc->res_pool->mpc;
enum dc_color_space color_space;
struct tg_color black_color = {0};
bool enableStereo= stream->timing.timing_3d_format == 
TIMING_3D_FORMAT_NONE ?
-- 
2.14.1

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[PATCH 40/73] drm/amd/display: Fixed not set scaler bug.

[Harry Wentland]

From: Yongqiang Sun 

New scaler parameter assign to dpp is after early return,
cause next flip scaler not program.

Change-Id: I4af97d37de194429116378ce7bbb820b21b7a6af
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 242a568294e2..4b5b70907202 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -650,6 +650,9 @@ void dpp1_dscl_set_scaler_manual_scale(
 
if (memcmp(>scl_data, scl_data, sizeof(*scl_data)) == 0)
return;
+
+   dpp->scl_data = *scl_data;
+
/* Recout */
dpp1_dscl_set_recout(dpp, _data->recout);
 
@@ -701,5 +704,4 @@ void dpp1_dscl_set_scaler_manual_scale(
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
-   dpp->scl_data = *scl_data;
 }
-- 
2.14.1

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[PATCH 66/73] drm/amd/display: Optimize front end programming.

[Harry Wentland]

From: Yongqiang Sun 

for video scaling changes,
Reduce reg access count from 1044 to 447, duration time
from 4.6ms to 3ms.

Change-Id: I92c5f7a30044b977dea5d4334ac12876b8ae5ae5
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 219 +++--
 1 file changed, 111 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f46e13efca..30f458701f9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1453,6 +1453,89 @@ static void dcn10_enable_per_frame_crtc_position_reset(
 }
 */
 
+static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
+   struct vm_system_aperture_param *apt,
+   struct dce_hwseq *hws)
+{
+   PHYSICAL_ADDRESS_LOC physical_page_number;
+   uint32_t logical_addr_low;
+   uint32_t logical_addr_high;
+
+   REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+   PHYSICAL_PAGE_NUMBER_MSB, 
_page_number.high_part);
+   REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+   PHYSICAL_PAGE_NUMBER_LSB, 
_page_number.low_part);
+
+   REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+   LOGICAL_ADDR, _addr_low);
+
+   REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+   LOGICAL_ADDR, _addr_high);
+
+   apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
+   apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
+   apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
+}
+
+/* Temporary read settings, future will get values from kmd directly */
+static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
+   struct vm_context0_param *vm0,
+   struct dce_hwseq *hws)
+{
+   PHYSICAL_ADDRESS_LOC fb_base;
+   PHYSICAL_ADDRESS_LOC fb_offset;
+   uint32_t fb_base_value;
+   uint32_t fb_offset_value;
+
+   REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, _base_value);
+   REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, _offset_value);
+
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+   PAGE_DIRECTORY_ENTRY_HI32, >pte_base.high_part);
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+   PAGE_DIRECTORY_ENTRY_LO32, >pte_base.low_part);
+
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+   LOGICAL_PAGE_NUMBER_HI4, >pte_start.high_part);
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+   LOGICAL_PAGE_NUMBER_LO32, >pte_start.low_part);
+
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+   LOGICAL_PAGE_NUMBER_HI4, >pte_end.high_part);
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+   LOGICAL_PAGE_NUMBER_LO32, >pte_end.low_part);
+
+   REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+   PHYSICAL_PAGE_ADDR_HI4, >fault_default.high_part);
+   REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+   PHYSICAL_PAGE_ADDR_LO32, >fault_default.low_part);
+
+   /*
+* The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
+* Therefore we need to do
+* DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = 
VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+* - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
+*/
+   fb_base.quad_part = (uint64_t)fb_base_value << 24;
+   fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
+   vm0->pte_base.quad_part += fb_base.quad_part;
+   vm0->pte_base.quad_part -= fb_offset.quad_part;
+}
+
+
+static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
+{
+   struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+   struct vm_system_aperture_param apt = { {{ 0 } } };
+   struct vm_context0_param vm0 = { { { 0 } } };
+
+   mmhub_read_vm_system_aperture_settings(hubp1, , hws);
+   mmhub_read_vm_context0_settings(hubp1, , hws);
+
+   hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, );
+   hubp->funcs->hubp_set_vm_context0_settings(hubp, );
+}
+
 static void dcn10_enable_plane(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
@@ -1515,6 +1598,8 @@ static void dcn10_enable_plane(
print_rq_dlg_ttu(dc, pipe_ctx);
}
 */
+   if (dc->config.gpu_vm_support)
+   dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
 
if (dc->debug.sanity_checks) {
dcn10_verify_allow_pstate_change_high(dc);
@@ -1737,93 +1822,6 @@ void build_prescale_params(struct  dc_bias_and_scale 
*bias_and_scale,
}
 }
 
-static void 

[PATCH 69/73] drm/amd/display: Move dc_link interface to separate header

[Harry Wentland]

Change-Id: Id35bc6b48dde03068ed554fe7dcf72bd40009769
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h  | 175 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h | 207 +++
 2 files changed, 208 insertions(+), 174 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_link.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 170cdcb5a027..5c509707ccd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -653,171 +653,7 @@ struct dpcd_caps {
bool dpcd_display_control_capable;
 };
 
-struct dc_link_status {
-   struct dpcd_caps *dpcd_caps;
-};
-
-/* DP MST stream allocation (payload bandwidth number) */
-struct link_mst_stream_allocation {
-   /* DIG front */
-   const struct stream_encoder *stream_enc;
-   /* associate DRM payload table with DC stream encoder */
-   uint8_t vcp_id;
-   /* number of slots required for the DP stream in transport packet */
-   uint8_t slot_count;
-};
-
-/* DP MST stream allocation table */
-struct link_mst_stream_allocation_table {
-   /* number of DP video streams */
-   int stream_count;
-   /* array of stream allocations */
-   struct link_mst_stream_allocation 
stream_allocations[MAX_CONTROLLER_NUM];
-};
-
-/*
- * A link contains one or more sinks and their connected status.
- * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
- */
-struct dc_link {
-   struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
-   unsigned int sink_count;
-   struct dc_sink *local_sink;
-   unsigned int link_index;
-   enum dc_connection_type type;
-   enum signal_type connector_signal;
-   enum dc_irq_source irq_source_hpd;
-   enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
-   /* caps is the same as reported_link_cap. link_traing use
-* reported_link_cap. Will clean up.  TODO
-*/
-   struct dc_link_settings reported_link_cap;
-   struct dc_link_settings verified_link_cap;
-   struct dc_link_settings cur_link_settings;
-   struct dc_lane_settings cur_lane_setting;
-   struct dc_link_settings preferred_link_setting;
-
-   uint8_t ddc_hw_inst;
-
-   uint8_t hpd_src;
-
-   uint8_t link_enc_hw_inst;
-
-   bool test_pattern_enabled;
-   union compliance_test_state compliance_test_state;
-
-   void *priv;
-
-   struct ddc_service *ddc;
-
-   bool aux_mode;
-
-   /* Private to DC core */
-
-   const struct dc *dc;
-
-   struct dc_context *ctx;
-
-   struct link_encoder *link_enc;
-   struct graphics_object_id link_id;
-   union ddi_channel_mapping ddi_channel_mapping;
-   struct connector_device_tag_info device_tag;
-   struct dpcd_caps dpcd_caps;
-   unsigned short chip_caps;
-   unsigned int dpcd_sink_count;
-   enum edp_revision edp_revision;
-   bool psr_enabled;
-
-   /* MST record stream using this link */
-   struct link_flags {
-   bool dp_keep_receiver_powered;
-   } wa_flags;
-   struct link_mst_stream_allocation_table mst_stream_alloc_table;
-
-   struct dc_link_status link_status;
-
-};
-
-const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
-
-/*
- * Return an enumerated dc_link.  dc_link order is constant and determined at
- * boot time.  They cannot be created or destroyed.
- * Use dc_get_caps() to get number of links.
- */
-static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t 
link_index)
-{
-   return dc->links[link_index];
-}
-
-/* Set backlight level of an embedded panel (eDP, LVDS). */
-bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
-   uint32_t frame_ramp, const struct dc_stream_state *stream);
-
-bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool 
wait);
-
-bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
-
-bool dc_link_setup_psr(struct dc_link *dc_link,
-   const struct dc_stream_state *stream, struct psr_config 
*psr_config,
-   struct psr_context *psr_context);
-
-/* Request DC to detect if there is a Panel connected.
- * boot - If this call is during initial boot.
- * Return false for any type of detection failure or MST detection
- * true otherwise. True meaning further action is required (status update
- * and OS notification).
- */
-enum dc_detect_reason {
-   DETECT_REASON_BOOT,
-   DETECT_REASON_HPD,
-   DETECT_REASON_HPDRX,
-};
-
-bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
-
-/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
- * Return:
- * true - Downstream port status changed. DM 

[PATCH 51/73] drm/amd/display: Loosen plane_info and scaling_info checks

[Harry Wentland]

From: Andrew Jiang 

Make it so that differing dcc and plane size fields don't necessarily
result in a full update, along with upscaling modes. This allows us to
save some unnecessary full updates.

Change-Id: I5ea98fa690e8ed136d39e2de0af8cbe10806c4b4
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 802aebaa2e11..de7332cffaa2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1130,9 +1130,7 @@ static enum surface_update_type 
get_plane_info_update_type(
/* Full update parameters */
temp_plane_info.color_space = u->surface->color_space;
temp_plane_info.input_tf = u->surface->input_tf;
-   temp_plane_info.dcc = u->surface->dcc;
temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
-   temp_plane_info.plane_size = u->surface->plane_size;
temp_plane_info.rotation = u->surface->rotation;
temp_plane_info.stereo_format = u->surface->stereo_format;
 
@@ -1175,14 +1173,23 @@ static enum surface_update_type  
get_scaling_info_update_type(
if (!u->scaling_info)
return UPDATE_TYPE_FAST;
 
-   if (u->scaling_info->src_rect.width != u->surface->src_rect.width
-   || u->scaling_info->src_rect.height != 
u->surface->src_rect.height
-   || u->scaling_info->clip_rect.width != 
u->surface->clip_rect.width
+   if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
|| u->scaling_info->clip_rect.height != 
u->surface->clip_rect.height
|| u->scaling_info->dst_rect.width != 
u->surface->dst_rect.width
|| u->scaling_info->dst_rect.height != 
u->surface->dst_rect.height)
return UPDATE_TYPE_FULL;
 
+   if (u->scaling_info->src_rect.width != u->surface->src_rect.width
+   || u->scaling_info->src_rect.height != 
u->surface->src_rect.height) {
+
+   if (u->scaling_info->src_rect.width > u->surface->src_rect.width
+   && u->scaling_info->src_rect.height > 
u->surface->src_rect.height)
+   return UPDATE_TYPE_FULL;
+
+   /* Upscaling does not require a full update */
+   return UPDATE_TYPE_MED;
+   }
+
if (u->scaling_info->src_rect.x != u->surface->src_rect.x
|| u->scaling_info->src_rect.y != u->surface->src_rect.y
|| u->scaling_info->clip_rect.x != 
u->surface->clip_rect.x
-- 
2.14.1

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[PATCH 27/73] drm/amd/display: use num_timing_generator instead of pipe_count

[Harry Wentland]

From: Ken Chalmers 

The two are not necessarily the same.

Change-Id: I585542651c2a57502d4c37e0f9393ece4426e455
Signed-off-by: Ken Chalmers 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5cac22519c37..99f478c52421 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -154,7 +154,7 @@ void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin 
\t "
"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot 
\t underflow\n");
 
-   for (i = 0; i < pool->pipe_count; i++) {
+   for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
struct timing_generator *tg = pool->timing_generators[i];
struct dcn_otg_state s = {0};
 
-- 
2.14.1

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[PATCH 37/73] drm/amd/display: dal 3.1.15

[Harry Wentland]

From: Tony Cheng 

Change-Id: I58812cc60def70f03da97e90eff052c461db4dbb
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index acb36594acc2..8cdc63f273ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.14"
+#define DC_VER "3.1.15"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 71/73] drm/amd/display: remove stream_func vtable

[Harry Wentland]

From: Tony Cheng 

Change-Id: I5fd90f7b53efd60dc2a0559edfcc90e9ab1bf5ff
Signed-off-by: Tony Cheng 
Reviewed-by: Sun peng Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 32 
 1 file changed, 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c509707ccd6..dbb03b3e2c23 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -144,37 +144,6 @@ struct dc_cap_funcs {
struct dc_surface_dcc_cap *output);
 };
 
-struct dc_stream_state_funcs {
-   bool (*adjust_vmin_vmax)(struct dc *dc,
-   struct dc_stream_state **stream,
-   int num_streams,
-   int vmin,
-   int vmax);
-   bool (*get_crtc_position)(struct dc *dc,
-   struct dc_stream_state **stream,
-   int num_streams,
-   unsigned int *v_pos,
-   unsigned int *nom_v_pos);
-
-   bool (*set_gamut_remap)(struct dc *dc,
-   const struct dc_stream_state *stream);
-
-   bool (*program_csc_matrix)(struct dc *dc,
-   struct dc_stream_state *stream);
-
-   void (*set_static_screen_events)(struct dc *dc,
-   struct dc_stream_state **stream,
-   int num_streams,
-   const struct dc_static_screen_events *events);
-
-   void (*set_dither_option)(struct dc_stream_state *stream,
-   enum dc_dither_option option);
-
-   void (*set_dpms)(struct dc *dc,
-   struct dc_stream_state *stream,
-   bool dpms_off);
-};
-
 struct link_training_settings;
 
 struct dc_link_funcs {
@@ -268,7 +237,6 @@ struct dce_hwseq;
 struct dc {
struct dc_caps caps;
struct dc_cap_funcs cap_funcs;
-   struct dc_stream_state_funcs stream_funcs;
struct dc_link_funcs link_funcs;
struct dc_config config;
struct dc_debug debug;
-- 
2.14.1

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[PATCH 68/73] drm/amd/display: Move dc_stream interface to separate header

[Harry Wentland]

Change-Id: I390b96c79693dc7d00e39f8dfb8700cf20b7c3f3
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h| 223 +---
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 271 +
 2 files changed, 273 insertions(+), 221 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dc_stream.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5fe86fab6995..170cdcb5a027 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -137,6 +137,7 @@ struct dc;
 struct dc_plane_state;
 struct dc_state;
 
+
 struct dc_cap_funcs {
bool (*get_dcc_compression_cap)(const struct dc *dc,
const struct dc_dcc_surface_param *input,
@@ -577,168 +578,7 @@ struct dc_flip_addrs {
 bool dc_post_update_surfaces_to_stream(
struct dc *dc);
 
-/***
- * Stream Interfaces
- 
**/
-
-struct dc_stream_status {
-   int primary_otg_inst;
-   int stream_enc_inst;
-   int plane_count;
-   struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
-
-   /*
-* link this stream passes through
-*/
-   struct dc_link *link;
-};
-
-struct dc_stream_state {
-   struct dc_sink *sink;
-   struct dc_crtc_timing timing;
-
-   struct rect src; /* composition area */
-   struct rect dst; /* stream addressable area */
-
-   struct audio_info audio_info;
-
-   struct freesync_context freesync_ctx;
-
-   struct dc_hdr_static_metadata hdr_static_metadata;
-   struct dc_transfer_func *out_transfer_func;
-   struct colorspace_transform gamut_remap_matrix;
-   struct csc_transform csc_color_matrix;
-
-   enum dc_color_space output_color_space;
-   enum dc_dither_option dither_option;
-
-   enum view_3d_format view_format;
-
-   bool ignore_msa_timing_param;
-   /* TODO: custom INFO packets */
-   /* TODO: ABM info (DMCU) */
-   /* TODO: PSR info */
-   /* TODO: CEA VIC */
-
-   /* from core_stream struct */
-   struct dc_context *ctx;
-
-   /* used by DCP and FMT */
-   struct bit_depth_reduction_params bit_depth_params;
-   struct clamping_and_pixel_encoding_params clamping;
-
-   int phy_pix_clk;
-   enum signal_type signal;
-   bool dpms_off;
-
-   struct dc_stream_status status;
-
-   struct dc_cursor_attributes cursor_attributes;
-
-   /* from stream struct */
-   struct kref refcount;
-
-   struct crtc_trigger_info triggered_crtc_reset;
-
-};
-
-struct dc_stream_update {
-   struct rect src;
-   struct rect dst;
-   struct dc_transfer_func *out_transfer_func;
-   struct dc_hdr_static_metadata *hdr_static_metadata;
-};
-
-bool dc_is_stream_unchanged(
-   struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-bool dc_is_stream_scaling_unchanged(
-   struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-
-/*
- * Set up surface attributes and associate to a stream
- * The surfaces parameter is an absolute set of all surface active for the 
stream.
- * If no surfaces are provided, the stream will be blanked; no memory read.
- * Any flip related attribute changes must be done through this interface.
- *
- * After this call:
- *   Surfaces attributes are programmed and configured to be composed into 
stream.
- *   This does not trigger a flip.  No surface address is programmed.
- */
-
-bool dc_commit_planes_to_stream(
-   struct dc *dc,
-   struct dc_plane_state **plane_states,
-   uint8_t new_plane_count,
-   struct dc_stream_state *dc_stream,
-   struct dc_state *state);
-
-void dc_commit_updates_for_stream(struct dc *dc,
-   struct dc_surface_update *srf_updates,
-   int surface_count,
-   struct dc_stream_state *stream,
-   struct dc_stream_update *stream_update,
-   struct dc_plane_state **plane_states,
-   struct dc_state *state);
-/*
- * Log the current stream state.
- */
-void dc_stream_log(
-   const struct dc_stream_state *stream,
-   struct dal_logger *dc_logger,
-   enum dc_log_type log_type);
-
-uint8_t dc_get_current_stream_count(struct dc *dc);
-struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-
-/*
- * Return the current frame counter.
- */
-uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
-
-/* TODO: Return parsed values rather than direct register read
- * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
- * being refactored properly to be dce-specific
- */
-bool 

[PATCH 72/73] drm/amd/display: Fix Linux after optimize frontend programming

[Harry Wentland]

We still require the update_plane_addr call in commit_planes_for_stream.

Change-Id: I281c0106e02bf9828a750c28590f12726d16196d
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ca9e6bc13352..b71422d636ac 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1308,11 +1308,8 @@ static void commit_planes_for_stream(struct dc *dc,
if (pipe_ctx->plane_state != plane_state)
continue;
 
-   if (update_type == UPDATE_TYPE_FAST) {
-   if (srf_updates[i].flip_addr)
-   dc->hwss.update_plane_addr(dc, 
pipe_ctx);
-   continue;
-   }
+   if (srf_updates[i].flip_addr)
+   dc->hwss.update_plane_addr(dc, pipe_ctx);
}
}
 
-- 
2.14.1

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[PATCH 59/73] drm/amd/display: Remove legacy unused workaround

[Harry Wentland]

From: Andrew Jiang 

We shouldn't be able to get a non-visible plane into DC anymore.

Change-Id: I152ff6dabe8e022fd200d0aab42e64e0444b70f9
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +--
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1ccc0c018b0e..95a6795af6d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1153,9 +1153,7 @@ static unsigned int pixel_format_to_bpp(enum 
surface_pixel_format format)
}
 }
 
-static enum surface_update_type get_plane_info_update_type(
-   const struct dc_surface_update *u,
-   int surface_index)
+static enum surface_update_type get_plane_info_update_type(const struct 
dc_surface_update *u)
 {
struct dc_plane_info temp_plane_info;
memset(_plane_info, 0, sizeof(temp_plane_info));
@@ -1179,11 +1177,6 @@ static enum surface_update_type 
get_plane_info_update_type(
temp_plane_info.rotation = u->surface->rotation;
temp_plane_info.stereo_format = u->surface->stereo_format;
 
-   if (surface_index == 0)
-   temp_plane_info.visible = u->plane_info->visible;
-   else
-   temp_plane_info.visible = u->surface->visible;
-
if (memcmp(u->plane_info, _plane_info,
sizeof(struct dc_plane_info)) != 0)
return UPDATE_TYPE_FULL;
@@ -1246,10 +1239,8 @@ static enum surface_update_type  
get_scaling_info_update_type(
return UPDATE_TYPE_FAST;
 }
 
-static enum surface_update_type det_surface_update(
-   const struct dc *dc,
-   const struct dc_surface_update *u,
-   int surface_index)
+static enum surface_update_type det_surface_update(const struct dc *dc,
+   
   const struct dc_surface_update *u)
 {
const struct dc_state *context = dc->current_state;
enum surface_update_type type = UPDATE_TYPE_FAST;
@@ -1258,7 +1249,7 @@ static enum surface_update_type det_surface_update(
if (!is_surface_in_context(context, u->surface))
return UPDATE_TYPE_FULL;
 
-   type = get_plane_info_update_type(u, surface_index);
+   type = get_plane_info_update_type(u);
if (overall_type < type)
overall_type = type;
 
@@ -1293,7 +1284,7 @@ enum surface_update_type 
dc_check_update_surfaces_for_stream(
 
for (i = 0 ; i < surface_count; i++) {
enum surface_update_type type =
-   det_surface_update(dc, [i], i);
+   det_surface_update(dc, [i]);
 
if (type == UPDATE_TYPE_FULL)
return type;
-- 
2.14.1

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[PATCH 62/73] drm/amd/display: Added Opp and Diags Interface for P to I

[Harry Wentland]

From: Arun Pandey 

Change-Id: I47b7c9a88eebe84c238f20cd1c9206d06eace7e7
Signed-off-by: Arun Pandey 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   | 29 +++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   | 38 --
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h| 15 +
 6 files changed, 44 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ffce33fb5540..0bc1cb889992 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -431,13 +431,13 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
struct dc *dc)
 {
struct dc_stream_state *stream = pipe_ctx->stream;
+   struct mpc *mpc = dc->res_pool->mpc;
enum dc_color_space color_space;
struct tg_color black_color = {0};
bool enableStereo= stream->timing.timing_3d_format == 
TIMING_3D_FORMAT_NONE ?
false:true;
bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 
-
/* by upper caller loop, pipe0 is parent pipe and be called first.
 * back end is set up by for pipe0. Other children pipe share back end
 * with pipe 0. No program is needed.
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 5028619d4fb4..b016f4cbd45c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -335,7 +335,7 @@ void mpc10_update_blend_mode(
MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
 }
 
-static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
 {
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
int opp_id = 0xF;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 683ce4aaa76e..e85e1f342266 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -134,5 +134,6 @@ void mpc10_assert_idle_mpcc(
 void mpc10_update_blend_mode(
struct mpc *mpc,
struct mpcc_cfg *cfg);
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 71385a004f52..341210060cf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,25 +38,6 @@
oppn10->base.ctx
 
 
-enum dpg_mode {
-   /* RGB colour block mode */
-   DPG_MODE_RGB_COLOUR_BLOCK,
-   /* YCbCr-601 colour block mode */
-   DPG_MODE_YCBCR_601_COLOUR_BLOCK,
-   /* YCbCr-709 colour block mode */
-   DPG_MODE_YCBCR_709_COLOUR_BLOCK,
-   /* Vertical bar mode */
-   DPG_MODE_VERTICAL_BAR,
-   /* Horizontal bar mode */
-   DPG_MODE_HORIZONTAL_BAR,
-   /* Single ramp mode */
-   DPG_MODE_RGB_SINGLE_RAMP,
-   /* Dual ramp mode */
-   DPG_MODE_RGB_DUAL_RAMP,
-   /* RGB XR BIAS mode */
-   DPG_MODE_RGB_XR_BIAS
-};
-
 /* FORMATTER /
 
 /**
@@ -154,7 +135,7 @@ static void opp1_set_spatial_dither(
FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void opp1_program_bit_depth_reduction(
+void opp1_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
 {
@@ -242,7 +223,7 @@ static void opp1_set_clamping(
 
 }
 
-static void opp1_set_dyn_expansion(
+void opp1_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
@@ -292,7 +273,7 @@ static void opp1_program_clamping_and_pixel_encoding(
opp1_set_pixel_encoding(oppn10, params);
 }
 
-static void opp1_program_fmt(
+void opp1_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
@@ -315,7 +296,7 @@ static void opp1_program_fmt(
return;
 }
 
-static void opp1_set_stereo_polarity(
+void opp1_set_stereo_polarity(
struct output_pixel_processor *opp,
bool enable, bool rightEyePolarity)
 {
@@ -328,7 +309,7 @@ static void opp1_set_stereo_polarity(
 /* Constructor, Destructor   */
 

[PATCH 53/73] drm/amd/display: Apply work around for stutter.

[Harry Wentland]

From: Yongqiang Sun 

Power on one plane after disable all the planes, for
a hw bug work around to resolve stutter efficiency issue.

Change-Id: Ifc696c800f9402afb9615a974657c8b06a94b334
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |   2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 153 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h   |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  10 +-
 6 files changed, 84 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index de7332cffaa2..615541d8eb21 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -935,7 +935,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
if (context->res_ctx.pipe_ctx[i].stream == NULL ||
context->res_ctx.pipe_ctx[i].plane_state == NULL) {
context->res_ctx.pipe_ctx[i].pipe_idx = i;
-   dc->hwss.power_down_front_end(dc, 
>res_ctx.pipe_ctx[i]);
+   dc->hwss.disable_plane(dc, 
>res_ctx.pipe_ctx[i]);
}
 
/* 3rd param should be true, temp w/a for RV*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f6f06bcaac01..28c977f49773 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1413,7 +1413,7 @@ static void disable_vga_and_power_gate_all_controllers(
true);
 
dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
-   dc->hwss.power_down_front_end(dc,
+   dc->hwss.disable_plane(dc,
>current_state->res_ctx.pipe_ctx[i]);
}
 }
@@ -1836,7 +1836,7 @@ static void dce110_reset_hw_ctx_wrap(
if (old_clk)
old_clk->funcs->cs_power_down(old_clk);
 
-   dc->hwss.power_down_front_end(dc, pipe_ctx_old);
+   dc->hwss.disable_plane(dc, pipe_ctx_old);
 
pipe_ctx_old->stream = NULL;
}
@@ -2061,8 +2061,8 @@ enum dc_status dce110_apply_ctx_to_hw(
context,
dc);
 
-   if (dc->hwss.power_on_front_end)
-   dc->hwss.power_on_front_end(dc, pipe_ctx, context);
+   if (dc->hwss.enable_plane)
+   dc->hwss.enable_plane(dc, pipe_ctx, context);
 
if (DC_OK != status)
return status;
@@ -2967,7 +2967,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.unblank_stream = dce110_unblank_stream,
.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
.enable_display_power_gating = dce110_enable_display_power_gating,
-   .power_down_front_end = dce110_power_down_fe,
+   .disable_plane = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
.set_bandwidth = dce110_set_bandwidth,
.set_drr = set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cb73d25aca4c..7d1821fb3607 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -363,11 +363,8 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 {
struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = dc->res_pool->hubps[0];
-   int pwr_status = 0;
 
-   REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, _status);
-   /* Don't need to blank if hubp is power gated*/
-   if (pwr_status == 2)
+   if (!hws->wa_state.DEGVIDCN10_253_applied)
return;
 
hubp->funcs->set_blank(hubp, true);
@@ -378,16 +375,29 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
hubp_pg_control(hws, 0, false);
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 0);
+
+   hws->wa_state.DEGVIDCN10_253_applied = false;
 }
 
 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 {
struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = dc->res_pool->hubps[0];
+   int i;
 
if (dc->debug.disable_stutter)
return;
 
+   if (!hws->wa.DEGVIDCN10_253)
+   return;
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   if (!dc->res_pool->hubps[i]->power_gated)
+   

[PATCH 58/73] drm/amd/display: Early return on stream programming failure

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

The fail goto is incorrect. It will incorrectly release the dc_states on
stream programming failure.

Change-Id: Ifefa4561266aaef10235e02dc687f5c0f637e6c1
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c1ae293b41b3..1ccc0c018b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -893,7 +893,7 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
result = dc->hwss.apply_ctx_to_hw(dc, context);
 
if (result != DC_OK)
-   goto fail;
+   return result;
 
if (context->stream_count > 1) {
enable_timing_multisync(dc, context);
@@ -932,7 +932,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
context->streams[i]->timing.pix_clk_khz);
}
 
-fail:
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
dc_release_state(dc->current_state);
-- 
2.14.1

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[PATCH 34/73] drm/amd/display: Add transfer function to dc_surface_update

[Harry Wentland]

From: SivapiriyanKumarasamy 

Change-Id: Ic42be4e0033db8d402f5688aef7c3cea6f7e0119
Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 86a9c927a312..acb36594acc2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -475,6 +475,8 @@ struct dc_surface_update {
 */
/* gamma TO BE REMOVED */
struct dc_gamma *gamma;
+   enum color_transfer_func color_input_tf;
+   enum color_transfer_func color_output_tf;
struct dc_transfer_func *in_transfer_func;
 
struct csc_transform *input_csc_color_matrix;
-- 
2.14.1

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[PATCH 70/73] drm/amd/display: Remove unnecessary dc_stream vtable

[Harry Wentland]

There's no need to have this as a vtable. The vtable was initially
used for stream_adjust_vmin_vmax but the condition checked here
(set_drr) is always true, hence we don't need to assign this
dynamically anymore.

Change-Id: I60e3c213b4566b3808b8feb001b93b74bcf7f17a
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 136 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  18 +++
 .../drm/amd/display/modules/freesync/freesync.c|  84 +
 3 files changed, 51 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c2931989eefa..ca9e6bc13352 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -158,7 +158,7 @@ static bool create_links(
return false;
 }
 
-static bool stream_adjust_vmin_vmax(struct dc *dc,
+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state **streams, int num_streams,
int vmin, int vmax)
 {
@@ -183,7 +183,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc,
return ret;
 }
 
-static bool stream_get_crtc_position(struct dc *dc,
+bool dc_stream_get_crtc_position(struct dc *dc,
struct dc_stream_state **streams, int num_streams,
unsigned int *v_pos, unsigned int *nom_v_pos)
 {
@@ -208,45 +208,7 @@ static bool stream_get_crtc_position(struct dc *dc,
return ret;
 }
 
-static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state 
*stream)
-{
-   int i = 0;
-   bool ret = false;
-   struct pipe_ctx *pipes;
-
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
-   pipes = >current_state->res_ctx.pipe_ctx[i];
-   dc->hwss.program_gamut_remap(pipes);
-   ret = true;
-   }
-   }
-
-   return ret;
-}
-
-static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
-{
-   int i = 0;
-   bool ret = false;
-   struct pipe_ctx *pipes;
-
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (dc->current_state->res_ctx.pipe_ctx[i].stream
-   == stream) {
-
-   pipes = >current_state->res_ctx.pipe_ctx[i];
-   dc->hwss.program_csc_matrix(pipes,
-   stream->output_color_space,
-   stream->csc_color_matrix.matrix);
-   ret = true;
-   }
-   }
-
-   return ret;
-}
-
-static void set_static_screen_events(struct dc *dc,
+void dc_stream_set_static_screen_events(struct dc *dc,
struct dc_stream_state **streams,
int num_streams,
const struct dc_static_screen_events *events)
@@ -337,100 +299,8 @@ static void set_test_pattern(
cust_pattern_size);
 }
 
-static void set_dither_option(struct dc_stream_state *stream,
-   enum dc_dither_option option)
-{
-   struct bit_depth_reduction_params params;
-   struct dc_link *link = stream->status.link;
-   struct pipe_ctx *pipes = NULL;
-   int i;
-
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
-   stream) {
-   pipes = >dc->current_state->res_ctx.pipe_ctx[i];
-   break;
-   }
-   }
-
-   memset(, 0, sizeof(params));
-   if (!pipes)
-   return;
-   if (option > DITHER_OPTION_MAX)
-   return;
-
-   stream->dither_option = option;
-
-   resource_build_bit_depth_reduction_params(stream,
-   );
-   stream->bit_depth_params = params;
-   pipes->stream_res.opp->funcs->
-   opp_program_bit_depth_reduction(pipes->stream_res.opp, );
-}
-
-void set_dpms(
-   struct dc *dc,
-   struct dc_stream_state *stream,
-   bool dpms_off)
-{
-   struct pipe_ctx *pipe_ctx = NULL;
-   int i;
-
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
-   pipe_ctx = >current_state->res_ctx.pipe_ctx[i];
-   break;
-   }
-   }
-
-   if (!pipe_ctx) {
-   ASSERT(0);
-   return;
-   }
-
-   if (stream->dpms_off != dpms_off) {
-   stream->dpms_off = dpms_off;
-
-   if (dpms_off) {
-   core_link_disable_stream(pipe_ctx,
-   KEEP_ACQUIRED_RESOURCE);
-
-   dc->hwss.pplib_apply_display_requirements(
-   

[PATCH 45/73] drm/amd/display: Remove extra arr_points element

[Harry Wentland]

arr_points[1] and [2] were duplicated. Remove the extra
one. If we ever need more points we can add them but the
current state of affairs is confusing.

Change-Id: Ib72a1cb90940e9d52f241432c160f14393992523
Signed-off-by: Harry Wentland 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 7 ---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 7 ---
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h| 2 +-
 5 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 4ff874a43f7a..543b4901e987 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1277,7 +1277,7 @@ static void regamma_config_regions_and_segments(struct 
dce_transform *xfm_dce,
 
REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
  REGAMMA_CNTLA_EXP_REGION_END_BASE, 
params->arr_points[1].custom_float_y,
- REGAMMA_CNTLA_EXP_REGION_END_SLOPE, 
params->arr_points[2].custom_float_slope);
+ REGAMMA_CNTLA_EXP_REGION_END_SLOPE, 
params->arr_points[1].custom_float_slope);
 
curve = params->arr_curve_points;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index bf76698b30c1..d411d0a8b9d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -539,8 +539,6 @@ static bool dce110_translate_regamma_to_hw_format(const 
struct dc_transfer_func
dal_fixed31_32_from_int(segment_start));
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
dal_fixed31_32_from_int(segment_end));
-   arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-   dal_fixed31_32_from_int(segment_end));
 
y_r = rgb_resulted[0].red;
y_g = rgb_resulted[0].green;
@@ -563,10 +561,8 @@ static bool dce110_translate_regamma_to_hw_format(const 
struct dc_transfer_func
y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
 
arr_points[1].y = y3_max;
-   arr_points[2].y = y3_max;
 
arr_points[1].slope = dal_fixed31_32_zero;
-   arr_points[2].slope = dal_fixed31_32_zero;
 
if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
/* for PQ, we want to have a straight line from last HW X point,
@@ -578,9 +574,6 @@ static bool dce110_translate_regamma_to_hw_format(const 
struct dc_transfer_func
arr_points[1].slope = dal_fixed31_32_div(
dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
dal_fixed31_32_sub(end_value, arr_points[1].x));
-   arr_points[2].slope = dal_fixed31_32_div(
-   dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-   dal_fixed31_32_sub(end_value, arr_points[1].x));
}
 
regamma_params->hw_points_num = hw_points;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index e98ed3058ea2..9b65b77e8823 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -175,7 +175,7 @@ static void regamma_config_regions_and_segments(
value = 0;
set_reg_field_value(
value,
-   params->arr_points[2].custom_float_slope,
+   params->arr_points[1].custom_float_slope,
GAMMA_CORR_CNTLA_END_CNTL2,
GAMMA_CORR_CNTLA_EXP_REGION_END_BASE);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 666c6c0f882a..c4a6ad3f7e25 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1158,8 +1158,6 @@ static bool dcn10_translate_regamma_to_hw_format(const 
struct dc_transfer_func
dal_fixed31_32_from_int(segment_start));
arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
dal_fixed31_32_from_int(segment_end));
-   arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-   dal_fixed31_32_from_int(segment_end));
 
y_r = rgb_resulted[0].red;
y_g = rgb_resulted[0].green;
@@ -1181,10 +1179,8 @@ static bool 

[PATCH 64/73] drm/amd/display: Add check update surfaces for stream wrapper

[Harry Wentland]

From: Andrew Jiang 

This allows us to properly clear and set the update flags for all cases.

Change-Id: I9d4f8295db086f4401284098420af8a37c6bea44
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 24 ++--
 drivers/gpu/drm/amd/display/dc/dc.h  |  2 +-
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0294ff865406..c2931989eefa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1304,7 +1304,7 @@ static enum surface_update_type det_surface_update(const 
struct dc *dc,
return overall_type;
 }
 
-enum surface_update_type dc_check_update_surfaces_for_stream(
+static enum surface_update_type check_update_surfaces_for_stream(
struct dc *dc,
struct dc_surface_update *updates,
int surface_count,
@@ -1324,7 +1324,6 @@ enum surface_update_type 
dc_check_update_surfaces_for_stream(
enum surface_update_type type =
det_surface_update(dc, [i]);
 
-   updates[i].surface->update_type = type;
if (type == UPDATE_TYPE_FULL)
return type;
 
@@ -1334,6 +1333,27 @@ enum surface_update_type 
dc_check_update_surfaces_for_stream(
return overall_type;
 }
 
+enum surface_update_type dc_check_update_surfaces_for_stream(
+   struct dc *dc,
+   struct dc_surface_update *updates,
+   int surface_count,
+   struct dc_stream_update *stream_update,
+   const struct dc_stream_status *stream_status)
+{
+   int i;
+   enum surface_update_type type;
+
+   for (i = 0; i < surface_count; i++)
+   updates[i].surface->update_flags.raw = 0;
+
+   type = check_update_surfaces_for_stream(dc, updates, surface_count, 
stream_update, stream_status);
+   if (type == UPDATE_TYPE_FULL)
+   for (i = 0; i < surface_count; i++)
+   updates[i].surface->update_flags.bits.full_update = 1;
+
+   return type;
+}
+
 static struct dc_stream_status *stream_get_status(
struct dc_state *ctx,
struct dc_stream_state *stream)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index fb45e1170f42..5fe86fab6995 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -453,6 +453,7 @@ union surface_update_flags {
uint32_t bandwidth_change:1;
uint32_t clock_change:1;
uint32_t stereo_format_change:1;
+   uint32_t full_update:1;
} bits;
 
uint32_t raw;
@@ -492,7 +493,6 @@ struct dc_plane_state {
bool horizontal_mirror;
 
union surface_update_flags update_flags;
-   enum surface_update_type update_type;
/* private to DC core */
struct dc_plane_status status;
struct dc_context *ctx;
-- 
2.14.1

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[PATCH 31/73] drm/amd/display: add warning on long reg_wait

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: I237ee9baaeb91434d94abe0b2ce052f9f4f67799
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c 
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 0d84b2a1ccfd..c584252669fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -156,8 +156,13 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
 
field_value = get_reg_field_value_ex(reg_val, mask, shift);
 
-   if (field_value == condition_value)
+   if (field_value == condition_value) {
+   if (i * delay_between_poll_us > 1000)
+   dm_output_to_console("REG_WAIT taking a while: 
%dms in %s line:%d\n",
+   delay_between_poll_us * i / 
1000,
+   func_name, line);
return reg_val;
+   }
}
 
dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
-- 
2.14.1

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[PATCH 33/73] drm/amd/display: send display_count msg so SMU can enter S0i2

[Harry Wentland]

From: Hersen Wu 

SMU can future lower voltages in long idle case when all display is off.

If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.

otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state.  before is not neccessary as we are out of S0i2
when driver execute code, but send message before anyways for correctness.

Change-Id: Ic2a3c808eab514c42e0691e694767b0139579b78
Signed-off-by: Hersen Wu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 12 ++--
 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c |  2 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |  5 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h   |  4 
 5 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d969bf116645..d6938bf19c8f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -383,11 +383,19 @@ void set_dpms(
 
if (stream->dpms_off != dpms_off) {
stream->dpms_off = dpms_off;
-   if (dpms_off)
+
+   if (dpms_off) {
core_link_disable_stream(pipe_ctx,
KEEP_ACQUIRED_RESOURCE);
-   else
+
+   dc->hwss.pplib_apply_display_requirements(
+   dc, dc->current_state);
+   } else {
+   dc->hwss.pplib_apply_display_requirements(
+   dc, dc->current_state);
+
core_link_enable_stream(dc->current_state, pipe_ctx);
+   }
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index e7a694835e3e..469af0587604 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
 
dc->hwss.enable_display_power_gating = 
dce100_enable_display_power_gating;
dc->hwss.set_bandwidth = dce100_set_bandwidth;
+   dc->hwss.pplib_apply_display_requirements =
+   dce100_pplib_apply_display_requirements;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8d9a6b504046..bf76698b30c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2593,6 +2593,10 @@ void dce110_fill_display_configs(
 
ASSERT(pipe_ctx != NULL);
 
+   /* only notify active stream */
+   if (stream->dpms_off)
+   continue;
+
num_cfgs++;
cfg->signal = pipe_ctx->stream->signal;
cfg->pipe_idx = pipe_ctx->pipe_idx;
@@ -3022,6 +3026,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
.ready_shared_resources = ready_shared_resources,
.optimize_shared_resources = optimize_shared_resources,
+   .pplib_apply_display_requirements = pplib_apply_display_requirements,
.edp_backlight_control = hwss_edp_backlight_control,
.edp_power_control = hwss_edp_power_control,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5d1fb1c297a3..73e7afb360b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2567,6 +2567,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
.ready_shared_resources = ready_shared_resources,
.optimize_shared_resources = optimize_shared_resources,
+   .pplib_apply_display_requirements =
+   dcn10_pplib_apply_display_requirements,
.edp_backlight_control = hwss_edp_backlight_control,
.edp_power_control = hwss_edp_power_control
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 19cfca91bb4e..1d8852683f1f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -183,12 +183,16 @@ struct hw_sequencer_funcs {
 
void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
void 

[PATCH 63/73] drm/amd/display: Rename pitch_alignment to linear_pitch_alignment

[Harry Wentland]

From: Andrew Jiang 

Also initialize this to 64 for all ASICs.

Change-Id: Ia745d8d17e176ac2f65c6ac398d93bdc77fe75d6
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 1 +
 drivers/gpu/drm/amd/display/dc/dc.h   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 -
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index bb053cbd4db1..0294ff865406 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -696,6 +696,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
 
dc->caps.max_links = dc->link_count;
dc->caps.max_audios = dc->res_pool->audio_count;
+   dc->caps.linear_pitch_alignment = 64;
 
dc->config = init_params->flags;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f6d431a942a1..fb45e1170f42 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -58,7 +58,7 @@ struct dc_caps {
uint32_t i2c_speed_in_khz;
unsigned int max_cursor_size;
unsigned int max_video_width;
-   int pitch_alignment;
+   int linear_pitch_alignment;
bool dcc_const_color;
bool dynamic_audio;
bool is_apu;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 7eb11c61c44e..d818a71b82c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1268,7 +1268,6 @@ static bool construct(
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
dc->caps.max_cursor_size = 256;
-   dc->caps.pitch_alignment = 64; /* Alignment is 64 on DCN1 */
dc->caps.max_slave_planes = 1;
dc->caps.is_apu = true;
 
-- 
2.14.1

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[PATCH 60/73] drm/amd/display: Add update flags in to determine surface update type

[Harry Wentland]

From: Andrew Jiang 

This way, we can know exactly what triggered the update type we're
looking at, and we can simplify the logic for determining what exactly
needs to be updated in the future.

Also allow a dst rect size increase to go through a medium update,
since that does not require us to increase clock or bandwidth.

Change-Id: I06ac694e33c33d4c8bfc31a34b664060b04116a8
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 123 ---
 drivers/gpu/drm/amd/display/dc/dc.h  |  93 +++
 2 files changed, 140 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 95a6795af6d9..82e6d33133ab 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -54,6 +54,13 @@
 
/***
  * Private functions
  
**/
+
+static inline void elevate_update_type(enum surface_update_type *original, 
enum surface_update_type new)
+{
+   if (new > *original)
+   *original = new;
+}
+
 static void destroy_links(struct dc *dc)
 {
uint32_t i;
@@ -1155,77 +1162,88 @@ static unsigned int pixel_format_to_bpp(enum 
surface_pixel_format format)
 
 static enum surface_update_type get_plane_info_update_type(const struct 
dc_surface_update *u)
 {
-   struct dc_plane_info temp_plane_info;
-   memset(_plane_info, 0, sizeof(temp_plane_info));
+   union surface_update_flags *update_flags = >surface->update_flags;
 
if (!u->plane_info)
return UPDATE_TYPE_FAST;
 
-   temp_plane_info = *u->plane_info;
+   if (u->plane_info->color_space != u->surface->color_space)
+   update_flags->bits.color_space_change = 1;
 
-   /* Copy all parameters that will cause a full update
-* from current surface, the rest of the parameters
-* from provided plane configuration.
-* Perform memory compare and special validation
-* for those that can cause fast/medium updates
-*/
+   if (u->plane_info->input_tf != u->surface->input_tf)
+   update_flags->bits.input_tf_change = 1;
 
-   /* Full update parameters */
-   temp_plane_info.color_space = u->surface->color_space;
-   temp_plane_info.input_tf = u->surface->input_tf;
-   temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
-   temp_plane_info.rotation = u->surface->rotation;
-   temp_plane_info.stereo_format = u->surface->stereo_format;
+   if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
+   update_flags->bits.horizontal_mirror_change = 1;
 
-   if (memcmp(u->plane_info, _plane_info,
-   sizeof(struct dc_plane_info)) != 0)
-   return UPDATE_TYPE_FULL;
+   if (u->plane_info->rotation != u->surface->rotation)
+   update_flags->bits.rotation_change = 1;
+
+   if (u->plane_info->stereo_format != u->surface->stereo_format)
+   update_flags->bits.stereo_format_change = 1;
+
+   if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
+   update_flags->bits.per_pixel_alpha_change = 1;
 
if (pixel_format_to_bpp(u->plane_info->format) !=
-   pixel_format_to_bpp(u->surface->format)) {
+   pixel_format_to_bpp(u->surface->format))
/* different bytes per element will require full bandwidth
 * and DML calculation
 */
-   return UPDATE_TYPE_FULL;
-   }
+   update_flags->bits.bpp_change = 1;
 
if (memcmp(>plane_info->tiling_info, >surface->tiling_info,
sizeof(union dc_tiling_info)) != 0) {
+   update_flags->bits.swizzle_change = 1;
/* todo: below are HW dependent, we should add a hook to
 * DCE/N resource and validated there.
 */
-   if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
+   if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
/* swizzled mode requires RQ to be setup properly,
 * thus need to run DML to calculate RQ settings
 */
-   return UPDATE_TYPE_FULL;
-   }
+   update_flags->bits.bandwidth_change = 1;
}
 
+   if (update_flags->bits.rotation_change
+   || update_flags->bits.stereo_format_change
+   || update_flags->bits.bpp_change
+   || update_flags->bits.bandwidth_change)
+   

[PATCH 35/73] drm/amd/display: fix dcn10_hubbub_wm_read_state

[Harry Wentland]

From: Ken Chalmers 

The ALLOW_SR registers might not always be available.

Change-Id: I715cffd3e56caee38ceed7af112182a7a51ce39a
Signed-off-by: Ken Chalmers 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c| 26 +++---
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 23c4573f7a34..eb8317187f30 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -42,36 +42,46 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 {
struct dcn_hubbub_wm_set *s;
 
+   memset(wm, 0, sizeof(struct dcn_hubbub_wm));
+
s = >sets[0];
s->wm_set = 0;
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
s->pte_meta_urgent = 
REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
-   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
-   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+   if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
+   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+   }
s->dram_clk_chanage = 
REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
 
s = >sets[1];
s->wm_set = 1;
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
s->pte_meta_urgent = 
REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
-   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
-   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
+   if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
+   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
+   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
+   }
s->dram_clk_chanage = 
REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
 
s = >sets[2];
s->wm_set = 2;
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
s->pte_meta_urgent = 
REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
-   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
-   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
+   if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
+   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
+   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
+   }
s->dram_clk_chanage = 
REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
 
s = >sets[3];
s->wm_set = 3;
s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
s->pte_meta_urgent = 
REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
-   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
-   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
+   if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
+   s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
+   s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
+   }
s->dram_clk_chanage = 
REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
-- 
2.14.1

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[PATCH 67/73] drm/amd/display: Fix formatting for null pointer dereference fix

[Harry Wentland]

Change-Id: I277078c8d6c547fb5a685845f6617bf9886c6fe4
Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index f561232e8867..1efa5b62e257 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -285,7 +285,7 @@ bool dc_stream_set_cursor_position(
pos_cpy.enable = false;
 
 
-   if (ipp !=NULL && ipp->funcs->ipp_cursor_set_position != NULL)
+   if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
ipp->funcs->ipp_cursor_set_position(ipp, _cpy, 
);
 
if (mi != NULL && mi->funcs->set_cursor_position != NULL)
-- 
2.14.1

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[PATCH 47/73] drm/amd/display: Remove unused register read in program_pwl

[Harry Wentland]

Change-Id: I28eb763419eec834c591c03281abd22ad446b2e7
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 97414abbc69d..330dbe9989d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1181,7 +1181,6 @@ static void program_pwl(
struct dce_transform *xfm_dce,
const struct pwl_params *params)
 {
-   uint32_t value;
int retval;
uint8_t max_tries = 10;
uint8_t counter = 0;
@@ -1198,7 +1197,6 @@ static void program_pwl(
 
while (counter < max_tries) {
if (REG(DCFE_MEM_PWR_STATUS)) {
-   value = REG_READ(DCFE_MEM_PWR_STATUS);
REG_GET(DCFE_MEM_PWR_STATUS,
DCP_REGAMMA_MEM_PWR_STATE,
);
@@ -1207,7 +1205,6 @@ static void program_pwl(
break;
++counter;
} else {
-   value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL);
REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
REGAMMA_LUT_MEM_PWR_STATE,
);
-- 
2.14.1

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[PATCH 49/73] drm/amd/display: combine output signal and signal

[Harry Wentland]

From: Eric Yang 

output signal used to be a public member to be used by DM to override
the stream signal. Now since there is no longer separation between
public and private part of stream, they are combined. The overriding
was not working properly as well, which is addressed by this change

Change-Id: Icd7487eb3e29078ee940a85bc916f7b6f9685a8e
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++-
 drivers/gpu/drm/amd/display/dc/dc.h |  2 --
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index de04b95e103a..f561232e8867 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -36,16 +36,13 @@
 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
 static void update_stream_signal(struct dc_stream_state *stream)
 {
-   if (stream->output_signal == SIGNAL_TYPE_NONE) {
-   struct dc_sink *dc_sink = stream->sink;
 
-   if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
-   stream->signal = stream->sink->link->connector_signal;
-   else
-   stream->signal = dc_sink->sink_signal;
-   } else {
-   stream->signal = stream->output_signal;
-   }
+   struct dc_sink *dc_sink = stream->sink;
+
+   if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
+   stream->signal = stream->sink->link->connector_signal;
+   else
+   stream->signal = dc_sink->sink_signal;
 
if (dc_is_dvi_signal(stream->signal)) {
if (stream->timing.pix_clk_khz > 
TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 74955f458fbb..f2647b40f3cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -579,8 +579,6 @@ struct dc_stream_state {
struct colorspace_transform gamut_remap_matrix;
struct csc_transform csc_color_matrix;
 
-   enum signal_type output_signal;
-
enum dc_color_space output_color_space;
enum dc_dither_option dither_option;
 
-- 
2.14.1

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[PATCH 57/73] drm/amd/display: Change frontend/backend programming sequence

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

This is a follow-up to the following change:

Yongqiang Sun: Program front end first when set mode.

Due to pipe-splitting features, how we handle stream enabling and
disabling needs to change.

In the case of pipe split disable, two planes need to be combined back
into the same stream. This needs to be done before any stream
programming happens.

The previous patch addresses this, but breaks cross-platform
compatibility. It's not guaranteed that a dc commit will be called
separately to program planes and streams.

Therefore, we handle the combined commit case by doing plane programming
both before and after stream programming, to handle pipe split disable
and plane enable respectively.

Change-Id: Ia8120f1f9d9e322556577b3054e3b19a1d860de3
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 41 ++--
 1 file changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d70dbc102123..c1ae293b41b3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -874,6 +874,33 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc);
 
+   /* Combine planes if required, in case of pipe split disable */
+   for (i = 0; i < dc->current_state->stream_count; i++) {
+   dc->hwss.apply_ctx_for_surface(
+   dc, dc->current_state->streams[i],
+   dc->current_state->stream_status[i].plane_count,
+   dc->current_state);
+   }
+
+   /* Program hardware */
+   dc->hwss.ready_shared_resources(dc, context);
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   pipe = >res_ctx.pipe_ctx[i];
+   dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
+   }
+
+   result = dc->hwss.apply_ctx_to_hw(dc, context);
+
+   if (result != DC_OK)
+   goto fail;
+
+   if (context->stream_count > 1) {
+   enable_timing_multisync(dc, context);
+   program_timing_sync(dc, context);
+   }
+
+   /* Program all planes within new context*/
for (i = 0; i < context->stream_count; i++) {
const struct dc_sink *sink = context->streams[i]->sink;
 
@@ -905,19 +932,7 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
context->streams[i]->timing.pix_clk_khz);
}
 
-   dc->hwss.ready_shared_resources(dc, context);
-
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   pipe = >res_ctx.pipe_ctx[i];
-   dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
-   }
-   result = dc->hwss.apply_ctx_to_hw(dc, context);
-
-   if (context->stream_count > 1) {
-   enable_timing_multisync(dc, context);
-   program_timing_sync(dc, context);
-   }
-
+fail:
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
dc_release_state(dc->current_state);
-- 
2.14.1

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[PATCH 52/73] drm/amd/display: remove dcn10 wait on tg unlock

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: Ifde23126bc8528f42ad73fa19e6bf48d17a2233b
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index d248067810c8..73ff78f9cae1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -571,11 +571,6 @@ static void tgn10_unlock(struct timing_generator *tg)
 
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 0);
-
-   /* why are we waiting here? */
-   REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
-   OTG_UPDATE_PENDING, 0,
-   1, 10);
 }
 
 static void tgn10_get_position(struct timing_generator *tg,
-- 
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[PATCH 44/73] drm/amd/display: add flip_immediate to commit update for stream

[Harry Wentland]

From: Bhawanpreet Lakha 

This struct is not updated on page flip and causes vblank_mode
to not work as expected

Change-Id: I0e8684c5b67ec5670054f4bb849fa26bc60ed4b1
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d6938bf19c8f..802aebaa2e11 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1409,8 +1409,11 @@ void dc_commit_updates_for_stream(struct dc *dc,
/* TODO: On flip we don't build the state, so it still has the
 * old address. Which is why we are updating the address here
 */
-   if (srf_updates[i].flip_addr)
+   if (srf_updates[i].flip_addr) {
surface->address = srf_updates[i].flip_addr->address;
+   surface->flip_immediate = 
srf_updates[i].flip_addr->flip_immediate;
+
+   }
 
if (update_type >= UPDATE_TYPE_MED) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
-- 
2.14.1

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[PATCH 55/73] drm/amd/display: Optimize programming front end

[Harry Wentland]

From: Yongqiang Sun 

In case of update type is medium, optimize squence,
reduce programing time.

Change-Id: Ib1793408897b0c4d4a64434c239c3703d43e83d9
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 22 +---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 42 ++
 2 files changed, 27 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 615541d8eb21..56df1304e49c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1314,7 +1314,7 @@ static void commit_planes_for_stream(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
 
-   if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)
+   if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state)
continue;
 
if (!pipe_ctx->top_pipe &&
@@ -1335,26 +1335,20 @@ static void commit_planes_for_stream(struct dc *dc,
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
 
-   if (update_type == UPDATE_TYPE_MED)
-   dc->hwss.apply_ctx_for_surface(
-   dc, stream, surface_count, context);
-
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
 
-   if (pipe_ctx->plane_state != plane_state)
+   if (pipe_ctx->stream != stream)
continue;
 
-   if (srf_updates[i].flip_addr)
-   dc->hwss.update_plane_addr(dc, pipe_ctx);
-
-   if (update_type == UPDATE_TYPE_FAST)
+   if (pipe_ctx->plane_state != plane_state)
continue;
 
-   /* work around to program degamma regs for split pipe 
after set mode. */
-   if (srf_updates[i].in_transfer_func ||
-   (pipe_ctx->top_pipe && 
pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
-   dc->hwss.set_input_transfer_func(pipe_ctx, 
pipe_ctx->plane_state);
+   if (update_type == UPDATE_TYPE_FAST) {
+   if (srf_updates[i].flip_addr)
+   dc->hwss.update_plane_addr(dc, 
pipe_ctx);
+   continue;
+   }
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7d1821fb3607..ffce33fb5540 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -555,7 +555,7 @@ static void reset_back_end_for_pipe(
pipe_ctx->pipe_idx, 
pipe_ctx->stream_res.tg->inst);
 }
 
-void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
static bool should_log_hw_state; /* prevent hw state log by default */
 
@@ -1331,7 +1331,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
DC_SYNC_INFO("Multi-display sync is complete\n");
 }
 
-static void print_rq_dlg_ttu(
+/*static void print_rq_dlg_ttu(
struct dc *core_dc,
struct pipe_ctx *pipe_ctx)
 {
@@ -1452,13 +1452,13 @@ static void print_rq_dlg_ttu(
pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
);
 }
+*/
 
 static void dcn10_enable_plane(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
 {
-   struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct dce_hwseq *hws = dc->hwseq;
 
if (dc->debug.sanity_checks) {
@@ -1479,6 +1479,7 @@ static void dcn10_enable_plane(
OPP_PIPE_CLOCK_EN, 1);
/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 
0x1f);*/
 
+/* TODO: enable/disable in dm as per update type.
if (plane_state) {
dm_logger_write(dc->ctx->logger, LOG_DC,
"Pipe:%d 0x%x: addr hi:0x%x, "
@@ -1514,6 +1515,7 @@ static void dcn10_enable_plane(
pipe_ctx->plane_res.scl_data.recout.y);
print_rq_dlg_ttu(dc, pipe_ctx);
}
+*/
 
if (dc->debug.sanity_checks) {
dcn10_verify_allow_pstate_change_high(dc);
@@ -1947,16 +1949,8 @@ static void 

[PATCH 32/73] drm/amd/display: Modified front end initiail in init_hw

[Harry Wentland]

From: Yongqiang Sun 

Optimized front end initial sequence, reset MPC module
properly.

Change-Id: Id223308988505a15a9e0fc26f908beb1e42ed4a4
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 66 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 11 
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 11 
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|  2 +
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  1 +
 5 files changed, 74 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bd30d49e574a..5d1fb1c297a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -616,10 +616,6 @@ static void plane_atomic_disable(struct dc *dc, struct 
pipe_ctx *pipe_ctx)
struct hubp *hubp = dc->res_pool->hubps[fe_idx];
struct mpc *mpc = dc->res_pool->mpc;
int opp_id = hubp->opp_id;
-   struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
-   if (tg == NULL)
-   return;
 
if (opp_id == 0xf)
return;
@@ -700,6 +696,8 @@ static void dcn10_init_hw(struct dc *dc)
struct abm *abm = dc->res_pool->abm;
struct dmcu *dmcu = dc->res_pool->dmcu;
struct dce_hwseq *hws = dc->hwseq;
+   struct dc_bios *dcb = dc->ctx->dc_bios;
+   struct dc_state  *context = dc->current_state;
 
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
REG_WRITE(REFCLK_CNTL, 0);
@@ -720,9 +718,10 @@ static void dcn10_init_hw(struct dc *dc)
}
/* end of FPGA. Below if real ASIC */
 
-   bios_golden_init(dc);
-
-   disable_vga(dc->hwseq);
+   if (!dcb->funcs->is_accelerated_mode(dcb)) {
+   bios_golden_init(dc);
+   disable_vga(dc->hwseq);
+   }
 
for (i = 0; i < dc->link_count; i++) {
/* Power up AND update implementation according to the
@@ -738,22 +737,55 @@ static void dcn10_init_hw(struct dc *dc)
}
 
for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   struct dpp *dpp = dc->res_pool->dpps[i];
struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
 
-   dpp->funcs->dpp_reset(dpp);
-   dc->res_pool->mpc->funcs->remove(
-   dc->res_pool->mpc, 
&(dc->res_pool->opps[i]->mpc_tree),
-   dc->res_pool->opps[i]->inst, i);
+   if (tg->funcs->is_tg_enabled(tg))
+   tg->funcs->lock(tg);
+   }
 
-   /* Blank controller using driver code instead of
-* command table.
-*/
-   tg->funcs->set_blank(tg, true);
-   hwss_wait_for_blank_complete(tg);
+   /* Blank controller using driver code instead of
+* command table.
+*/
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
+
+   if (tg->funcs->is_tg_enabled(tg)) {
+   tg->funcs->set_blank(tg, true);
+   hwss_wait_for_blank_complete(tg);
+   }
+   }
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
+   struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+
+   pipe_ctx->stream_res.tg = tg;
+   pipe_ctx->pipe_idx = i;
+   pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i];
+   pipe_ctx->plane_res.hubp->mpcc_id = i;
+   pipe_ctx->plane_res.hubp->opp_id =
+   
dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+
+   plane_atomic_disconnect(dc, pipe_ctx);
+   }
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
 
+   if (tg->funcs->is_tg_enabled(tg))
+   tg->funcs->unlock(tg);
+   }
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
+   struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+
+   plane_atomic_disable(dc, pipe_ctx);
plane_atomic_power_down(dc, i);
 
+   pipe_ctx->stream_res.tg = NULL;
+   pipe_ctx->plane_res.hubp = NULL;
+
tg->funcs->tg_init(tg);
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 

[PATCH 41/73] drm/amd/display: Check aux channel before MST resume

[Harry Wentland]

From: "Jerry (Fangzhi) Zuo" 

It is to fix: MST display failed to resume from S3

At the beginning of resume from S3, need to check if mgr->aux is
NULL. Fake MST encoder doesn't have real aux channel.

Change-Id: I15de6ab99da01841d62912dd98e6cc74d9100801
Signed-off-by: Jerry (Fangzhi) Zuo 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bdef1ed0dfac..b88a7cca61a8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -520,7 +520,8 @@ static int detect_mst_link_for_all_connectors(struct 
drm_device *dev)
 
list_for_each_entry(connector, >mode_config.connector_list, head) {
aconnector = to_amdgpu_dm_connector(connector);
-   if (aconnector->dc_link->type == dc_connection_mst_branch) {
+   if (aconnector->dc_link->type == dc_connection_mst_branch &&
+   aconnector->mst_mgr.aux) {
DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p 
[id: %d]\n",
aconnector, aconnector->base.base.id);
 
-- 
2.14.1

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[PATCH 36/73] drm/amd/display: Remove unused OPP functions from interface

[Harry Wentland]

From: Eric Bernstein 

Change-Id: Ib79e69b0178219e02819a7b92cc1cb1bea9b5a68
Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 8141b677fda9..cd6b0d4cd457 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -281,15 +281,6 @@ struct opp_funcs {
bool enable,
bool rightEyePolarity);
 
-   void (*opp_set_test_pattern)(
-   struct output_pixel_processor *opp,
-   bool enable);
-
-   void (*opp_dpg_blank_enable)(
-   struct output_pixel_processor *opp,
-   bool enable,
-   int width,
-   int height);
 };
 
 #endif
-- 
2.14.1

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[PATCH 01/73] drm/amd/display: Multi display synchronization logic

[Harry Wentland]

From: Mikita Lipski 

This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one

There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.

Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM

Feature is developed for DCN1 and DCE11

Change-Id: I605c576250f13d68f010de03390090233be3385e
Signed-off-by: Mikita Lipski 
Reviewed-by: Mikita Lipski 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  54 -
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  26 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   3 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  16 ++
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  46 +++-
 .../display/dc/dce110/dce110_timing_generator.c| 265 +
 .../display/dc/dce110/dce110_timing_generator.h|   6 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  29 ++-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |  66 -
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   5 +
 11 files changed, 456 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ccfbf14c0f09..de901fdd53cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2275,6 +2275,56 @@ static int create_fake_sink(struct amdgpu_dm_connector 
*aconnector)
return 0;
 }
 
+static void set_multisync_trigger_params(
+   struct dc_stream_state *stream)
+{
+   if (stream->triggered_crtc_reset.enabled) {
+   stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
+   stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
+   }
+}
+
+static void set_master_stream(struct dc_stream_state *stream_set[],
+ int stream_count)
+{
+   int j, highest_rfr = 0, master_stream = 0;
+
+   for (j = 0;  j < stream_count; j++) {
+   if (stream_set[j] && 
stream_set[j]->triggered_crtc_reset.enabled) {
+   int refresh_rate = 0;
+
+   refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
+   
(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
+   if (refresh_rate > highest_rfr) {
+   highest_rfr = refresh_rate;
+   master_stream = j;
+   }
+   }
+   }
+   for (j = 0;  j < stream_count; j++) {
+   if (stream_set[j] && j != master_stream)
+   stream_set[j]->triggered_crtc_reset.event_source = 
stream_set[master_stream];
+   }
+}
+
+static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
+{
+   int i = 0;
+
+   if (context->stream_count < 2)
+   return;
+   for (i = 0; i < context->stream_count ; i++) {
+   if (!context->streams[i])
+   continue;
+   /* TODO: add a function to read AMD VSDB bits and will set
+* crtc_sync_master.multi_sync_enabled flag
+* For now its set to false
+*/
+   set_multisync_trigger_params(context->streams[i]);
+   }
+   set_master_stream(context->streams, context->stream_count);
+}
+
 static struct dc_stream_state *
 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
   const struct drm_display_mode *drm_mode,
@@ -4143,8 +4193,10 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
}
}
 
-   if (dm_state->context)
+   if (dm_state->context) {
+   dm_enable_per_frame_crtc_master_sync(dm_state->context);
WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
+   }
 
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 725a29f70b88..270e84a210c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -674,6 +674,28 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
 }
 
+static void enable_timing_multisync(
+   struct dc *dc,
+   struct dc_state *ctx)
+{
+   int i = 0, multisync_count = 0;
+   int pipe_count = 

[PATCH 43/73] drm/amd/display: dal 3.1.16

[Harry Wentland]

From: Tony Cheng 

Change-Id: If2b7804a5074077c3581f53db337768877fffc98
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cdc63f273ca..74955f458fbb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.15"
+#define DC_VER "3.1.16"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 42/73] drm/amd/display: always call set output tf

[Harry Wentland]

From: Eric Yang 

Temporary solution to fix gamma adjustment not
working.

Change-Id: I1884bcee28f7d71cbd5f6edd56423f01c32107b1
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 73e7afb360b1..666c6c0f882a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2058,8 +2058,14 @@ static void program_all_pipe_in_tree(
 
if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
dc->hwss.set_input_transfer_func(pipe_ctx, 
pipe_ctx->plane_state);
-   dc->hwss.set_output_transfer_func(pipe_ctx, 
pipe_ctx->stream);
}
+
+   /*
+* TODO: This can be further optimized/cleaned up
+* Always call this for now since it does memcmp inside before
+* doing heavy calculation and programming
+*/
+   dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
}
 
if (dc->debug.sanity_checks) {
-- 
2.14.1

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[PATCH 03/73] drm/amd/display: fix AZ clock not enabled before program AZ endpoint

[Harry Wentland]

From: Charlene Liu 

Change-Id: Ie8683cbe4791557054eba856aee6e06c948fc1f0
Signed-off-by: Charlene Liu 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 --
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index d882adf746a5..81c40f8864db 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -348,29 +348,44 @@ static void set_audio_latency(
 
 void dce_aud_az_enable(struct audio *audio)
 {
+   struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = 
AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
-   if (get_reg_field_value(value,
+   set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-   AUDIO_ENABLED) != 1)
+   CLOCK_GATING_DISABLE);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
 
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
+   value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+
+   dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+   "\n\t= AUDIO:dce_aud_az_enable: index: %u  
data: 0x%x\n",
+   audio->inst, value);
 }
 
 void dce_aud_az_disable(struct audio *audio)
 {
uint32_t value;
+   struct dce_audio *aud = DCE_AUD(audio);
 
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
set_reg_field_value(value, 0,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
+   AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
+   set_reg_field_value(value, 0,
+   AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+   CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
+   value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+   dm_logger_write(CTX->logger, LOG_HW_AUDIO,
+   "\n\t= AUDIO:dce_aud_az_disable: index: %u  
data: 0x%x\n",
+   audio->inst, value);
 }
 
 void dce_aud_az_configure(
@@ -390,6 +405,11 @@ void dce_aud_az_configure(
bool is_ac3_supported = false;
union audio_sample_rates sample_rate;
uint32_t strlen = 0;
+   value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+   set_reg_field_value(value, 1,
+   AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+   CLOCK_GATING_DISABLE);
+   AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
/* Speaker Allocation */
/*
@@ -852,6 +872,7 @@ static bool dce_aud_endpoint_valid(struct audio *audio)
 void dce_aud_hw_init(
struct audio *audio)
 {
+   uint32_t value;
struct dce_audio *aud = DCE_AUD(audio);
 
/* we only need to program the following registers once, so we only do
@@ -863,6 +884,12 @@ void dce_aud_hw_init(
 * Suport R6 - 44.1khz
 * Suport R7 - 48khz
 */
+   /*disable clock gating before write to endpoint register*/
+   value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+   set_reg_field_value(value, 1,
+   AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+   CLOCK_GATING_DISABLE);
+   AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
AUDIO_RATE_CAPABILITIES, 0x70);
 
-- 
2.14.1

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[PATCH 15/73] drm/amd/display: Don't use dc_link in link_encoder

[Harry Wentland]

From: Andrew Jiang 

dc_link is at a higher level than link_encoder, and we only want
higher-level components to be able to access lower-level ones,
not the other way around.

Change-Id: I634b117b386938fb7ddba50c50484fadd54ad485
Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +++---
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 34 +++-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  5 +--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 46 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 ++
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  2 +-
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  3 +-
 10 files changed, 57 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a6a762a26fd2..3b394a5f1c66 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum 
signal_type signal)
else
dp_disable_link_phy_mst(link, signal);
} else
-   link->link_enc->funcs->disable_output(link->link_enc, signal, 
link);
+   link->link_enc->funcs->disable_output(link->link_enc, signal);
 }
 
 bool dp_active_dongle_validate_timing(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 9a33b471270a..f2902569be2e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -89,7 +89,7 @@ void dp_enable_link_phy(
 
if (dc_is_dp_sst_signal(signal)) {
if (signal == SIGNAL_TYPE_EDP) {
-   link->dc->hwss.edp_power_control(link->link_enc, true);
+   link->dc->hwss.edp_power_control(link, true);
link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
@@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum 
signal_type signal)
if (signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, false);
edp_receiver_ready_T9(link);
-   link->link_enc->funcs->disable_output(link->link_enc, signal, 
link);
-   link->dc->hwss.edp_power_control(link->link_enc, false);
+   link->link_enc->funcs->disable_output(link->link_enc, signal);
+   link->dc->hwss.edp_power_control(link, false);
} else
-   link->link_enc->funcs->disable_output(link->link_enc, signal, 
link);
+   link->link_enc->funcs->disable_output(link->link_enc, signal);
 
/* Clear current link setting.*/
memset(>cur_link_settings, 0,
@@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link,
 
link->link_enc->funcs->disable_output(
link->link_enc,
-   SIGNAL_TYPE_DISPLAY_PORT,
-   link);
+   SIGNAL_TYPE_DISPLAY_PORT);
 
/* Clear current link setting. */
memset(>cur_link_settings, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index fe88852b4774..bad70c6b3aad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init(
 
ASSERT(result == BP_RESULT_OK);
 
-   } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-   ctx->dc->hwss.edp_power_control(enc, true);
}
aux_initialize(enc110);
 
@@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output(
  */
 void dce110_link_encoder_disable_output(
struct link_encoder *enc,
-   enum signal_type signal,
-   struct dc_link *link)
+   enum signal_type signal)
 {
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
struct dc_context *ctx = enc110->base.ctx;
@@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output(
/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
return;
}
-   if (enc110->base.connector.id == CONNECTOR_ID_EDP)
-   ctx->dc->hwss.edp_backlight_control(link, false);
  

[PATCH 18/73] drm/amd/display: Add OPP DPG blank function

[Harry Wentland]

From: Eric Bernstein 

Added a function to blank data using OPP DPG.
Clean up code to prepare for pseudocode review with HW.

Change-Id: Iac5e99e1eb72b8dd74c244e8d06d54bae9ab3ce2
Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 62 +++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 45 +++--
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h  |  6 +++
 3 files changed, 51 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index a136f70b7a3c..71385a004f52 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,6 +38,24 @@
oppn10->base.ctx
 
 
+enum dpg_mode {
+   /* RGB colour block mode */
+   DPG_MODE_RGB_COLOUR_BLOCK,
+   /* YCbCr-601 colour block mode */
+   DPG_MODE_YCBCR_601_COLOUR_BLOCK,
+   /* YCbCr-709 colour block mode */
+   DPG_MODE_YCBCR_709_COLOUR_BLOCK,
+   /* Vertical bar mode */
+   DPG_MODE_VERTICAL_BAR,
+   /* Horizontal bar mode */
+   DPG_MODE_HORIZONTAL_BAR,
+   /* Single ramp mode */
+   DPG_MODE_RGB_SINGLE_RAMP,
+   /* Dual ramp mode */
+   DPG_MODE_RGB_DUAL_RAMP,
+   /* RGB XR BIAS mode */
+   DPG_MODE_RGB_XR_BIAS
+};
 
 /* FORMATTER /
 
@@ -47,7 +65,7 @@
  * 2) enable truncation
  * 3) HW remove 12bit FMT support for DCE11 power saving reason.
  */
-static void set_truncation(
+static void opp1_set_truncation(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
 {
@@ -57,7 +75,7 @@ static void set_truncation(
FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
 }
 
-static void set_spatial_dither(
+static void opp1_set_spatial_dither(
struct dcn10_opp *oppn10,
const struct bit_depth_reduction_params *params)
 {
@@ -136,14 +154,14 @@ static void set_spatial_dither(
FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void oppn10_program_bit_depth_reduction(
+static void opp1_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
 {
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 
-   set_truncation(oppn10, params);
-   set_spatial_dither(oppn10, params);
+   opp1_set_truncation(oppn10, params);
+   opp1_set_spatial_dither(oppn10, params);
/* TODO
 * set_temporal_dither(oppn10, params);
 */
@@ -156,7 +174,7 @@ static void oppn10_program_bit_depth_reduction(
  * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
  * 1: YCbCr 4:2:2
  */
-static void set_pixel_encoding(
+static void opp1_set_pixel_encoding(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
 {
@@ -186,7 +204,7 @@ static void set_pixel_encoding(
  * 7 for programable
  * 2) Enable clamp if Limited range requested
  */
-static void opp_set_clamping(
+static void opp1_set_clamping(
struct dcn10_opp *oppn10,
const struct clamping_and_pixel_encoding_params *params)
 {
@@ -224,7 +242,7 @@ static void opp_set_clamping(
 
 }
 
-static void oppn10_set_dyn_expansion(
+static void opp1_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
@@ -264,17 +282,17 @@ static void oppn10_set_dyn_expansion(
}
 }
 
-static void opp_program_clamping_and_pixel_encoding(
+static void opp1_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params)
 {
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 
-   opp_set_clamping(oppn10, params);
-   set_pixel_encoding(oppn10, params);
+   opp1_set_clamping(oppn10, params);
+   opp1_set_pixel_encoding(oppn10, params);
 }
 
-static void oppn10_program_fmt(
+static void opp1_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
@@ -286,20 +304,18 @@ static void oppn10_program_fmt(
 
/* dithering is affected by , hence should be
 * programmed afterwards */
-   oppn10_program_bit_depth_reduction(
+   opp1_program_bit_depth_reduction(
opp,
fmt_bit_depth);
 
-   opp_program_clamping_and_pixel_encoding(
+   opp1_program_clamping_and_pixel_encoding(
opp,
clamping);
 
return;
 }
 
-
-
-static void oppn10_set_stereo_polarity(
+static void opp1_set_stereo_polarity(
struct 

[PATCH 10/73] drm/amd/display: Only update dchub if hubbub is available

[Harry Wentland]

From: Yue Hin Lau 

Change-Id: Id3ccff0209ae76330eb346c4ffd3aa3b6bf1909b
Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f79871d1227d..ebb39b8c1551 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2509,7 +2509,8 @@ void dcn10_update_pending_status(struct pipe_ctx 
*pipe_ctx)
 
 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
 {
-   hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+   if (hws->ctx->dc->res_pool->hubbub != NULL)
+   hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
 }
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
-- 
2.14.1

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[PATCH 11/73] drm/amd/display: get remote dpcd caps for timing validation

[Harry Wentland]

From: Eric Yang 

Change-Id: Iebe803ec074af7648329af111217da2a50f8426c
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c|  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dc.h  |  1 +
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 28 +++-
 4 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index be9a182d6fb3..a6a762a26fd2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1869,7 +1869,7 @@ enum dc_status dc_link_validate_mode_timing(
const struct dc_crtc_timing *timing)
 {
uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
-   struct dc_dongle_caps *dongle_caps = 
>link_status.dpcd_caps->dongle_caps;
+   struct dc_dongle_caps *dongle_caps = >dpcd_caps.dongle_caps;
 
/* A hack to avoid failing any modes for EDID override feature on
 * topology change such as lower quality cable for DP or different 
dongle
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e97b42a03a2..cd87d85f1ce2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2132,7 +2132,7 @@ static void get_active_converter_info(
 
union dwnstream_port_caps_byte3_hdmi
hdmi_caps = {.raw = det_caps[3] };
-   union dwnstream_port_caps_byte1
+   union dwnstream_port_caps_byte2
hdmi_color_caps = {.raw = det_caps[2] };

link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
det_caps[1] * 25000;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 79e2ddbc3399..ee05b8ee3785 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1031,6 +1031,7 @@ struct dc_sink {
 
/* private to dc_sink.c */
struct kref refcount;
+
 };
 
 void dc_sink_retain(struct dc_sink *sink);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 77e2de69cca3..2726b02e006b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -255,7 +255,7 @@ enum dpcd_downstream_port_detailed_type {
DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 };
 
-union dwnstream_port_caps_byte1 {
+union dwnstream_port_caps_byte2 {
struct {
uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
uint8_t RESERVED:6;
@@ -298,6 +298,32 @@ union dwnstream_port_caps_byte3_hdmi {
 
 /*4-byte structure for detailed capabilities of a down-stream port
 (DP-to-TMDS converter).*/
+union dwnstream_portxcaps {
+   struct {
+   union dwnstream_port_caps_byte0 byte0;
+   unsigned char max_TMDS_clock;   //byte1
+   union dwnstream_port_caps_byte2 byte2;
+
+   union {
+   union dwnstream_port_caps_byte3_dvi byteDVI;
+   union dwnstream_port_caps_byte3_hdmi byteHDMI;
+   } byte3;
+   } bytes;
+
+   unsigned char raw[4];
+};
+
+union downstream_port {
+   struct {
+   unsigned char   present:1;
+   unsigned char   type:2;
+   unsigned char   format_conv:1;
+   unsigned char   detailed_caps:1;
+   unsigned char   reserved:3;
+   } bits;
+   unsigned char raw;
+};
+
 
 union sink_status {
struct {
-- 
2.14.1

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[PATCH 00/73] DC Linux Patches Nov 9, 2017

[Harry Wentland]

 * Whole bunch of Raven (DCN) work
 * Bunch of cleanups


Andrew Jiang (7):
  drm/amd/display: Don't use dc_link in link_encoder
  drm/amd/display: Report pitch_alignment for DCN
  drm/amd/display: Loosen plane_info and scaling_info checks
  drm/amd/display: Remove legacy unused workaround
  drm/amd/display: Add update flags in to determine surface update type
  drm/amd/display: Rename pitch_alignment to linear_pitch_alignment
  drm/amd/display: Add check update surfaces for stream wrapper

Arun Pandey (1):
  drm/amd/display: Added Opp and Diags Interface for P to I

Bhawanpreet Lakha (1):
  drm/amd/display: add flip_immediate to commit update for stream

Charlene Liu (2):
  drm/amd/display: fix AZ clock not enabled before program AZ endpoint
  drm/amd/display: Do post_update_surfaces on new state

Dmytro Laktyushkin (6):
  drm/amd/display: cache pwl params and scl_data to avoid extra
programming
  drm/amd/display: fix regamma programming
  drm/amd/display: fix uninitialized variable warning
  drm/amd/display: remove unnecessary waits in dcn10
  drm/amd/display: add warning on long reg_wait
  drm/amd/display: remove dcn10 wait on tg unlock

Eric Bernstein (3):
  drm/amd/display: Call ipp_program_bias_and_scale only if available
  drm/amd/display: Add OPP DPG blank function
  drm/amd/display: Remove unused OPP functions from interface

Eric Yang (4):
  drm/amd/display: get remote dpcd caps for timing validation
  drm/amd/display: fix MST link training fail division by 0
  drm/amd/display: always call set output tf
  drm/amd/display: combine output signal and signal

Harry Wentland (12):
  drm/amd/display: Both timing_sync and multisync need stream_count > 1
  drm/amd/display: Bunch of indentation cleanups in color stuff
  drm/amd/display: Fix some more color indentations
  drm/amd/display: Remove extra arr_points element
  drm/amd/display: Bunch more color indentation cleanups
  drm/amd/display: Remove unused register read in program_pwl
  drm/amd/display: A few more color indentation changes
  drm/amd/display: Fix formatting for null pointer dereference fix
  drm/amd/display: Move dc_stream interface to separate header
  drm/amd/display: Move dc_link interface to separate header
  drm/amd/display: Remove unnecessary dc_stream vtable
  drm/amd/display: Fix Linux after optimize frontend programming

Hersen Wu (1):
  drm/amd/display: send display_count msg so SMU can enter S0i2

Jerry (Fangzhi) Zuo (2):
  drm/amd/display: Miss register MST encoder cbs
  drm/amd/display: Check aux channel before MST resume

Ken Chalmers (2):
  drm/amd/display: use num_timing_generator instead of pipe_count
  drm/amd/display: fix dcn10_hubbub_wm_read_state

Leo (Sunpeng) Li (6):
  drm/amd/display: Fix warnings on S3 resume
  drm/amd/display: Remove dangling planes on dc commit state
  drm/amd/display: Change frontend/backend programming sequence
  drm/amd/display: Early return on stream programming failure
  drm/amd/display: Fix unused variable warning
  drm/amd/display: Fix use before initialize warning

Mikita Lipski (1):
  drm/amd/display: Multi display synchronization logic

Roman Li (2):
  drm/amd/display: use configurable FBC option in dm
  drm/amd/display: Fix unbalanced locking in surface apply

SivapiriyanKumarasamy (1):
  drm/amd/display: Add transfer function to dc_surface_update

Tony Cheng (8):
  drm/amd/display: dal 3.1.11
  drm/amd/display: dal 3.1.12
  drm/amd/display: dal 3.1.13
  drm/amd/display: dal 3.1.14
  drm/amd/display: dal 3.1.15
  drm/amd/display: dal 3.1.16
  drm/amd/display: fix plane update prior to stream enablement
  drm/amd/display: remove stream_func vtable

Yongqiang Sun (8):
  drm/amd/display: Enalbe blank data double buffer after mpc
disconnected.
  drm/amd/display: Add tg_init interface.
  drm/amd/display: Refactor disable front end pipes.
  drm/amd/display: Modified front end initiail in init_hw
  drm/amd/display: Fixed not set scaler bug.
  drm/amd/display: Apply work around for stutter.
  drm/amd/display: Optimize programming front end
  drm/amd/display: Optimize front end programming.

Yue Hin Lau (6):
  drm/amd/display: create new function prototype update_dchub for dcn
  drm/amd/display: function renaming for hubbub
  drm/amd/display: hubbub function flipping true and false
  drm/amd/display: Only update dchub if hubbub is available
  drm/amd/display: call set csc_default if enable adjustment is false
  drm/amd/display: renaming dpp function to follow naming convention

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 100 ++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |   4 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c|  12 +-
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 458 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  10 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |  11 +-
 

[PATCH 23/73] drm/amd/display: Refactor disable front end pipes.

[Harry Wentland]

From: Yongqiang Sun 

There are different code to disable front end, it is
difficult to debug and adding new process.
This refactor makes all disable front end call the same
functions.

Change-Id: Ia88b26851bcea426104a8dd9093b912d03424c9a
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  15 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 262 +++--
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   2 +-
 5 files changed, 154 insertions(+), 138 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 6d64a069648e..88a004cc2690 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1064,6 +1064,9 @@ bool dcn_validate_bandwidth(
hsplit_pipe->stream = NULL;
hsplit_pipe->top_pipe = NULL;
hsplit_pipe->bottom_pipe = NULL;
+   /* Clear plane_res and stream_res */
+   memset(_pipe->plane_res, 0, 
sizeof(hsplit_pipe->plane_res));
+   memset(_pipe->stream_res, 0, 
sizeof(hsplit_pipe->stream_res));
resource_build_scaling_params(pipe);
}
/* for now important to do this after pipe 
split for building e2e params */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6219dd49..16d645d6da25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -924,9 +924,11 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
post_surface_trace(dc);
 
for (i = 0; i < dc->res_pool->pipe_count; i++)
-   if (context->res_ctx.pipe_ctx[i].stream == NULL
-   || context->res_ctx.pipe_ctx[i].plane_state == 
NULL)
-   dc->hwss.power_down_front_end(dc, i);
+   if (context->res_ctx.pipe_ctx[i].stream == NULL ||
+   context->res_ctx.pipe_ctx[i].plane_state == NULL) {
+   context->res_ctx.pipe_ctx[i].pipe_idx = i;
+   dc->hwss.power_down_front_end(dc, 
>res_ctx.pipe_ctx[i]);
+   }
 
/* 3rd param should be true, temp w/a for RV*/
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -1300,8 +1302,11 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state)
continue;
 
-   if (!pipe_ctx->top_pipe && pipe_ctx->stream) {
-   struct dc_stream_status *stream_status = 
stream_get_status(context, pipe_ctx->stream);
+   if (!pipe_ctx->top_pipe &&
+   pipe_ctx->stream &&
+   pipe_ctx->stream == stream) {
+   struct dc_stream_status *stream_status =
+   stream_get_status(context, 
pipe_ctx->stream);
 
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, 
stream_status->plane_count, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4135de2d7203..a50e24f95ca9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1466,7 +1466,9 @@ static void disable_vga_and_power_gate_all_controllers(
enable_display_pipe_clock_gating(ctx,
true);
 
-   dc->hwss.power_down_front_end(dc, i);
+   dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
+   dc->hwss.power_down_front_end(dc,
+   >current_state->res_ctx.pipe_ctx[i]);
}
 }
 
@@ -1888,7 +1890,7 @@ static void dce110_reset_hw_ctx_wrap(
if (old_clk)
old_clk->funcs->cs_power_down(old_clk);
 
-   dc->hwss.power_down_front_end(dc, 
pipe_ctx_old->pipe_idx);
+   dc->hwss.power_down_front_end(dc, pipe_ctx_old);
 
pipe_ctx_old->stream = NULL;
}
@@ -2948,8 +2950,10 @@ static void dce110_apply_ctx_for_surface(
}
 }
 
-static void dce110_power_down_fe(struct dc *dc, int fe_idx)
+static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+  

[PATCH 29/73] drm/amd/display: fix uninitialized variable warning

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: Ida9244b5d9c44b8fc12c18a1bfb460e18778e04f
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index bbf93c94a977..d8929b31e5ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -188,7 +188,7 @@ static void dpp1_cm_set_regamma_pwl(
struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma 
mode)
 {
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-   uint32_t re_mode;
+   uint32_t re_mode = 0;
 
switch (mode) {
case OPP_REGAMMA_BYPASS:
-- 
2.14.1

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[PATCH 26/73] drm/amd/display: Fix some more color indentations

[Harry Wentland]

Change-Id: Ib7290f11372f258308a5e8be69f964e0407c54d6
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 11 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  7 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 35 +++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 44 --
 4 files changed, 36 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77fb1b54694b..1c7f22146bc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2119,6 +2119,7 @@ fill_stream_properties_from_drm_display_mode(struct 
dc_stream_state *stream,
 const struct drm_connector 
*connector)
 {
struct dc_crtc_timing *timing_out = >timing;
+   struct dc_transfer_func *tf = dc_create_transfer_func();
 
memset(timing_out, 0, sizeof(struct dc_crtc_timing));
 
@@ -2162,13 +2163,9 @@ fill_stream_properties_from_drm_display_mode(struct 
dc_stream_state *stream,
 
stream->output_color_space = get_output_color_space(timing_out);
 
-   {
-   struct dc_transfer_func *tf = dc_create_transfer_func();
-
-   tf->type = TF_TYPE_PREDEFINED;
-   tf->tf = TRANSFER_FUNCTION_SRGB;
-   stream->out_transfer_func = tf;
-   }
+   tf->type = TF_TYPE_PREDEFINED;
+   tf->tf = TRANSFER_FUNCTION_SRGB;
+   stream->out_transfer_func = tf;
 }
 
 static void fill_audio_info(struct audio_info *audio_info,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 16d645d6da25..7fe62beb2d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1337,10 +1337,9 @@ static void commit_planes_for_stream(struct dc *dc,
continue;
 
/* work around to program degamma regs for split pipe 
after set mode. */
-   if (srf_updates[i].in_transfer_func || 
(pipe_ctx->top_pipe &&
-   pipe_ctx->top_pipe->plane_state == 
pipe_ctx->plane_state))
-   dc->hwss.set_input_transfer_func(
-   pipe_ctx, 
pipe_ctx->plane_state);
+   if (srf_updates[i].in_transfer_func ||
+   (pipe_ctx->top_pipe && 
pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state))
+   dc->hwss.set_input_transfer_func(pipe_ctx, 
pipe_ctx->plane_state);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 81cf6c68588e..8d9a6b504046 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -257,9 +257,9 @@ static void build_prescale_params(struct 
ipp_prescale_params *prescale_params,
}
 }
 
-static bool dce110_set_input_transfer_func(
-   struct pipe_ctx *pipe_ctx,
-   const struct dc_plane_state *plane_state)
+static bool
+dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+  const struct dc_plane_state *plane_state)
 {
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
const struct dc_transfer_func *tf = NULL;
@@ -280,25 +280,19 @@ static bool dce110_set_input_transfer_func(
 
if (tf == NULL) {
/* Default case if no input transfer function specified */
-   ipp->funcs->ipp_set_degamma(ipp,
-   IPP_DEGAMMA_MODE_HW_sRGB);
+   ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
} else if (tf->type == TF_TYPE_PREDEFINED) {
switch (tf->tf) {
case TRANSFER_FUNCTION_SRGB:
-   ipp->funcs->ipp_set_degamma(ipp,
-   IPP_DEGAMMA_MODE_HW_sRGB);
+   ipp->funcs->ipp_set_degamma(ipp, 
IPP_DEGAMMA_MODE_HW_sRGB);
break;
case TRANSFER_FUNCTION_BT709:
-   ipp->funcs->ipp_set_degamma(ipp,
-   IPP_DEGAMMA_MODE_HW_xvYCC);
+   ipp->funcs->ipp_set_degamma(ipp, 
IPP_DEGAMMA_MODE_HW_xvYCC);
break;
case TRANSFER_FUNCTION_LINEAR:
-   ipp->funcs->ipp_set_degamma(ipp,
-   IPP_DEGAMMA_MODE_BYPASS);
+   ipp->funcs->ipp_set_degamma(ipp, 
IPP_DEGAMMA_MODE_BYPASS);
break;
 

[PATCH 08/73] drm/amd/display: use configurable FBC option in dm

[Harry Wentland]

From: Roman Li 

Replace ENABLE_FBC macro with config option CONFIG_DRM_AMD_DC_FBC
in dm. DC code has been already updated the same way.

Change-Id: I8c0e8deb6fe1387a7364822d12c2cc5beb888998
Signed-off-by: Roman Li 
Reviewed-by: Shirish Shankarappa 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index de901fdd53cc..77fb1b54694b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -344,7 +344,7 @@ static void hotplug_notify_work_func(struct work_struct 
*work)
drm_kms_helper_hotplug_event(dev);
 }
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 #include "dal_asic_id.h"
 /* Allocate memory for FBC compressed data  */
 /* TODO: Dynamic allocation */
@@ -422,7 +422,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
else
init_data.log_mask = DC_MIN_LOG_MASK;
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
if (adev->family == FAMILY_CZ)
amdgpu_dm_initialize_fbc(adev);
init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 6b81e124ea57..450379d684cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -72,7 +72,7 @@ struct irq_list_head {
struct work_struct work;
 };
 
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
 struct dm_comressor_info {
void *cpu_addr;
struct amdgpu_bo *bo_ptr;
@@ -142,7 +142,7 @@ struct amdgpu_display_manager {
 * Caches device atomic state for suspend/resume
 */
struct drm_atomic_state *cached_state;
-#ifdef ENABLE_FBC
+#if defined(CONFIG_DRM_AMD_DC_FBC)
struct dm_comressor_info compressor;
 #endif
 };
-- 
2.14.1

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[PATCH 22/73] drm/amd/display: dal 3.1.14

[Harry Wentland]

From: Tony Cheng 

Change-Id: I87463dfba34a246c9ec5f2a0cf417b9943683f7e
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index fbafc8b93a85..86a9c927a312 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.13"
+#define DC_VER "3.1.14"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 14/73] drm/amd/display: Both timing_sync and multisync need stream_count > 1

[Harry Wentland]

Previous code threw a warning about misleading indentation

Change-Id: I93e5998448e2c80d1b084231a3ef575bc1a0dfdd
Signed-off-by: Harry Wentland 
Reviewed-by: Mikita Lipski 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f3fd062bcdd2..6219dd49 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -874,9 +874,10 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
}
result = dc->hwss.apply_ctx_to_hw(dc, context);
 
-   if (context->stream_count > 1)
+   if (context->stream_count > 1) {
enable_timing_multisync(dc, context);
program_timing_sync(dc, context);
+   }
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-- 
2.14.1

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[PATCH 25/73] drm/amd/display: Bunch of indentation cleanups in color stuff

[Harry Wentland]

Trying to align with kernel coding style and make it a bit more
readable.

Change-Id: I7d4a06e221509a1b063c539223add2b73462a599
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 170 -
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  10 +-
 2 files changed, 68 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index ae32af31eff1..4ff874a43f7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1260,124 +1260,87 @@ static void program_pwl(
REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
 }
 
-static void regamma_config_regions_and_segments(
-   struct dce_transform *xfm_dce,
-   const struct pwl_params *params)
+static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
+   const struct pwl_params *params)
 {
const struct gamma_curve *curve;
 
-   {
-   REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
-   REGAMMA_CNTLA_EXP_REGION_START, 
params->arr_points[0].custom_float_x,
-   REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
-   }
-   {
-   REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
-   REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, 
params->arr_points[0].custom_float_slope);
-
-   }
-   {
-   REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
-   REGAMMA_CNTLA_EXP_REGION_END, 
params->arr_points[1].custom_float_x);
-   }
-   {
-   REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
-   REGAMMA_CNTLA_EXP_REGION_END_BASE, 
params->arr_points[1].custom_float_y,
-   REGAMMA_CNTLA_EXP_REGION_END_SLOPE, 
params->arr_points[2].custom_float_slope);
-   }
-
-   curve = params->arr_curve_points;
+   REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
+ REGAMMA_CNTLA_EXP_REGION_START, 
params->arr_points[0].custom_float_x,
+ REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
 
-   {
-   REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
-   REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-   REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, 
curve[0].segments_num,
-   REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-   REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, 
curve[1].segments_num);
-   }
+   REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
+   REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, 
params->arr_points[0].custom_float_slope);
 
-   curve += 2;
+   REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
+   REGAMMA_CNTLA_EXP_REGION_END, 
params->arr_points[1].custom_float_x);
 
-   {
-   REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
-   REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-   REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, 
curve[0].segments_num,
-   REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-   REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, 
curve[1].segments_num);
+   REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
+ REGAMMA_CNTLA_EXP_REGION_END_BASE, 
params->arr_points[1].custom_float_y,
+ REGAMMA_CNTLA_EXP_REGION_END_SLOPE, 
params->arr_points[2].custom_float_slope);
 
-   }
+   curve = params->arr_curve_points;
 
+   REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, 
curve[1].segments_num);
curve += 2;
 
-   {
-   REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
-   REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-   REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, 
curve[0].segments_num,
-   REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-   REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, 
curve[1].segments_num);
-
-   }
-
+   REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
+ REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, 
curve[1].segments_num);
curve += 2;
 
-   {
-   REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
-   

[PATCH 07/73] drm/amd/display: dal 3.1.11

[Harry Wentland]

From: Tony Cheng 

Change-Id: Iec51322a9e35f8ad8729168df7e6c88d42799e8c
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index a51a9c748c1a..79e2ddbc3399 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.10"
+#define DC_VER "3.1.11"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 19/73] drm/amd/display: call set csc_default if enable adjustment is false

[Harry Wentland]

From: Yue Hin Lau 

Change-Id: Id7507b6af4ab877fc10c5549985ac2633fe3f124
Signed-off-by: Yue Hin Lau 
Reviewed-by: Eric Bernstein 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   | 6 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 8b894ebc4e17..4355cc21b111 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1381,7 +1381,7 @@ void dpp1_cm_set_output_csc_adjustment(
 
 void dpp1_cm_set_output_csc_default(
struct dpp *dpp_base,
-   const struct default_adjustment *default_adjust);
+   enum dc_color_space colorspace);
 
 void dpp1_cm_set_gamut_remap(
struct dpp *dpp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 9cb44c90e746..bb430c0ec1b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -225,14 +225,13 @@ void dpp1_cm_set_gamut_remap(
 
 void dpp1_cm_set_output_csc_default(
struct dpp *dpp_base,
-   const struct default_adjustment *default_adjust)
+   enum dc_color_space colorspace)
 {
 
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t ocsc_mode = 0;
 
-   if (default_adjust != NULL) {
-   switch (default_adjust->out_color_space) {
+   switch (colorspace) {
case COLOR_SPACE_SRGB:
case COLOR_SPACE_2020_RGB_FULLRANGE:
ocsc_mode = 0;
@@ -253,7 +252,6 @@ void dpp1_cm_set_output_csc_default(
case COLOR_SPACE_UNKNOWN:
default:
break;
-   }
}
 
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7579e51761cb..81192d68ce65 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1608,6 +1608,8 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
tbl_entry.color_space = color_space;
//tbl_entry.regval = matrix;

pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, 
_entry);
+   } else {
+   
pipe_ctx->plane_res.dpp->funcs->opp_set_csc_default(pipe_ctx->plane_res.dpp, 
colorspace);
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 71078d184289..3b1486c3d05c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -64,7 +64,7 @@ struct dpp_funcs {
 
void (*opp_set_csc_default)(
struct dpp *dpp,
-   const struct default_adjustment *default_adjust);
+   enum dc_color_space colorspace);
 
void (*opp_set_csc_adjustment)(
struct dpp *dpp,
-- 
2.14.1

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[PATCH 16/73] drm/amd/display: cache pwl params and scl_data to avoid extra programming

[Harry Wentland]

From: Dmytro Laktyushkin 

This saves us about 5000 reg writes per full update. This translates to about
4 writes over the course of single eDP bootup.

Change-Id: If8e0c7bac744d8a3e2c56271c09453152025ccc8
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 41 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  6 ++--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  3 ++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 10 +++---
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h|  8 ++---
 5 files changed, 30 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index c5f4d5caf976..e9cf9d1514eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -178,32 +178,14 @@ void dpp_reset(struct dpp *dpp_base)
dpp->filter_h = NULL;
dpp->filter_v = NULL;
 
-   /* set boundary mode to 0 */
-   REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
+   memset(>scl_data, 0, sizeof(dpp->scl_data));
+   memset(>pwl_data, 0, sizeof(dpp->pwl_data));
 }
 
 
 
 static void dpp1_cm_set_regamma_pwl(
-   struct dpp *dpp_base, const struct pwl_params *params)
-{
-   struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-
-   dpp1_cm_power_on_regamma_lut(dpp_base, true);
-   dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
-
-   if (dpp->is_write_to_ram_a_safe)
-   dpp1_cm_program_regamma_luta_settings(dpp_base, params);
-   else
-   dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
-
-   dpp1_cm_program_regamma_lut(
-   dpp_base, params->rgb_resulted, params->hw_points_num);
-}
-
-static void dpp1_cm_set_regamma_mode(
-   struct dpp *dpp_base,
-   enum opp_regamma mode)
+   struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma 
mode)
 {
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t re_mode = 0;
@@ -221,13 +203,27 @@ static void dpp1_cm_set_regamma_mode(
re_mode = 2;
break;
case OPP_REGAMMA_USER:
+   if (memcmp(>pwl_data, params, sizeof(*params)) == 0)
+   return;
+
+   dpp1_cm_power_on_regamma_lut(dpp_base, true);
+   dpp1_cm_configure_regamma_lut(dpp_base, 
dpp->is_write_to_ram_a_safe);
+
+   if (dpp->is_write_to_ram_a_safe)
+   dpp1_cm_program_regamma_luta_settings(dpp_base, params);
+   else
+   dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
+
+   dpp1_cm_program_regamma_lut(
+   dpp_base, params->rgb_resulted, 
params->hw_points_num);
+   dpp->pwl_data = *params;
+
re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
break;
default:
break;
}
-
REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
REG_UPDATE_2(OBUF_CONTROL,
OBUF_BYPASS, obuf_bypass,
@@ -454,7 +450,6 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.opp_program_regamma_lutb_settings = 
dpp1_cm_program_regamma_lutb_settings,
.opp_program_regamma_luta_settings = 
dpp1_cm_program_regamma_luta_settings,
.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
-   .opp_set_regamma_mode = dpp1_cm_set_regamma_mode,
.ipp_program_bias_and_scale = dpp1_program_bias_and_scale,
.ipp_set_degamma = dpp1_set_degamma,
.ipp_program_input_lut  = dpp1_program_input_lut,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 880e366568a3..8b894ebc4e17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -54,7 +54,6 @@
SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI(DSCL_AUTOCAL, DSCL, id), \
SRI(SCL_BLACK_OFFSET, DSCL, id), \
-   SRI(DSCL_CONTROL, DSCL, id), \
SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
@@ -194,7 +193,6 @@
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
-   TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\

[PATCH 24/73] drm/amd/display: fix MST link training fail division by 0

[Harry Wentland]

From: Eric Yang 

When link training fail in MST case, we will divide by 0
when calculating avg_time_slots_per_mtp, so we cannot
proceed.

Change-Id: Iae7aef320deb3c204f3450544c36f89b075a5c21
Signed-off-by: Eric Yang 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 3b394a5f1c66..7b0e43c0685c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2386,9 +2386,11 @@ void core_link_enable_stream(
 
/* Abort stream enable *unless* the failure was due to
 * DP link training - some DP monitors will recover and
-* show the stream anyway.
+* show the stream anyway. But MST displays can't 
proceed
+* without link training.
 */
-   if (status != DC_FAIL_DP_LINK_TRAINING) {
+   if (status != DC_FAIL_DP_LINK_TRAINING ||
+   pipe_ctx->stream->signal == 
SIGNAL_TYPE_DISPLAY_PORT_MST) {
BREAK_TO_DEBUGGER();
return;
}
-- 
2.14.1

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[PATCH 09/73] drm/amd/display: Call ipp_program_bias_and_scale only if available

[Harry Wentland]

From: Eric Bernstein 

Also move some register definitions to common DCN regs.

Change-Id: I6da468797abb0662e144aff073c62ab6a3ad430e
Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 16 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c|  3 ++-
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 3a6ebd14eea2..880e366568a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -73,6 +73,9 @@
SRI(RECOUT_START, DSCL, id), \
SRI(RECOUT_SIZE, DSCL, id), \
SRI(OBUF_CONTROL, DSCL, id), \
+   SRI(CM_ICSC_CONTROL, CM, id), \
+   SRI(CM_ICSC_C11_C12, CM, id), \
+   SRI(CM_ICSC_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -124,9 +127,6 @@
SRI(CM_OCSC_CONTROL, CM, id), \
SRI(CM_OCSC_C11_C12, CM, id), \
SRI(CM_OCSC_C33_C34, CM, id), \
-   SRI(CM_ICSC_CONTROL, CM, id), \
-   SRI(CM_ICSC_C11_C12, CM, id), \
-   SRI(CM_ICSC_C33_C34, CM, id), \
SRI(CM_BNS_VALUES_R, CM, id), \
SRI(CM_BNS_VALUES_G, CM, id), \
SRI(CM_BNS_VALUES_B, CM, id), \
@@ -239,6 +239,11 @@
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
+   TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
+   TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
+   TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
+   TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
+   TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, 
mask_sh), \
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, 
CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, 
mask_sh), \
@@ -327,11 +332,6 @@
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
-   TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
-   TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
-   TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
-   TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
-   TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0bdf06969c83..f79871d1227d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1903,7 +1903,8 @@ static void update_dchubp_dpp(
 
//set scale and bias registers
build_prescale_params(_params, plane_state);
-   dpp->funcs->ipp_program_bias_and_scale(dpp, _params);
+   if (dpp->funcs->ipp_program_bias_and_scale)
+   dpp->funcs->ipp_program_bias_and_scale(dpp, _params);
 
mpcc_cfg.dpp_id = hubp->inst;
mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
-- 
2.14.1

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[PATCH 13/73] drm/amd/display: Add tg_init interface.

[Harry Wentland]

From: Yongqiang Sun 

Clear OPTC underflow status when init_hw.

Change-Id: I96953ee2d842a53ee343da88cffbef1eac2df95b
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |  2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 10 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h  |  2 ++
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ebb39b8c1551..dc37551399ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -742,6 +742,8 @@ static void dcn10_init_hw(struct dc *dc)
hwss_wait_for_blank_complete(tg);
 
dcn10_power_down_fe(dc, i);
+
+   tg->funcs->tg_init(tg);
}
 
for (i = 0; i < dc->res_pool->audio_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 5d1edb017b1c..819c4edd77a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1213,6 +1213,13 @@ void tgn10_read_otg_state(struct dcn10_timing_generator 
*tgn10,
OPTC_UNDERFLOW_OCCURRED_STATUS, 
>underflow_occurred_status);
 }
 
+static void tgn10_tg_init(struct timing_generator *tg)
+{
+   struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+   tgn10_set_blank_data_double_buffer(tg, true);
+   REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
+}
 
 static const struct timing_generator_funcs dcn10_tg_funcs = {
.validate_timing = tgn10_validate_timing,
@@ -1243,7 +1250,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs 
= {
.set_test_pattern = tgn10_set_test_pattern,
.program_stereo = tgn10_program_stereo,
.is_stereo_left_eye = tgn10_is_stereo_left_eye,
-   .set_blank_data_double_buffer = 
tgn10_set_blank_data_double_buffer
+   .set_blank_data_double_buffer = 
tgn10_set_blank_data_double_buffer,
+   .tg_init = tgn10_tg_init,
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 395820606013..bb1cbfdc3554 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -210,6 +210,7 @@ struct dcn_tg_registers {
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, 
mask_sh),\
+   SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, 
mask_sh),\
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
@@ -330,6 +331,7 @@ struct dcn_tg_registers {
type OPTC_SRC_SEL;\
type OPTC_SEG0_SRC_SEL;\
type OPTC_UNDERFLOW_OCCURRED_STATUS;\
+   type OPTC_UNDERFLOW_CLEAR;\
type OPPBUF_ACTIVE_WIDTH;\
type OPPBUF_3D_VACT_SPACE1_SIZE;\
type VTG0_ENABLE;\
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 83f0b1d49e8b..f77dca87cbbc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -184,6 +184,8 @@ struct timing_generator_funcs {
bool (*is_stereo_left_eye)(struct timing_generator *tg);
 
void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool 
enable);
+
+   void (*tg_init)(struct timing_generator *tg);
 };
 
 #endif
-- 
2.14.1

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[PATCH 02/73] drm/amd/display: create new function prototype update_dchub for dcn

[Harry Wentland]

From: Yue Hin Lau 

dcn version of update_dchub now uses hubbub instead of hwseq

Change-Id: I6335897c721870cf023346dc52d65071a2f1cf8a
Signed-off-by: Yue Hin Lau 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3a2457f8f2d1..ced6c41876a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2493,7 +2493,10 @@ void dcn10_update_pending_status(struct pipe_ctx 
*pipe_ctx)
}
 }
 
-
+void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+{
+   hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+}
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
@@ -2503,6 +2506,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
.set_plane_config = set_plane_config,
.update_plane_addr = dcn10_update_plane_addr,
+   .update_dchub = dcn10_update_dchub,
.update_pending_status = dcn10_update_pending_status,
.set_input_transfer_func = dcn10_set_input_transfer_func,
.set_output_transfer_func = dcn10_set_output_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 701ed09d5bba..2e6122c4670a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1459,7 +1459,7 @@ static bool construct(
pool->base.hubbub = dcn10_hubbub_create(ctx);
if (pool->base.hubbub == NULL) {
BREAK_TO_DEBUGGER();
-   dm_error("DC: failed to create mpc!\n");
+   dm_error("DC: failed to create hubbub!\n");
goto fail;
}
 
-- 
2.14.1

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[PATCH 12/73] drm/amd/display: Enalbe blank data double buffer after mpc disconnected.

[Harry Wentland]

From: Yongqiang Sun 

Change-Id: I60d84f57d93870769fdb2d8f1e870121c2a28f15
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 19 ++-
 .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h  |  2 ++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index c178cc0bd426..5d1edb017b1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -290,6 +290,16 @@ static void tgn10_program_timing(
 
 }
 
+static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, 
bool enable)
+{
+   struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+   uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
+
+   REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+   OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 
blank_data_double_buffer_enable);
+}
+
 /**
  * unblank_crtc
  * Call ASIC Control Object to UnBlank CRTC.
@@ -306,8 +316,7 @@ static void tgn10_unblank_crtc(struct timing_generator *tg)
 * this check will be removed.
 */
if (vertical_interrupt_enable)
-   REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-   OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1);
+   tgn10_set_blank_data_double_buffer(tg, true);
 
REG_UPDATE_2(OTG_BLANK_CONTROL,
OTG_BLANK_DATA_EN, 0,
@@ -334,8 +343,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg)
OTG_BLANK_DATA_EN, 1,
1, 10);
 
-   REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-   OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
+   tgn10_set_blank_data_double_buffer(tg, false);
 }
 
 static void tgn10_set_blank(struct timing_generator *tg,
@@ -1234,7 +1242,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs 
= {
.set_static_screen_control = tgn10_set_static_screen_control,
.set_test_pattern = tgn10_set_test_pattern,
.program_stereo = tgn10_program_stereo,
-   .is_stereo_left_eye = tgn10_is_stereo_left_eye
+   .is_stereo_left_eye = tgn10_is_stereo_left_eye,
+   .set_blank_data_double_buffer = 
tgn10_set_blank_data_double_buffer
 };
 
 void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 75f7a01b9175..83f0b1d49e8b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -182,6 +182,8 @@ struct timing_generator_funcs {
void (*program_stereo)(struct timing_generator *tg,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags 
*flags);
bool (*is_stereo_left_eye)(struct timing_generator *tg);
+
+   void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool 
enable);
 };
 
 #endif
-- 
2.14.1

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[PATCH 06/73] drm/amd/display: hubbub function flipping true and false

[Harry Wentland]

From: Yue Hin Lau 

no logic change

Change-Id: I31bdbba1abeb64d54e385456b58839160b1e188b
Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c   | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index b1c9ba241ba4..23c4573f7a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -139,7 +139,7 @@ bool hubbub1_verify_allow_pstate_change_high(
"pstate took longer than 
expected ~%dus\n",
i);
 
-   return false;
+   return true;
}
if (max_sampled_pstate_wait_us < i)
max_sampled_pstate_wait_us = i;
@@ -159,7 +159,7 @@ bool hubbub1_verify_allow_pstate_change_high(
"pstate TEST_DEBUG_DATA: 0x%X\n",
debug_data);
 
-   return true;
+   return false;
 }
 
 static uint32_t convert_and_clamp(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e2dc834e89d3..0bdf06969c83 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -548,7 +548,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
static bool should_log_hw_state; /* prevent hw state log by default */
 
-   if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
+   if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
if (should_log_hw_state) {
dcn10_log_hw_state(dc);
}
-- 
2.14.1

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[PATCH 05/73] drm/amd/display: Do post_update_surfaces on new state

[Harry Wentland]

From: Charlene Liu 

Change-Id: I98a09a622bbcf92e52377eb5eb14970bc604adc2
Signed-off-by: Charlene Liu 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 270e84a210c8..f3fd062bcdd2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1427,10 +1427,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
stream_update,
update_type,
context);
-
-   if (update_type >= UPDATE_TYPE_FULL)
-   dc_post_update_surfaces_to_stream(dc);
-
+   /*update current_State*/
if (dc->current_state != context) {
 
struct dc_state *old = dc->current_state;
@@ -1439,6 +1436,9 @@ void dc_commit_updates_for_stream(struct dc *dc,
dc_release_state(old);
 
}
+   /*let's use current_state to update watermark etc*/
+   if (update_type >= UPDATE_TYPE_FULL)
+   dc_post_update_surfaces_to_stream(dc);
 
return;
 
-- 
2.14.1

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[PATCH 21/73] drm/amd/display: renaming dpp function to follow naming convention

[Harry Wentland]

From: Yue Hin Lau 

Change-Id: I01d8cc3095891bc44dcfb319729975b3dad6510e
Signed-off-by: Yue Hin Lau 
Reviewed-by: Yuehin Lau 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 28 ++---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 29 +++---
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h| 28 ++---
 3 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index e9cf9d1514eb..21eba82aba97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -442,20 +442,20 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
.dpp_get_optimal_number_of_taps = 
dpp_get_optimal_number_of_taps,
.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
-   .opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
-   .opp_set_csc_default = dpp1_cm_set_output_csc_default,
-   .opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
-   .opp_program_regamma_lut = dpp1_cm_program_regamma_lut,
-   .opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
-   .opp_program_regamma_lutb_settings = 
dpp1_cm_program_regamma_lutb_settings,
-   .opp_program_regamma_luta_settings = 
dpp1_cm_program_regamma_luta_settings,
-   .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
-   .ipp_program_bias_and_scale = dpp1_program_bias_and_scale,
-   .ipp_set_degamma = dpp1_set_degamma,
-   .ipp_program_input_lut  = dpp1_program_input_lut,
-   .ipp_program_degamma_pwl= dpp1_set_degamma_pwl,
-   .ipp_setup  = dpp1_cnv_setup,
-   .ipp_full_bypass= dpp1_full_bypass,
+   .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
+   .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
+   .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
+   .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
+   .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
+   .dpp_program_regamma_lutb_settings = 
dpp1_cm_program_regamma_lutb_settings,
+   .dpp_program_regamma_luta_settings = 
dpp1_cm_program_regamma_luta_settings,
+   .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
+   .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
+   .dpp_set_degamma = dpp1_set_degamma,
+   .dpp_program_input_lut  = dpp1_program_input_lut,
+   .dpp_program_degamma_pwl= dpp1_set_degamma_pwl,
+   .dpp_setup  = dpp1_cnv_setup,
+   .dpp_full_bypass= dpp1_full_bypass,
.set_cursor_attributes = dpp1_set_cursor_attributes,
.set_cursor_position = dpp1_set_cursor_position,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 81192d68ce65..2496a54c998d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -869,23 +869,23 @@ static bool dcn10_set_input_transfer_func(
tf = plane_state->in_transfer_func;
 
if (plane_state->gamma_correction && dce_use_lut(plane_state))
-   dpp_base->funcs->ipp_program_input_lut(dpp_base,
+   dpp_base->funcs->dpp_program_input_lut(dpp_base,
plane_state->gamma_correction);
 
if (tf == NULL)
-   dpp_base->funcs->ipp_set_degamma(dpp_base, 
IPP_DEGAMMA_MODE_BYPASS);
+   dpp_base->funcs->dpp_set_degamma(dpp_base, 
IPP_DEGAMMA_MODE_BYPASS);
else if (tf->type == TF_TYPE_PREDEFINED) {
switch (tf->tf) {
case TRANSFER_FUNCTION_SRGB:
-   dpp_base->funcs->ipp_set_degamma(dpp_base,
+   dpp_base->funcs->dpp_set_degamma(dpp_base,
IPP_DEGAMMA_MODE_HW_sRGB);
break;
case TRANSFER_FUNCTION_BT709:
-   dpp_base->funcs->ipp_set_degamma(dpp_base,
+   dpp_base->funcs->dpp_set_degamma(dpp_base,
IPP_DEGAMMA_MODE_HW_xvYCC);
break;
case TRANSFER_FUNCTION_LINEAR:
-   dpp_base->funcs->ipp_set_degamma(dpp_base,
+   dpp_base->funcs->dpp_set_degamma(dpp_base,
  

Re: [PATCH] amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check

[Harry Wentland]

On 2017-11-09 12:38 PM, Michel Dänzer wrote:
> From: Michel Dänzer 
> 
> The atomic_check hook is expected to fail in some cases, e.g. if the
> modeset operation requested by userspace cannot be performed, so it must
> not spam dmesg on failure.
> 
> Fixes spurious
> 
>  [drm:amdgpu_dm_atomic_check [amdgpu]] *ERROR* Atomic state validation failed 
> with error :-35 !
> 
> error messages on DPMS off with CONFIG_DEBUG_WW_MUTEX_SLOWPATH enabled.
> 
> While we're at it, fix up the existing DRM_DEBUG_DRIVER strings.
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index ccfbf14c0f09..ed8b7524b741 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4691,10 +4691,8 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> *dev,
>   bool lock_and_validation_needed = false;
>  
>   ret = drm_atomic_helper_check_modeset(dev, state);
> - if (ret) {
> - DRM_ERROR("Atomic state validation failed with error :%d !\n", 
> ret);
> - return ret;
> - }
> + if (ret)
> + goto fail;
>  
>   /*
>* legacy_cursor_update should be made false for SoC's having
> @@ -4811,11 +4809,11 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> *dev,
>  
>  fail:
>   if (ret == -EDEADLK)
> - DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
> + DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
>   else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
> - DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
> + DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
>   else
> - DRM_ERROR("Atomic check failed with err: %d \n", ret);
> + DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
>  
>   return ret;
>  }
> 
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Re: [PATCH 0/7] *** GPU recover V3 ***

[Alex Deucher]

On Thu, Nov 9, 2017 at 4:35 AM, Julien Isorce  wrote:
> Hi Monk.
>
> I am interested on this. Currently when a "ring X stalled for more than N
> sec" happens it usually goes into the gpu reset routine.
> Does it always cause the vram to be lost ? Could you explain what happens if
> the vram remains lost ?

It means the contents of vram are gone or unreliable.  In that case
applications need to re-initialize all of their buffers before
submitting any work.  You really need to add GL_robustness support to
any applications you care about.  Whether vram is lost or not depends
on the reset method and the asic.  E.g., soft reset of a specific
engine won't cause a loss of vram, but a full adapter reset or an FLR
may.

>
> I am asking this because I experienced some recurrent gpu reset that are
> marked succeeded from the log but fail in the "resume" step.
> I would not be interested in this if it would always leave a chance to the
> user to cleanly reboot the machine.
>
> The issue is that it can require a hard reboot without kernel panic and
> without keeping the keyboard responding to magic keys.
> Are those patches trying to address this issue ?
>
> Note that here "issue" is not referring to the root cause of a ring X
> stalled and it is also not referring to why "resume" step fails.

There were a few issues that caused problems with GPU reset.  The
biggest was that the GPU scheduler deadlocked in certain cases so if
you got a GPU hang, the driver locked up.  That should mostly be
straightened out at this point.  I think there may still be some
deadlocks in the modesetting code after a reset.  Once that is sorted,
it will come down to fine tuning the actual reset sequences.  Full
adapter resets are the easiest to get working reliably (and are
already implemented in the driver), but also the most destructive.

Alex

>
> Thx a lot
> Julien
>
>
> On 30 October 2017 at 04:15, Monk Liu  wrote:
>>
>> *** job skipping logic in scheduler part is re-implemented  ***
>>
>> Monk Liu (7):
>>   amd/scheduler:imple job skip feature(v3)
>>   drm/amdgpu:implement new GPU recover(v3)
>>   drm/amdgpu:cleanup in_sriov_reset and lock_reset
>>   drm/amdgpu:cleanup ucode_init_bo
>>   drm/amdgpu:block kms open during gpu_reset
>>   drm/amdgpu/sriov:fix memory leak in psp_load_fw
>>   drm/amdgpu:fix random missing of FLR NOTIFY
>>
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   9 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 311
>> --
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c |  10 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   |   2 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  18 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   3 +
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  22 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   4 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |   2 -
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |   2 -
>>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |   6 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   6 +-
>>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  16 +-
>>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c |   2 +-
>>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  39 ++--
>>  15 files changed, 220 insertions(+), 232 deletions(-)
>>
>> --
>> 2.7.4
>>
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>
>
>
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Re: [PATCH 7/7] drm/ttm: optimize ttm_mem_evict_first v2

[Michel Dänzer]

On 09/11/17 09:59 AM, Christian König wrote:
> Deleted BOs with the same reservation object can be reaped even if they
> can't be reserved.
> 
> v2: rebase and we still need to remove/add the BO from/to the LRU.
> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/ttm/ttm_bo.c | 39 +++
>  1 file changed, 31 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index 50a678b504f3..6545c4344684 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -735,20 +735,37 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object 
> *bo,
>  EXPORT_SYMBOL(ttm_bo_eviction_valuable);
>  
>  static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
> - uint32_t mem_type,
> - const struct ttm_place *place,
> - bool interruptible,
> - bool no_wait_gpu)
> +struct reservation_object *resv,
> +uint32_t mem_type,
> +const struct ttm_place *place,
> +bool interruptible,
> +bool no_wait_gpu)
>  {
>   struct ttm_bo_global *glob = bdev->glob;
>   struct ttm_mem_type_manager *man = >man[mem_type];
>   struct ttm_buffer_object *bo;
>   int ret = -EBUSY;
> + bool locked;
>   unsigned i;
>  
>   spin_lock(>lru_lock);
>   for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
>   list_for_each_entry(bo, >lru[i], lru) {
> + if (bo->resv == resv) {
> + if (list_empty(>ddestroy))
> + continue;
> +
> + if (place &&
> + !bdev->driver->eviction_valuable(bo, place))
> + continue;
> +
> + ttm_bo_del_from_lru(bo);

Is this necessary, despite the existing ttm_bo_del_from_lru call before
unlocking the LRU lock? If yes, why isn't this necessary in the bo->resv
!= resv case?


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Re: [PATCH] amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check

[Alex Deucher]

On Thu, Nov 9, 2017 at 12:38 PM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> The atomic_check hook is expected to fail in some cases, e.g. if the
> modeset operation requested by userspace cannot be performed, so it must
> not spam dmesg on failure.
>
> Fixes spurious
>
>  [drm:amdgpu_dm_atomic_check [amdgpu]] *ERROR* Atomic state validation failed 
> with error :-35 !
>
> error messages on DPMS off with CONFIG_DEBUG_WW_MUTEX_SLOWPATH enabled.
>
> While we're at it, fix up the existing DRM_DEBUG_DRIVER strings.
>
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index ccfbf14c0f09..ed8b7524b741 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4691,10 +4691,8 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> *dev,
> bool lock_and_validation_needed = false;
>
> ret = drm_atomic_helper_check_modeset(dev, state);
> -   if (ret) {
> -   DRM_ERROR("Atomic state validation failed with error :%d 
> !\n", ret);
> -   return ret;
> -   }
> +   if (ret)
> +   goto fail;
>
> /*
>  * legacy_cursor_update should be made false for SoC's having
> @@ -4811,11 +4809,11 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> *dev,
>
>  fail:
> if (ret == -EDEADLK)
> -   DRM_DEBUG_DRIVER("Atomic check stopped due to to 
> deadlock.\n");
> +   DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
> else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
> -   DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
> +   DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
> else
> -   DRM_ERROR("Atomic check failed with err: %d \n", ret);
> +   DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
>
> return ret;
>  }
> --
> 2.15.0
>
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Re: [PATCH] drm/amd/powerplay: fix copy-n-paste error on vddci_buf index

[Alex Deucher]

On Thu, Nov 9, 2017 at 6:35 AM, Colin King  wrote:
> From: Colin Ian King 
>
> The index to vddci_buf is using profile->ucElbVDDC_Num rather
> than profile->ucElbVDDCI_Num; this looks like a copy-n-paste
> error from previous code for the vddc_buf array and I'm pretty
> sure this is incorrect. Fix this by using the correct variable.
>
> Detected by CoverityScan, CID#1457172 ("Copy-paste error")
>
> Fixes: 970d9804b00d ("drm/amd/powerplay: Add support functions for CI to 
> ppatomctrl.c")
> Signed-off-by: Colin Ian King 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
> index a129bc5b1844..c6febbf0bf69 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
> @@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct 
> pp_hwmgr *hwmgr,
> if (vddci_id_buf[i] == virtual_voltage_id) {
> for (j = 0; j < 
> profile->ucLeakageBinNum; j++) {
> if (efuse_voltage_id <= 
> leakage_bin[j]) {
> -   *vddci = vddci_buf[j 
> * profile->ucElbVDDC_Num + i];
> +   *vddci = vddci_buf[j 
> * profile->ucElbVDDCI_Num + i];
> break;
> }
> }
> --
> 2.14.1
>
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Re: [PATCH 4/7] drm/ttm: user reservation object wrappers

[Christian König]

Am 09.11.2017 um 17:50 schrieb Michel Dänzer:

On 09/11/17 09:59 AM, Christian König wrote:

Consistently use the reservation object wrappers instead of accessing
the ww_mutex directly.

Additional to that use the reservation object wrappers directly instead of
calling __ttm_bo_reserve with fixed parameters.

Signed-off-by: Christian König 

[...]


@@ -1823,7 +1823,9 @@ int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo)
return -ERESTARTSYS;
if (!ww_mutex_is_locked(>resv->lock))
goto out_unlock;
-   ret = __ttm_bo_reserve(bo, true, false, NULL);
+   ret = reservation_object_lock_interruptible(bo->resv, NULL);
+   if (ret = -EINTR)
+   ret = -ERESTARTSYS;

Typo in the test, must be

 if (ret == -EINTR)


This bug caused the Xorg process to hang for me when trying to run
glxgears, requiring a hard reboot. Did you accidentally send an untested
version of this patch?
Yeah, just stumbled over this as well. I accidentally merged the fix for 
this into a later patch which I didn't send out yet.


Consider it fixed,
Christian.
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Re: [PATCH 4/7] drm/ttm: user reservation object wrappers

[Michel Dänzer]

On 09/11/17 09:59 AM, Christian König wrote:
> Consistently use the reservation object wrappers instead of accessing
> the ww_mutex directly.
> 
> Additional to that use the reservation object wrappers directly instead of
> calling __ttm_bo_reserve with fixed parameters.
> 
> Signed-off-by: Christian König 

[...]

> @@ -1823,7 +1823,9 @@ int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo)
>   return -ERESTARTSYS;
>   if (!ww_mutex_is_locked(>resv->lock))
>   goto out_unlock;
> - ret = __ttm_bo_reserve(bo, true, false, NULL);
> + ret = reservation_object_lock_interruptible(bo->resv, NULL);
> + if (ret = -EINTR)
> + ret = -ERESTARTSYS;

Typo in the test, must be

if (ret == -EINTR)


This bug caused the Xorg process to hang for me when trying to run
glxgears, requiring a hard reboot. Did you accidentally send an untested
version of this patch?


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Re: [PATCH 2/4] drm/amdgpu: cleanup vm_size handling

[Alex Deucher]

On Thu, Nov 9, 2017 at 9:49 AM, Christian König
 wrote:
> It's pointless to have the same value twice, just always use max_pfn.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  7 +++
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 13 +
>  6 files changed, 17 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 407d3dad8f97..94500358eccc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device 
> *adev,
>   * @adev: amdgpu_device pointer
>   * @vm_size: the default vm size if it's set auto
>   */
> -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
>uint32_t fragment_size_default)
>  {
> /* adjust vm size firstly */
> -   if (amdgpu_vm_size == -1)
> -   adev->vm_manager.vm_size = vm_size;
> -   else
> -   adev->vm_manager.vm_size = amdgpu_vm_size;
> +   if (amdgpu_vm_size != -1)
> +   vm_size = amdgpu_vm_size;
> +
> +   adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
>
> /* block size depends on vm size */
> if (amdgpu_vm_block_size == -1)
> adev->vm_manager.block_size =
> -   amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
> +   amdgpu_vm_get_block_size(vm_size);
> else
> adev->vm_manager.block_size = amdgpu_vm_block_size;
>
> amdgpu_vm_set_fragment_size(adev, fragment_size_default);
>
> -   DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is 
> %u-bit\n",
> -   adev->vm_manager.vm_size, adev->vm_manager.block_size,
> -   adev->vm_manager.fragment_size);
> +   DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is 
> %u-bit\n",
> +vm_size, adev->vm_manager.block_size,
> +adev->vm_manager.fragment_size);
>  }
>
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index aa914256b4bc..c7b796c12775 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -220,7 +220,6 @@ struct amdgpu_vm_manager {
>
> uint64_tmax_pfn;
> uint32_tnum_level;
> -   uint64_tvm_size;
> uint32_tblock_size;
> uint32_tfragment_size;
> /* vram base address for page table entry  */
> @@ -312,9 +311,9 @@ struct amdgpu_bo_va_mapping 
> *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
>  void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
>   struct amdgpu_bo_va *bo_va);
>  void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
> -   uint32_t fragment_size_default);
> -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
> -   uint32_t fragment_size_default);
> +uint32_t fragment_size_default);
> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
> +  uint32_t fragment_size_default);
>  int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file 
> *filp);
>  bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
>   struct amdgpu_job *job);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index d2a43db22cff..c8e47c36608e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
> return r;
>
> amdgpu_vm_adjust_size(adev, 64, 9);
> -   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>
> adev->mc.mc_mask = 0xffULL;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 6c6a7e14359c..2b7338e22409 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
>  * Max GPUVM size for cayman and SI is 40 bits.
>  */
> amdgpu_vm_adjust_size(adev, 64, 9);
> -   

Re: [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result

[Alex Deucher]

On Thu, Nov 9, 2017 at 9:49 AM, Christian König
 wrote:
> Not sure what that should originally been good for, but it doesn't seem
> to make any sense any more.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/cik.c   | 40 
> +-
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c |  8 +++
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 -
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 38 
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  8 +++
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 18 +++
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  8 +++
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  | 12 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 -
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  8 +++
>  drivers/gpu/drm/amd/amdgpu/si.c| 34 ++---
>  drivers/gpu/drm/amd/amdgpu/soc15.c |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/vi.c| 10 -
>  15 files changed, 113 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c 
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 793b1470284d..6128080ff662 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct 
> amdgpu_device *adev)
> case CHIP_BONAIRE:
> amdgpu_program_register_sequence(adev,
>  bonaire_mgcg_cgcg_init,
> -(const 
> u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
> +
> ARRAY_SIZE(bonaire_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
>  bonaire_golden_registers,
> -(const 
> u32)ARRAY_SIZE(bonaire_golden_registers));
> +
> ARRAY_SIZE(bonaire_golden_registers));
> amdgpu_program_register_sequence(adev,
>  
> bonaire_golden_common_registers,
> -(const 
> u32)ARRAY_SIZE(bonaire_golden_common_registers));
> +
> ARRAY_SIZE(bonaire_golden_common_registers));
> amdgpu_program_register_sequence(adev,
>  bonaire_golden_spm_registers,
> -(const 
> u32)ARRAY_SIZE(bonaire_golden_spm_registers));
> +
> ARRAY_SIZE(bonaire_golden_spm_registers));
> break;
> case CHIP_KABINI:
> amdgpu_program_register_sequence(adev,
>  kalindi_mgcg_cgcg_init,
> -(const 
> u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> +
> ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
>  kalindi_golden_registers,
> -(const 
> u32)ARRAY_SIZE(kalindi_golden_registers));
> +
> ARRAY_SIZE(kalindi_golden_registers));
> amdgpu_program_register_sequence(adev,
>  
> kalindi_golden_common_registers,
> -(const 
> u32)ARRAY_SIZE(kalindi_golden_common_registers));
> +
> ARRAY_SIZE(kalindi_golden_common_registers));
> amdgpu_program_register_sequence(adev,
>  kalindi_golden_spm_registers,
> -(const 
> u32)ARRAY_SIZE(kalindi_golden_spm_registers));
> +
> ARRAY_SIZE(kalindi_golden_spm_registers));
> break;
> case CHIP_MULLINS:
> amdgpu_program_register_sequence(adev,
>  kalindi_mgcg_cgcg_init,
> -(const 
> u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> +
> ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
>  godavari_golden_registers,
> -(const 
> 

Re: [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10

[Christian König]

Am 09.11.2017 um 15:59 schrieb Michel Dänzer:

On 09/11/17 03:49 PM, Christian König wrote:

Similar to the CPU address space the VA on Vega10 has a hole in it.

[...]


diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4710e51099c2..81c34132fbd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
  
+	if (args->va_address >= AMDGPU_VA_HOLE_START &&

+   args->va_address < AMDGPU_VA_HOLE_END) {
+   dev_err(>pdev->dev,
+   "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
+   args->va_address, AMDGPU_VA_HOLE_START,
+   AMDGPU_VA_HOLE_END);
+   return -EINVAL;
+   }

This should probably be dev_dbg instead of dev_err, to prevent buggy (or
malicious) userspace from spamming dmesg.


Good point, and yes we have quite a number of other issues like that one.

Going to fix this in v2 of the patches.

Christian.

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Re: [PATCH] drm/amdgpu: Add common golden settings for GFX9

[Alex Deucher]

On Thu, Nov 9, 2017 at 3:03 AM,   wrote:
> From: Ken Wang 
>
> Signed-off-by: Ken Wang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5a4c074..ee565d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] =
> SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x0800
>  };
>
> +static const u32 golden_settings_gc_9_x_common[] =
> +{
> +   SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0x, 0x,
> +   SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0x, 0x2544c382
> +};
> +
>  #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
>  #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x2442
>
> @@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct 
> amdgpu_device *adev)
> default:
> break;
> }
> +
> +   amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
> +   (const 
> u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
>  }
>
>  static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
> --
> 2.7.4
>
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH] drm/amd/powerplay: fix copy-n-paste error on vddci_buf index

[Colin King]

From: Colin Ian King 

The index to vddci_buf is using profile->ucElbVDDC_Num rather
than profile->ucElbVDDCI_Num; this looks like a copy-n-paste
error from previous code for the vddc_buf array and I'm pretty
sure this is incorrect. Fix this by using the correct variable.

Detected by CoverityScan, CID#1457172 ("Copy-paste error")

Fixes: 970d9804b00d ("drm/amd/powerplay: Add support functions for CI to 
ppatomctrl.c")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index a129bc5b1844..c6febbf0bf69 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct 
pp_hwmgr *hwmgr,
if (vddci_id_buf[i] == virtual_voltage_id) {
for (j = 0; j < 
profile->ucLeakageBinNum; j++) {
if (efuse_voltage_id <= 
leakage_bin[j]) {
-   *vddci = vddci_buf[j * 
profile->ucElbVDDC_Num + i];
+   *vddci = vddci_buf[j * 
profile->ucElbVDDCI_Num + i];
break;
}
}
-- 
2.14.1

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Re: [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10

[Michel Dänzer]

On 09/11/17 03:49 PM, Christian König wrote:
> Similar to the CPU address space the VA on Vega10 has a hole in it.

[...]

> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 4710e51099c2..81c34132fbd5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void 
> *data,
>   return -EINVAL;
>   }
>  
> + if (args->va_address >= AMDGPU_VA_HOLE_START &&
> + args->va_address < AMDGPU_VA_HOLE_END) {
> + dev_err(>pdev->dev,
> + "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
> + args->va_address, AMDGPU_VA_HOLE_START,
> + AMDGPU_VA_HOLE_END);
> + return -EINVAL;
> + }

This should probably be dev_dbg instead of dev_err, to prevent buggy (or
malicious) userspace from spamming dmesg.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[PATCH 3/4] drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit

[Christian König]

Even when it's a small handle it as 64bit value as well.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  | 3 ++-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index fb72edc4c026..4710e51099c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -556,9 +556,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
dev_err(>pdev->dev,
-   "va_address 0x%lX is in reserved area 0x%X\n",
-   (unsigned long)args->va_address,
-   AMDGPU_VA_RESERVED_SIZE);
+   "va_address 0x%LX is in reserved area 0x%LX\n",
+   args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index c7b796c12775..e8f8896d18db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_MMHUB   1
 
 /* hardcode that limit for now */
-#define AMDGPU_VA_RESERVED_SIZE(8 << 20)
+#define AMDGPU_VA_RESERVED_SIZE(8ULL << 20)
+
 /* max vmids dedicated for process */
 #define AMDGPU_VM_MAX_RESERVED_VMID1
 
-- 
2.11.0

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[PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10

[Christian König]

Similar to the CPU address space the VA on Vega10 has a hole in it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  5 +
 4 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 354c874888f1..b15591c879ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -869,8 +869,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping *m;
struct amdgpu_bo *aobj = NULL;
struct amdgpu_cs_chunk *chunk;
+   uint64_t offset, va_start;
struct amdgpu_ib *ib;
-   uint64_t offset;
uint8_t *kptr;
 
chunk = >chunks[i];
@@ -880,14 +880,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device 
*adev,
if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
continue;
 
-   r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
-  , );
+   va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
+   r = amdgpu_cs_find_mapping(p, va_start, , );
if (r) {
DRM_ERROR("IB va_start is invalid\n");
return r;
}
 
-   if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+   if ((va_start + chunk_ib->ib_bytes) >
(m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
DRM_ERROR("IB va_start+ib_bytes is invalid\n");
return -EINVAL;
@@ -900,7 +900,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
}
 
offset = m->start * AMDGPU_GPU_PAGE_SIZE;
-   kptr += chunk_ib->va_start - offset;
+   kptr += va_start - offset;
 
memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
amdgpu_bo_kunmap(aobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4710e51099c2..81c34132fbd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
 
+   if (args->va_address >= AMDGPU_VA_HOLE_START &&
+   args->va_address < AMDGPU_VA_HOLE_END) {
+   dev_err(>pdev->dev,
+   "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
+   args->va_address, AMDGPU_VA_HOLE_START,
+   AMDGPU_VA_HOLE_END);
+   return -EINVAL;
+   }
+
+   args->va_address &= AMDGPU_VA_HOLE_MASK;
+
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_err(>pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 1d56b5b5c25d..694d953e9cb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -589,7 +589,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (amdgpu_sriov_vf(adev))
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
-   dev_info.virtual_address_max = 
(uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+   dev_info.virtual_address_max =
+   min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
+   AMDGPU_VA_HOLE_START);
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, 
AMDGPU_GPU_PAGE_SIZE);
dev_info.pte_fragment_size = (1 << 
adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e8f8896d18db..31cd57592546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -96,6 +96,11 @@ struct amdgpu_bo_list_entry;
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE(8ULL << 20)
 
+/* VA hole for 48bit addresses on Vega10 */
+#define AMDGPU_VA_HOLE_START   

[PATCH 2/4] drm/amdgpu: cleanup vm_size handling

[Christian König]

It's pointless to have the same value twice, just always use max_pfn.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  7 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 13 +
 6 files changed, 17 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 407d3dad8f97..94500358eccc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device 
*adev,
  * @adev: amdgpu_device pointer
  * @vm_size: the default vm size if it's set auto
  */
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
   uint32_t fragment_size_default)
 {
/* adjust vm size firstly */
-   if (amdgpu_vm_size == -1)
-   adev->vm_manager.vm_size = vm_size;
-   else
-   adev->vm_manager.vm_size = amdgpu_vm_size;
+   if (amdgpu_vm_size != -1)
+   vm_size = amdgpu_vm_size;
+
+   adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
 
/* block size depends on vm size */
if (amdgpu_vm_block_size == -1)
adev->vm_manager.block_size =
-   amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
+   amdgpu_vm_get_block_size(vm_size);
else
adev->vm_manager.block_size = amdgpu_vm_block_size;
 
amdgpu_vm_set_fragment_size(adev, fragment_size_default);
 
-   DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is 
%u-bit\n",
-   adev->vm_manager.vm_size, adev->vm_manager.block_size,
-   adev->vm_manager.fragment_size);
+   DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is 
%u-bit\n",
+vm_size, adev->vm_manager.block_size,
+adev->vm_manager.fragment_size);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index aa914256b4bc..c7b796c12775 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -220,7 +220,6 @@ struct amdgpu_vm_manager {
 
uint64_tmax_pfn;
uint32_tnum_level;
-   uint64_tvm_size;
uint32_tblock_size;
uint32_tfragment_size;
/* vram base address for page table entry  */
@@ -312,9 +311,9 @@ struct amdgpu_bo_va_mapping 
*amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
  struct amdgpu_bo_va *bo_va);
 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
-   uint32_t fragment_size_default);
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
-   uint32_t fragment_size_default);
+uint32_t fragment_size_default);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+  uint32_t fragment_size_default);
 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  struct amdgpu_job *job);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d2a43db22cff..c8e47c36608e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
return r;
 
amdgpu_vm_adjust_size(adev, 64, 9);
-   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
adev->mc.mc_mask = 0xffULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 6c6a7e14359c..2b7338e22409 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
 * Max GPUVM size for cayman and SI is 40 bits.
 */
amdgpu_vm_adjust_size(adev, 64, 9);
-   adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
/* Set the internal MC address mask
 * This is the max address of the GPU's
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index edbe0df24d90..e30a96a8f49b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ 

[PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result

[Christian König]

Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/cik.c   | 40 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 -
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 38 
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  8 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 18 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  8 +++
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  | 12 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 -
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/si.c| 34 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/vi.c| 10 -
 15 files changed, 113 insertions(+), 113 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 793b1470284d..6128080ff662 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct 
amdgpu_device *adev)
case CHIP_BONAIRE:
amdgpu_program_register_sequence(adev,
 bonaire_mgcg_cgcg_init,
-(const 
u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+
ARRAY_SIZE(bonaire_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
 bonaire_golden_registers,
-(const 
u32)ARRAY_SIZE(bonaire_golden_registers));
+
ARRAY_SIZE(bonaire_golden_registers));
amdgpu_program_register_sequence(adev,
 
bonaire_golden_common_registers,
-(const 
u32)ARRAY_SIZE(bonaire_golden_common_registers));
+
ARRAY_SIZE(bonaire_golden_common_registers));
amdgpu_program_register_sequence(adev,
 bonaire_golden_spm_registers,
-(const 
u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+
ARRAY_SIZE(bonaire_golden_spm_registers));
break;
case CHIP_KABINI:
amdgpu_program_register_sequence(adev,
 kalindi_mgcg_cgcg_init,
-(const 
u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+
ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
 kalindi_golden_registers,
-(const 
u32)ARRAY_SIZE(kalindi_golden_registers));
+
ARRAY_SIZE(kalindi_golden_registers));
amdgpu_program_register_sequence(adev,
 
kalindi_golden_common_registers,
-(const 
u32)ARRAY_SIZE(kalindi_golden_common_registers));
+
ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev,
 kalindi_golden_spm_registers,
-(const 
u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+
ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_MULLINS:
amdgpu_program_register_sequence(adev,
 kalindi_mgcg_cgcg_init,
-(const 
u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+
ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
 godavari_golden_registers,
-(const 
u32)ARRAY_SIZE(godavari_golden_registers));
+
ARRAY_SIZE(godavari_golden_registers));
amdgpu_program_register_sequence(adev,
 
kalindi_golden_common_registers,
-(const 

Re: [RFC 0/7] UVD support for SI in amdgpu

[Christian König]

Am 09.11.2017 um 15:37 schrieb Piotr Redlewski:

On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:

Am 09.11.2017 um 00:54 schrieb Alex Deucher:

On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski  wrote:

Hi,

Following series implements UVD support for SI in amdgpu driver. Code is based
on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
it requires tahiti uvd firmware with added header - I've created simple script
to produce exactly this, so if anyone is interested it can be found here:
https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43

Code is based on amd-staging-drm-next branch in Alex's tree. After applying
these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
and mpv.

Some comments/issues for the patches:
1. To make uvd work, I had to bring back fb location programming. Using location
programmed by vbios, vram location is not available for uvd mc (at least on my
machine) due to too wide address. Starting address is 40-bit long for fb, but
uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
in radeon driver)

Something else must be going on.  The vram location is irrelevant with
respect to the limitations of UVD.  I think the limitations with UVD
are more to do with the location of the active buffers relative to
each other rather than the absolute location of some aperture in the
GPU's address space.  CI has the same limitation as I recall so there
is probably a bug somewhere.  Windows has used the fb location as set
by the vbios since evergreen, so it definitely should work.


2. I don't know why, but I couldn't get the uvd to boot without setting uvd mc
offsets before starting other engines. Because of that I set it in .sw_init
function. In my opinion this should be fixed as it generally doesn't follow
amdgpu driver architecture (hardware setup during software setup stage) and
probably will break suspending and resume (I didn't test it). As I mentioned,
I couldn't figure out why this is happening, so I count on help with finding fix
for this.

It's just that your initialization order is incorrect.

Try to add the UVD block a bit earlier (before the PP lib block I think) in
si_set_ip_blocks.

Unfortunately it looks that's not it. I've tried to move up the UVD block in
the blocks' list, and no matter where it is put it won't boot without
configuring UVD mc in the software init phase. Moreover, even with UVD mc
initialization in the software init, UVD won't boot when placed before gfx
block. I don't know whether this means anything.

Any other ideas?


Yeah, I see this won't work without further modifications.

Need to discuss internally how we want to fix this.

Going to leave you a note when I know more,
Christian.



Regards,
Piotr


Regards,
Christian.


3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
this file is generated, so fix should be made wherever it is generated from. For
now I removed offending lines just to silence the compiler warnings.
4. I'm not sure whether I choose the right version for the uvd. Existing code in
si.c suggested that it should be 3.1, however I went with the 4.0, because for
this version there are available new style headers.

I think the regs are pretty much the same between 3.x and 4.x so it
should be fine.

Alex



Regards,
Piotr

Piotr Redlewski (7):
drm/amdgpu: remove duplicated definitions of some of the SI registers
drm/amdgpu/uvd4: fix some register's mask and shift definitions
drm/amdgpu/gmc6: don't use vram location programmed by the vbios
drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
drm/amdgpu: enable UVD for SI

   drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
   drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |   6 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  14 +
   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 114 ++-
   drivers/gpu/drm/amd/amdgpu/dce_v6_0.h  |   5 +
   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   7 -
   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  40 +-
   drivers/gpu/drm/amd/amdgpu/si.c| 256 ++-
   drivers/gpu/drm/amd/amdgpu/si_ih.c |   3 +
   drivers/gpu/drm/amd/amdgpu/sid.h   |  52 +-
   drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c  | 810 
+
   drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h  |  29 +
   .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h |   2 -
   13 files changed, 1273 insertions(+), 68 deletions(-)
   create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
   create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h

--
2.15.0

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Re: [RFC 0/7] UVD support for SI in amdgpu

[Piotr Redlewski]

On Thu, Nov 09, 2017 at 09:42:57AM +0100, Christian König wrote:
> Am 09.11.2017 um 00:54 schrieb Alex Deucher:
> > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski  
> > wrote:
> > > Hi,
> > > 
> > > Following series implements UVD support for SI in amdgpu driver. Code is 
> > > based
> > > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To 
> > > work,
> > > it requires tahiti uvd firmware with added header - I've created simple 
> > > script
> > > to produce exactly this, so if anyone is interested it can be found here:
> > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > > 
> > > Code is based on amd-staging-drm-next branch in Alex's tree. After 
> > > applying
> > > these patches, uvd boots up and seems to work ok. I've tested it with 
> > > vdpauinfo
> > > and mpv.
> > > 
> > > Some comments/issues for the patches:
> > > 1. To make uvd work, I had to bring back fb location programming. Using 
> > > location
> > > programmed by vbios, vram location is not available for uvd mc (at least 
> > > on my
> > > machine) due to too wide address. Starting address is 40-bit long for fb, 
> > > but
> > > uvd mc supports only 32-bits (judging by comments in amdgpu code and 
> > > actual code
> > > in radeon driver)
> > Something else must be going on.  The vram location is irrelevant with
> > respect to the limitations of UVD.  I think the limitations with UVD
> > are more to do with the location of the active buffers relative to
> > each other rather than the absolute location of some aperture in the
> > GPU's address space.  CI has the same limitation as I recall so there
> > is probably a bug somewhere.  Windows has used the fb location as set
> > by the vbios since evergreen, so it definitely should work.
> > 
> > > 2. I don't know why, but I couldn't get the uvd to boot without setting 
> > > uvd mc
> > > offsets before starting other engines. Because of that I set it in 
> > > .sw_init
> > > function. In my opinion this should be fixed as it generally doesn't 
> > > follow
> > > amdgpu driver architecture (hardware setup during software setup stage) 
> > > and
> > > probably will break suspending and resume (I didn't test it). As I 
> > > mentioned,
> > > I couldn't figure out why this is happening, so I count on help with 
> > > finding fix
> > > for this.
> 
> It's just that your initialization order is incorrect.
> 
> Try to add the UVD block a bit earlier (before the PP lib block I think) in
> si_set_ip_blocks.

Unfortunately it looks that's not it. I've tried to move up the UVD block in
the blocks' list, and no matter where it is put it won't boot without
configuring UVD mc in the software init phase. Moreover, even with UVD mc
initialization in the software init, UVD won't boot when placed before gfx
block. I don't know whether this means anything.

Any other ideas?

Regards,
Piotr

> 
> Regards,
> Christian.
> 
> > > 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. 
> > > I guess
> > > this file is generated, so fix should be made wherever it is generated 
> > > from. For
> > > now I removed offending lines just to silence the compiler warnings.
> > > 4. I'm not sure whether I choose the right version for the uvd. Existing 
> > > code in
> > > si.c suggested that it should be 3.1, however I went with the 4.0, 
> > > because for
> > > this version there are available new style headers.
> > I think the regs are pretty much the same between 3.x and 4.x so it
> > should be fine.
> > 
> > Alex
> > 
> > 
> > > Regards,
> > > Piotr
> > > 
> > > Piotr Redlewski (7):
> > >drm/amdgpu: remove duplicated definitions of some of the SI registers
> > >drm/amdgpu/uvd4: fix some register's mask and shift definitions
> > >drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> > >drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> > >drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> > >drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> > >drm/amdgpu: enable UVD for SI
> > > 
> > >   drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
> > >   drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |   6 +
> > >   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  14 +
> > >   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 114 ++-
> > >   drivers/gpu/drm/amd/amdgpu/dce_v6_0.h  |   5 +
> > >   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   7 -
> > >   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  40 +-
> > >   drivers/gpu/drm/amd/amdgpu/si.c| 256 ++-
> > >   drivers/gpu/drm/amd/amdgpu/si_ih.c |   3 +
> > >   drivers/gpu/drm/amd/amdgpu/sid.h   |  52 +-
> > >   drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c  | 810 
> > > +
> > >   drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h  |  29 +
> > >   

Re: [RFC 0/7] UVD support for SI in amdgpu

[Piotr Redlewski]

On Thu, Nov 09, 2017 at 01:17:36PM +0100, Christian König wrote:
> Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:
> > On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> > > Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > > > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> > > > > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski 
> > > > >  wrote:
> > > > > > Hi,
> > > > > > 
> > > > > > Following series implements UVD support for SI in amdgpu driver. 
> > > > > > Code is based
> > > > > > on CIK's UVD support in amdgpu and SI's UVD support in radeon 
> > > > > > drivers. To work,
> > > > > > it requires tahiti uvd firmware with added header - I've created 
> > > > > > simple script
> > > > > > to produce exactly this, so if anyone is interested it can be found 
> > > > > > here:
> > > > > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > > > > > 
> > > > > > Code is based on amd-staging-drm-next branch in Alex's tree. After 
> > > > > > applying
> > > > > > these patches, uvd boots up and seems to work ok. I've tested it 
> > > > > > with vdpauinfo
> > > > > > and mpv.
> > > > > > 
> > > > > > Some comments/issues for the patches:
> > > > > > 1. To make uvd work, I had to bring back fb location programming. 
> > > > > > Using location
> > > > > > programmed by vbios, vram location is not available for uvd mc (at 
> > > > > > least on my
> > > > > > machine) due to too wide address. Starting address is 40-bit long 
> > > > > > for fb, but
> > > > > > uvd mc supports only 32-bits (judging by comments in amdgpu code 
> > > > > > and actual code
> > > > > > in radeon driver)
> > > > > Something else must be going on.  The vram location is irrelevant with
> > > > > respect to the limitations of UVD.  I think the limitations with UVD
> > > > > are more to do with the location of the active buffers relative to
> > > > > each other rather than the absolute location of some aperture in the
> > > > > GPU's address space.  CI has the same limitation as I recall so there
> > > > > is probably a bug somewhere.  Windows has used the fb location as set
> > > > > by the vbios since evergreen, so it definitely should work.
> > > > > 
> > > > If this is the case, then there must be something missing in UVD mc 
> > > > controller
> > > > programming. When using vbios, I get following location:
> > > > amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 
> > > > 0x00F47FFF (2048M used)
> > > > 
> > > > When UVD bo is created, it starts at address 0xf400243000 and this 
> > > > value is used
> > > > for programming UVD mc offsets. Programming is done in the following 
> > > > way:
> > > > addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> > > > WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> > > > 
> > > > Because address of the bo is wider than 32-bit, this won't work. It 
> > > > would be the
> > > > same if UVD bo would be created at the beginning of the VRAM.
> > > > 
> > > > Any ideas how to handle this?
> > > Are you programming UVD_LMI_EXT40_ADDR?
> > > 
> > > But I'm not sure if we ever handled that correctly in the SI code.
> > Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
> >   /* bits 32-39 */
> > addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
> > WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
> 
> Ok, I've checked the firmware in the meantime and found that we never
> released firmware which supports the full 40bit addressing.
> 
> That's why this will never work correctly. Going to check if we can get
> updated firmware out of the door.

Ok, so let's wait for the new firmware. Thanks for your help Christian.

Regards,
Piotr

> 
> Regards,
> Christian.
> 
> > 
> > Regards,
> > Piotr
> 
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Re: [RFC 0/7] UVD support for SI in amdgpu

[Christian König]

Am 09.11.2017 um 11:53 schrieb Piotr Redlewski:

On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:

Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:

On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:

On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski  wrote:

Hi,

Following series implements UVD support for SI in amdgpu driver. Code is based
on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To work,
it requires tahiti uvd firmware with added header - I've created simple script
to produce exactly this, so if anyone is interested it can be found here:
https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43

Code is based on amd-staging-drm-next branch in Alex's tree. After applying
these patches, uvd boots up and seems to work ok. I've tested it with vdpauinfo
and mpv.

Some comments/issues for the patches:
1. To make uvd work, I had to bring back fb location programming. Using location
programmed by vbios, vram location is not available for uvd mc (at least on my
machine) due to too wide address. Starting address is 40-bit long for fb, but
uvd mc supports only 32-bits (judging by comments in amdgpu code and actual code
in radeon driver)

Something else must be going on.  The vram location is irrelevant with
respect to the limitations of UVD.  I think the limitations with UVD
are more to do with the location of the active buffers relative to
each other rather than the absolute location of some aperture in the
GPU's address space.  CI has the same limitation as I recall so there
is probably a bug somewhere.  Windows has used the fb location as set
by the vbios since evergreen, so it definitely should work.


If this is the case, then there must be something missing in UVD mc controller
programming. When using vbios, I get following location:
amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 0x00F47FFF (2048M 
used)

When UVD bo is created, it starts at address 0xf400243000 and this value is used
for programming UVD mc offsets. Programming is done in the following way:
addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);

Because address of the bo is wider than 32-bit, this won't work. It would be the
same if UVD bo would be created at the beginning of the VRAM.

Any ideas how to handle this?

Are you programming UVD_LMI_EXT40_ADDR?

But I'm not sure if we ever handled that correctly in the SI code.

Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
  /* bits 32-39 */
addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));


Ok, I've checked the firmware in the meantime and found that we never 
released firmware which supports the full 40bit addressing.


That's why this will never work correctly. Going to check if we can get 
updated firmware out of the door.


Regards,
Christian.



Regards,
Piotr


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Re: [RFC 0/7] UVD support for SI in amdgpu

[Piotr Redlewski]

On Thu, Nov 09, 2017 at 11:09:42AM +0100, Christian König wrote:
> Am 09.11.2017 um 10:54 schrieb Piotr Redlewski:
> > On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> > > On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski  
> > > wrote:
> > > > Hi,
> > > > 
> > > > Following series implements UVD support for SI in amdgpu driver. Code 
> > > > is based
> > > > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. 
> > > > To work,
> > > > it requires tahiti uvd firmware with added header - I've created simple 
> > > > script
> > > > to produce exactly this, so if anyone is interested it can be found 
> > > > here:
> > > > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> > > > 
> > > > Code is based on amd-staging-drm-next branch in Alex's tree. After 
> > > > applying
> > > > these patches, uvd boots up and seems to work ok. I've tested it with 
> > > > vdpauinfo
> > > > and mpv.
> > > > 
> > > > Some comments/issues for the patches:
> > > > 1. To make uvd work, I had to bring back fb location programming. Using 
> > > > location
> > > > programmed by vbios, vram location is not available for uvd mc (at 
> > > > least on my
> > > > machine) due to too wide address. Starting address is 40-bit long for 
> > > > fb, but
> > > > uvd mc supports only 32-bits (judging by comments in amdgpu code and 
> > > > actual code
> > > > in radeon driver)
> > > Something else must be going on.  The vram location is irrelevant with
> > > respect to the limitations of UVD.  I think the limitations with UVD
> > > are more to do with the location of the active buffers relative to
> > > each other rather than the absolute location of some aperture in the
> > > GPU's address space.  CI has the same limitation as I recall so there
> > > is probably a bug somewhere.  Windows has used the fb location as set
> > > by the vbios since evergreen, so it definitely should work.
> > > 
> > If this is the case, then there must be something missing in UVD mc 
> > controller
> > programming. When using vbios, I get following location:
> > amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 0x00F47FFF 
> > (2048M used)
> > 
> > When UVD bo is created, it starts at address 0xf400243000 and this value is 
> > used
> > for programming UVD mc offsets. Programming is done in the following way:
> > addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
> > WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
> > 
> > Because address of the bo is wider than 32-bit, this won't work. It would 
> > be the
> > same if UVD bo would be created at the beginning of the VRAM.
> > 
> > Any ideas how to handle this?
> 
> Are you programming UVD_LMI_EXT40_ADDR?
> 
> But I'm not sure if we ever handled that correctly in the SI code.
Yes, I do it exactly the same as it is done in radeon (and CIK in amdgpu):
 /* bits 32-39 */
addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

Regards,
Piotr
> 
> Regards,
> Christian.
> 
> > 
> > > > 2. I don't know why, but I couldn't get the uvd to boot without setting 
> > > > uvd mc
> > > > offsets before starting other engines. Because of that I set it in 
> > > > .sw_init
> > > > function. In my opinion this should be fixed as it generally doesn't 
> > > > follow
> > > > amdgpu driver architecture (hardware setup during software setup stage) 
> > > > and
> > > > probably will break suspending and resume (I didn't test it). As I 
> > > > mentioned,
> > > > I couldn't figure out why this is happening, so I count on help with 
> > > > finding fix
> > > > for this.
> > > > 3. I found some redefinitions in 
> > > > include/asic_reg/uvd/uvd_4_0_sh_mask.h. I guess
> > > > this file is generated, so fix should be made wherever it is generated 
> > > > from. For
> > > > now I removed offending lines just to silence the compiler warnings.
> > > > 4. I'm not sure whether I choose the right version for the uvd. 
> > > > Existing code in
> > > > si.c suggested that it should be 3.1, however I went with the 4.0, 
> > > > because for
> > > > this version there are available new style headers.
> > > I think the regs are pretty much the same between 3.x and 4.x so it
> > > should be fine.
> > Great.
> > 
> > Regards,
> > Piotr
> > > Alex
> > > 
> > > 
> > > > Regards,
> > > > Piotr
> > > > 
> > > > Piotr Redlewski (7):
> > > >drm/amdgpu: remove duplicated definitions of some of the SI registers
> > > >drm/amdgpu/uvd4: fix some register's mask and shift definitions
> > > >drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> > > >drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> > > >drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> > > >drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> > > >drm/amdgpu: enable UVD for SI
> > > > 
> > > >   drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
> > > >   

Re: [PATCH umr] Switch GRBM index when reading wave data directly.

[Nicolai Hähnle]

Reviewed-by: Nicolai Hähnle 

On 08.11.2017 19:39, Tom St Denis wrote:

Signed-off-by: Tom St Denis 
---
  src/lib/wave_status.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/src/lib/wave_status.c b/src/lib/wave_status.c
index fe2add779fdd..7f0130bb9347 100644
--- a/src/lib/wave_status.c
+++ b/src/lib/wave_status.c
@@ -116,7 +116,9 @@ static int umr_get_wave_status_vi(struct umr_asic *asic, 
unsigned se, unsigned s
read(asic->fd.wave, , 32*4);
} else {
int n = 0;
+   umr_grbm_select_index(asic, se, sh, cu);
read_wave_status_via_mmio(asic, simd, wave, [0], );
+   umr_grbm_select_index(asic, 0x, 0x, 0x);
}
  
  	if (buf[0] != 0) {

@@ -218,7 +220,9 @@ static int umr_get_wave_status_ai(struct umr_asic *asic, 
unsigned se, unsigned s
read(asic->fd.wave, , 32*4);
} else {
int n = 0;
+   umr_grbm_select_index(asic, se, sh, cu);
read_wave_status_via_mmio(asic, simd, wave, [0], );
+   umr_grbm_select_index(asic, 0x, 0x, 0x);
}
  
  	if (buf[0] != 1) {





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Re: [RFC 0/7] UVD support for SI in amdgpu

[Piotr Redlewski]

On Wed, Nov 08, 2017 at 06:54:18PM -0500, Alex Deucher wrote:
> On Wed, Nov 8, 2017 at 5:38 PM, Piotr Redlewski  wrote:
> > Hi,
> >
> > Following series implements UVD support for SI in amdgpu driver. Code is 
> > based
> > on CIK's UVD support in amdgpu and SI's UVD support in radeon drivers. To 
> > work,
> > it requires tahiti uvd firmware with added header - I've created simple 
> > script
> > to produce exactly this, so if anyone is interested it can be found here:
> > https://gist.github.com/anonymous/6d974a970340f7f64b6fcc4f95267e43
> >
> > Code is based on amd-staging-drm-next branch in Alex's tree. After applying
> > these patches, uvd boots up and seems to work ok. I've tested it with 
> > vdpauinfo
> > and mpv.
> >
> > Some comments/issues for the patches:
> > 1. To make uvd work, I had to bring back fb location programming. Using 
> > location
> > programmed by vbios, vram location is not available for uvd mc (at least on 
> > my
> > machine) due to too wide address. Starting address is 40-bit long for fb, 
> > but
> > uvd mc supports only 32-bits (judging by comments in amdgpu code and actual 
> > code
> > in radeon driver)
> 
> Something else must be going on.  The vram location is irrelevant with
> respect to the limitations of UVD.  I think the limitations with UVD
> are more to do with the location of the active buffers relative to
> each other rather than the absolute location of some aperture in the
> GPU's address space.  CI has the same limitation as I recall so there
> is probably a bug somewhere.  Windows has used the fb location as set
> by the vbios since evergreen, so it definitely should work.
> 
If this is the case, then there must be something missing in UVD mc controller
programming. When using vbios, I get following location:
amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 0x00F47FFF (2048M 
used)

When UVD bo is created, it starts at address 0xf400243000 and this value is used
for programming UVD mc offsets. Programming is done in the following way:
addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);

Because address of the bo is wider than 32-bit, this won't work. It would be the
same if UVD bo would be created at the beginning of the VRAM.

Any ideas how to handle this?

> > 2. I don't know why, but I couldn't get the uvd to boot without setting uvd 
> > mc
> > offsets before starting other engines. Because of that I set it in .sw_init
> > function. In my opinion this should be fixed as it generally doesn't follow
> > amdgpu driver architecture (hardware setup during software setup stage) and
> > probably will break suspending and resume (I didn't test it). As I 
> > mentioned,
> > I couldn't figure out why this is happening, so I count on help with 
> > finding fix
> > for this.
> > 3. I found some redefinitions in include/asic_reg/uvd/uvd_4_0_sh_mask.h. I 
> > guess
> > this file is generated, so fix should be made wherever it is generated 
> > from. For
> > now I removed offending lines just to silence the compiler warnings.
> > 4. I'm not sure whether I choose the right version for the uvd. Existing 
> > code in
> > si.c suggested that it should be 3.1, however I went with the 4.0, because 
> > for
> > this version there are available new style headers.
> 
> I think the regs are pretty much the same between 3.x and 4.x so it
> should be fine.
Great.

Regards,
Piotr
> 
> Alex
> 
> 
> >
> > Regards,
> > Piotr
> >
> > Piotr Redlewski (7):
> >   drm/amdgpu: remove duplicated definitions of some of the SI registers
> >   drm/amdgpu/uvd4: fix some register's mask and shift definitions
> >   drm/amdgpu/gmc6: don't use vram location programmed by the vbios
> >   drm/amdgpu/uvd4: add early init stage functions for uvd 4.0
> >   drm/amdgpu/uvd4: add sw init and fini stages' functions for uvd 4.0
> >   drm/amdgpu/uvd4: add hardware specific functions for uvd 4.0
> >   drm/amdgpu: enable UVD for SI
> >
> >  drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |   6 +
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  14 +
> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 114 ++-
> >  drivers/gpu/drm/amd/amdgpu/dce_v6_0.h  |   5 +
> >  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |   7 -
> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  40 +-
> >  drivers/gpu/drm/amd/amdgpu/si.c| 256 ++-
> >  drivers/gpu/drm/amd/amdgpu/si_ih.c |   3 +
> >  drivers/gpu/drm/amd/amdgpu/sid.h   |  52 +-
> >  drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c  | 810 
> > +
> >  drivers/gpu/drm/amd/amdgpu/uvd_v4_0.h  |  29 +
> >  .../drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h |   2 -
> >  13 files changed, 1273 insertions(+), 68 deletions(-)
> >  create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_0.c
> >  create mode 

Sorry for the commit noise on libdrm

[Christian König]

I've accidentally pushed two incomplete WIP patches to the libdrm master 
repository yesterday.


Just noticed the mistake and reverted the two.

Sorry for the noise,
Christian.
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Re: [PATCH 0/7] *** GPU recover V3 ***

[Julien Isorce]

Hi Monk.

I am interested on this. Currently when a "ring X stalled for more than N
sec" happens it usually goes into the gpu reset routine.
Does it always cause the vram to be lost ? Could you explain what happens
if the vram remains lost ?

I am asking this because I experienced some recurrent gpu reset that are
marked succeeded from the log but fail in the "resume" step.
I would not be interested in this if it would always leave a chance to the
user to cleanly reboot the machine.

The issue is that it can require a hard reboot without kernel panic and
without keeping the keyboard responding to magic keys.
Are those patches trying to address this issue ?

Note that here "issue" is not referring to the root cause of a ring X
stalled and it is also not referring to why "resume" step fails.

Thx a lot
Julien


On 30 October 2017 at 04:15, Monk Liu  wrote:

> *** job skipping logic in scheduler part is re-implemented  ***
>
> Monk Liu (7):
>   amd/scheduler:imple job skip feature(v3)
>   drm/amdgpu:implement new GPU recover(v3)
>   drm/amdgpu:cleanup in_sriov_reset and lock_reset
>   drm/amdgpu:cleanup ucode_init_bo
>   drm/amdgpu:block kms open during gpu_reset
>   drm/amdgpu/sriov:fix memory leak in psp_load_fw
>   drm/amdgpu:fix random missing of FLR NOTIFY
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   9 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 311
> --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c |  10 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  18 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   3 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  22 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   4 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |   2 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |   2 -
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |   6 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   6 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  16 +-
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c |   2 +-
>  drivers/gpu/drm/amd/scheduler/gpu_scheduler.c |  39 ++--
>  15 files changed, 220 insertions(+), 232 deletions(-)
>
> --
> 2.7.4
>
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Re: [PATCH v2 2/3] ASoC: rt5645: Wait for 400msec before concluding on value of RT5645_VENDOR_ID2

[Agrawal, Akshu]

On 11/8/2017 11:39 PM, Mark Brown wrote:

On Wed, Nov 08, 2017 at 12:24:03PM -0500, Alex Deucher wrote:


regmap_read(regmap, RT5645_VENDOR_ID2, );
  
+	/*

+* Read after 400msec, as it is the interval required between
+* read and power On.
+*/
+   msleep(TIME_TO_POWER_MS);
+   regmap_read(regmap, RT5645_VENDOR_ID2, );
+


This leaves the original read in there so we've both got the early read
(which might upset things potentially) and the delayed read.  Shouldn't
we just be adding a msleep() before the existing read?



My bad, I should have removed the addition of register read from the patch.
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Re: [PATCH] drm/amdgpu: Fix null pointer issue in amdgpu_cs_wait_any_fence

[Christian König]

Am 09.11.2017 um 08:59 schrieb Emily Deng:

The array[first] may be null when the fence has already been signaled.

BUG: SWDEV-136239

Signed-off-by: Emily Deng 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 354c874..182df08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1502,8 +1502,11 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device 
*adev,
memset(wait, 0, sizeof(*wait));
wait->out.status = (r > 0);
wait->out.first_signaled = first;
-   /* set return value 0 to indicate success */
-   r = array[first]->error;
+
+   if (array[first])
+   r = array[first]->error;
+   else
+   r = 0;
  
  err_free_fence_array:

for (i = 0; i < fence_count; i++)



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[PATCH 6/7] drm/ttm: make unlocking in ttm_bo_cleanup_refs optional

[Christian König]

Needed for the next patch.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c | 52 
 1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 6f5d18366e6e..50a678b504f3 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -486,20 +486,21 @@ static void ttm_bo_cleanup_refs_or_queue(struct 
ttm_buffer_object *bo)
 }
 
 /**
- * function ttm_bo_cleanup_refs_and_unlock
+ * function ttm_bo_cleanup_refs
  * If bo idle, remove from delayed- and lru lists, and unref.
  * If not idle, do nothing.
  *
  * Must be called with lru_lock and reservation held, this function
- * will drop both before returning.
+ * will drop the lru lock and optionally the reservation lock before returning.
  *
  * @interruptible Any sleeps should occur interruptibly.
  * @no_wait_gpu   Never wait for gpu. Return -EBUSY instead.
+ * @unlock_resv   Unlock the reservation lock as well.
  */
 
-static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo,
- bool interruptible,
- bool no_wait_gpu)
+static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo,
+  bool interruptible, bool no_wait_gpu,
+  bool unlock_resv)
 {
struct ttm_bo_global *glob = bo->glob;
struct reservation_object *resv;
@@ -518,7 +519,8 @@ static int ttm_bo_cleanup_refs_and_unlock(struct 
ttm_buffer_object *bo,
if (ret && !no_wait_gpu) {
long lret;
 
-   reservation_object_unlock(bo->resv);
+   if (unlock_resv)
+   reservation_object_unlock(bo->resv);
spin_unlock(>lru_lock);
 
lret = reservation_object_wait_timeout_rcu(resv, true,
@@ -531,19 +533,22 @@ static int ttm_bo_cleanup_refs_and_unlock(struct 
ttm_buffer_object *bo,
return -EBUSY;
 
spin_lock(>lru_lock);
-   ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY;
-
-   /*
-* We raced, and lost, someone else holds the reservation now,
-* and is probably busy in ttm_bo_cleanup_memtype_use.
-*
-* Even if it's not the case, because we finished waiting any
-* delayed destruction would succeed, so just return success
-* here.
-*/
-   if (ret) {
-   spin_unlock(>lru_lock);
-   return 0;
+   if (unlock_resv) {
+   ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY;
+   /*
+* We raced, and lost, someone else holds the 
reservation now,
+* and is probably busy in ttm_bo_cleanup_memtype_use.
+*
+* Even if it's not the case, because we finished 
waiting any
+* delayed destruction would succeed, so just return 
success
+* here.
+*/
+   if (ret) {
+   spin_unlock(>lru_lock);
+   return 0;
+   }
+   } else {
+   ret = 0;
}
}
 
@@ -600,8 +605,8 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device 
*bdev, bool remove_all)
}
 
if (!ret)
-   ret = ttm_bo_cleanup_refs_and_unlock(entry, false,
-!remove_all);
+   ret = ttm_bo_cleanup_refs(entry, false, !remove_all,
+ true);
else
spin_unlock(>lru_lock);
 
@@ -770,8 +775,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
kref_get(>list_kref);
 
if (!list_empty(>ddestroy)) {
-   ret = ttm_bo_cleanup_refs_and_unlock(bo, interruptible,
-no_wait_gpu);
+   ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, true);
kref_put(>list_kref, ttm_bo_release_list);
return ret;
}
@@ -1735,7 +1739,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
kref_get(>list_kref);
 
if (!list_empty(>ddestroy)) {
-   ret = ttm_bo_cleanup_refs_and_unlock(bo, false, false);
+   ret = ttm_bo_cleanup_refs(bo, false, false, true);
kref_put(>list_kref, ttm_bo_release_list);
return ret;
}
-- 
2.11.0

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[PATCH 5/7] drm/ttm: remove ttm_bo_unreserve_ticket

[Christian König]

Just another alias for ttm_bo_unreserve.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/nouveau/nouveau_gem.c |  2 +-
 include/drm/ttm/ttm_bo_driver.h   | 13 -
 2 files changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c 
b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 2170534101ca..dedd58fee67b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -349,7 +349,7 @@ validate_fini_no_ticket(struct validate_op *op, struct 
nouveau_fence *fence,
 
list_del(>entry);
nvbo->reserved_by = NULL;
-   ttm_bo_unreserve_ticket(>bo, >ticket);
+   ttm_bo_unreserve(>bo);
drm_gem_object_unreference_unlocked(>gem);
}
 }
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 3659cf6150d2..cba1477aa983 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -957,19 +957,6 @@ static inline void ttm_bo_unreserve(struct 
ttm_buffer_object *bo)
reservation_object_unlock(bo->resv);
 }
 
-/**
- * ttm_bo_unreserve_ticket
- * @bo: A pointer to a struct ttm_buffer_object.
- * @ticket: ww_acquire_ctx used for reserving
- *
- * Unreserve a previous reservation of @bo made with @ticket.
- */
-static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo,
-  struct ww_acquire_ctx *t)
-{
-   ttm_bo_unreserve(bo);
-}
-
 /*
  * ttm_bo_util.c
  */
-- 
2.11.0

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[PATCH 7/7] drm/ttm: optimize ttm_mem_evict_first v2

[Christian König]

Deleted BOs with the same reservation object can be reaped even if they
can't be reserved.

v2: rebase and we still need to remove/add the BO from/to the LRU.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c | 39 +++
 1 file changed, 31 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 50a678b504f3..6545c4344684 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -735,20 +735,37 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object 
*bo,
 EXPORT_SYMBOL(ttm_bo_eviction_valuable);
 
 static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
-   uint32_t mem_type,
-   const struct ttm_place *place,
-   bool interruptible,
-   bool no_wait_gpu)
+  struct reservation_object *resv,
+  uint32_t mem_type,
+  const struct ttm_place *place,
+  bool interruptible,
+  bool no_wait_gpu)
 {
struct ttm_bo_global *glob = bdev->glob;
struct ttm_mem_type_manager *man = >man[mem_type];
struct ttm_buffer_object *bo;
int ret = -EBUSY;
+   bool locked;
unsigned i;
 
spin_lock(>lru_lock);
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
list_for_each_entry(bo, >lru[i], lru) {
+   if (bo->resv == resv) {
+   if (list_empty(>ddestroy))
+   continue;
+
+   if (place &&
+   !bdev->driver->eviction_valuable(bo, place))
+   continue;
+
+   ttm_bo_del_from_lru(bo);
+
+   ret = 0;
+   locked = false;
+   break;
+   }
+
ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY;
if (ret)
continue;
@@ -760,6 +777,7 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
continue;
}
 
+   locked = true;
break;
}
 
@@ -775,7 +793,8 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
kref_get(>list_kref);
 
if (!list_empty(>ddestroy)) {
-   ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu, true);
+   ret = ttm_bo_cleanup_refs(bo, interruptible, no_wait_gpu,
+ locked);
kref_put(>list_kref, ttm_bo_release_list);
return ret;
}
@@ -786,7 +805,10 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
BUG_ON(ret != 0);
 
ret = ttm_bo_evict(bo, interruptible, no_wait_gpu);
-   ttm_bo_unreserve(bo);
+   if (locked)
+   ttm_bo_unreserve(bo);
+   else
+   ttm_bo_add_to_lru(bo);
 
kref_put(>list_kref, ttm_bo_release_list);
return ret;
@@ -850,7 +872,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object 
*bo,
return ret;
if (mem->mm_node)
break;
-   ret = ttm_mem_evict_first(bdev, mem_type, place,
+   ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place,
  interruptible, no_wait_gpu);
if (unlikely(ret != 0))
return ret;
@@ -1353,7 +1375,8 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device 
*bdev,
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
while (!list_empty(>lru[i])) {
spin_unlock(>lru_lock);
-   ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, 
false);
+   ret = ttm_mem_evict_first(bdev, NULL, mem_type, NULL,
+ false, false);
if (ret)
return ret;
spin_lock(>lru_lock);
-- 
2.11.0

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