[pull] radeon, amdgpu, and ttm drm-fixes-4.15

[Alex Deucher]

Hi Dave,

Fixes for 4.15.  Highlights:
- DC fixes for S3, gamma, audio, pageflipping, etc.
- fix a regression in radeon from kfd removal
- fix a ttm regression with swiotlb disabled
- misc other fixes

The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.15

for you to fetch changes up to 7fdf165a52505392eb059902b0df55e79a45c25f:

  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd (2017-11-29 14:43:20 
-0500)


Alex Deucher (4):
  drm/amdgpu/gfx7: cache raster_config values
  drm/amdgpu: used cached gca values for cik_read_register
  Revert "drm/amdgpu: fix rmmod KCQ disable failed error"
  drm/amdgpu: drop experimental flag for raven

Andrew Jiang (1):
  drm/amd/display: Don't reject 3D timings

Andrey Grodzovsky (1):
  drm/amd/display: Switch to drm_atomic_helper_wait_for_flip_done

Bhawanpreet Lakha (1):
  drm/amd/display: Add null check for 24BPP (xfm and dpp)

Charlene Liu (2):
  drm/amd/display: fix seq issue: turn on clock before programming afmt.
  drm/amd/display: try to find matching audio inst for enc inst first

Christian König (2):
  drm/amdgpu: don't try to move pinned BOs
  drm/ttm: fix populate_and_map() functions once more

Colin Ian King (1):
  drm/amd/display: fix memory leaks on error exit return

Dmytro Laktyushkin (3):
  drm/amd/display: fix split recout calculation
  drm/amd/display: fix split recout offset
  drm/amd/display: fix split viewport rounding error

Eric Yang (1):
  drm/amd/display: Add timing validation against dongle cap

Harry Wentland (6):
  drm/amd/display: Fix amdgpu_dm bugs found by smatch
  drm/amd/display: Bunch of smatch error and warning fixes in DC
  drm/amd/display: Fix use before NULL check in validate_timing
  drm/amd/display: Fix hubp check in set_cursor_position
  drm/amd/display: Fix potential NULL and mem leak in create_links
  drm/amd/display: Fix couple more inconsistent NULL checks in dc_resource

Hersen Wu (2):
  drm/amd/display: Handle as MST first and then DP dongle if sink support 
both
  drm/amd/display: USB-C / thunderbolt dock specific workaround

Jerry (Fangzhi) Zuo (1):
  drm/amd/display: Check aux channel before MST resume

Jordan Lazare (1):
  drm/amd/display: Revert noisy assert messages

Leo (Sunpeng) Li (3):
  drm/amd/display: Should disable when new stream is null
  drm/amd/display: Do DC mode-change check when adding CRTCs
  drm/amd/display: Do not put drm_atomic_state on resume

Leo Liu (1):
  drm/amdgpu: move UVD/VCE and VCN structure out from union

Michel Dänzer (2):
  drm/amdgpu: Set adev->vcn.irq.num_types for VCN
  drm/amdgpu: Use unsigned ring indices in amdgpu_queue_mgr_map

Oded Gabbay (1):
  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

Roman Li (2):
  drm/amd/display: Fix S3 topology change
  drm/amd/display: fix gamma setting

Shirish S (1):
  drm/amd/display: check plane state before validating fbc

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  18 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   3 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c  |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c  |   6 +-
 drivers/gpu/drm/amd/amdgpu/cik.c   | 111 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  16 +++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  31 --
 .../gpu/drm/amd/display/dc/basics/log_helpers.c|   5 +
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  15 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 102 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 106 +++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  54 ++
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|   9 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c |  10 +-
 .../drm/amd/display/dc/dce/dce_stream_encoder.c|   3 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  32 +++---
 .../drm/amd/display/dc/dce110/dce110_resource.c|  12 ++-
 .../display/dc/dce110/dce110_timing_generator.c|   8 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   6 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |   3 -
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   7 --
 drivers/gpu/drm/radeon/cik.c   |  24 

Re: [PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Felix Kuehling]

You can see the state of the queues in debugfs:
/sys/kernel/debug/kfd/... You can look at MQDs and HQDs.

If your application isn't stopping queues deliberately, queues get
disabled by evictions, usually temporarily. You'll see kernel messages
when that happens.

A VM fault will result in queues of the offending process getting
disabled permanently. Again, you'll see messages about that in the
kernel log.

The RPTR can also stop advancing if you have an infinite loop in a
shader program, or just a shader that takes a very long time to execute.
Or maybe if you have some dependencies (barriers) in your AQL packets
that never get satisfied.

The function you changed only affects the HIQ, the queue that KFD uses
to control the HWS. It does not affect user mode queues. If your problem
is with a user mode queue, your change should have no effect at all.

Regards,
  Felix


On 2017-11-29 04:43 PM, Jan Vesely wrote:
> On Mon, 2017-11-20 at 14:22 -0500, Felix Kuehling wrote:
>> I think this patch is not correct. The EOP-mem is not associated with
>> the queue size. The EOP buffer is a separate buffer used by the firmware
>> to handle command completion. As I understand it, this allows more
>> concurrency, while still making it look like all commands in the queue
>> are completing in order.
> thanks for the explanation. I was looking for a source of a CP hang
> (rptr stops advancing), but bumping the eop size actually mode things
> worse. Is there a way to find out if a queue got disabled and for what
> reason? (I'm running ROCK-1.6.x based kernel)
>
> thanks,
> Jan
>
>> Regards,
>>   Felix
>>
>>
>> On 2017-11-19 03:19 AM, Oded Gabbay wrote:
>>> On Thu, Nov 16, 2017 at 11:36 PM, Jan Vesely  wrote:
 Signed-off-by: Jan Vesely 
 ---
  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
 b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
 index f1d48281e322..b3bee39661ab 100644
 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
 +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
 @@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, 
 struct kfd_dev *dev,
 enum kfd_queue_type type, unsigned int queue_size)
  {
 int retval;
 +   unsigned int size = ALIGN(queue_size, PAGE_SIZE);

 -   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
 +   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
 if (retval != 0)
 return false;

 kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
 kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;

 -   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
 +   memset(kq->eop_kernel_addr, 0, size);

 return true;
  }
 --
 2.13.6

 ___
 amd-gfx mailing list
 amd-gfx@lists.freedesktop.org
 https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>> Thanks!
>>> Applied to -next tree
>>> Oded
>>> ___
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Jan Vesely]

On Mon, 2017-11-20 at 14:22 -0500, Felix Kuehling wrote:
> I think this patch is not correct. The EOP-mem is not associated with
> the queue size. The EOP buffer is a separate buffer used by the firmware
> to handle command completion. As I understand it, this allows more
> concurrency, while still making it look like all commands in the queue
> are completing in order.

thanks for the explanation. I was looking for a source of a CP hang
(rptr stops advancing), but bumping the eop size actually mode things
worse. Is there a way to find out if a queue got disabled and for what
reason? (I'm running ROCK-1.6.x based kernel)

thanks,
Jan

> 
> Regards,
>   Felix
> 
> 
> On 2017-11-19 03:19 AM, Oded Gabbay wrote:
> > On Thu, Nov 16, 2017 at 11:36 PM, Jan Vesely  wrote:
> > > Signed-off-by: Jan Vesely 
> > > ---
> > >  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
> > > b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
> > > index f1d48281e322..b3bee39661ab 100644
> > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
> > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
> > > @@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, 
> > > struct kfd_dev *dev,
> > > enum kfd_queue_type type, unsigned int queue_size)
> > >  {
> > > int retval;
> > > +   unsigned int size = ALIGN(queue_size, PAGE_SIZE);
> > > 
> > > -   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
> > > +   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
> > > if (retval != 0)
> > > return false;
> > > 
> > > kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
> > > kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
> > > 
> > > -   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
> > > +   memset(kq->eop_kernel_addr, 0, size);
> > > 
> > > return true;
> > >  }
> > > --
> > > 2.13.6
> > > 
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > 
> > Thanks!
> > Applied to -next tree
> > Oded
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
> 


signature.asc
Description: This is a digitally signed message part
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 1/2] drm/amd/display: Use macro for isnan check

[Alex Deucher]

On Wed, Nov 29, 2017 at 3:55 PM, Harry Wentland  wrote:
> In code provided by HW teams we do a NaN check on floats
> by comparing the number against itself. This confuses most
> people including myself. Macro it out to make it self-explanatory.
>
> Don't do a NaN check for int.
>
> v2: parantheses around 'number' expression
>
> Signed-off-by: Harry Wentland 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> index b6abe0f3bb15..ae38cdb80915 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> @@ -25,37 +25,35 @@
>
>  #include "dcn_calc_math.h"
>
> +#define isNaN(number) ((number) != (number))
> +
>  float dcn_bw_mod(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 - arg1 * ((int) (arg1 / arg2));
>  }
>
>  float dcn_bw_min2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 < arg2 ? arg1 : arg2;
>  }
>
>  unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
>  {
> -   if (arg1 != arg1)
> -   return arg2;
> -   if (arg2 != arg2)
> -   return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
>  float dcn_bw_max2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 1/2] drm/amd/display: Use macro for isnan check

[Harry Wentland]

In code provided by HW teams we do a NaN check on floats
by comparing the number against itself. This confuses most
people including myself. Macro it out to make it self-explanatory.

Don't do a NaN check for int.

v2: parantheses around 'number' expression

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index b6abe0f3bb15..ae38cdb80915 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -25,37 +25,35 @@
 
 #include "dcn_calc_math.h"
 
+#define isNaN(number) ((number) != (number))
+
 float dcn_bw_mod(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 - arg1 * ((int) (arg1 / arg2));
 }
 
 float dcn_bw_min2(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 < arg2 ? arg1 : arg2;
 }
 
 unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
 {
-   if (arg1 != arg1)
-   return arg2;
-   if (arg2 != arg2)
-   return arg1;
return arg1 > arg2 ? arg1 : arg2;
 }
 float dcn_bw_max2(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 > arg2 ? arg1 : arg2;
 }
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 2/2] drm/amd/display: Add disclaimer to BW and DML code provided by HW

[Harry Wentland]

This code can sometimes look troubling but we trust it as it comes from
HW teams with a guarantee of correctness. Add a note to these files to
explain this.

v2: thing -> things

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  9 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c |  9 +
 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c  |  9 +
 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |  9 +
 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 10 ++
 8 files changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 6347712db834..2e11fac2a63d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -29,6 +29,15 @@
 #include "core_types.h"
 #include "dal_asic_id.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 
/***
  * Private Functions
  
**/
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 626f9cf8aad2..366aace8c323 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -27,6 +27,15 @@
 #include "dcn_calc_auto.h"
 #include "dcn_calc_math.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 /*REVISION#250*/
 void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index ae38cdb80915..7600a4a4abc7 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -27,6 +27,15 @@
 
 #define isNaN(number) ((number) != (number))
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 float dcn_bw_mod(const float arg1, const float arg2)
 {
if (isNaN(arg1))
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a4fbca34bcdf..b5bc9159f48e 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -33,6 +33,15 @@
 #include "dcn10/dcn10_resource.h"
 #include "dcn_calc_math.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 1f337ecfeab0..260e113fcc02 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -28,6 +28,15 @@
 
 #include "dml_inline_defs.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0x
 static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c 

RE: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

[Liu, Shaoyun]

There are other place of the golden register setting where I already replace 
the SOC15_REG_OFFSET with SOC15_REG_ENTRY.   All these GDS register offset are 
based on GC_BASE0 (0x2000) so how about I use following defines 

#define  VG10_GC_BASE0_OFFSET(reg)  (0x2000 + reg)   

And use it to replace the SOC15_REG_OFFSET used in amdgpu_gds_reg_offset[]

Regards
Shaoyun.liu

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] 
Sent: Wednesday, November 29, 2017 3:08 PM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static 
const array

Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:
> Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
> Signed-off-by: Shaoyun Liu 
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 259 
> +++---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  14 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  13 +-
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  12 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c|  88 +-
>   drivers/gpu/drm/amd/amdgpu/soc15.c|  93 ---
>   drivers/gpu/drm/amd/amdgpu/soc15.h|   4 +
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h |   3 +
>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |   3 +-
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +-
>   10 files changed, 278 insertions(+), 213 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5497ed6..f0560d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -67,150 +67,151 @@
>   
>   static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
>   {
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
> - { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
> -   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
> - { 

RE: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

[Liu, Shaoyun]

Thanks for the review .  The reason to use define here is the original function 
didn't take the adev as parameter .  If I change it here , all the caller of 
this function need to be changed . If you think that's  proper way  I can 
change it.  But do you think it's  better to put it in another change so this 
patch  will looks much more cleaner . 

Regards
Shaoyun.liu

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] 
Sent: Wednesday, November 29, 2017 3:05 PM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for 
register access for SOC15

Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:
> Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
> Signed-off-by: Shaoyun Liu 
> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++
>   drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 
> ---
>   2 files changed, 11 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 4c55f21..e324c66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -107,24 +107,9 @@
>   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 
> 0x0002
>   };
>   
> -static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 
> internal_offset) -{
> - u32 base = 0;
> -
> - switch (instance) {
> - case 0:
> - base = SDMA0_BASE.instance[0].segment[0];
> - break;
> - case 1:
> - base = SDMA1_BASE.instance[0].segment[0];
> - break;
> - default:
> - BUG();
> - break;
> - }
> -
> - return base + internal_offset;
> -}
> +#define sdma_v4_0_get_reg_offset(inst, offset) ( 0 == inst ? \
> + (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : \
> + (adev->reg_offset[SDMA1_HWIP][0][0] + offset))

Please keep that a function, not a define.

Apart from that looks really good to me.

Christian.

>   
>   static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
>   {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 7a8e4e28..62a6e21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -54,42 +54,24 @@ struct nbio_pcie_index_data {
>   
> (ip##_BASE__INST##inst##_SEG4 + reg)
>   
>   #define WREG32_FIELD15(ip, idx, reg, field, val)\
> - WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, 
> idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, 
> field))
> + WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  
> \
> + (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) 
> \
> + & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, 
> +field))
>   
>   #define RREG32_SOC15(ip, inst, reg) \
> - RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> - (ip##_BASE__INST##inst##_SEG4 + reg))
> + RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>   
>   #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> - RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> - (ip##_BASE__INST##inst##_SEG4 + reg) + offset)
> + RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + 
> +offset)
>   
>   #define WREG32_SOC15(ip, inst, reg, value) \
> - WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
> - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> - (ip##_BASE__INST##inst##_SEG4 + reg), value)
> + WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), 
> +value)
>   
>   #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> - WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + 
> reg : \
> - (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
> - (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
> - (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
> -   

Re: [PATCH 1/2] drm/amd/display: Use macro for isnan check

[Alex Deucher]

On Wed, Nov 29, 2017 at 3:21 PM, Harry Wentland  wrote:
> In code provided by HW teams we do a NaN check on floats
> by comparing the number against itself. This confuses most
> people including myself. Macro it out to make it self-explanatory.
>
> Don't do a NaN check for int.
>
> Signed-off-by: Harry Wentland 
> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> index b6abe0f3bb15..102b5db28402 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> @@ -25,37 +25,35 @@
>
>  #include "dcn_calc_math.h"
>
> +#define isNaN(number) number != number

To be on the safe side, you may want to add some parens around the
argument in case someone passes in an expression.  E.g.,

#define isNaN(number) ((number) != (number))

Alex

> +
>  float dcn_bw_mod(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 - arg1 * ((int) (arg1 / arg2));
>  }
>
>  float dcn_bw_min2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 < arg2 ? arg1 : arg2;
>  }
>
>  unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
>  {
> -   if (arg1 != arg1)
> -   return arg2;
> -   if (arg2 != arg2)
> -   return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
>  float dcn_bw_max2(const float arg1, const float arg2)
>  {
> -   if (arg1 != arg1)
> +   if (isNaN(arg1))
> return arg2;
> -   if (arg2 != arg2)
> +   if (isNaN(arg2))
> return arg1;
> return arg1 > arg2 ? arg1 : arg2;
>  }
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/2] drm/amd/display: Use macro for isnan check

[Harry Wentland]

In code provided by HW teams we do a NaN check on floats
by comparing the number against itself. This confuses most
people including myself. Macro it out to make it self-explanatory.

Don't do a NaN check for int.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index b6abe0f3bb15..102b5db28402 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -25,37 +25,35 @@
 
 #include "dcn_calc_math.h"
 
+#define isNaN(number) number != number
+
 float dcn_bw_mod(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 - arg1 * ((int) (arg1 / arg2));
 }
 
 float dcn_bw_min2(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 < arg2 ? arg1 : arg2;
 }
 
 unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
 {
-   if (arg1 != arg1)
-   return arg2;
-   if (arg2 != arg2)
-   return arg1;
return arg1 > arg2 ? arg1 : arg2;
 }
 float dcn_bw_max2(const float arg1, const float arg2)
 {
-   if (arg1 != arg1)
+   if (isNaN(arg1))
return arg2;
-   if (arg2 != arg2)
+   if (isNaN(arg2))
return arg1;
return arg1 > arg2 ? arg1 : arg2;
 }
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] drm/amd/display: Add disclaimer to BW and DML code provided by HW

[Harry Wentland]

This code can sometimes look troubling but we trust it as it comes from
HW teams with a guarantee of correctness. Add a note to these files to
explain this.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c  |  9 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  9 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c |  9 +
 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c  |  9 +
 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |  9 +
 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 10 ++
 8 files changed, 73 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 6347712db834..75afb4077651 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -29,6 +29,15 @@
 #include "core_types.h"
 #include "dal_asic_id.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do thing in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 
/***
  * Private Functions
  
**/
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 626f9cf8aad2..e3408f121cdc 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -27,6 +27,15 @@
 #include "dcn_calc_auto.h"
 #include "dcn_calc_math.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do thing in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 /*REVISION#250*/
 void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index 102b5db28402..2522c9e66232 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -25,6 +25,15 @@
 
 #include "dcn_calc_math.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do thing in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 #define isNaN(number) number != number
 
 float dcn_bw_mod(const float arg1, const float arg2)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a4fbca34bcdf..b702b87318fd 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -33,6 +33,15 @@
 #include "dcn10/dcn10_resource.h"
 #include "dcn_calc_math.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do thing in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 1f337ecfeab0..7d7cc04042c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -28,6 +28,15 @@
 
 #include "dml_inline_defs.h"
 
+/*
+ * NOTE:
+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do thing in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0x
 static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c 

Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

[Christian König]

Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:

Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu 
---
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 259 +++---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  14 +-
  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  13 +-
  drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  12 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c|  88 +-
  drivers/gpu/drm/amd/amdgpu/soc15.c|  93 ---
  drivers/gpu/drm/amd/amdgpu/soc15.h|   4 +
  drivers/gpu/drm/amd/amdgpu/soc15_common.h |   3 +
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +-
  10 files changed, 278 insertions(+), 213 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5497ed6..f0560d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -67,150 +67,151 @@
  
  static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =

  {
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
+   /* Fix me if GC base for the register is not 0x2000 in the future asic 
*/


Yeah, we need a better solution for this.

How about a VG10_GOLDEN_REG macro or something like this?

Regards,
Christian.


+   { (0x2000 + mmGDS_VMID0_BASE),
+ (0x2000 + mmGDS_VMID0_SIZE),
+ (0x2000 + mmGDS_GWS_VMID0),
+ (0x2000 + mmGDS_OA_VMID0) },
+   { (0x2000 + mmGDS_VMID1_BASE),
+ (0x2000 + mmGDS_VMID1_SIZE),
+ (0x2000 + mmGDS_GWS_VMID1),
+ (0x2000 + 

Re: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

[Christian König]

Am 29.11.2017 um 20:09 schrieb Shaoyun Liu:

Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
Signed-off-by: Shaoyun Liu 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++
  drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ---
  2 files changed, 11 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4c55f21..e324c66 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -107,24 +107,9 @@
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 
0x0002
  };
  
-static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)

-{
-   u32 base = 0;
-
-   switch (instance) {
-   case 0:
-   base = SDMA0_BASE.instance[0].segment[0];
-   break;
-   case 1:
-   base = SDMA1_BASE.instance[0].segment[0];
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   return base + internal_offset;
-}
+#define sdma_v4_0_get_reg_offset(inst, offset) ( 0 == inst ? \
+   (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : \
+   (adev->reg_offset[SDMA1_HWIP][0][0] + offset))


Please keep that a function, not a define.

Apart from that looks really good to me.

Christian.

  
  static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)

  {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 7a8e4e28..62a6e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -54,42 +54,24 @@ struct nbio_pcie_index_data {
  
(ip##_BASE__INST##inst##_SEG4 + reg)
  
  #define WREG32_FIELD15(ip, idx, reg, field, val)	\

-   WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, 
mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+   WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  
 \
+   (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) 
 \
+   & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  
  #define RREG32_SOC15(ip, inst, reg) \

-   RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg))
+   RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  
  #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \

-   RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg) + offset)
+   RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + 
offset)
  
  #define WREG32_SOC15(ip, inst, reg, value) \

-   WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg), value)
+   WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
  
  #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \

-   WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + 
reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg), value)
+   WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + 
reg), value)
  
  #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \

-   WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg) + offset, value)
+   WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + 
offset, value)
  
  #endif
  

Re: [PATCH 1/7] drm/amdgpu: fix VM PD addr shift

[Felix Kuehling]

Hi Christian,

I've finally found the time to review the patch series. It makes sense
to me.

I think the explanation on patch 1 ("The block size only affects the
leave nodes, everything else is fixed.") also applies to patch 2 and
would make it easier to understand the motivation for the change.

Other than that, the series is Reviewed-by: Felix Kuehling


Regards,
  Felix


On 2017-11-27 11:02 AM, Christian König wrote:
> The block size only affects the leave nodes, everything else is fixed.
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 28 +++-
>  1 file changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 122379dfc7d8..f1e541e9b514 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -139,6 +139,24 @@ struct amdgpu_prt_cb {
>  };
>  
>  /**
> + * amdgpu_vm_level_shift - return the addr shift for each level
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Returns the number of bits the pfn needs to be right shifted for a level.
> + */
> +static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
> +   unsigned level)
> +{
> + if (level != adev->vm_manager.num_level)
> + return 9 * (adev->vm_manager.num_level - level - 1) +
> + adev->vm_manager.block_size;
> + else
> + /* For the page tables on the leaves */
> + return 0;
> +}
> +
> +/**
>   * amdgpu_vm_num_entries - return the number of entries in a PD/PT
>   *
>   * @adev: amdgpu_device pointer
> @@ -288,8 +306,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
> *adev,
> uint64_t saddr, uint64_t eaddr,
> unsigned level)
>  {
> - unsigned shift = (adev->vm_manager.num_level - level) *
> - adev->vm_manager.block_size;
> + unsigned shift = amdgpu_vm_level_shift(adev, level);
>   unsigned pt_idx, from, to;
>   int r;
>   u64 flags;
> @@ -1302,18 +1319,19 @@ void amdgpu_vm_get_entry(struct 
> amdgpu_pte_update_params *p, uint64_t addr,
>struct amdgpu_vm_pt **entry,
>struct amdgpu_vm_pt **parent)
>  {
> - unsigned idx, level = p->adev->vm_manager.num_level;
> + unsigned level = 0;
>  
>   *parent = NULL;
>   *entry = >vm->root;
>   while ((*entry)->entries) {
> - idx = addr >> (p->adev->vm_manager.block_size * level--);
> + unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++);
> +
>   idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
>   *parent = *entry;
>   *entry = &(*entry)->entries[idx];
>   }
>  
> - if (level)
> + if (level != p->adev->vm_manager.num_level)
>   *entry = NULL;
>  }
>  

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset

[Shaoyun Liu]

Change-Id: Ibfeb782a67e07c4b0d24b1e1903f860735a307e6
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 25 ---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  4 
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c|  9 
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c |  9 
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/soc15.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |  6 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 +
 9 files changed, 58 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index cdf4426..2016d45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -142,7 +142,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
unsigned int utimeout);
 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
-static uint32_t get_watch_base_addr(void);
+static uint32_t get_watch_base_addr(struct amdgpu_device *adev);
 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 static int kgd_address_watch_execute(struct kgd_dev *kgd,
unsigned int watch_point_id,
@@ -439,10 +439,11 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, 
uint32_t pipe_id)
return 0;
 }
 
-static uint32_t get_sdma_base_addr(unsigned int engine_id,
-  unsigned int queue_id)
+static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+   unsigned int engine_id,
+   unsigned int queue_id)
 {
-   static const uint32_t base[2] = {
+   uint32_t base[2] = {
SOC15_REG_OFFSET(SDMA0, 0,
 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
SOC15_REG_OFFSET(SDMA1, 0,
@@ -458,7 +459,7 @@ static uint32_t get_sdma_base_addr(unsigned int engine_id,
return retval;
 }
 
-static uint32_t get_watch_base_addr(void)
+static uint32_t get_watch_base_addr(struct amdgpu_device *adev)
 {
uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
mmTCP_WATCH0_ADDR_H;
@@ -617,7 +618,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
uint64_t __user *wptr64 = (uint64_t __user *)wptr;
 
m = get_sdma_mqd(mqd);
-   sdma_base_addr = get_sdma_base_addr(m->sdma_engine_id,
+   sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
m->sdma_queue_id);
sdmax_gfx_context_cntl = m->sdma_engine_id ?
SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
@@ -684,7 +685,7 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 uint32_t (**dump)[2], uint32_t *n_regs)
 {
struct amdgpu_device *adev = get_amdgpu_device(kgd);
-   uint32_t sdma_base_addr = get_sdma_base_addr(engine_id, queue_id);
+   uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
uint32_t i = 0, reg;
 #undef HQD_N_REGS
 #define HQD_N_REGS (19+6+7+10)
@@ -740,7 +741,7 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, 
void *mqd)
uint32_t sdma_rlc_rb_cntl;
 
m = get_sdma_mqd(mqd);
-   sdma_base_addr = get_sdma_base_addr(m->sdma_engine_id,
+   sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
m->sdma_queue_id);
 
sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
@@ -869,7 +870,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void 
*mqd,
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
m = get_sdma_mqd(mqd);
-   sdma_base_addr = get_sdma_base_addr(m->sdma_engine_id,
+   sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
m->sdma_queue_id);
 
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
@@ -1035,7 +1036,7 @@ static int kgd_address_watch_disable(struct kgd_dev *kgd)
cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
cntl.bitfields.atc = 1;
 
-   watch_base_addr = get_watch_base_addr();
+   watch_base_addr = get_watch_base_addr(adev);
/* Turning off this address until we set all the registers */
for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
WREG32(watch_base_addr +
@@ -1056,7 +1057,7 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd,
union TCP_WATCH_CNTL_BITS cntl;
uint32_t watch_base_addr;
 
-   

[PATCH 5/5] drm/admgpu: Reduce the usage of soc15ip.h

[Shaoyun Liu]

Change-Id: I132079eb13264aeab62c9e40c1a351609f15f90e
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   | 1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c  | 1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 1 -
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 1 -
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c| 1 -
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c| 1 -
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c| 1 -
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 1 -
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c| 1 -
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 2 --
 17 files changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 2016d45..61fd2b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -31,7 +31,6 @@
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_amdkfd_gfx_v8.h"
-#include "soc15ip.h"
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
 #include "vega10_enum.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index d7ba048..d4b23d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -35,7 +35,6 @@
 #include "soc15d.h"
 #include "soc15_common.h"
 
-#include "soc15ip.h"
 #include "vcn/vcn_1_0_offset.h"
 
 /* 1 second timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fa45602..0c73f2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -28,7 +28,6 @@
 #include "soc15.h"
 #include "soc15d.h"
 
-#include "soc15ip.h"
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
 #include "vega10_enum.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index f1effad..1d392f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -23,7 +23,6 @@
 #include "amdgpu.h"
 #include "gfxhub_v1_0.h"
 
-#include "soc15ip.h"
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
 #include "gc/gc_9_0_default.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ca66e1c..3be7d7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -25,7 +25,6 @@
 #include "gmc_v9_0.h"
 #include "amdgpu_atomfirmware.h"
 
-#include "soc15ip.h"
 #include "hdp/hdp_4_0_offset.h"
 #include "hdp/hdp_4_0_sh_mask.h"
 #include "gc/gc_9_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index bd160d8..0c5a76f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -23,7 +23,6 @@
 #include "amdgpu.h"
 #include "mmhub_v1_0.h"
 
-#include "soc15ip.h"
 #include "mmhub/mmhub_1_0_offset.h"
 #include "mmhub/mmhub_1_0_sh_mask.h"
 #include "mmhub/mmhub_1_0_default.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index ad9054e..71f5690 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -22,7 +22,6 @@
  */
 
 #include "amdgpu.h"
-#include "soc15ip.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
 #include "gc/gc_9_0_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 3b87b8a..5c16957 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -24,7 +24,6 @@
 #include "amdgpu_atombios.h"
 #include "nbio_v6_1.h"
 
-#include "soc15ip.h"
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 7252d572..1da424c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -24,7 +24,6 @@
 #include "amdgpu_atombios.h"
 #include "nbio_v7_0.h"
 
-#include "soc15ip.h"
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index acaf789..5a9fe24 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ 

[PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

[Shaoyun Liu]

Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 259 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  14 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  13 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  12 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c|  88 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c|  93 ---
 drivers/gpu/drm/amd/amdgpu/soc15.h|   4 +
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |   3 +
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |   3 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +-
 10 files changed, 278 insertions(+), 213 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5497ed6..f0560d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -67,150 +67,151 @@
 
 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 {
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
+   /* Fix me if GC base for the register is not 0x2000 in the future asic 
*/
+   { (0x2000 + mmGDS_VMID0_BASE),
+ (0x2000 + mmGDS_VMID0_SIZE),
+ (0x2000 + mmGDS_GWS_VMID0),
+ (0x2000 + mmGDS_OA_VMID0) },
+   { (0x2000 + mmGDS_VMID1_BASE),
+ (0x2000 + mmGDS_VMID1_SIZE),
+ (0x2000 + mmGDS_GWS_VMID1),
+ (0x2000 + mmGDS_OA_VMID1) },
+   { (0x2000 + mmGDS_VMID2_BASE),
+ (0x2000 + mmGDS_VMID2_SIZE),
+ (0x2000 + mmGDS_GWS_VMID2),
+ (0x2000 + mmGDS_OA_VMID2) },
+   { (0x2000 + 

[PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

[Shaoyun Liu]

Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++
 drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ---
 2 files changed, 11 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4c55f21..e324c66 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -107,24 +107,9 @@
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 
0x0002
 };
 
-static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
-{
-   u32 base = 0;
-
-   switch (instance) {
-   case 0:
-   base = SDMA0_BASE.instance[0].segment[0];
-   break;
-   case 1:
-   base = SDMA1_BASE.instance[0].segment[0];
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   return base + internal_offset;
-}
+#define sdma_v4_0_get_reg_offset(inst, offset) ( 0 == inst ? \
+   (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : \
+   (adev->reg_offset[SDMA1_HWIP][0][0] + offset))
 
 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 7a8e4e28..62a6e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -54,42 +54,24 @@ struct nbio_pcie_index_data {
 
(ip##_BASE__INST##inst##_SEG4 + reg)
 
 #define WREG32_FIELD15(ip, idx, reg, field, val)   \
-   WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, 
idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, 
field))
+   WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  
\
+   (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) 
\
+   & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 
 #define RREG32_SOC15(ip, inst, reg) \
-   RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg))
+   RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
 
 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
-   RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg) + offset)
+   RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + 
offset)
 
 #define WREG32_SOC15(ip, inst, reg, value) \
-   WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg), value)
+   WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
 
 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
-   WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + 
reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg), value)
+   WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + 
reg), value)
 
 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
-   WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
-   (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
-   (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
-   (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
-   (ip##_BASE__INST##inst##_SEG4 + reg) + offset, value)
+   WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + 
offset, value)
 
 #endif
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/5] drm/amdgpu: Dynamic initialize IP base offset

[Shaoyun Liu]

Change-Id: I84217de7c188f8886383500da3c91e488086586b
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 27 ++
 drivers/gpu/drm/amd/amdgpu/soc15.c   | 10 +
 drivers/gpu/drm/amd/amdgpu/soc15.h   |  2 +
 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 56 
 5 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f864570..6bb231c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -41,7 +41,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o 
kv_dpm.o \
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
-   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
+   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o
 
 # add GMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 71620fc..1625e41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1438,6 +1438,30 @@ struct amdgpu_fw_vram_usage {
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, 
uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, 
uint32_t);
 
+/* Define the HW IP blocks will be used in driver , add more if necessary */
+enum amd_hw_ip_block_type {
+   GC_HWIP = 1,
+   HDP_HWIP,
+   SDMA0_HWIP,
+   SDMA1_HWIP,
+   MMHUB_HWIP,
+   ATHUB_HWIP,
+   NBIO_HWIP,
+   MP0_HWIP,
+   UVD_HWIP,
+   VCN_HWIP = UVD_HWIP,
+   VCE_HWIP,
+   DF_HWIP,
+   DCE_HWIP,
+   OSSSYS_HWIP,
+   SMUIO_HWIP,
+   PWR_HWIP,
+   NBIF_HWIP,
+   MAX_HWIP
+};
+
+#define HWIP_MAX_INSTANCE  6
+
 struct amd_powerplay {
struct cgs_device *cgs_device;
void *pp_handle;
@@ -1630,6 +1654,9 @@ struct amdgpu_device {
/* amdkfd interface */
struct kfd_dev  *kfd;
 
+   /* soc15 register offset based on ip, instance and  segment */
+   uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+
/* delayed work_func for deferring clockgating during resume */
struct delayed_work late_init_work;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f134ca0..7c88bcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -516,6 +516,16 @@ static void soc15_enable_doorbell_aperture(struct 
amdgpu_device *adev,
 
 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 {
+   /* Set IP register base before any HW register access */
+   switch (adev->asic_type) {
+   case CHIP_VEGA10:
+   case CHIP_RAVEN:
+   vega10_reg_base_init(adev);
+   break;
+   default:
+   return -EINVAL;
+   }
+
nbio_v6_1_detect_hw_virt(adev);
 
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h 
b/drivers/gpu/drm/amd/amdgpu/soc15.h
index acb3cdb..c34496f 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -33,4 +33,6 @@ void soc15_grbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
 int soc15_set_ip_blocks(struct amdgpu_device *adev);
 
+int vega10_reg_base_init(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
new file mode 100644
index 000..b7bdd04
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN 

Re: [PATCH 0/5] drm/radeon: Clean up rest of amdkfd support

[Christian König]

Am 29.11.2017 um 18:24 schrieb Michel Dänzer:

From: Michel Dänzer 


Reviewed-by: Christian König  for the series.



The first four patches are mostly straight reverts of changes which
were made for amdkfd support, patch 5 cleans up a leftover define.

Michel Dänzer (5):
   Revert "drm/radeon: adding synchronization for GRBM GFX"
   Revert "drm/radeon: Report doorbell configuration to amdkfd"
   Revert "drm/radeon/cik: Don't touch int of pipes 1-7"
   Revert "drm/radeon: reduce number of free VMIDs and pipes in KV"
   drm/radeon: Remove KFD_CIK_SDMA_QUEUE_OFFSET

  drivers/gpu/drm/radeon/cik.c   | 114 +++--
  drivers/gpu/drm/radeon/cik_reg.h   |   2 -
  drivers/gpu/drm/radeon/radeon.h|   6 --
  drivers/gpu/drm/radeon/radeon_device.c |  32 -
  4 files changed, 81 insertions(+), 73 deletions(-)



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/5] drm/radeon: Clean up rest of amdkfd support

[Michel Dänzer]

From: Michel Dänzer 

The first four patches are mostly straight reverts of changes which
were made for amdkfd support, patch 5 cleans up a leftover define.

Michel Dänzer (5):
  Revert "drm/radeon: adding synchronization for GRBM GFX"
  Revert "drm/radeon: Report doorbell configuration to amdkfd"
  Revert "drm/radeon/cik: Don't touch int of pipes 1-7"
  Revert "drm/radeon: reduce number of free VMIDs and pipes in KV"
  drm/radeon: Remove KFD_CIK_SDMA_QUEUE_OFFSET

 drivers/gpu/drm/radeon/cik.c   | 114 +++--
 drivers/gpu/drm/radeon/cik_reg.h   |   2 -
 drivers/gpu/drm/radeon/radeon.h|   6 --
 drivers/gpu/drm/radeon/radeon_device.c |  32 -
 4 files changed, 81 insertions(+), 73 deletions(-)

-- 
2.15.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/5] Revert "drm/radeon: adding synchronization for GRBM GFX"

[Michel Dänzer]

From: Michel Dänzer 

This reverts commit 1c0a46255f8d7daf5b601668836e185fd1294e94. Not needed
anymore, since amdkfd is no longer supported with radeon.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/cik.c   | 26 --
 drivers/gpu/drm/radeon/radeon.h|  2 --
 drivers/gpu/drm/radeon/radeon_device.c |  1 -
 3 files changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index a6511918f632..33fdf085a52e 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1627,8 +1627,6 @@ static const u32 godavari_golden_registers[] =
 
 static void cik_init_golden_registers(struct radeon_device *rdev)
 {
-   /* Some of the registers might be dependent on GRBM_GFX_INDEX */
-   mutex_lock(>grbm_idx_mutex);
switch (rdev->family) {
case CHIP_BONAIRE:
radeon_program_register_sequence(rdev,
@@ -1703,7 +1701,6 @@ static void cik_init_golden_registers(struct 
radeon_device *rdev)
default:
break;
}
-   mutex_unlock(>grbm_idx_mutex);
 }
 
 /**
@@ -3120,7 +3117,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
u32 disabled_rbs = 0;
u32 enabled_rbs = 0;
 
-   mutex_lock(>grbm_idx_mutex);
for (i = 0; i < se_num; i++) {
for (j = 0; j < sh_per_se; j++) {
cik_select_se_sh(rdev, i, j);
@@ -3132,7 +3128,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
}
}
cik_select_se_sh(rdev, 0x, 0x);
-   mutex_unlock(>grbm_idx_mutex);
 
mask = 1;
for (i = 0; i < max_rb_num_per_se * se_num; i++) {
@@ -3143,7 +3138,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
 
rdev->config.cik.backend_enable_mask = enabled_rbs;
 
-   mutex_lock(>grbm_idx_mutex);
for (i = 0; i < se_num; i++) {
cik_select_se_sh(rdev, i, 0x);
data = 0;
@@ -3171,7 +3165,6 @@ static void cik_setup_rb(struct radeon_device *rdev,
WREG32(PA_SC_RASTER_CONFIG, data);
}
cik_select_se_sh(rdev, 0x, 0x);
-   mutex_unlock(>grbm_idx_mutex);
 }
 
 /**
@@ -3391,12 +3384,6 @@ static void cik_gpu_init(struct radeon_device *rdev)
/* set HW defaults for 3D engine */
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 
-   mutex_lock(>grbm_idx_mutex);
-   /*
-* making sure that the following register writes will be broadcasted
-* to all the shaders
-*/
-   cik_select_se_sh(rdev, 0x, 0x);
WREG32(SX_DEBUG_1, 0x20);
 
WREG32(TA_CNTL_AUX, 0x0001);
@@ -3452,7 +3439,6 @@ static void cik_gpu_init(struct radeon_device *rdev)
 
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
-   mutex_unlock(>grbm_idx_mutex);
 
udelay(50);
 }
@@ -5830,7 +5816,6 @@ static void cik_wait_for_rlc_serdes(struct radeon_device 
*rdev)
u32 i, j, k;
u32 mask;
 
-   mutex_lock(>grbm_idx_mutex);
for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
cik_select_se_sh(rdev, i, j);
@@ -5842,7 +5827,6 @@ static void cik_wait_for_rlc_serdes(struct radeon_device 
*rdev)
}
}
cik_select_se_sh(rdev, 0x, 0x);
-   mutex_unlock(>grbm_idx_mutex);
 
mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | 
TC1_MASTER_BUSY;
for (k = 0; k < rdev->usec_timeout; k++) {
@@ -5977,12 +5961,10 @@ static int cik_rlc_resume(struct radeon_device *rdev)
WREG32(RLC_LB_CNTR_INIT, 0);
WREG32(RLC_LB_CNTR_MAX, 0x8000);
 
-   mutex_lock(>grbm_idx_mutex);
cik_select_se_sh(rdev, 0x, 0x);
WREG32(RLC_LB_INIT_CU_MASK, 0x);
WREG32(RLC_LB_PARAMS, 0x00600408);
WREG32(RLC_LB_CNTL, 0x8004);
-   mutex_unlock(>grbm_idx_mutex);
 
WREG32(RLC_MC_CNTL, 0);
WREG32(RLC_UCODE_CNTL, 0);
@@ -6049,13 +6031,11 @@ static void cik_enable_cgcg(struct radeon_device *rdev, 
bool enable)
 
tmp = cik_halt_rlc(rdev);
 
-   mutex_lock(>grbm_idx_mutex);
cik_select_se_sh(rdev, 0x, 0x);
WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0x);
WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0x);
tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
WREG32(RLC_SERDES_WR_CTRL, tmp2);
-   mutex_unlock(>grbm_idx_mutex);
 
cik_update_rlc(rdev, tmp);
 
@@ -6098,13 +6078,11 @@ static void cik_enable_mgcg(struct radeon_device *rdev, 
bool enable)
 
tmp = 

[PATCH 5/5] drm/radeon: Remove KFD_CIK_SDMA_QUEUE_OFFSET

[Michel Dänzer]

From: Michel Dänzer 

Leftover from recently removed amdkfd support.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/cik_reg.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index 4e883fdc59d8..318377df09ef 100644
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -147,8 +147,6 @@
 
 #define CIK_LB_DESKTOP_HEIGHT 0x6b0c
 
-#define KFD_CIK_SDMA_QUEUE_OFFSET  0x200
-
 #define SQ_IND_INDEX   0x8DE0
 #define SQ_CMD 0x8DEC
 #define SQ_IND_DATA0x8DE4
-- 
2.15.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] Revert "drm/radeon/cik: Don't touch int of pipes 1-7"

[Michel Dänzer]

From: Michel Dänzer 

This reverts commit 28b57b856b635ea0d44f1281e2efdc963c100ea3. radeon
doesn't support amdkfd anymore, so the latter doesn't set up interrupts
for pipes 1-7.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/cik.c | 71 +++-
 1 file changed, 70 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 33fdf085a52e..160d697fceeb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7048,7 +7048,8 @@ static int cik_irq_init(struct radeon_device *rdev)
 int cik_irq_set(struct radeon_device *rdev)
 {
u32 cp_int_cntl;
-   u32 cp_m1p0;
+   u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
+   u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
u32 grbm_int_cntl = 0;
@@ -7081,6 +7082,13 @@ int cik_irq_set(struct radeon_device *rdev)
dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
 
cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+   cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
 
/* enable CP interrupts on all rings */
if (atomic_read(>irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
@@ -7095,6 +7103,33 @@ int cik_irq_set(struct radeon_device *rdev)
case 0:
cp_m1p0 |= TIME_STAMP_INT_ENABLE;
break;
+   case 1:
+   cp_m1p1 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 2:
+   cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 3:
+   cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   default:
+   DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe 
%d\n", ring->pipe);
+   break;
+   }
+   } else if (ring->me == 2) {
+   switch (ring->pipe) {
+   case 0:
+   cp_m2p0 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 1:
+   cp_m2p1 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 2:
+   cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 3:
+   cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+   break;
default:
DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe 
%d\n", ring->pipe);
break;
@@ -7111,6 +7146,33 @@ int cik_irq_set(struct radeon_device *rdev)
case 0:
cp_m1p0 |= TIME_STAMP_INT_ENABLE;
break;
+   case 1:
+   cp_m1p1 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 2:
+   cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 3:
+   cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   default:
+   DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe 
%d\n", ring->pipe);
+   break;
+   }
+   } else if (ring->me == 2) {
+   switch (ring->pipe) {
+   case 0:
+   cp_m2p0 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 1:
+   cp_m2p1 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 2:
+   cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+   break;
+   case 3:
+   cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+   break;
default:

[PATCH 2/5] Revert "drm/radeon: Report doorbell configuration to amdkfd"

[Michel Dänzer]

From: Michel Dänzer 

This reverts commit ebff8453d3a57a2405c4d96d9f9c4f4acc7d4d79. Unused
since amdkfd is no longer supported with radeon.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/radeon.h|  4 
 drivers/gpu/drm/radeon/radeon_device.c | 31 ---
 2 files changed, 35 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b808c3bdcfd8..d34887873dea 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -731,10 +731,6 @@ struct radeon_doorbell {
 
 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
-void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
- phys_addr_t *aperture_base,
- size_t *aperture_size,
- size_t *start_offset);
 
 /*
  * IRQS.
diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
b/drivers/gpu/drm/radeon/radeon_device.c
index e0b9fa4aaa9f..8d3e3d2e0090 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -392,37 +392,6 @@ void radeon_doorbell_free(struct radeon_device *rdev, u32 
doorbell)
__clear_bit(doorbell, rdev->doorbell.used);
 }
 
-/**
- * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
- *setup KFD
- *
- * @rdev: radeon_device pointer
- * @aperture_base: output returning doorbell aperture base physical address
- * @aperture_size: output returning doorbell aperture size in bytes
- * @start_offset: output returning # of doorbell bytes reserved for radeon.
- *
- * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
- * takes doorbells required for its own rings and reports the setup to KFD.
- * Radeon reserved doorbells are at the start of the doorbell aperture.
- */
-void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
- phys_addr_t *aperture_base,
- size_t *aperture_size,
- size_t *start_offset)
-{
-   /* The first num_doorbells are used by radeon.
-* KFD takes whatever's left in the aperture. */
-   if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
-   *aperture_base = rdev->doorbell.base;
-   *aperture_size = rdev->doorbell.size;
-   *start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
-   } else {
-   *aperture_base = 0;
-   *aperture_size = 0;
-   *start_offset = 0;
-   }
-}
-
 /*
  * radeon_wb_*()
  * Writeback is the the method by which the the GPU updates special pages
-- 
2.15.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] Revert "drm/radeon: reduce number of free VMIDs and pipes in KV"

[Michel Dänzer]

From: Michel Dänzer 

This reverts the remaining changes of commit
62a7b7fbd08ef745bb51e8728e89125a0ba6327e, because radeon doesn't support
amdkfd anymore. The number of VMIDs was already changed back when amdkfd
support was removed.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/radeon/cik.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 160d697fceeb..d3045a371a55 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4418,11 +4418,12 @@ static int cik_mec_init(struct radeon_device *rdev)
/*
 * KV:2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
-* Nonetheless, we assign only 1 pipe because all other pipes will
-* be handled by KFD
 */
-   rdev->mec.num_mec = 1;
-   rdev->mec.num_pipe = 1;
+   if (rdev->family == CHIP_KAVERI)
+   rdev->mec.num_mec = 2;
+   else
+   rdev->mec.num_mec = 1;
+   rdev->mec.num_pipe = 4;
rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
 
if (rdev->mec.hpd_eop_obj == NULL) {
@@ -4565,8 +4566,11 @@ static int cik_cp_compute_resume(struct radeon_device 
*rdev)
/* init the pipes */
mutex_lock(>srbm_mutex);
 
-   for (i = 0; i < rdev->mec.num_pipe; ++i) {
-   cik_srbm_select(rdev, 0, i, 0, 0);
+   for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) {
+   int me = (i < 4) ? 1 : 2;
+   int pipe = (i < 4) ? i : (i - 4);
+
+   cik_srbm_select(rdev, me, pipe, 0, 0);
 
eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 
2) ;
/* write the EOP addr */
@@ -4583,6 +4587,7 @@ static int cik_cp_compute_resume(struct radeon_device 
*rdev)
WREG32(CP_HPD_EOP_CONTROL, tmp);
 
}
+   cik_srbm_select(rdev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
 
/* init the queues.  Just two for now. */
-- 
2.15.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Christian König]

Am 29.11.2017 um 17:52 schrieb Li, Samuel:

To explain the operations a little bit, the tests include repeated testing of 
the following sequences,
91 const int sequences[4][4] = {
92 { STEP_MMAP, STEP_FAULT, STEP_FLIP, STEP_DRAW },
93 { STEP_MMAP, STEP_FLIP, STEP_DRAW, STEP_SKIP },
94 { STEP_MMAP, STEP_DRAW, STEP_FLIP, STEP_SKIP },
95 { STEP_FLIP, STEP_MMAP, STEP_DRAW, STEP_SKIP },
96 };
Here STEP_MMAP includes prime_mmap() and begin_cpu_access(). STEP_DRAW includes 
repeated cpu reads/writes.
It looks to me the dma_buf has to be pinned to gtt here, to prevent it being 
pinned back by STEP_FLIP before drawing.


When STEP_FLIP needs the BO in VRAM it would fail when we pin it to GTT 
while it is mapped and that is not something we can do.


What we can do is migrate the BO into GTT when we mmap it and migrate it 
back to VRAM on demand when it is pinned.


When scanning out from GTT is implemented the flip will then 
automatically pin it to GTT instead of VRAM.



I've send out a WIP branch a for this a few weeks ago, but haven't worked on
this in a while. BTW it is only supported on Carizzo and Raven.

Can you show me the branch? Looks like we need to get if finished.


The amdgpu part was already done and is also already committed IIRC 
(that was only a bunch of bugs fixes anyway).


What's missing is the DC part, they need to do some extra bandwith 
calculation when scanning out from GTT is enabled and that was 
problematic to always activate.


You need to ping Harry about the status there.

Christian.



Sam





-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 29, 2017 10:01 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma
buf.


What is the concern for scanning out from GTT on APUs?

It's simply not implemented yet. You need quite a bunch of different setup in
DC for this to work.

I've send out a WIP branch a for this a few weeks ago, but haven't worked on
this in a while. BTW it is only supported on Carizzo and Raven.

But even then pinning a BO to GTT for this would still be a no-go. We could
just avoid the copy on scanout when the BO is already inside GTT because of
the CPU access.

In general we should rather work on this as Michel described and avoid
creating the BO in VRAM in the first place if possible.

Regards,
Christian.

Am 29.11.2017 um 15:56 schrieb Li, Samuel:

One major purpose of the ChromeOS mmap_test is to avoid buffer copying.

What is the concern for scanning out from GTT on APUs?

Sam


-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 29, 2017 9:54 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
dma buf.

And exactly that's the reason why it is a no-go.

Scanning out from GTT isn't supported at the moment.

Christian.

Am 29.11.2017 um 15:48 schrieb Li, Samuel:

Actually it needs to be pinned here, since otherwise page flip will
pin it into

vram.

SAm



-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Wednesday, November 29, 2017 4:39 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
dma buf.

Am 29.11.2017 um 01:20 schrieb Samuel Li:

To improve cpu read performance. This is implemented for APUs

currently.

And once more a NAK for this approach.

What we could do is migrate the BO to GTT during mmap, but pinning
it is out of question.

Regards,
Christian.


Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108

++

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
 5 files changed, 126 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..193db70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct

drm_device *dev,

 struct dma_buf *amdgpu_gem_prime_export(struct drm_device

*dev,

struct drm_gem_object

*gobj,

int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct

drm_device

*dev,

+   struct dma_buf *dma_buf);
 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
 struct reservation_object *amdgpu_gem_prime_res_obj(struct
drm_gem_object *); diff --git

Re: [PATCH] drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

[Deucher, Alexander]

I'll add it to my -fixes branch.


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Wednesday, November 29, 2017 11:57:26 AM
To: Oded Gabbay
Cc: Deucher, Alexander; deathsim...@vodafone.de; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

On 2017-11-29 04:23 PM, Oded Gabbay wrote:
> VMIDs 8-16 in Kaveri were reserved for use by the amdkfd driver.
> Because we removed amdkfd support from radeon, those VMIDs are now
> used by radeon and are initialized by radeon.
>
> This patch removes the function that initialized those VMIDs for amdkfd
> use.
> This initialization overridden the radeon initialization and caused GPU
> faults and GUI crashed.
>
> This bug was found by Michel Dänzer.
>
> Signed-off-by: Oded Gabbay 

Pushed to our internal amd-staging-drm-next branch, with some
modifications to the tags in the commit log, thanks!


Alex, this needs to go into 4.15.


--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

[Michel Dänzer]

On 2017-11-29 04:23 PM, Oded Gabbay wrote:
> VMIDs 8-16 in Kaveri were reserved for use by the amdkfd driver.
> Because we removed amdkfd support from radeon, those VMIDs are now
> used by radeon and are initialized by radeon.
> 
> This patch removes the function that initialized those VMIDs for amdkfd
> use.
> This initialization overridden the radeon initialization and caused GPU
> faults and GUI crashed.
> 
> This bug was found by Michel Dänzer.
> 
> Signed-off-by: Oded Gabbay 

Pushed to our internal amd-staging-drm-next branch, with some
modifications to the tags in the commit log, thanks!


Alex, this needs to go into 4.15.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Li, Samuel]

To explain the operations a little bit, the tests include repeated testing of 
the following sequences,
91 const int sequences[4][4] = {
92 { STEP_MMAP, STEP_FAULT, STEP_FLIP, STEP_DRAW },
93 { STEP_MMAP, STEP_FLIP, STEP_DRAW, STEP_SKIP },
94 { STEP_MMAP, STEP_DRAW, STEP_FLIP, STEP_SKIP },
95 { STEP_FLIP, STEP_MMAP, STEP_DRAW, STEP_SKIP },
96 };
Here STEP_MMAP includes prime_mmap() and begin_cpu_access(). STEP_DRAW includes 
repeated cpu reads/writes.
It looks to me the dma_buf has to be pinned to gtt here, to prevent it being 
pinned back by STEP_FLIP before drawing.

> I've send out a WIP branch a for this a few weeks ago, but haven't worked on
> this in a while. BTW it is only supported on Carizzo and Raven.
Can you show me the branch? Looks like we need to get if finished.

Sam




> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, November 29, 2017 10:01 AM
> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma
> buf.
> 
> > What is the concern for scanning out from GTT on APUs?
> It's simply not implemented yet. You need quite a bunch of different setup in
> DC for this to work.
> 
> I've send out a WIP branch a for this a few weeks ago, but haven't worked on
> this in a while. BTW it is only supported on Carizzo and Raven.
> 
> But even then pinning a BO to GTT for this would still be a no-go. We could
> just avoid the copy on scanout when the BO is already inside GTT because of
> the CPU access.
> 
> In general we should rather work on this as Michel described and avoid
> creating the BO in VRAM in the first place if possible.
> 
> Regards,
> Christian.
> 
> Am 29.11.2017 um 15:56 schrieb Li, Samuel:
> > One major purpose of the ChromeOS mmap_test is to avoid buffer copying.
> What is the concern for scanning out from GTT on APUs?
> >
> > Sam
> >
> >> -Original Message-
> >> From: Koenig, Christian
> >> Sent: Wednesday, November 29, 2017 9:54 AM
> >> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> >> Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
> >> dma buf.
> >>
> >> And exactly that's the reason why it is a no-go.
> >>
> >> Scanning out from GTT isn't supported at the moment.
> >>
> >> Christian.
> >>
> >> Am 29.11.2017 um 15:48 schrieb Li, Samuel:
> >>> Actually it needs to be pinned here, since otherwise page flip will
> >>> pin it into
> >> vram.
> >>> SAm
> >>>
> >>>
>  -Original Message-
>  From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
>  Sent: Wednesday, November 29, 2017 4:39 AM
>  To: Li, Samuel ; amd-gfx@lists.freedesktop.org
>  Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
>  dma buf.
> 
>  Am 29.11.2017 um 01:20 schrieb Samuel Li:
> > To improve cpu read performance. This is implemented for APUs
> >> currently.
>  And once more a NAK for this approach.
> 
>  What we could do is migrate the BO to GTT during mmap, but pinning
>  it is out of question.
> 
>  Regards,
>  Christian.
> 
> > Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108
>  ++
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
> > 5 files changed, 126 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index f8657c3..193db70 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct
>  drm_device *dev,
> > struct dma_buf *amdgpu_gem_prime_export(struct drm_device
> *dev,
> > struct drm_gem_object
> *gobj,
> > int flags);
> > +struct drm_gem_object *amdgpu_gem_prime_import(struct
> >> drm_device
>  *dev,
> > +   struct dma_buf *dma_buf);
> > int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
> > void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
> > struct reservation_object *amdgpu_gem_prime_res_obj(struct
> > drm_gem_object *); diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index d704a45..b5483e4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -147,6 

Re: [PATCH] drm/amdgpu: fix amdgpu_sync_resv v2

[Andres Rodriguez]

On 2017-11-29 08:10 AM, Christian König wrote:

Hi Andres,

just a gentle ping to see if you have noticed this.

Thanks,
Christian.

Am 24.11.2017 um 13:49 schrieb Christian König:

Fixes a bug introduced by AMDGPU_GEM_CREATE_EXPLICIT_SYNC. We still need
to wait for pipelined moves in the shared fences list.

v2: fix typo

Signed-off-by: Christian König 


Hi Christian,

Sorry, last few weeks have been a little hectic.

This patch looks good to me. You can add:
Reviewed-by: Andres Rodriguez 

The steamvr explicit sync use cases are untouched by this patch, so we 
should be good on that front as well.


Kind Regards,
Andres


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 ++-
  1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c

index a4bf21f8f1c1..bbbc40d630a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -191,9 +191,6 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
  f = reservation_object_get_excl(resv);
  r = amdgpu_sync_fence(adev, sync, f);
-    if (explicit_sync)
-    return r;
-
  flist = reservation_object_get_list(resv);
  if (!flist || r)
  return r;
@@ -212,11 +209,11 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
   (fence_owner == AMDGPU_FENCE_OWNER_VM)))
  continue;
-    /* Ignore fence from the same owner as
+    /* Ignore fence from the same owner and explicit one as
   * long as it isn't undefined.
   */
  if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
-    fence_owner == owner)
+    (fence_owner == owner || explicit_sync))
  continue;
  }



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 20/43] drm/amd/display: Add optimized_required flag

[Leo Li]

On 2017-11-23 02:52 PM, Harry Wentland wrote:

Signed-off-by: Harry Wentland 


Reviewed-by: Leo (Sunpeng) Li 


---
  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
  drivers/gpu/drm/amd/display/dc/dc.h  | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 98eff80acffa..19d96aeaa113 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -788,6 +788,8 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
dc->hwss.disable_plane(dc, 
>res_ctx.pipe_ctx[i]);
}
  
+	dc->optimized_required = false;

+
/* 3rd param should be true, temp w/a for RV*/
  #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < 
DCN_VERSION_1_0);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 71f1802a25d7..9fbcfd7b5f8d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -250,6 +250,8 @@ struct dc {
 */
struct dm_pp_display_configuration prev_display_config;
  
+	bool optimized_required;

+
/* FBC compressor */
  #if defined(CONFIG_DRM_AMD_DC_FBC)
struct compressor *fbc_compressor;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

[Christian König]

Am 29.11.2017 um 16:23 schrieb Oded Gabbay:

VMIDs 8-16 in Kaveri were reserved for use by the amdkfd driver.
Because we removed amdkfd support from radeon, those VMIDs are now
used by radeon and are initialized by radeon.

This patch removes the function that initialized those VMIDs for amdkfd
use.
This initialization overridden the radeon initialization and caused GPU
faults and GUI crashed.

This bug was found by Michel Dänzer.

Signed-off-by: Oded Gabbay 


Acked-by: Christian König 


---
  drivers/gpu/drm/radeon/cik.c | 24 
  1 file changed, 24 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 898f9a0..a651191 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5451,28 +5451,6 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
WREG32(VM_INVALIDATE_REQUEST, 0x1);
  }
  
-static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)

-{
-   int i;
-   uint32_t sh_mem_bases, sh_mem_config;
-
-   sh_mem_bases = 0x6000 | 0x6000 << 16;
-   sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-   sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
-
-   mutex_lock(>srbm_mutex);
-   for (i = 8; i < 16; i++) {
-   cik_srbm_select(rdev, 0, 0, 0, i);
-   /* CP and shaders */
-   WREG32(SH_MEM_CONFIG, sh_mem_config);
-   WREG32(SH_MEM_APE1_BASE, 1);
-   WREG32(SH_MEM_APE1_LIMIT, 0);
-   WREG32(SH_MEM_BASES, sh_mem_bases);
-   }
-   cik_srbm_select(rdev, 0, 0, 0, 0);
-   mutex_unlock(>srbm_mutex);
-}
-
  /**
   * cik_pcie_gart_enable - gart enable
   *
@@ -5586,8 +5564,6 @@ static int cik_pcie_gart_enable(struct radeon_device 
*rdev)
cik_srbm_select(rdev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
  
-	cik_pcie_init_compute_vmid(rdev);

-
cik_pcie_gart_tlb_flush(rdev);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 (unsigned)(rdev->mc.gtt_size >> 20),


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd

[Oded Gabbay]

VMIDs 8-16 in Kaveri were reserved for use by the amdkfd driver.
Because we removed amdkfd support from radeon, those VMIDs are now
used by radeon and are initialized by radeon.

This patch removes the function that initialized those VMIDs for amdkfd
use.
This initialization overridden the radeon initialization and caused GPU
faults and GUI crashed.

This bug was found by Michel Dänzer.

Signed-off-by: Oded Gabbay 
---
 drivers/gpu/drm/radeon/cik.c | 24 
 1 file changed, 24 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 898f9a0..a651191 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5451,28 +5451,6 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
WREG32(VM_INVALIDATE_REQUEST, 0x1);
 }
 
-static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)
-{
-   int i;
-   uint32_t sh_mem_bases, sh_mem_config;
-
-   sh_mem_bases = 0x6000 | 0x6000 << 16;
-   sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-   sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
-
-   mutex_lock(>srbm_mutex);
-   for (i = 8; i < 16; i++) {
-   cik_srbm_select(rdev, 0, 0, 0, i);
-   /* CP and shaders */
-   WREG32(SH_MEM_CONFIG, sh_mem_config);
-   WREG32(SH_MEM_APE1_BASE, 1);
-   WREG32(SH_MEM_APE1_LIMIT, 0);
-   WREG32(SH_MEM_BASES, sh_mem_bases);
-   }
-   cik_srbm_select(rdev, 0, 0, 0, 0);
-   mutex_unlock(>srbm_mutex);
-}
-
 /**
  * cik_pcie_gart_enable - gart enable
  *
@@ -5586,8 +5564,6 @@ static int cik_pcie_gart_enable(struct radeon_device 
*rdev)
cik_srbm_select(rdev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
 
-   cik_pcie_init_compute_vmid(rdev);
-
cik_pcie_gart_tlb_flush(rdev);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 (unsigned)(rdev->mc.gtt_size >> 20),
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Christian König]

What is the concern for scanning out from GTT on APUs?
It's simply not implemented yet. You need quite a bunch of different 
setup in DC for this to work.


I've send out a WIP branch a for this a few weeks ago, but haven't 
worked on this in a while. BTW it is only supported on Carizzo and Raven.


But even then pinning a BO to GTT for this would still be a no-go. We 
could just avoid the copy on scanout when the BO is already inside GTT 
because of the CPU access.


In general we should rather work on this as Michel described and avoid 
creating the BO in VRAM in the first place if possible.


Regards,
Christian.

Am 29.11.2017 um 15:56 schrieb Li, Samuel:

One major purpose of the ChromeOS mmap_test is to avoid buffer copying. What is 
the concern for scanning out from GTT on APUs?

Sam


-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 29, 2017 9:54 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma
buf.

And exactly that's the reason why it is a no-go.

Scanning out from GTT isn't supported at the moment.

Christian.

Am 29.11.2017 um 15:48 schrieb Li, Samuel:

Actually it needs to be pinned here, since otherwise page flip will pin it into

vram.

SAm



-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Wednesday, November 29, 2017 4:39 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
dma buf.

Am 29.11.2017 um 01:20 schrieb Samuel Li:

To improve cpu read performance. This is implemented for APUs

currently.

And once more a NAK for this approach.

What we could do is migrate the BO to GTT during mmap, but pinning it
is out of question.

Regards,
Christian.


Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108

++

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
5 files changed, 126 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..193db70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct

drm_device *dev,

struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
struct drm_gem_object *gobj,
int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct

drm_device

*dev,

+   struct dma_buf *dma_buf);
int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
struct reservation_object *amdgpu_gem_prime_res_obj(struct
drm_gem_object *); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index d704a45..b5483e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -147,6 +147,7 @@ int amdgpu_crtc_page_flip_target(struct

drm_crtc

*crtc,

struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+   bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev-
flags
+& AMD_IS_APU);
struct amdgpu_framebuffer *old_amdgpu_fb;
struct amdgpu_framebuffer *new_amdgpu_fb;
struct drm_gem_object *obj;
@@ -190,8 +191,13 @@ int amdgpu_crtc_page_flip_target(struct
drm_crtc *crtc,

r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM,

);

if (unlikely(r != 0)) {
-   DRM_ERROR("failed to pin new abo buffer before flip\n");
-   goto unreserve;
+   /* latest APUs support gtt scan out */
+   if (gtt_scannable)
+   r = amdgpu_bo_pin(new_abo,

AMDGPU_GEM_DOMAIN_GTT, );

+   if (unlikely(r != 0)) {
+   DRM_ERROR("failed to pin new abo buffer before

flip\n");

+   goto unreserve;
+   }
}

r = reservation_object_get_fences_rcu(new_abo->tbo.resv,
>excl, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 31383e0..df30b08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -868,7 +868,7 @@ static struct drm_driver kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = amdgpu_gem_prime_export,
-   .gem_prime_import 

RE: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Li, Samuel]

One major purpose of the ChromeOS mmap_test is to avoid buffer copying. What is 
the concern for scanning out from GTT on APUs?

Sam

> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, November 29, 2017 9:54 AM
> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma
> buf.
> 
> And exactly that's the reason why it is a no-go.
> 
> Scanning out from GTT isn't supported at the moment.
> 
> Christian.
> 
> Am 29.11.2017 um 15:48 schrieb Li, Samuel:
> > Actually it needs to be pinned here, since otherwise page flip will pin it 
> > into
> vram.
> >
> > SAm
> >
> >
> >> -Original Message-
> >> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> >> Sent: Wednesday, November 29, 2017 4:39 AM
> >> To: Li, Samuel ; amd-gfx@lists.freedesktop.org
> >> Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses
> >> dma buf.
> >>
> >> Am 29.11.2017 um 01:20 schrieb Samuel Li:
> >>> To improve cpu read performance. This is implemented for APUs
> currently.
> >> And once more a NAK for this approach.
> >>
> >> What we could do is migrate the BO to GTT during mmap, but pinning it
> >> is out of question.
> >>
> >> Regards,
> >> Christian.
> >>
> >>> Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108
> >> ++
> >>>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
> >>>5 files changed, 126 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index f8657c3..193db70 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct
> >> drm_device *dev,
> >>>struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> >>>   struct drm_gem_object *gobj,
> >>>   int flags);
> >>> +struct drm_gem_object *amdgpu_gem_prime_import(struct
> drm_device
> >> *dev,
> >>> + struct dma_buf *dma_buf);
> >>>int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
> >>>void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
> >>>struct reservation_object *amdgpu_gem_prime_res_obj(struct
> >>> drm_gem_object *); diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> index d704a45..b5483e4 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> @@ -147,6 +147,7 @@ int amdgpu_crtc_page_flip_target(struct
> drm_crtc
> >> *crtc,
> >>>   struct drm_device *dev = crtc->dev;
> >>>   struct amdgpu_device *adev = dev->dev_private;
> >>>   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> >>> + bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev-
> >>> flags
> >>> +& AMD_IS_APU);
> >>>   struct amdgpu_framebuffer *old_amdgpu_fb;
> >>>   struct amdgpu_framebuffer *new_amdgpu_fb;
> >>>   struct drm_gem_object *obj;
> >>> @@ -190,8 +191,13 @@ int amdgpu_crtc_page_flip_target(struct
> >>> drm_crtc *crtc,
> >>>
> >>>   r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM,
> >> );
> >>>   if (unlikely(r != 0)) {
> >>> - DRM_ERROR("failed to pin new abo buffer before flip\n");
> >>> - goto unreserve;
> >>> + /* latest APUs support gtt scan out */
> >>> + if (gtt_scannable)
> >>> + r = amdgpu_bo_pin(new_abo,
> >> AMDGPU_GEM_DOMAIN_GTT, );
> >>> + if (unlikely(r != 0)) {
> >>> + DRM_ERROR("failed to pin new abo buffer before
> >> flip\n");
> >>> + goto unreserve;
> >>> + }
> >>>   }
> >>>
> >>>   r = reservation_object_get_fences_rcu(new_abo->tbo.resv,
> >>> >excl, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> index 31383e0..df30b08 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> @@ -868,7 +868,7 @@ static struct drm_driver kms_driver = {
> >>>   .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> >>>   .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> >>>   .gem_prime_export = amdgpu_gem_prime_export,
> >>> - .gem_prime_import = drm_gem_prime_import,
> >>> + .gem_prime_import = amdgpu_gem_prime_import,
> >>>   .gem_prime_pin = amdgpu_gem_prime_pin,
> >>>   .gem_prime_unpin = 

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Michel Dänzer]

On 2017-11-29 03:40 PM, Oded Gabbay wrote:
> On Wed, Nov 29, 2017 at 2:31 PM, Oded Gabbay  wrote:
>> On Wed, Nov 29, 2017 at 1:16 PM, Michel Dänzer  wrote:
>>> On 2017-11-01 09:31 AM, Oded Gabbay wrote:
 ok, taken to -next.
>>>
>>> This change broke the radeon driver on my Kaveri laptop. The gdm login
>>> screen works, but logging into the GNOME on Xorg session quickly results
>>> in a GPU hang and associated badness, see the attached dmesg.
>>>
>>> Reverting this change on top of drm-next makes it work again.
>>>
>>> On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
>>> reduce number of free VMIDs and pipes in KV") and 28b57b856b63
>>> ("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.
>>>
>>> Any ideas for what else is missing?
>>>
>>> Note that the amdkfd driver isn't actually active anyway, because I'm
>>> disabling the IOMMU. Is it possible that it's still doing or triggering
>>> some needed HW setup before it bails in that case?
>>>
>>>
>>> P.S. Assuming we can fix this without reverting, maybe we could also
>>> remove rdev->grbm_idx_mutex again?
>>>
>>> --
>>> Earthling Michel Dänzer   |   http://www.amd.com
>>> Libre software enthusiast | Mesa and X developer
>>
>> Hi Michel,
>> Even without IOMMU, amdkfd will initialize the module and internal
>> structures per device, up to the point where it tries to register a
>> callback with the iommu driver.
>> If IOMMU is disabled, it will fail then with the following error
>> message (in dmesg): "error getting iommu info. is the iommu enabled?"
>>
>> Having said that, it doesn't initialize anything in the device H/W
>> itself, so I find this very weird.
>>
>> I looked at the patch itself again and I don't see anything suspicious.
>>
>> I'll try to resurrect my Kaveri machine to check this, but it will
>> take some time.
>>
>> Oded
> 
> Any chance that the increase of VMIDs from 8 to 16 somehow (although I
> don't know how) caused this problem ?
> The desktop gui also didn't work for me, but when I changed the VMID
> number back to 8 (in cik.c) the gui worked again.
> 
> Michel, could you try this as well ?

Yeah, that also occurred to me in the meantime, and I can confirm your
findings.

My guess right now is that it's related to cik_pcie_init_compute_vmid.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Christian König]

And exactly that's the reason why it is a no-go.

Scanning out from GTT isn't supported at the moment.

Christian.

Am 29.11.2017 um 15:48 schrieb Li, Samuel:

Actually it needs to be pinned here, since otherwise page flip will pin it into 
vram.

SAm



-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Wednesday, November 29, 2017 4:39 AM
To: Li, Samuel ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma
buf.

Am 29.11.2017 um 01:20 schrieb Samuel Li:

To improve cpu read performance. This is implemented for APUs currently.

And once more a NAK for this approach.

What we could do is migrate the BO to GTT during mmap, but pinning it is out
of question.

Regards,
Christian.


Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
   drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108

++

   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
   5 files changed, 126 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..193db70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct

drm_device *dev,

   struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
struct drm_gem_object *gobj,
int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device

*dev,

+   struct dma_buf *dma_buf);
   int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
   void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
   struct reservation_object *amdgpu_gem_prime_res_obj(struct
drm_gem_object *); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index d704a45..b5483e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -147,6 +147,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc

*crtc,

struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+   bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev-
flags
+& AMD_IS_APU);
struct amdgpu_framebuffer *old_amdgpu_fb;
struct amdgpu_framebuffer *new_amdgpu_fb;
struct drm_gem_object *obj;
@@ -190,8 +191,13 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc
*crtc,

r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM,

);

if (unlikely(r != 0)) {
-   DRM_ERROR("failed to pin new abo buffer before flip\n");
-   goto unreserve;
+   /* latest APUs support gtt scan out */
+   if (gtt_scannable)
+   r = amdgpu_bo_pin(new_abo,

AMDGPU_GEM_DOMAIN_GTT, );

+   if (unlikely(r != 0)) {
+   DRM_ERROR("failed to pin new abo buffer before

flip\n");

+   goto unreserve;
+   }
}

r = reservation_object_get_fences_rcu(new_abo->tbo.resv,
>excl, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 31383e0..df30b08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -868,7 +868,7 @@ static struct drm_driver kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = amdgpu_gem_prime_export,
-   .gem_prime_import = drm_gem_prime_import,
+   .gem_prime_import = amdgpu_gem_prime_import,
.gem_prime_pin = amdgpu_gem_prime_pin,
.gem_prime_unpin = amdgpu_gem_prime_unpin,
.gem_prime_res_obj = amdgpu_gem_prime_res_obj, diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index ae9c106..9e1424d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -164,6 +164,82 @@ struct reservation_object

*amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)

return bo->tbo.resv;
   }

+static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,

enum

+dma_data_direction direction) {
+   struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   long i, ret = 0;
+   unsigned old_count;
+   bool reads = (direction == DMA_BIDIRECTIONAL || direction ==

DMA_FROM_DEVICE);

+   bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev-
flags & 

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Christian König]

Am 29.11.2017 um 15:40 schrieb Oded Gabbay:

On Wed, Nov 29, 2017 at 2:31 PM, Oded Gabbay  wrote:

On Wed, Nov 29, 2017 at 1:16 PM, Michel Dänzer  wrote:

On 2017-11-01 09:31 AM, Oded Gabbay wrote:

ok, taken to -next.

This change broke the radeon driver on my Kaveri laptop. The gdm login
screen works, but logging into the GNOME on Xorg session quickly results
in a GPU hang and associated badness, see the attached dmesg.

Reverting this change on top of drm-next makes it work again.

On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
reduce number of free VMIDs and pipes in KV") and 28b57b856b63
("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.

Any ideas for what else is missing?

Note that the amdkfd driver isn't actually active anyway, because I'm
disabling the IOMMU. Is it possible that it's still doing or triggering
some needed HW setup before it bails in that case?


P.S. Assuming we can fix this without reverting, maybe we could also
remove rdev->grbm_idx_mutex again?

--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer

Hi Michel,
Even without IOMMU, amdkfd will initialize the module and internal
structures per device, up to the point where it tries to register a
callback with the iommu driver.
If IOMMU is disabled, it will fail then with the following error
message (in dmesg): "error getting iommu info. is the iommu enabled?"

Having said that, it doesn't initialize anything in the device H/W
itself, so I find this very weird.

I looked at the patch itself again and I don't see anything suspicious.

I'll try to resurrect my Kaveri machine to check this, but it will
take some time.

Oded

Any chance that the increase of VMIDs from 8 to 16 somehow (although I
don't know how) caused this problem ?


Yeah, that's my first suspicion as well. We haven't used the higher 
VMIDs in a while on radeon and so there could be bugs in the code.



The desktop gui also didn't work for me, but when I changed the VMID
number back to 8 (in cik.c) the gui worked again.


Good to know, going to test this as well later today.

Regards,
Christian.



Michel, could you try this as well ?

Thanks,
Oded


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Oded Gabbay]

On Wed, Nov 29, 2017 at 2:31 PM, Oded Gabbay  wrote:
> On Wed, Nov 29, 2017 at 1:16 PM, Michel Dänzer  wrote:
>> On 2017-11-01 09:31 AM, Oded Gabbay wrote:
>>> ok, taken to -next.
>>
>> This change broke the radeon driver on my Kaveri laptop. The gdm login
>> screen works, but logging into the GNOME on Xorg session quickly results
>> in a GPU hang and associated badness, see the attached dmesg.
>>
>> Reverting this change on top of drm-next makes it work again.
>>
>> On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
>> reduce number of free VMIDs and pipes in KV") and 28b57b856b63
>> ("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.
>>
>> Any ideas for what else is missing?
>>
>> Note that the amdkfd driver isn't actually active anyway, because I'm
>> disabling the IOMMU. Is it possible that it's still doing or triggering
>> some needed HW setup before it bails in that case?
>>
>>
>> P.S. Assuming we can fix this without reverting, maybe we could also
>> remove rdev->grbm_idx_mutex again?
>>
>> --
>> Earthling Michel Dänzer   |   http://www.amd.com
>> Libre software enthusiast | Mesa and X developer
>
> Hi Michel,
> Even without IOMMU, amdkfd will initialize the module and internal
> structures per device, up to the point where it tries to register a
> callback with the iommu driver.
> If IOMMU is disabled, it will fail then with the following error
> message (in dmesg): "error getting iommu info. is the iommu enabled?"
>
> Having said that, it doesn't initialize anything in the device H/W
> itself, so I find this very weird.
>
> I looked at the patch itself again and I don't see anything suspicious.
>
> I'll try to resurrect my Kaveri machine to check this, but it will
> take some time.
>
> Oded

Any chance that the increase of VMIDs from 8 to 16 somehow (although I
don't know how) caused this problem ?
The desktop gui also didn't work for me, but when I changed the VMID
number back to 8 (in cik.c) the gui worked again.

Michel, could you try this as well ?

Thanks,
Oded
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Christian König]

Am 29.11.2017 um 13:31 schrieb Oded Gabbay:

On Wed, Nov 29, 2017 at 1:16 PM, Michel Dänzer  wrote:

On 2017-11-01 09:31 AM, Oded Gabbay wrote:

ok, taken to -next.

This change broke the radeon driver on my Kaveri laptop. The gdm login
screen works, but logging into the GNOME on Xorg session quickly results
in a GPU hang and associated badness, see the attached dmesg.

Reverting this change on top of drm-next makes it work again.

On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
reduce number of free VMIDs and pipes in KV") and 28b57b856b63
("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.

Any ideas for what else is missing?

Note that the amdkfd driver isn't actually active anyway, because I'm
disabling the IOMMU. Is it possible that it's still doing or triggering
some needed HW setup before it bails in that case?


P.S. Assuming we can fix this without reverting, maybe we could also
remove rdev->grbm_idx_mutex again?

--
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer

Hi Michel,
Even without IOMMU, amdkfd will initialize the module and internal
structures per device, up to the point where it tries to register a
callback with the iommu driver.
If IOMMU is disabled, it will fail then with the following error
message (in dmesg): "error getting iommu info. is the iommu enabled?"

Having said that, it doesn't initialize anything in the device H/W
itself, so I find this very weird.

I looked at the patch itself again and I don't see anything suspicious.

I'll try to resurrect my Kaveri machine to check this, but it will
take some time.


My best guess is that there is something broken with the VMID handling 
on Radeon.


I have a Kaveri running amdgpu as one of my test systems here and 
switching to radeon for a test should be trivial.


Going to give that a try later today if I have time.

Christian.



Oded


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix amdgpu_sync_resv v2

[Christian König]

Hi Andres,

just a gentle ping to see if you have noticed this.

Thanks,
Christian.

Am 24.11.2017 um 13:49 schrieb Christian König:

Fixes a bug introduced by AMDGPU_GEM_CREATE_EXPLICIT_SYNC. We still need
to wait for pipelined moves in the shared fences list.

v2: fix typo

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 ++-
  1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index a4bf21f8f1c1..bbbc40d630a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -191,9 +191,6 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
f = reservation_object_get_excl(resv);
r = amdgpu_sync_fence(adev, sync, f);
  
-	if (explicit_sync)

-   return r;
-
flist = reservation_object_get_list(resv);
if (!flist || r)
return r;
@@ -212,11 +209,11 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
 (fence_owner == AMDGPU_FENCE_OWNER_VM)))
continue;
  
-			/* Ignore fence from the same owner as

+   /* Ignore fence from the same owner and explicit one as
 * long as it isn't undefined.
 */
if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
-   fence_owner == owner)
+   (fence_owner == owner || explicit_sync))
continue;
}
  


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Oded Gabbay]

On Wed, Nov 29, 2017 at 1:16 PM, Michel Dänzer  wrote:
> On 2017-11-01 09:31 AM, Oded Gabbay wrote:
>> ok, taken to -next.
>
> This change broke the radeon driver on my Kaveri laptop. The gdm login
> screen works, but logging into the GNOME on Xorg session quickly results
> in a GPU hang and associated badness, see the attached dmesg.
>
> Reverting this change on top of drm-next makes it work again.
>
> On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
> reduce number of free VMIDs and pipes in KV") and 28b57b856b63
> ("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.
>
> Any ideas for what else is missing?
>
> Note that the amdkfd driver isn't actually active anyway, because I'm
> disabling the IOMMU. Is it possible that it's still doing or triggering
> some needed HW setup before it bails in that case?
>
>
> P.S. Assuming we can fix this without reverting, maybe we could also
> remove rdev->grbm_idx_mutex again?
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer

Hi Michel,
Even without IOMMU, amdkfd will initialize the module and internal
structures per device, up to the point where it tries to register a
callback with the iommu driver.
If IOMMU is disabled, it will fail then with the following error
message (in dmesg): "error getting iommu info. is the iommu enabled?"

Having said that, it doesn't initialize anything in the device H/W
itself, so I find this very weird.

I looked at the patch itself again and I don't see anything suspicious.

I'll try to resurrect my Kaveri machine to check this, but it will
take some time.

Oded
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read()

[Tom St Denis]

The callback functions always write to the start of
the array.  The 'offset' parameter instructs
the callbacks the offset into the registers to start
reading from.  So we always copy from the temporary buffer
starting at offset 0.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 48e892e57368..544d18a1fefb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3800,7 +3800,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
struct amdgpu_device *adev = f->f_inode->i_private;
int r;
ssize_t result = 0;
-   uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
+   uint32_t x, offset, se, sh, cu, wave, simd, thread, bank, *data;
 
if (size & 3 || *pos & 3)
return -EINVAL;
@@ -3834,10 +3834,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
amdgpu_gfx_select_se_sh(adev, 0x, 0x, 0x);
mutex_unlock(>grbm_idx_mutex);
 
+   x = 0;
while (size) {
uint32_t value;
 
-   value = data[offset++];
+   value = data[x++];
r = put_user(value, (uint32_t *)buf);
if (r) {
result = r;
-- 
2.12.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: deprecate and remove KFD interface

[Michel Dänzer]

On 2017-11-01 09:31 AM, Oded Gabbay wrote:
> ok, taken to -next.

This change broke the radeon driver on my Kaveri laptop. The gdm login
screen works, but logging into the GNOME on Xorg session quickly results
in a GPU hang and associated badness, see the attached dmesg.

Reverting this change on top of drm-next makes it work again.

On a hunch, I've tried reverting commits 62a7b7fbd08e ("drm/radeon:
reduce number of free VMIDs and pipes in KV") and 28b57b856b63
("drm/radeon/cik: Don't touch int of pipes 1-7"), but no luck.

Any ideas for what else is missing?

Note that the amdkfd driver isn't actually active anyway, because I'm
disabling the IOMMU. Is it possible that it's still doing or triggering
some needed HW setup before it bails in that case?


P.S. Assuming we can fix this without reverting, maybe we could also
remove rdev->grbm_idx_mutex again?

-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
[0.00] Linux version 4.14.2+ (daenzer@kaveri) (gcc version 7.2.0 
(Debian 7.2.0-16)) #295 SMP Mon Nov 27 10:35:18 CET 2017
[0.00] Command line: BOOT_IMAGE=/vmlinuz-4.14.2+ 
root=/dev/mapper/tok--l8--mdaenzer--vg-root ro single iommu=soft radeon.bapm=1 
forcefsck
[0.00] random: get_random_u32 called from bsp_init_amd+0x1d9/0x220 with 
crng_init=0
[0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point 
registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[0.00] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, 
using 'standard' format.
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0008dfff] usable
[0.00] BIOS-e820: [mem 0x0008e000-0x0008] ACPI NVS
[0.00] BIOS-e820: [mem 0x0009-0x0009efff] usable
[0.00] BIOS-e820: [mem 0x0009f000-0x0009] reserved
[0.00] BIOS-e820: [mem 0x0010-0x7d9a1fff] usable
[0.00] BIOS-e820: [mem 0x7d9a2000-0x7dfa1fff] type 20
[0.00] BIOS-e820: [mem 0x7dfa2000-0x7e89dfff] reserved
[0.00] BIOS-e820: [mem 0x7e89e000-0x7ef9dfff] ACPI NVS
[0.00] BIOS-e820: [mem 0x7ef9e000-0x7effefff] ACPI data
[0.00] BIOS-e820: [mem 0x7efff000-0x7eff] usable
[0.00] BIOS-e820: [mem 0xfec1-0xfec10fff] reserved
[0.00] BIOS-e820: [mem 0xfed8-0xfed80fff] reserved
[0.00] BIOS-e820: [mem 0xff83-0xff84efff] reserved
[0.00] BIOS-e820: [mem 0x0001-0x00023eff] usable
[0.00] NX (Execute Disable) protection: active
[0.00] efi: EFI v2.31 by HPQ
[0.00] efi:  ACPI=0x7effe000  ACPI 2.0=0x7effe014  SMBIOS=0x7e053c98 
[0.00] random: fast init done
[0.00] SMBIOS 2.7 present.
[0.00] DMI: Hewlett-Packard HP EliteBook 725 G2/221D, BIOS M84 Ver. 
01.44 09/26/2016
[0.00] tsc: Fast TSC calibration using PIT
[0.00] e820: update [mem 0x-0x0fff] usable ==> reserved
[0.00] e820: remove [mem 0x000a-0x000f] usable
[0.00] e820: last_pfn = 0x23f000 max_arch_pfn = 0x4
[0.00] MTRR default type: uncachable
[0.00] MTRR fixed ranges enabled:
[0.00]   0-9 write-back
[0.00]   A-B uncachable
[0.00]   C-F write-through
[0.00] MTRR variable ranges enabled:
[0.00]   0 base  mask 8000 write-back
[0.00]   1 base FF80 mask FF80 write-protect
[0.00]   2 disabled
[0.00]   3 disabled
[0.00]   4 disabled
[0.00]   5 disabled
[0.00]   6 disabled
[0.00]   7 disabled
[0.00] TOM2: 00023f00 aka 9200M
[0.00] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[0.00] e820: last_pfn = 0x7f000 max_arch_pfn = 0x4
[0.00] Base memory trampoline at [9fbd40099000] 99000 size 24576
[0.00] Using GB pages for direct mapping
[0.00] BRK [0x10a3de000, 0x10a3defff] PGTABLE
[0.00] BRK [0x10a3df000, 0x10a3d] PGTABLE
[0.00] BRK [0x10a3e, 0x10a3e0fff] PGTABLE
[0.00] BRK [0x10a3e1000, 0x10a3e1fff] PGTABLE
[0.00] BRK [0x10a3e2000, 0x10a3e2fff] PGTABLE
[0.00] BRK [0x10a3e3000, 0x10a3e3fff] PGTABLE
[0.00] BRK [0x10a3e4000, 0x10a3e4fff] PGTABLE
[0.00] BRK [0x10a3e5000, 0x10a3e5fff] PGTABLE
[0.00] Secure boot could not be determined
[0.00] RAMDISK: [mem 0x33277000-0x35932fff]
[0.00] ACPI: Early table checksum 

Re: [PATCH 02/13] fbdev: add remove_conflicting_pci_framebuffers()

[Daniel Vetter]

On Tue, Nov 28, 2017 at 12:30:30PM +, Sudip Mukherjee wrote:
> On Tue, Nov 28, 2017 at 12:32:38PM +0100, Greg KH wrote:
> > On Tue, Nov 28, 2017 at 11:22:17AM +0100, Daniel Vetter wrote:
> > > On Mon, Nov 27, 2017 at 08:52:19PM +, Sudip Mukherjee wrote:
> > > > On Mon, Nov 27, 2017 at 11:27:59AM +0100, Daniel Vetter wrote:
> > > > > On Fri, Nov 24, 2017 at 06:53:31PM +0100, Michał Mirosław wrote:
> > > > > > Almost all drivers using remove_conflicting_framebuffers() wrap it 
> > > > > > with
> > > > > > the same code. Extract common part from PCI drivers into separate
> > > > > > remove_conflicting_pci_framebuffers().
> > > > > > 
> > > > > > Signed-off-by: Michał Mirosław 
> > > > > 
> > > > > Since the only driver that seems to use this is the staging one, 
> > > > > which imo
> > > > > is a DOA project, not sure it's worth to bother with this here.
> > > > 
> > > > afaik, this device is used in production by few manufacturers and it is
> > > > usefull for them to have it in the tree and the only reason it is still
> > > > in staging is because Tomi announced he will not take any new drivers in
> > > > fbdev. And, so I have not taken the initiative to properly move it out
> > > > of staging. I think Bartlomiej will also not accept new drivers in 
> > > > fbdev.
> > > 
> > > Imo, if no one cares about porting it to kms (which will give you an fbdev
> > > driver for free), then we should throw it out. At least I thought staging
> > > was only for stuff that had a reasonable chance to get mainlined. Not as a
> > > dumping ground for drivers that people use, but don't bother to get ready
> > > for mainline.
> > > 
> > > Greg?
> > 
> > Yes, if no one is working to get it out of staging, that means no one
> > cares about it, and it needs to be removed from the tree.
> 
> Agreed. I was not working on getting it out of staging as there is no
> place for it to go.
> But, Teddy Wang told me that they have a working drm driver for it, but
> it is not atomic like Daniel was asking for. If it is ok, then I can send
> in a patch to remove the existing sm750 from staging and add the new sm750
> drm driver to staging. And after it is ready, we can go ahead with moving
> it out of staging to drm.

Please keep the todo item that it needs to be converted to atomic. And
tbh, it's probably faster if you just submit it to dri-devel, assuming you
have time to work on it. For small drivers we tend to be fairly quick in
getting them into good enough shape.

Staging is also a major pain for drm subsystem refactorings, I really,
really, really prefer we don't add more than the vbox pain we have
already.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/1] drm/amdgpu: Pin to gtt before cpu accesses dma buf.

[Christian König]

Am 29.11.2017 um 01:20 schrieb Samuel Li:

To improve cpu read performance. This is implemented for APUs currently.


And once more a NAK for this approach.

What we could do is migrate the BO to GTT during mmap, but pinning it is 
out of question.


Regards,
Christian.



Change-Id: I300a7daed8f2b0ba6be71a43196a6b8617ddc62e
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  10 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 108 ++
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   8 +-
  5 files changed, 126 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..193db70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -417,6 +417,8 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
  struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
struct drm_gem_object *gobj,
int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
+   struct dma_buf *dma_buf);
  int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
  void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
  struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index d704a45..b5483e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -147,6 +147,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+   bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev->flags & 
AMD_IS_APU);
struct amdgpu_framebuffer *old_amdgpu_fb;
struct amdgpu_framebuffer *new_amdgpu_fb;
struct drm_gem_object *obj;
@@ -190,8 +191,13 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
  
  	r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, );

if (unlikely(r != 0)) {
-   DRM_ERROR("failed to pin new abo buffer before flip\n");
-   goto unreserve;
+   /* latest APUs support gtt scan out */
+   if (gtt_scannable)
+   r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_GTT, 
);
+   if (unlikely(r != 0)) {
+   DRM_ERROR("failed to pin new abo buffer before flip\n");
+   goto unreserve;
+   }
}
  
  	r = reservation_object_get_fences_rcu(new_abo->tbo.resv, >excl,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 31383e0..df30b08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -868,7 +868,7 @@ static struct drm_driver kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = amdgpu_gem_prime_export,
-   .gem_prime_import = drm_gem_prime_import,
+   .gem_prime_import = amdgpu_gem_prime_import,
.gem_prime_pin = amdgpu_gem_prime_pin,
.gem_prime_unpin = amdgpu_gem_prime_unpin,
.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index ae9c106..9e1424d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -164,6 +164,82 @@ struct reservation_object *amdgpu_gem_prime_res_obj(struct 
drm_gem_object *obj)
return bo->tbo.resv;
  }
  
+static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)

+{
+   struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   long i, ret = 0;
+   unsigned old_count;
+   bool reads = (direction == DMA_BIDIRECTIONAL || direction == 
DMA_FROM_DEVICE);
+   bool gtt_scannable = (adev->asic_type >= CHIP_CARRIZO && adev->flags & 
AMD_IS_APU);
+   u32 domain;
+
+   if (!reads || !gtt_scannable)
+   return 0;
+
+   ret = amdgpu_bo_reserve(bo, false);
+   if (unlikely(ret != 0))
+   return ret;
+
+   /*
+* Wait for all shared fences to complete before we switch to future
+* use of exclusive fence on this prime shared bo.
+*/
+   ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
+ MAX_SCHEDULE_TIMEOUT);
+
+   if (unlikely(ret < 0)) {
+ 

Re: [PATCH] drm/amd/amdgpu: set gtt size according to system memory size only

[Christian König]

Am 29.11.2017 um 10:12 schrieb Roger He:

Change-Id: Ib634375b90d875fe04a890fc82fb1e3b7112676a
Signed-off-by: Roger He 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++-
  1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 17bf0ce..d0661907 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1330,11 +1330,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
struct sysinfo si;
  
  		si_meminfo();

-   gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-  adev->mc.mc_vram_size),
-  ((uint64_t)si.totalram * si.mem_unit * 3/4));
-   }
-   else
+   gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20,
+   (uint64_t)si.totalram * si.mem_unit * 3/4);
+   } else
gtt_size = (uint64_t)amdgpu_gtt_size << 20;
r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
if (r) {


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)

[Christian König]

Hi Frank,

well that explains why we do it, but not the background.

Anyway feel free to add an Acked-by: Christian König 
 to the patch and commit it.


Regards,
Christian.

Am 29.11.2017 um 04:10 schrieb Min, Frank:

Hi Christian,
I have talked with hw team for the reason why adding the masks. the answer is "bits 
24-27 of the VCE_VCPU_CACHE_OFFSETx registers should be set to the cache window # (0 for 
window 0, 1 for window 1, etc.)"

Best Regards,
Frank

-邮件原件-
发件人: Min, Frank
发送时间: 2017年11月23日 12:08
收件人: Koenig, Christian ; amd-gfx@lists.freedesktop.org; 
Liu, Leo 
主题: RE: [PATCH] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)

Hi Leo,
Would you please comments on Christian's questions?

Best Regards,
Frank

-Original Message-
From: Min, Frank
Sent: Wednesday, November 22, 2017 4:04 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org; Liu, 
Leo 
Subject: RE: [PATCH] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)

Hi Christian,
Thanks again for your review.

And for the mask change my understanding is it is to be used for mark different part of fw 
(1<<24 is for stack and 2<<24 is for the data).
And more detailed background would need Leo give us.

Best Regards,
Frank

-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 22, 2017 3:57 PM
To: Min, Frank ; amd-gfx@lists.freedesktop.org; Liu, Leo 

Subject: Re: [PATCH] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)

Hi Frank,

thanks, the patch looks much better now.


The masks using is to programming the stack and data part for vce fw. And this 
part of code is borrowed from the non-sriov sequences.

In this case Leo can you explain this strange masks used for the
VCE_VCPU_CACHE_OFFSET* registers?


MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_VCPU_CACHE_OFFSET0),
-   offset & 0x7FFF);
+   offset & ~0x0f00);

...

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_VCPU_CACHE_OFFSET1),
-   offset & 0x7FFF);
+   (offset & ~0x0f00) | (1 << 24));

Using ~0x0f00 looks really odd here and what should the "| (1 << 24)" part 
be about?

Thanks,
Christian.

Am 22.11.2017 um 06:11 schrieb Min, Frank:

Hi Christian,
Patch updated according to your suggestions.
The masks using is to programming the stack and data part for vce fw. And this 
part of code is borrowed from the non-sriov sequences.

Best Regards,
Frank

1. program vce 4.0 fw with 48 bit address 2. correct vce 4.0 fw stack
and date offset

Change-Id: Ic1bc49c21d3a90c477d11162f9d6d9e2073fbbd3
Signed-off-by: Frank Min 
---
   drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 38 
+++
   1 file changed, 25 insertions(+), 13 deletions(-)  mode change
100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
old mode 100644
new mode 100755
index 7574554..024a1be
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -243,37 +243,49 @@ static int vce_v4_0_sriov_start(struct amdgpu_device 
*adev)
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
mmVCE_LMI_VM_CTRL), 0);
   
   		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
-   
adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
-   
adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
+   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+   
mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+   
mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
+   
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) &
+0xff);
} else {
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
+   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
+   
mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
 

[PATCH] drm/amd/amdgpu: set gtt size according to system memory size only

[Roger He]

Change-Id: Ib634375b90d875fe04a890fc82fb1e3b7112676a
Signed-off-by: Roger He 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 17bf0ce..d0661907 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1330,11 +1330,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
struct sysinfo si;
 
si_meminfo();
-   gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-  adev->mc.mc_vram_size),
-  ((uint64_t)si.totalram * si.mem_unit * 3/4));
-   }
-   else
+   gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20,
+   (uint64_t)si.totalram * si.mem_unit * 3/4);
+   } else
gtt_size = (uint64_t)amdgpu_gtt_size << 20;
r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
if (r) {
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

radeon GPU lockup followed by list_del corruption

[Jonathon Reinhart]

Hello,

I just encountered a one-off GPU lockup (evidenced by a display
freeze, followed by several "flashes"). The GPU was mostly inactive,
with just Chrome and some gnome-terminals open.

GPU: Radeon HD 7850
Kernel: 4.10.13-200.fc25.x86_64

I decided to email this list rather than ignore this seemingly random
event because:

1. The GPU, although a few years old, wasn't doing any heavy
processing, indicating heat-related faults.

2. While driver bugs may manifest themselves in light of hardware
troubles, the "list_del corruption" BUG is highly undesirable -- a GPU
lockup shouldn't panic the box.

I've uploaded the full dmesg log:
https://gist.github.com/JonathonReinhart/ede339261daa00e6924a92cc32c6e26e
Notable snippets are posted at the end of this message.

Let me know if I can provide any more information.

Regards,

Jonathon Reinhart





Nov 28 21:24:29.743859 kernel: WARNING: CPU: 3 PID: 32172 at
drivers/gpu/drm/radeon/radeon_object.c:84 radeon_ttm_bo_destroy+0xf6/0
   x100 [radeon]
...
Nov 28 21:25:03.899302 kernel: radeon :01:00.0: still active bo inside vm
Nov 28 21:25:03.899353 kernel: list_del corruption. prev->next should
be 913cfff40500, but was 913dc1dc6380
Nov 28 21:25:03.899377 kernel: [ cut here ]
Nov 28 21:25:03.899396 kernel: kernel BUG at lib/list_debug.c:52!
Nov 28 21:25:03.899542 kernel: invalid opcode:  [#1] SMP
Nov 28 21:25:03.899665 kernel: Modules linked in: veth
nf_conntrack_netlink xt_addrtype br_netfilter dm_thin_pool
dm_persistent_data dm_bio_prison loop xt_CHECKSUM ipt_MASQUERADE
nf_nat_masquerade_ipv4 tun nf_conntrack_netbios_ns
nf_conntrack_broadcast xt_CT ip6t_rpfilter ip6t_REJECT nf_reject_ipv6
xt_conntrack ip_set nfnetlink ebtable_nat ebtable_broute bridge stp
llc ip6table_raw ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6
nf_nat_ipv6 ip6table_mangle ip6table_security iptable_raw iptable_nat
nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack
libcrc32c iptable_mangle iptable_security ebtable_filter ebtables
ip6table_filter ip6_tables binfmt_misc fuse usblp raid1 intel_rapl
x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel iTCO_wdt
eeepc_wmi iTCO_vendor_support asus_wmi sparse_keymap rfkill kvm
Nov 28 21:25:03.899694 kernel:  mxm_wmi irqbypass crct10dif_pclmul
crc32_pclmul ghash_clmulni_intel intel_cstate intel_uncore
intel_rapl_perf snd_hda_codec_realtek snd_hda_codec_generic
snd_hda_codec_hdmi snd_hda_intel snd_hda_codec joydev lpc_ich i2c_i801
snd_hda_core snd_hwdep snd_seq snd_seq_device snd_pcm snd_timer snd
soundcore mei_me video wmi mei shpchp tpm_tis tpm_tis_core tpm nfsd
auth_rpcgss nfs_acl lockd grace sunrpc hid_logitech_hidpp
hid_logitech_dj ata_generic pata_acpi amdkfd amd_iommu_v2 radeon
crc32c_intel i2c_algo_bit drm_kms_helper serio_raw ttm drm
firewire_ohci pata_marvell r8169 firewire_core crc_itu_t mii fjes
Nov 28 21:25:03.899713 kernel: CPU: 0 PID: 32172 Comm: chrome Tainted:
GW   4.10.13-200.fc25.x86_64 #1
Nov 28 21:25:03.899831 kernel: Hardware name: System manufacturer
System Product Name/P8P67 LE, BIOS 3801 09/12/2013
Nov 28 21:25:03.899897 kernel: task: 9140c8d7a580 task.stack:
9e9601a64000
Nov 28 21:25:03.899915 kernel: RIP: 0010:__list_del_entry_valid+0x75/0x90
Nov 28 21:25:03.899934 kernel: RSP: 0018:9e9601a67b40 EFLAGS: 00010286
Nov 28 21:25:03.899948 kernel: RAX: 0054 RBX:
913cfff40500 RCX: 0006
Nov 28 21:25:03.899965 kernel: RDX:  RSI:
0246 RDI: 9140dec0e0e0
Nov 28 21:25:03.899981 kernel: RBP: 9e9601a67b40 R08:
000c7b0c R09: 2854
Nov 28 21:25:03.900083 kernel: R10: 0004 R11:
a2224d0f R12: 913dc51c5c00
Nov 28 21:25:03.900104 kernel: R13: 913d6da30400 R14:
913ce3f7f000 R15: 9140c7578000
Nov 28 21:25:03.900121 kernel: FS:  7f57694e1f80()
GS:9140dec0() knlGS:
Nov 28 21:25:03.900190 kernel: CS:  0010 DS:  ES:  CR0: 80050033
Nov 28 21:25:03.900211 kernel: CR2: 55f41a64728f CR3:
000112551000 CR4: 000426f0
Nov 28 21:25:03.900275 kernel: Call Trace:
Nov 28 21:25:03.900295 kernel:  radeon_vm_fini+0x89/0x250 [radeon]
Nov 28 21:25:03.900317 kernel:  radeon_driver_postclose_kms+0xf1/0x150 [radeon]
Nov 28 21:25:03.900333 kernel:  drm_release+0x28c/0x3a0 [drm]
Nov 28 21:25:03.900350 kernel:  __fput+0xdf/0x1e0
Nov 28 21:25:03.900365 kernel:  fput+0xe/0x10
Nov 28 21:25:03.900381 kernel:  task_work_run+0x80/0xa0
Nov 28 21:25:03.900397 kernel:  do_exit+0x2c8/0xb80
Nov 28 21:25:03.900416 kernel:  do_group_exit+0x47/0xb0
Nov 28 21:25:03.900454 kernel:  get_signal+0x289/0x630
Nov 28 21:25:03.900470 kernel:  do_signal+0x37/0x690
Nov 28 21:25:03.900487 kernel:  ? padata_reorder+0x160/0x1d0
Nov 28 21:25:03.900504 kernel:  ? is_prefetch.isra.18+0x95/0x1a0
Nov 28 21:25:03.900518 kernel:  ? padata_reorder+0x160/0x1d0
Nov 28 21:25:03.900535 kernel:  ? mm_fault_error+0x13c/0x190
Nov 28